Semiconductor device

Abstract

To provide a semiconductor device that has a transistor with good electrical characteristics.SOLUTION: Provided is a semiconductor device in which a storage circuit and a circuit are produced on the same substrate. The storage circuit has a capacitive element, a first transistor and a second transistor. The capacitive element and any one of a source and a drain of the second transistor are electrically connected with a gate of the first transistor. The circuit has a third transistor and a fourth transistor. Each of the first transistor and the third transistor has an active layer containing silicon. Each of the second transistor and the fourth transistor has an active layer containing an oxide semiconductor.SELECTED DRAWING: Figure 23

Description

[Technical field]

[0001] One aspect of the present invention relates to a circuit system using a semiconductor and other semiconductor devices. Another embodiment of the present invention relates to a driving method or a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical fields. The technical field of the present invention relates to a product, a method, or a manufacturing method. Process, Machine, Manufacture, or Composition of Matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices The present invention is also applicable to imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, and the like. Devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are semiconductors. The device may have a

[0004] In this specification, the circuit system includes a capacitance element, a transistor, a resistance element, a memory element, The term refers to a circuit that has semiconductor devices such as semiconductor elements and wiring. A driving circuit for driving the semiconductor device, a power supply circuit, etc. may be included. The system includes inverter circuits, NAND circuits, AND circuits, NOR circuits, OR circuits, and buffer , level shifter, XOR circuit, XNOR circuit, AND-NOR circuit, OR-NAND circuit , AND-OR-INV circuit, OR-AND-INV circuit, analog switch, flip Flops, settable flip-flops, resettable flip-flops, set and and resettable flip-flops, adders, half adders, multiplexers, demultiplexers lexers, registers, scan registers, retention registers, isolators, and detectors The coder, etc. may include one or more of: [Background technology]

[0005] The technology of constructing transistors using semiconductor materials is attracting attention. Electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices) Silicon-based semiconductor materials are widely used as semiconductor materials that can be used in transistors. are widely known, but oxide semiconductors are attracting attention as another material.

[0006] For example, zinc oxide or In-Ga-Zn oxide is used as the oxide semiconductor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2).

[0007] In recent years, miniaturized transistors have become more common as electronic devices become more powerful, smaller, and lighter. 2. Description of the Related Art There is an increasing demand for integrated circuits in which semiconductor elements such as transistors are densely integrated. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0009] One aspect of the present invention provides a circuit system having transistors with good electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor having good electrical characteristics. The object of the present invention is to provide a circuit system having a transistor and a capacitive element having a small capacitance. Another embodiment of the present invention is a circuit system including a transistor suitable for miniaturization. Another object of the present invention is to provide a system having a high switching speed. One of the objectives of the present invention is to provide a circuit system that can improve the operating speed. An object of one embodiment of the present invention is to provide a circuit system with improved writing speed. Another embodiment of the present invention provides a circuit system having an improved read speed. Another object of one embodiment of the present invention is to provide a circuit system with low power consumption. Another object of one embodiment of the present invention is to provide a memory element having good retention characteristics. One of the objectives is to provide a circuit system having a semiconductor device. Another object of the present invention is to provide a novel semiconductor device. It shall be one of the following.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor memory device including a capacitor and a transistor electrically connected to the capacitor. In the semiconductor device, the capacitance of the capacitive element is equal to or greater than 0.1 fF and less than 10 fF; The transistor includes an oxide semiconductor film, and is configured to perform writing to the semiconductor device when the semiconductor device is operated at room temperature. The semiconductor device has a delay time of 0.1 ns or more and less than 5 ns.

[0012] One embodiment of the present invention is a semiconductor device in which a memory circuit and a circuit are formed over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. The gate of the first transistor is connected to a capacitance element and the source or drain of the second transistor. The drains of the first and second transistors are electrically connected to each other, and the circuit includes a third transistor and a fourth transistor. a third transistor and a fourth transistor connected in series to each other. The first transistor and the third transistor have active layers including silicon. The second transistor and the fourth transistor each have an active layer formed of an oxide semiconductor film. The semiconductor device has the following features.

[0013] One embodiment of the present invention is a semiconductor device in which a memory circuit and a circuit are formed over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A capacitance element is connected to the gate of the first transistor, and a source or The drains of the third transistor and the fourth transistor are electrically connected to each other. a third transistor and a fourth transistor are connected in series with each other The first to fourth transistors each have an active layer formed using an oxide semiconductor film. It is a semiconductor device.

[0014] In each of the above aspects, the transistor having an active layer formed of an oxide semiconductor film is It is preferable that the channel length is 1 nm or more and less than 100 nm. In the oxide semiconductor film, oxygen, In, Zn, and M (M is Ti, Ga, Y, Z) are In addition, in each of the above embodiments, In the above-described embodiments, the oxide semiconductor film preferably has a crystal part. The film preferably has a crystal portion oriented along the c-axis. Effect of the Invention

[0015] According to one embodiment of the present invention, a circuit system having a transistor with good electrical characteristics is provided. Alternatively, according to one embodiment of the present invention, a transistor having good electrical properties can be provided. It is possible to provide a circuit system having a transistor and a capacitive element with a small electrostatic capacitance. According to one embodiment of the present invention, a circuit system including a transistor suitable for miniaturization is provided. Alternatively, according to one aspect of the present invention, the switching speed (also called the operating speed) can be improved. According to one embodiment of the present invention, a circuit system can be provided in which the following characteristics are improved: In this way, it is possible to provide a circuit system with improved writing speed. By this method, it is possible to provide a circuit system with improved read speed. According to one embodiment of the present invention, a circuit system with low power consumption can be provided. According to one aspect of the present invention, it is possible to provide a circuit system having a memory element with good retention characteristics. Alternatively, a novel circuit system can be provided. Alternatively, a novel semiconductor device can be provided. Locations can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a block diagram illustrating an example of a circuit system. [Diagram 2] (A)-(C) are circuit diagrams showing an example of a memory device. (D) is a cross-sectional view of the same. [Diagram 3] (A) is a schematic diagram showing an example of a memory cell array, and (B) is a circuit diagram showing an example of a memory cell. [Figure 4] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Diagram 5] 1A and 1B are timing charts showing an example of the operation of a memory cell array. [Figure 6] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Figure 7] FIG. 2 is a circuit diagram showing an example of a memory cell array. [Figure 8] FIG. 2 is a cross-sectional view showing an example of a memory cell array. [Figure 9] FIG. 2 is a cross-sectional view showing an example of a memory cell array. [Figure 10] A partially enlarged view of Figure 9. [Figure 11] FIG. 2 is a cross-sectional view showing an example of a memory cell array. [Figure 12] (B) is a top view showing an example of a transistor. (A) and (C) are cross-sectional views of the same. [Figure 13] (B) is a top view showing an example of a transistor. (A) and (C) are cross-sectional views of the same. [Figure 14] 1A to 1D are cross-sectional views showing an example of a transistor. [Figure 15] 1A to 1D are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 16] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 17] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a memory cell array. [Figure 18] 1A to 1C are cross-sectional views showing an example of a manufacturing method of a memory cell array. [Figure 19] 19A is a circuit diagram showing an example of a semiconductor device, and (B) and (C) are cross-sectional views showing a configuration example of the semiconductor device of FIG. [Figure 20] 20A is a circuit diagram showing an example of a semiconductor device, and (B) and (C) are cross-sectional views showing a configuration example of the semiconductor device of FIG. [Figure 21] 21A is a circuit diagram showing an example of a semiconductor device, and FIG. 21B is a cross-sectional view showing a configuration example of the semiconductor device of FIG. [Figure 22] 1A to 1I are circuit diagrams illustrating an example of a semiconductor device. [Diagram 23] 1A is a cross-sectional view showing a configuration example of a semiconductor device, and FIG. [Figure 24] 1A is a cross-sectional view showing a configuration example of a semiconductor device, and FIG. [Diagram 25] FIG. 1 illustrates an example of an RF device. [Figure 26] (A)-(F): Diagrams showing examples of using RF devices. [Figure 27] FIG. 2 illustrates an example of a CPU. [Figure 28] FIG. 2 is a circuit diagram showing an example of a memory circuit. [Figure 29] (A)-(F) are diagrams showing examples of electronic devices. [Diagram 30] 1A and 1B are diagrams illustrating band structures in a stacked structure of an insulating film and an oxide semiconductor film. [Diagram 31] FIG. 13 shows measurement results of cutoff frequencies of OS transistors. [Diagram 32] FIG. 13 shows the Vg-Id characteristics of the fabricated transistors. [Diagram 33] (A): Circuit diagram of the fabricated circuit system. (B): Layout diagram of the same. (C): Optical microscope photograph of the same. [Diagram 34] FIG. 4 is a schematic diagram showing operating waveforms during a write operation of the fabricated circuit system. [Diagram 35] FIG. 13 is a graph showing the relationship between the voltage of a floating node and the write time in the fabricated circuit system. [Diagram 36] FIG. 13 is a graph showing the relationship between the writing time and the capacitance of the fabricated circuit system. [Figure 37] DC characteristics of a transistor (CAAC-OS FET) using a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film. (A): Measurement results of drain current-gate voltage (Id-Vg) characteristics. (B): Measurement results of drain current-drain voltage (Id-Vd) characteristics. [Figure 38] FIG. 13 shows the measurement results of transconductance gm characteristics of a CAAC-OS FET. [Figure 39] FIG. 13 shows measurement results of high-frequency gain versus frequency of a CAAC-OS FET. [Diagram 40] This figure shows the relationship between Vd and the cutoff frequency and maximum oscillation frequency of a CAAC-OS FET. [Diagram 41] Circuit diagram of the fabricated memory circuit. [Diagram 42] 42 is a diagram showing the relationship between the load capacitance Cload and the write time of the memory circuit in FIG. 41. [Diagram 43] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 44] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 45] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 46] Electron diffraction pattern of CAAC-OS. [Figure 47] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 48] 1A to 1C are diagrams illustrating a method for forming a CAAC-OS film. [Figure 49] A diagram explaining the InMZnO4 crystal. [Figure 50] 1A to 1C are diagrams illustrating a method for forming a CAAC-OS film. [Figure 51] 1A to 1C are diagrams illustrating a method for forming a CAAC-OS film. [Figure 52] A diagram explaining the method for forming nc-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0019] In the configuration of the invention described below, the same parts or parts having similar functions are referred to as the same parts. Reference numerals are used in common between different drawings, and repeated explanations are omitted. When referring to an item, the hatch pattern is the same and no particular reference symbol may be used.

[0020] In each figure described in this specification, the size, layer thickness, or area of ​​each component is not shown for clarity. The figures may be exaggerated for illustrative purposes and are not necessarily limited to that scale.

[0021] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The number is not a limiting factor.

[0022] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. " refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. This also includes cases where the angle is between 85° and 95°.

[0023] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. The transistor in this specification can realize a switching operation that controls the switching state. is an IGFET (Insulated Gate Field Effect Tran) sistors and thin film transistors (TFTs) A transistor also has three elements called the gate, source, and drain. In this specification and the like, the two terminals other than the gate of a transistor are These are sometimes called the first terminal and second terminal of the transistor.

[0024] For example, in this specification, when it is explicitly stated that X and Y are connected, , when X and Y are electrically connected, and when X and Y are functionally connected, , and the case where X and Y are directly connected is also included. For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be modified in any manner without departing from the spirit or scope of the present invention. This also includes things other than relationships.

[0025] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0026] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) to allow current to flow. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0027] An example of a case where X and Y are functionally connected is the case where the functional connection between X and Y is possible. Circuits that perform the functions of the following: logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) (e.g., circuits that generate One or more devices (such as a synthesis circuit, memory circuit, or control circuit) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X is X and Y are said to be functionally connected if the signal is transmitted to Y.

[0028] When it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. When X and Y are connected together (i.e., when another element or circuit is between X and Y), X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected through a wire, and when X and Y are directly connected (i.e. , when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0029] For example, if the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z2 When it is electrically connected to Y through (or without) the source of the transistor ( or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do this.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor terminals, etc.) are electrically connected to each other, and X, the source (or first terminal, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in that order. Or, it can be expressed as "the source (or the first terminal) of the transistor is connected to the ) is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y. Electrically connected, X, the source (or first terminal, etc.) of the transistor, The first terminal (or the second terminal, etc.), Y are electrically connected in this order. Or, "X is the source (or first terminal, etc.) and drain ( or the second terminal, etc.) and X is electrically connected to the source (or is the first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y is the connection order Using the same expression as these examples, By specifying the order of connections in the circuit configuration, the source (or Distinguish between the first terminal (or the first terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. It should be noted that these expressions are merely examples and are not intended to be limiting. Here, X, Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminal, conductive film, layer, etc.).

[0031] (Embodiment 1) In this embodiment, a circuit system according to one embodiment of the present invention will be described with reference to FIGS. Here, a storage device will be described as an example of a circuit system.

[0032] <Example of circuit system configuration> FIG. 1 is a block diagram showing an example of a circuit system.

[0033] The circuit system 10 shown in FIG. 1 includes a memory cell array 12 and a peripheral circuit 14. The peripheral circuit 14 is electrically connected to the memory cell array 12. The peripheral circuit 14 includes: Row Driver, Column Driver r), and A / D converter. The edge circuit 14 may include a logic circuit or the like.

[0034] The memory cell array 12 and the peripheral circuit 1 electrically connected to the memory cell array 12 4 (here, a row selection driver, a column selection driver, and an A / D converter) , may be referred to as a storage device.

[0035] Here, a memory circuit that can be used in the circuit system of one embodiment of the present invention will be described with reference to FIG. An example of the above will be described.

[0036] FIG. 2A is a circuit diagram showing an example of a memory device. The memory circuit 25 shown in FIG. The memory circuit 25 includes a transistor 21, a transistor 22, and a capacitor 23. It is possible to retain data even when power is not supplied, and there is no limit to the number of times it can be written. In addition, the memory circuit 25 is, for example, a memory cell of the memory cell array 12 shown in FIG. It is possible to apply

[0037] Specifically, the transistor 21 and the transistor 22 are semiconductors including an oxide semiconductor. A transistor in which a channel is formed in a layer (hereinafter, sometimes referred to as an "OS transistor") As shown in FIG. 2(A), the OS (Oxide Semiconductor) The transistors marked with "tor" indicate transistors having an oxide semiconductor layer. The same is true for the other drawings. Also, in FIG. 2(A), a transistor 21 and a transistor In the illustrated embodiment, both of the transistors 22 are OS transistors, but the present invention is not limited thereto. At least one of the transistors 21 and 22 may be an OS transistor. It is highly preferred that transistor 22 be an OS transistor. By applying OS transistors to the memory circuit 25, it is possible to reduce the power consumption of the memory circuit 25. Specifically, since the off-state current of the transistor 22 can be reduced, It is possible to retain the stored contents. In other words, no refresh operation is required. This allows the frequency of refresh operations to be reduced significantly, so power consumption can be reduced sufficiently. It is possible to provide a memory circuit 25 having a reduced size.

[0038] In addition, the memory circuit 25 shown in FIG. 2A does not require a high voltage for writing data. For example, unlike conventional flash memory, the floating Since electrons are not injected into the floating gate or extracted from the floating gate, Therefore, the problem of deterioration of the insulator does not occur. There is no limit to the number of times that data can be rewritten, which is an issue with conventional flash memory, and it is highly reliable. This is a dramatically improved semiconductor device. This allows data to be written at high speed.

[0039] The capacitance of the capacitance element 23 of the memory circuit 25 is equal to or greater than 0.1 fF and less than 10 fF. By setting the capacitance of the capacitance element 23 in the above range, the writing speed can be improved. In other words, the writing time can be shortened. In principle, the write time is between 0.1 nsec and 5 nsec when operating at room temperature. Or, the write speed frequency can be set to 0.2 GHz at room temperature. The write speed can be set to 10 GHz or less at room temperature. This is converted to a bit rate of 400Mbps (bit pe r second) or more and 20 Gbps or less.

[0040] Here, the write time is the time period during which data is written by charging the capacitance element 23 of the memory circuit 25. In other words, it is the time required to charge the capacitance element 23 by 90% when writing The potential of the node FN is changed from a low level potential to a bit line (wire WB This refers to the time it takes for the potential of the material to rise to 90% of its original value (L).

[0041] The write speed is the time it takes for the write transistor in the memory circuit to go from a non-conductive state to a conductive state. Alternatively, the write speed may be expressed as a function of the current gain of the write transistor being 1 or more. In the memory circuit 25, the maximum frequency (cutoff frequency) of the transistor may be used. The transistor 22 serves as a write transistor.

[0042] Either or both of the transistors 21 and 22 have a channel length of It is preferable that the region is 1 nm or more and less than 100 nm, and the channel length is 5 nm or more and 60 nm or less. It is more preferable that the channel length of the transistor is in the range of 10 nm or less. By doing so, it is possible to obtain a miniaturized memory device or a circuit having the memory device and a small circuit area. It is possible to provide a low-power consumption circuit system having the memory device. do.

[0043] The memory circuit 25 shown in FIG. 2A includes a wiring WBL (also called a write bit wiring), RBL (also called read bit line), wiring WWL (also called write word line), The wiring RWL (also called read word wiring) and the wiring SL (also called source line) The wiring RBL is electrically connected to the first terminal of the transistor 21. The wiring SL is electrically connected to the second terminal of the transistor 21. The wiring WWL is electrically connected to the first terminal of the transistor 22. The gate electrode of the transistor 21 is electrically connected to the The second terminal of the capacitor 22 and the first terminal (first electrode) of the capacitance element 23 are electrically connected to each other. The line RWL is electrically connected to the second terminal (second electrode) of the capacitive element 23.

[0044] In addition, in FIG. 2A, the electrode of the capacitor 23 and the gate electrode of the transistor 21 are The electrically connected node is called node FN. The symbol "FN" indicates that the node is in an electrically floating state. In this specification, the term "node" refers to a node that can become a refers to a location on a wiring provided for electrically connecting elements.

[0045] In the memory circuit 25 shown in FIG. The write, hold and read operations of the memory circuit 25 are described below. The output will be explained.

[0046] In writing data, first, the potential of the wiring WWL is set to a potential at which the transistor 22 is turned on. This causes the transistor 22 to be turned on, and the gate of the transistor 21 The potential of the wiring WBL is applied to the electrode and the first terminal of the capacitance element 23. A predetermined charge is applied to the electrode 23. Here, the wiring WBL is at a low level or a high level. The capacitance element 23 is connected to the wiring WB Next, the potential of the wiring WWL is applied to the transistor 2 By turning off the transistor 22, the node FN is in an electrically floating state, and the charge applied to the capacitance element 23 is held. Then, data is written into the memory circuit 25 shown in FIG.

[0047] Since the off-state current of the transistor 22 is extremely small, the charge given to the capacitor 23 is Therefore, data can be retained even when power is not supplied. It becomes Noh.

[0048] The data read is explained below. A state in which a predetermined potential (constant potential) is applied to the wiring RBL. When an appropriate potential (read potential) is applied to the wiring RWL, the potential held in the capacitance element 23 The wiring SL has different potentials depending on the amount of charge. If the transistor 21 is an n-channel type, When a high-level potential is applied to the gate electrode of the transistor 21, Value V th_H In general, a low-level potential is applied to the gate electrode of the transistor 21. The apparent threshold V th_L Here, the apparent threshold voltage The voltage refers to the potential of the wiring RWL required to turn the transistor 21 on. Therefore, the potential of the wiring RWL is V th_H and V th_L The potential V between 0 Tosu By this, the potential applied to the gate electrode of the transistor 21 can be determined. For example, In the write operation, if a high-level potential is applied to the gate electrode of the transistor 21, In this case, the potential of the wiring RWL is V 0 (>V th_H ), transistor 21 is "on" When a low-level potential is applied, the potential of the wiring RWL becomes V 0 (< Vth_L ), the transistor 21 remains in the "off state." By determining the potential of the line RBL, the stored data can be read out.

[0049] When the memory circuits 25 are arranged in an array, the data of the desired memory circuit 25 is In this way, if the data is not read, the capacitance element The potential at which transistor 21 is in the "off state" regardless of the amount of charge held in 23 , that is, V th_H Alternatively, a smaller potential may be applied to the wiring RWL. When the charge stored in the capacitance element 23 exceeds the threshold voltage, the transistor 21 is turned on regardless of the charge stored in the capacitance element 23. The potential at which the potential becomes the "on-state", that is, V th_L If a larger potential is applied to the wiring RWL, good.

[0050] FIG. 2(A) shows an example of a two-transistor gain cell structure. The memory cell structure is as follows: For example, the memory circuit 26 shown in FIG. The storage circuit 27 can be applied to a memory cell.

[0051] The memory circuit 26 shown in FIG. 2B is an example of a three-transistor gain cell structure. In the memory circuit 26, the transistor 24 functions as a read transistor, and the wiring R The gate of the capacitance element 23 is electrically connected to the node FN. The first terminal is electrically connected to the line CNL. 25. When reading data, the wiring CNL The potential of the node FN can be increased by controlling the potential of the node FN.

[0052] The memory circuit 27 shown in FIG. 2C differs from the memory circuit 25 in that the transistor 21 is not provided. The memory circuit 27 can be driven in the same manner as the memory circuit 25. The data read operation of 27 will be described. When the transistor 22 is turned on, The wiring WBL in this state is electrically connected to the capacitance element 23, and the wiring capacitance associated with the wiring WBL and the capacitance element The charge is redistributed between the electrodes 23. As a result, the potential of the wiring WBL changes. The amount of change in the potential is determined by the amount of charge stored in the capacitance element 23 (or the amount of charge stored in the first terminal of the capacitance element 23). It takes different values ​​depending on the potential.

[0053] For example, the potential of the first terminal (node ​​FN) of the capacitance element 23 is V, and the capacitance of the capacitance element 23 is C , the wiring capacitance associated with the wiring WBL is CB, and the potential of the wiring WBL before the charge is redistributed is V B0, the potential of the wiring RWL is 0 [V], and the other electrode of the wiring capacitance associated with the wiring WBL is If the potential is 0 [V], the potential of the wiring WBL after the charge is redistributed is (CB × VB0 +C×V) / (CB+C). Therefore, the state of the memory circuit 27 is If the potential V of the first terminal has two states, V1 and V0 (V1>V0), the potential V1 is maintained. When the potential of the wiring WBL is When the potential V0 is maintained, the potential of the wiring WBL is (=(CB×VB0+C×V0) / (C Therefore, the potential of the wiring WBL is compared with a predetermined potential. This allows the data to be read out.

[0054] An example of the device structure of the memory circuit 25 shown in FIG. 1 shows a cross section of the transistors 21 and 22 of a memory circuit 25 in the channel length direction. In the actual memory circuit 25, the channels of the transistors 21 and 22 The longitudinal directions do not have to coincide with each other. This also applies to other drawings.

[0055] The memory circuit 25 shown in FIG. 1, the transistor 21 and the transistor 22 on the capacitor 23. The transistor 21 has a conductive film 32 on a substrate 31 and an insulating film 3 3, a semiconductor film 34a on the insulating film 33, a semiconductor film 34b on the semiconductor film 34a, and a semiconductor A conductive film 35 electrically connected to the semiconductor film 34b and a conductive film 35 electrically connected to the semiconductor film 34b. The conductive film 36, the conductive film 35, the semiconductor film 34b, and the semiconductor film 34c on the conductive film 36, The insulating film 37 is disposed on the film 34c, and the conductive film 38 is disposed on the insulating film 37.

[0056] In the transistor 21, the conductive film 32 functions as a backgate electrode. The insulating film 33 functions as an undercoat film for the semiconductor film 34 and as a gate insulating film. The conductive films 35 and 36 also function as a source electrode and a drain electrode. The insulating film 37 functions as a gate insulating film. It functions as a gate electrode.

[0057] The transistor 22 includes a conductive film 42, an insulating film 43 on the conductive film 42, and a semiconductor layer on the insulating film 43. The conductor film 44a, the semiconductor film 44b on the semiconductor film 44a, and the semiconductor film 44b are electrically connected to each other. a conductive film 45 electrically connected to the semiconductor film 44b; A semiconductor film 44b and a semiconductor film 44c on the conductive film 46, and an insulating film 47 on the semiconductor film 44c. and a conductive film 48 on the insulating film 47.

[0058] In the transistor 22, the conductive film 42 functions as a backgate electrode. The insulating film 43 functions as an undercoat film for the semiconductor film 44 and as a gate insulating film. The conductive films 45 and 46 also function as a source electrode and a drain electrode. The insulating film 47 functions as a gate insulating film. The transistor 21 and the transistor 22 function as a gate electrode. Although the structure in which 22 has a back gate electrode is illustrated, the present invention is not limited to this, and the back gate may be used. A configuration without the electrode may also be used.

[0059] As shown in FIG. 2D, the transistor 21, the capacitor 23, and the transistor 22 By arranging at least a part of the components in an overlapping manner, a circuit system with a small circuit area can be obtained. It is possible.

[0060] Next, an example of a semiconductor device including a plurality of memory circuits 25 shown in FIG. This will be explained with reference to FIG.

[0061] <Example of memory cell array configuration> FIG. 3A is a schematic diagram showing an example of a memory cell array. In the cell array 300, the subarrays SCA are arranged in a horizontal direction and b vertical direction (a and b are independent of each other) in a plane. Each sub-array SCA is arranged in an array of c (where c is a natural number) stacked. In this manner, the memory cell array 300 is made up of memory cells MC. It has a structure in which MCs are arranged three-dimensionally.

[0062] In the specification and drawings, in order to distinguish between the same elements (signals, wiring, elements, circuits, etc.), " In some cases, identifiers such as "[L1]" or "[L1]" may be added to terms to indicate row numbers, column numbers, or order. For example, “MC_j” is the jth (j is a natural number from 1 to c) ) memory cell MC.

[0063] The memory cells MC can have a circuit configuration similar to that of the memory circuits 25-27 (FIG. 2). FIG. 3B shows an example of a circuit diagram of the memory cell MC_j. MC_j includes a transistor Ta_j, a transistor Tb_j, and a capacitance element Ca_j. The memory cell MC_j shown in FIG. 3B is a modification of the memory circuit 25 shown in FIG. Here, the symbol "Ta_j" indicates that the transistor Ta is a constituent element of the memory cell MC_j. In other drawings, such symbols may be used.

[0064] A first terminal of the transistor Ta_j is electrically connected to the wiring BL, and a second terminal of the transistor Ta_j is The gate electrode of the transistor Ta_j is electrically connected to the gate electrode of the transistor Tb_j. The first terminal of the transistor Tb_j is electrically connected to the wiring WWL_j. The first terminal is electrically connected to the line SL. a first terminal (first electrode) of the transistor Tb_j is electrically connected to a gate electrode of the transistor Tb_j, The second terminal (second electrode) is electrically connected to the wiring RWL_j.

[0065] The transistor Ta_j has a back gate electrode (BG). For example, The transistor can be driven at a lower or higher potential than the source electrode. The threshold voltage of the Ta_j can be shifted in the positive or negative direction. By shifting the threshold voltage of the n-channel transistor in the positive direction, the gate voltage Normally-off is realized, in which the transistor is non-conductive (off state) even when the potential is 0V. In addition, the potential applied to the back gate electrode may be variable. In the case where the potential applied to the back gate electrode is made variable, the potential is controlled. A circuit for controlling the back gate electrode may be connected to the back gate electrode. The back gate electrode and the gate electrode of the transistor Ta_j may be connected to each other. By applying the same potential, the on-current increases, the initial characteristic variations are reduced, and -GBT( -Gate Bias-Temperature) Stress test deterioration suppression and different This makes it possible to suppress the fluctuation in the on-state current rise voltage at the drain voltage. By increasing the on-current of the transistor Ta_j, for example, the write operation of the memory cell array 300 can be performed. This can reduce the loading time.

[0066] Although not shown in FIG. 3B, the transistor Tb_j also has a back gate electrode. By providing a back gate electrode, the on-current of the transistor Tb_j can be increased. The increase in the on-current can reduce, for example, the read-out time of the memory cell array 300. The ejection speed can be increased.

[0067] Here, the voltage of the node FN is controlled by controlling the word signal given to the wiring WWL_j. The potential of the memory cell MC_j is set to a potential corresponding to the potential of the wiring BL. In addition, by controlling the read signal given to the wiring RWL_j, the wiring BL The potential of the node FN is set to a potential corresponding to the potential of the node FN. It means to read it out.

[0068] A potential corresponding to binary or multi-valued data is applied to the wiring BL. is k-bit (k is a natural number greater than or equal to 2) data. Specifically, it is 2-bit data. If there is, it is four-value data, and the signal input to the wiring BL has four types of potential levels. A read signal is applied to the wiring RWL_j. A signal for controlling the potential of node FN to selectively read data from the channel MC_j is A word signal is applied to the wire WWL_j. This is a signal that turns on the transistor Ta_j in order to provide the potential of L to the node FN. do.

[0069] The node FN is connected to a first electrode of the capacitor Ca_j, a second terminal of the transistor Ta_j, and It corresponds to any node on the wiring that connects the gate electrode of the transistor Tb_j. For example, For example, the node FN may be equipped with a liquid crystal element or an organic EL (Electroluminescence) element. In the case where the display element is provided, the memory cell M A portion of C_j can function as pixels of a display device.

[0070] The potential of the node FN is based on the data applied to the wiring BL. , the transistor Ta_j is turned off to be in an electrically floating state, and the capacitance The element Ca_j capacitively couples the wiring RWL_j and the transistor Tb_j. Therefore, the potential of the node FN can be changed by changing the potential of the wiring RWL_j. When the potential of the read signal applied to the wiring RWL_j is changed, The potential becomes the original potential plus the change in the potential of the read signal.

[0071] The transistor Ta_j switches between a conductive state and a non-conductive state to write data. The transistor Ta_j has a function as a switch that controls the input of the transistor Ta_j. By maintaining the state, the potential based on the written data is maintained. It is assumed that the transistor Ta_j is an n-channel transistor.

[0072] In addition, in the non-conducting state, the transistor Ta_j has a potential between the source electrode and the drain electrode. It is preferable to use a transistor having a low off-state current. The off-state current is low when the voltage between the source and drain electrodes is 10 V at room temperature. This means that the normalized off-state current per 1 μm of channel width is 10 zA or less. As a transistor with such a low off-state current, Examples include transistors.

[0073] By using a transistor with a small off-state current for the transistor Ta_j, Therefore, the potential of the node FN, which is in a floating state, can be maintained for a long period of time. Therefore, the refresh frequency of the memory cell MC_j can be reduced, and the power consumption Therefore, a semiconductor device with less noise can be realized.

[0074] For example, if the potential held at node FN is 3.15×10 for 10 years at 85°C, 8 seconds ) in order to hold the transistor Ta_j, the normalized off-state current per 1 fF of capacitance is The current value is 4.3yA (1yA is 1×10 -24 A) is preferably less than In this case, it is preferable that the allowable fluctuation in potential of the node FN is within 0.5 V. Alternatively, it is preferable that the normalized off-state current is less than 1.5 yA at 95°C. It is.

[0075] In the configuration of the memory cell MC_j shown in FIG. 3B, the transistor Ta_j is in a non-conducting state. By maintaining the potential of node FN, the charge at node FN is maintained. The transistor Ta_j is a switch that can suppress the fluctuation of potential caused by the movement of the It is particularly preferable that the transistor have a small off-state current.

[0076] Therefore, by using a transistor Ta_j with a small off-state current, The cell array 300 can be a non-volatile memory. The data written to C_j remains in the transistor until the transistor Ta_j is turned on again. The FN can continue to hold the

[0077] The transistor Tb_j has a source electrode and a drain electrode connected in series according to the potential of the node FN. In the configuration of the memory cell MC_j shown in FIG. The current Id flowing between the source electrode and the drain electrode of the transistor Tb_j is The current flowing between the line SL and the transistor Tb_j is, for example, a silicon active layer. The transistors used in the above (hereinafter referred to as Si transistors) may be used. An OS transistor using a conductor as an active layer may be used. j is an OS transistor and an n-channel transistor.

[0078] The transistors Ta_j and Tb_j have, for example, a switching speed of Fast n-channel transistors can be used. For example, the transistor switch The switching speed is 0.1 ns or more and less than 5 ns. By using an OS transistor containing an oxide (preferably containing In, Ga, and Zn), The above switching speed can be achieved by using the transistor switch. The switching speed refers to the time it takes for a transistor to go from a non-conducting state to a conducting state. The switching speed of a transistor is the current that is generated when the transistor is used as an amplifier. It may be expressed as the speed corresponding to the maximum frequency (cutoff frequency) at which the flow gain is 1 or more.

[0079] <Memory cell array circuit configuration example 1> Here, the memory cells MC_j shown in FIG. 3B are arranged three-dimensionally to form a memory cell array FIG. 4 shows an example of a memory cell array 300. FIG. 4 is a circuit diagram showing an example of a subarray SCA. The array SCA has c memory cells MC, and each memory cell MC is connected to a wiring BL and and wiring SL are shared.

[0080] <Example of memory cell array operation> Next, the operation of the memory cell array 300 shown in FIG. 5 is a timing chart illustrating an example of the operation of the rechargeable battery array 300. The diagram shows the wiring WWL_c, the wiring RWL_c, the node FN, the wiring BL, and the wiring SL. , which shows the changes in each signal applied to

[0081] First, the write operation will be described with reference to FIG. 5(A). Here, the write operation of binary data is described. However, the memory cell array 300 is not limited to writing binary data. In addition, multi-value data can be written. , a writing period T1, a quiescent period T2, and a non-selection period T3 are shown.

[0082] In the writing period T1, first, a potential V2 is applied to the wiring WWL_c. L has a potential according to the binary data, that is, a high (H) level potential or a low (L) level potential. A potential of the same level as that of the wiring BL is applied to the wiring SL. When BL is at H level, the line SL is also given a H level potential. At this time, the line SL is also supplied with an L level potential.

[0083] In the idle period T2, the wiring BL and the wiring SL are applied with a L-level potential, and the wiring RWL_ A potential V0 is applied to the wiring WWL_c and the wiring WWL_c. Here, the potential V0 is, for example, the ground potential. The potential V2 should be a positive potential. The absolute value of the potential V2 is greater than the potential of the H level. It is preferable that the potential is large, for example, the potential of the H level plus the threshold voltage of the transistor Ta_c. and less than the H-level potential plus three times the threshold voltage of the transistor Ta_c. Just do that.

[0084] In the non-selection period T3, a potential V1 is applied to the wiring RWL_c and the wiring WWL_c. The potential V1 may be, for example, a negative potential. The absolute value of the potential V1 is greater than the potential of the H level. For example, it is preferable that the potential is higher than the H level potential plus the threshold voltage of the transistor Tb_c. If it is large and less than three times the H level potential plus the threshold voltage of the transistor Tb_c, In addition, an L-level potential is applied to the wirings BL and SL.

[0085] Next, the read operation will be described with reference to FIG. The timing chart shows a period T4 in which the potential of the wiring BL is precharged, a period T5 in which the potential of the wiring BL is precharged, and a period T6 in which the potential of the wiring BL is precharged. 13, there are shown a period T5 during which the wiring BL is discharged for this purpose, and a period T6 during which the wiring BL is not selected.

[0086] In the period T4 shown in FIG. 5B, the wiring BL is precharged. At this time, the wiring WWL A potential V1 is applied to the wiring RWL_c. , V1 is a lower potential than V0. For example, V0 is the ground potential and V1 is a negative potential. In addition, a potential corresponding to the data is held at the node FN. The line BL is applied with an H-level potential (VH). The wiring SL is applied with an L-level potential. Here, it is preferable that the absolute value of the potential V1 is greater than the potential of the H level. For example, the potential of the H level plus the threshold voltage of the transistor Tb_c is greater than the potential of the H level. The potential should be less than three times the potential of the bell plus the threshold voltage of transistor Tb_c.

[0087] In the period T4, the wiring BL is supplied with an H-level potential VH and then is placed in an electrically floating state. That is, the wiring BL is in a state where a potential fluctuation occurs due to charging or discharging of electric charges. This floating state can be achieved by turning off the switch that applies a potential to the wiring BL.

[0088] Next, in a period T5 shown in FIG. 5B, the potential of the node FN is set to At this time, the line WWL_c is discharged at the potential V The line SL is supplied with a potential of L level as in the previous period. Since the potential V0 is applied to RWL_c, the potential of the node FN rises. The conduction state of the transistor Tb_c changes depending on the potential of FN. When the potential of the wiring BL When a low-level potential is written to the node FN, the potential of the node FN drops to the potential VL. Since the transistor Tb_c is off, the potential of the wiring BL is maintained at the H level. It will be held.

[0089] Next, in a period T6 shown in FIG. 5B, the potential of the wiring RWL_c is set to V1. This puts memory cell MC_c into a non-selected state. This enables the operation of reading data from memory cell MC_c. The work is completed.

[0090] <Memory cell array circuit configuration examples 2 and 3> Another circuit configuration example of the memory cell array 300 is shown in FIG. 6 and FIG. 7. 1 is a circuit diagram showing an example of a memory cell array 300, and is a circuit diagram of a sub-array SCA.

[0091] The circuit configuration example of FIG. 6 is a modification of FIG. 4. The difference from the example of FIG. 4 is that the odd-numbered memory cells The even-numbered memory cells MC and the even-numbered memory cells MC are electrically connected to different wirings SL. The odd-numbered memory cells MC and the even-numbered memory cells MC are alternately connected to the line BL. Therefore, the integration density of the sub-array SCA can be increased. In the sub-array SCA shown in FIG. 7, c Each memory cell MC shares one wiring SL. It can be made easier.

[0092] <Memory cell stack structure example 1> FIG. 8 is a cross-sectional view showing an example of a memory cell array. The example of FIG. 8 has the circuit configuration of FIG. This corresponds to an example in which a memory cell array is configured with sub-arrays SCA each having a plurality of sub-arrays.

[0093] Figure 8 shows three adjacent subarrays (SCA[α-1], SCA[α], and SCA[α The subarrays SCA are adjacent to each other when the x In the y-plane, one of the x and y coordinates differs by 1, while the other is the same. For example, , the y-coordinates of the three subarrays (SCA[α-1], SCA[α], SCA[α+1]) are If they are equal, then if the x-coordinate of the subarray SCA[α] is k (k is an integer between 2 and a), , the x-coordinate of the subarray SCA[α-1] is k-1, and the x-coordinate of the subarray SCA[α+1] is k-1. The x coordinate is k+1.

[0094] Figure 8 shows the memo of the subarrays (SCA[α-1], SCA[α], SCA[α+1]). The memory cells MC_1 and MC_2 are shown. A memory cell MC_3 is stacked on top of the memory cell MC_2, and the memory cells By increasing the number of stacked memory cells MC, the circuit area is increased. This allows the integration density of the memory cell array 300 to be increased without increasing the number of memory cells.

[0095] The device structure of the memory cell array 300 shown in FIG. In order to clarify the drawings, only some of the elements (transistors) constituting the memory cell array 300 are illustrated. The identification symbol "_1" is not attached to the symbols of the parts (e.g. Ta, etc.). The structure of the memory cell array 300 may be described with or without a suffix such as 1”. The same applies to the other drawings.

[0096] In each memory cell MC, the transistor Ta and the transistor Tb are made of an oxide semiconductor material. A capacitance element Ca is provided on the transistor Tb. An insulating film 216 is provided between the gate Tb and the capacitance element Ca. It is preferable that a part of the insulating film 115 overlaps with the transistor Tb. The conductive film 204a is sandwiched between the conductive film 151 and the conductive film 155 to form a capacitance element Ca. The conductive film 204b serves as a source electrode or a drain electrode of the transistor Tb. The conductive film 151 is connected to the gate electrode 20 of the transistor Tb via the plug 141. 3 and electrically connected to each other.

[0097] The transistor Ta is provided on the capacitance element Ca. An insulating film 156 is provided between the transistors Ta. At least a part of the transistor Ta is It is preferable that the conductive film 104a is provided so as to overlap with the capacitor element Ca. b functions as a source electrode or a drain electrode of the transistor Ta, respectively.

[0098] The conductive films 204a and 204b are electrically connected to a wiring SL (not shown). 04a is connected to the conductive film 104a via the plug 142, the conductive film 153, the plug 145, etc. The conductive film 204a and the conductive film 104a are electrically connected to the wiring BL (not shown). The plug 142, the conductive film 153, the plug 145, etc. are electrically connected to the wiring BL. It may also function as such.

[0099] Two adjacent memory cells MC_j share the plug 142, the conductive film 153, etc. Specifically, the memory cell MC_j of the subarray SCA[α] is the same as the memory cell MC_j of the subarray SCA[α-1 ] and the memory cell MC_j share the plug 142, the plug 145, and the conductive film 153. By sharing plugs and conductive layers between two adjacent sub-arrays SCA, The density of the array 300 can be increased.

[0100] In addition, the conductive film 104a and the conductive film 204b are shared by the adjacent MC_j. Specifically, the truncation of each of the subarrays SCA[α-1] and SCA[α] is The transistor Ta shares the conductive film 104a. Each transistor Tb of CA[α+1] shares the conductive film 204a. By sharing the conductive film, the integration density of the memory cell array 300 can be increased.

[0101] <Memory cell stack structure example 2> 9 and 10 show a modification of the memory cell array 300 shown in FIG. The memory cell array 300 shown in FIG. The layer 291 includes a transistor. The layer 92 and the layer 293 include a conductive film. The layer 294 includes a transistor. The layers 295 and 296 include conductive films, and the layer 297 includes a transistor.

[0102] In the sub-array SCA of the memory cell array 300 shown in FIG. The order is element Ca, transistor Ta, transistor Tb, capacitance element Ca, and transistor Ta. In contrast, in the sub-array SCA shown in FIG. By arranging the transistor Tb, the capacitance element Ca, the transistor Ta, and the capacitance The element Ca and the transistor Tb are stacked in this order. This simplifies the process. .

[0103] In the memory cell MC, a capacitance element Ca is provided on the transistor Tb. The transistor Ta is provided on the capacitance element Ca. The capacitance element Ca overlaps with the transistor Tb. It is preferable that the second insulating layer 10 has a region overlapping with the transistor Ta. A part of the capacitance element Ca has an area overlapping with the transistor Tb of the adjacent memory cell MC. By using the device structure shown in FIG. The degree of integration can be increased.

[0104] Specifically, in the subarray SCA[α], the memory cell MC_2 and the memory cell MC _3 has a symmetrical structure. Therefore, the capacitance element Ca is connected to the transistor Ta and The transistor Tb overlaps the transistor Tb. By using this structure, the sub-array SCA In the above, the memory cells MC can be arranged in a staggered manner, and the A capacitance element can be formed on the transistor Ta, which increases the degree of integration. 8, the process can be simplified.

[0105] In the subarray SCA[α], c memory cells MC are arranged in a staggered manner. As a result, in the two memory cells MC adjacent to each other on the top and bottom, the transistors Ta and In this way, the active region of the vertically adjacent memory cells is The transistors constituting the memory cell array 300 are formed in the same layer. Since the number of memory cells is reduced, the memory cell array 300 can be manufactured in fewer steps. By reducing the number of steps required for production, the yield can be increased. As the number of layers increases, the film stress of, for example, an insulating film, a conductive film, a semiconductor film, etc. Therefore, it is important to reduce the number of layers to be laminated. This makes it possible to reduce failures of the semiconductor device due to film peeling or the like.

[0106] <Memory cell stacking structure example 3> An example of a memory cell array is shown in Fig. 11. The memory cell array 300 shown in Fig. 8 and 9. FIG.

[0107] In the memory cell array 300 shown in FIG. 11, the memory cells MC are arranged in a staggered manner. 9 in the following respects. A capacitance element Ca is located, and a transistor Tb is located on the capacitance element Ca. In the several memory cells MC (MC_1 and MC_3 in FIG. 11), the transistors Tb The gate electrode 203 of the even-numbered memory cell M is electrically connected to the capacitance element Ca. In C (memory cell MC_2 and memory cell MC_4 in FIG. 11), the conductive film 205 is The conductive film 205 is electrically connected to the capacitance element Ca. It functions as a gate electrode.

[0108] That is, in the example of FIG. 11, there are memory cells MC_j, where j is an odd number, and memory cells MC_ In the example of FIG. 11, the transistors Ta and Tb are the same. The semiconductor film of the transistor Ta and the semiconductor film of the transistor Tb do not need to be formed in a single layer. The semiconductor film having the transistor T The semiconductor films of the transistors a and Tb are made of oxides with different constituent elements and atomic ratios. It is easy to form the semiconductor film.

[0109] The above is a description of the configuration example of the memory cell array 300. The structures of the transistors Ta and Tb included in the semiconductor device 300 will be described.

[0110] <Transistor configuration example 1> FIG. 12B is a top view illustrating an example of a structure of a transistor. FIG. 12(B) is a cross-sectional view taken along line AB in FIG. 12(B), and FIG. 12(C) is a cross-sectional view taken along line CD in FIG. 12(B). The transistor TR1 shown in FIG. 12 is an OS transistor. The transistor TR1 is an example of a transistor equivalent to the transistor Ta. It can also be applied to Tb.

[0111] The transistor TR1 includes a semiconductor film 101, a conductive film 104a, a conductive film 104b, and a gate insulating film. It has an insulating film 102 , a gate electrode 103 , a conductive film 105 , and an insulating film 114 .

[0112] The semiconductor film 101 is made up of a semiconductor film 101a in contact with the upper surface of the insulating film 114, a semiconductor film 101a a semiconductor film 101b in contact with the upper surface of the semiconductor film 101; In the example of FIG. 12A, the semiconductor film 101 includes a semiconductor film 101a, a semiconductor film 101b, and a semiconductor film 101c. The semiconductor film 101 has a laminated structure of the above-mentioned laminated film 101b and the semiconductor film 101c. The gate electrode 103, the gate insulating film 102, and the gate insulating film 103 may be formed as a single layer. The ends of the gate insulating film 102 and the semiconductor film 101c are approximately aligned. In the etching process for forming the film 101c, the gate electrode 103 functions as a mask. Because.

[0113] The conductive film 104a and the conductive film 104b serve as a source electrode and a drain electrode, respectively. The conductive film 104a and the conductive film 104b are in contact with the upper surface of the semiconductor film 101b. The semiconductor film 101c is formed by stacking the semiconductor film 101b and the conductive film 104. The gate electrode 103 is in contact with the upper surfaces of the gate insulating film 10a and the conductive film 104b. The conductive film 105 faces the semiconductor film 101 via the insulating film 114. 1. The conductive film 105 functions as a backgate electrode of the transistor TR1.

[0114] In other words, the semiconductor film 101a is provided between the insulating film 114 and the semiconductor film 101b. The semiconductor film 101c is provided between the semiconductor film 101b and the gate insulating film 102. The conductive film 104a and the conductive film 104b are in contact with the upper surface of the semiconductor film 101b. The side surface of the semiconductor film 101b is in contact with the bottom surface of the semiconductor film 101c. and contacts the conductive film 104b.

[0115] Note that the conductive film 105 may not be provided. The conductive film 105 may be electrically connected to the gate electrode 103. When the gate electrode 103 is electrically connected and the same potential is applied, the on-current increases. Addition, reduction of initial characteristic variation, -GBT(-Gate Bias-Temperatur e) Suppression of degradation during stress testing and rise of on-current at different drain voltages It is possible to suppress the voltage fluctuation by increasing the on-current of the transistor TR1. For example, the read speed of the memory cell array 300 can be increased.

[0116] In addition, the semiconductor film 101b is electrically surrounded by the electric field of the gate electrode 103. (The electric field of the conductive film electrically surrounds the semiconductor film, forming a transistor structure called s This is called a surrounded channel (s-channel) structure. The transistor TR1 is an s-channel device. In some cases, a channel may form throughout the bulk. In the s-channel structure, A large current can be passed between the source and drain electrodes of the transistor, and the current when it is conductive (ON The current) can be increased.

[0117] The above-mentioned s-channel structure provides a high on-current, making it suitable for miniaturized OS transistors. In addition, the OS transistor can be miniaturized, so the OS A semiconductor device having a transistor is a highly integrated and highly dense semiconductor device. For example, the OS transistor has a channel length of 1 nm or more and less than 100 nm. More preferably, the channel length has a region of 5 nm or more and 60 nm or less.

[0118] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part through which current flows when the transistor is on). The source (source region or source electrode) in the region where the channel is formed This refers to the distance between the transistor and the drain (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the above, the channel length is any one value, maximum value, or maximum in the region where the channel is formed. The minimum or average value.

[0119] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on state). The area where the gate electrode overlaps with the electrode (the part of the body through which current flows) forms a channel. In the region, the source (source region or source electrode) and the drain (drain region or This refers to the length of the part where the drain electrode faces the gate electrode. In this case, the channel width does not necessarily have the same value in all regions. The channel width of the data may not be fixed to a single value. The width of the channel is a value, a maximum value, a minimum value, or an average value in the region where the channel is formed. The average value.

[0120] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The channel width becomes larger than the apparent width shown in the figure, and the effect becomes non-negligible. For example, in a transistor with a fine and three-dimensional structure, The percentage of the channel region formed on the side of the semiconductor compared to the percentage of the channel region formed on the inside of the semiconductor. In that case, the apparent channel width shown in the top view may be In this case, the effective channel width where the channel is actually formed is larger than the actual channel width.

[0121] In addition, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If it is not known precisely, it is difficult to measure the effective channel width accurately.

[0122] Therefore, in this specification and the like, in a top view of a transistor, a semiconductor and a gate electrode overlap each other. The source (source region or source electrode) and the drain (drain region or The apparent channel width, which is the length of the part where the gate electrode (gate or drain electrode) faces the gate electrode, is called the " Surrounded Channel Width (SCW) In addition, in this specification, when the term "channel width" is used, it is sometimes referred to as the "enclosure In this specification, the term "channel width" may refer to the apparent channel width. When simply referred to as channel width, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosed channel width The values ​​are determined by obtaining cross-sectional TEM images and analyzing the images. It is possible.

[0123] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0124] Hereinafter, each component of the transistor TR1 shown in FIG. 12 will be described in detail.

[0125] <Insulating film that functions as a base film> The insulating film 114 preferably contains an oxide. In particular, the insulating film 114 preferably contains an oxide that releases oxygen by heating. In addition, the semiconductor film 101 is preferably provided over the insulating film 114. is preferred.

[0126] As an oxide material that releases oxygen by heating, It is preferable to use an oxide containing more oxygen than the stoichiometric composition. Oxide films containing oxygen were analyzed by thermal desorption spectroscopy (TDS). The amount of oxygen released, calculated as oxygen atoms, was 1 .0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3The oxide film is one in which the surface temperature of the film during the TDS analysis is 1 The range of 00°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower, is preferred.

[0127] As an oxide material that releases oxygen by heating, for example, silicon oxide or silicon oxynitride is used. It is preferable to use a material containing silicon, or a metal oxide can be used. Metal oxides include aluminum oxide, aluminum oxynitride, gallium oxide, and oxynitride. Gallium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride In this specification, silicon oxynitride refers to a compound thereof. Silicon oxide nitride is a material that has a higher oxygen content than nitrogen as a composition. This refers to a material that contains more nitrogen than oxygen.

[0128] When an oxide semiconductor is used for the semiconductor film 101, oxygen released from the insulating film 114 is converted into oxygen. This allows oxygen vacancies in the oxide semiconductor to be reduced. As a result, the fluctuation of the electrical characteristics of the transistor TR1 can be suppressed, and the reliability can be improved.

[0129] The upper surface of the insulating film 114 is planarized by, for example, CMP (Chemical Mechanical Polishing). The surface is flattened by a flattening process such as mechanical polishing. It is preferable.

[0130] <Semiconductor film> The semiconductor film 101 preferably contains a semiconductor having a band gap larger than that of silicon. Preferably, the semiconductor film 101 is made of an oxide semiconductor. By using semiconductor materials with a wide band gap and low carrier density, It is preferable to use such a material for the semiconductor film 101 because it can reduce the current in the OFF state. By using such a material, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor can be realized.

[0131] More specifically, it is preferable to use an oxide semiconductor film as the semiconductor film 101. For example, the semiconductor film 101b may have a composition of In:Ga:Zn=1:1:1, 2:1:3, 3:1:2 In the case of using an In-Ga-Zn oxide having an atomic ratio of 4:2:3, the semiconductor film 101 a or the semiconductor film 101c is In:Ga:Zn=1:3:2, 1:3:4, 1:3 1:6, 1:6:4, 1:6:8, 1:6:10, 1:9:6, or 1:2:3 The semiconductor film 101b may be an In-Ga-Zn oxide having a molecular weight ratio of 1000 to 10000. The atomic ratios of the solid film 101a and the semiconductor film 101c are each calculated by subtracting the above atomic ratios from the atomic ratios as an error. The semiconductor film 101a and the semiconductor film 101c are Materials having the same composition may be used, or materials having different compositions may be used.

[0132] In addition, when an In-M-Zn oxide is used as the semiconductor film 101b, the semiconductor film 101b The target used for forming the semiconductor film is a metal element contained in the target. The atomic ratio of In:M:Zn=x 1 :y 1 :z 1 When x 1 / y 1 The value is 1 / 3 z is equal to or greater than 6, preferably equal to or greater than 1 and equal to or less than 6; 1 / y 1 is 1 / 3 or more and 6 or less, preferably It is preferable to use an oxide having an atomic ratio of 1 to 6. 1 / y 1 6 or less This makes it easier to form a CAAC-OS film, which will be described later. Representative examples of atomic ratios are In:M:Zn=1:1:1, 2:1:3, 3:1:2, etc. There are some.

[0133] In addition, when In-M-Zn oxide is used as the semiconductor film 101a and the semiconductor film 101c, The target used for forming the semiconductor film that becomes the semiconductor film 101a and the semiconductor film 101c is The atomic ratio of the metal elements contained in the target is In:M:Zn=x 2 :y 2 :z 2 When x 2 / y 2 <x 1 / y 1 and z 2 / y 2 The value is 1 / 3 or more and 6 or less, It is preferable to use an oxide having an atomic ratio of 1 to 6. 2 / y 2 of By setting the concentration to 6 or less, it becomes easier to form a CAAC-OS film, which will be described later. Representative examples of atomic ratios of group elements are In:M:Zn=1:3:4, 1:3:6, 1:3 :8, etc.

[0134] The semiconductor film 101c is preferably formed of a gallium oxide film. The semiconductor film 101c has a blocking function to prevent diffusion of gallium. By forming the gate insulating film 102 from the semiconductor film 101a and the semiconductor film 101b, This can prevent indium diffusion, thereby reducing the off-current of the transistor TR1. Cut.

[0135] When forming an oxide semiconductor film by sputtering, the atomic ratio of the target may deviate from the target atomic ratio. In particular, zinc has a higher atomic ratio in the film than the atomic ratio in the target. The ratio of the number of atoms of zinc contained in the target may become smaller. It may be between 0 atomic% and 90 atomic%.

[0136] <Conductive film functioning as source electrode and drain electrode> The conductive film 104a and the conductive film 104b are made of aluminum, titanium, chromium, nickel, copper, Gold, such as yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals or alloys mainly composed of these metals are used in a single layer structure or a multilayer structure. A single-layer structure of aluminum film containing silicon, and a two-layer structure of aluminum film laminated on titanium film Two-layer structure with aluminum film laminated on tungsten film, copper-magnesium-aluminum Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film, A two-layer structure in which a copper film is laminated on a stainless steel film, a titanium film or titanium nitride film, and the titanium film Alternatively, an aluminum film or a copper film is laminated on the titanium nitride film, and then a titanium film is laminated on the aluminum film or a copper film. a three-layer structure in which a titanium nitride film or a molybdenum film is formed; An aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There are three-layer structures in which a molybdenum film or a molybdenum nitride film is further formed on top of the above. A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0137] <Gate insulating film> The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminate or a single layer.

[0138] The gate insulating film 102 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), hafnium aluminium doped with nitrogen Luminate (HfAl x O y N z ), using high-k materials such as yttrium oxide Good too.

[0139] The gate insulating film 102 may be made of aluminum oxide, magnesium oxide, or silicon oxide. Silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, silicon oxide oxides such as lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide Insulating film, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride The insulating film can be formed using a nitride insulating film such as those mentioned above, or a film made of a mixture of the above materials.

[0140] The gate insulating film 102 is made of an oxide having a stoichiometric composition similar to the insulating film 114. It is preferable to use an oxide insulating film containing more oxygen than silicon.

[0141] In addition, when a specific material is used for the gate insulating film, electrons are captured in the gate insulating film under specific conditions. For example, silicon oxide and hafnium oxide can be used to increase the threshold voltage. For example, hafnium oxide, aluminum oxide, and oxide are mixed in the gate insulating film. By using a material with many electron capture levels, such as tantalum, and by using a material that can withstand higher temperatures (the operating temperature of semiconductor devices), Or higher than the storage temperature, or 125°C to 450°C, typically 1 At a temperature of 50°C or higher and 300°C or lower, the potential of the gate electrode is set to the potential of the source electrode or drain electrode. By maintaining the higher temperature for at least one second, typically at least one minute, the gate voltage is released from the semiconductor layer. Electrons move toward the pole, some of which are captured by the electron capture level.

[0142] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The process of adding the conductive layer may be performed during the manufacturing process of a transistor.

[0143] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not to be allowed for more than 1 hour.

[0144] <Gate electrode> The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It is made of an alloy of metals. In addition, either manganese or zirconium Alternatively, a metal selected from one or more of the above may be used. Semiconductors such as polycrystalline silicon and silicides such as nickel silicide are used. The gate electrode 103 may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, or a titanium film stacked on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; A two-layer structure in which a tantalum nitride film is laminated on a tungsten nitride film, and a tungsten nitride film is laminated on a tantalum nitride film or a tungsten nitride film. A two-layer structure in which a titanium film is laminated on top of the titanium film, and an aluminum film is laminated on top of the titanium film. There are three-layer structures in which a titanium film is formed on top of the aluminum. One selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film made of a combination of a plurality of metals, or a nitride film may be used.

[0145] The gate electrode 103 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0146] In addition, an In-Ga-Zn oxynitride semiconductor film is formed between the gate electrode 103 and the gate insulating film. , In-Sn oxynitride semiconductor film, In-Ga oxynitride semiconductor film, In-Zn oxynitride semiconductor film Semiconductor film, Sn oxide nitride semiconductor film, In oxide nitride semiconductor film, metal nitride film (InN, These films have a specification of 5 eV or more, preferably 5.5 eV or more. Since the electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor, The threshold voltage of the transistor can be shifted to the positive side, resulting in a so-called normally-off transistor. For example, an In-Ga-Zn oxynitride semiconductor film can be used to realize a switching element with the following characteristics: When used, the nitrogen concentration is at least higher than that of the semiconductor film 101, specifically, 7 atomic % or more of I An n-Ga-Zn oxynitride semiconductor film is used.

[0147] <Conductive film functioning as a back gate electrode> The conductive film 105 may be formed using a material similar to that of the gate electrode 103 .

[0148] <Transistor configuration example 2-6> Next, a configuration example different from that of the transistor TR1 shown in FIG. 12 will be described. 14 shows a modified example of the transistor TR1.

[0149] In the transistor TR1 shown in FIG. 12, the ends of the gate insulating film 102 and the semiconductor film 101c are The TR2 shown in FIG. 13 is a semiconductor film 101c having an end portion. The gate insulating film 102 is located inside the transistor. 13(A) is a cross-sectional view taken along line AB in FIG. 13(C) is a cross-sectional view taken along the line CD of the same.

[0150] The transistors shown in FIG. 14 are the transistor Ta of the memory cell MC and the transistor 14 is a cross-sectional view of a transistor in the channel length direction.

[0151] The transistor TR3 shown in FIG. 14A is a modification of the transistor TR2. The structures of the conductive film 104a and the conductive film 104b are different. For example, the transistor TR3 is fabricated as follows. In order to form the semiconductor film 101a and the semiconductor film 101b, In order to achieve this, two semiconductor films are formed, and the conductive film 104a and the conductive film 104b are formed on the stacked film of the semiconductor films. A resist mask is formed on the conductive film, and the conductive film is etched. A mask made of a conductive film is formed by etching the semiconductor film stack using this mask. Then, the semiconductor film 101a and the semiconductor film 101b are formed by etching. 104a and a conductive film 104b are formed.

[0152] The transistor TR4 shown in FIG. 14B is a modified example of the transistor TR2. In the transistor TR4, the semiconductor film 101c is in contact with the lower surfaces of the conductive film 104a and the conductive film 104b. By adopting such a structure, the semiconductor film 101a and the semiconductor film 101b are provided. The films constituting the semiconductor film 101c are exposed to the air during deposition. Since the films can be formed continuously without any step, defects at the interfaces can be reduced.

[0153] The transistor TR5 shown in FIG. 14C is a modified example of the transistor TR4. In the transistor TR5, an opening is provided in the insulating film 116 to form a plug 118a and a plug 118b. The plugs are used as the source and drain electrodes of a transistor.

[0154] The transistor TR6 shown in FIG. 14D is a modified example of the transistor TR5. In transistor TR6, low resistance regions 171a and 171b are provided in semiconductor film 101. For example, the low resistance region is formed as follows. Next, a gate insulating film 102 and a gate electrode 103 are formed. Next, using the gate electrode 103 as a mask, the low resistance region 171a and the low resistance region 171b are The low resistance regions 171a and 171b are regions with high carrier density.

[0155] Methods for increasing carrier density include, for example, adding impurities and forming oxygen vacancies. For example, one way to increase the carrier density is to add elements by ion implantation. Examples of elements that can be used include argon, boron, carbon, and magnesium. , aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium Chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium Zirconium, Niobium, Molybdenum, Indium, Tin, Lanthanum, Cerium, Neo It is preferable to add one or more selected from the group consisting of zinc, hafnium, tantalum and tungsten. The low resistance region 171a and the low resistance region 171b are doped with the above-mentioned impurity element at a concentration of 5×10 19 atoms / cm 3 More than 1×10 20 atoms / cm 3 More than that, Preferably 2 x 10 20 atoms / cm 3 More preferably, 5×10 20 atom s / cm 3 This is an area that includes the above.

[0156] The low resistance region 171a and the low resistance region 171b can trap unnecessary hydrogen. There is a possibility that unnecessary hydrogen may be trapped in the low resistance region 171a and the low resistance region 171b. This makes it possible to lower the hydrogen concentration in the channel region.

[0157] The above is a list of transistors that can be applied to the transistors Ta and Tb. 1 is a diagram illustrating an example of the configuration of the data transfer device.

[0158] <Memory cell fabrication method example> 15 to 18, a method for fabricating the memory cell array 300 shown in FIG. 9 will be described below. Here, an example of the method will be described. In this example, the transistors Ta and Tb are The transistor TR2 shown is applied.

[0159] A substrate 100 is prepared. The substrate 100 is, for example, a single crystal silicon substrate (p-type semiconductor (including n-type semiconductor substrates), silicon carbide and gallium nitride-based A compound semiconductor substrate, a glass substrate, or the like can be used. In the following, a case where single crystal silicon is used as the substrate 100 will be described. This article explains:

[0160] Next, a conductive film that will become the conductive film 105 and the like is formed on the substrate 100. The conductive film can be formed by, for example, sputtering, CVD (thermal CVD, MOCVD, etc. The methods used are D method, PECVD method, MBE method, ALD method, PLD method, etc. Next, a resist mask is formed, and unnecessary portions of the conductive film that will become the conductive film 105 and the like are etched away. The resist mask is then removed, and the conductive film 105 and the like are formed.

[0161] Next, an insulating film 114 is formed on the substrate 100 and the conductive film 105. For example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), The insulating layer can be formed by using the MBE method, the ALD method, the PLD method, or the like. The coating properties can be improved by forming the film by a CVD method, preferably a PECVD method. In order to reduce damage caused by plasma, thermal CVD and MOCV are also preferred. The ALD method or the ALD method is preferred.

[0162] In order to make the insulating film 114 contain excess oxygen, the insulating film 114 is heated in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to remove oxygen. Alternatively, a region containing the fluorine atom may be formed, or both approaches may be combined.

[0163] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions, etc.) may be added to the insulating film 114 after the film formation. The oxygen introduction method includes introducing oxygen into the film to form a region containing excess oxygen. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Plasma treatment or the like can be used.

[0164] In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include: Oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. In the oxygen introduction process, a rare gas may be added to the oxygen-containing gas. For example, a mixture of carbon dioxide, hydrogen and argon may be used. stomach.

[0165] After the insulating film 114 is formed, the insulating film 114 is polished by a CMP method or the like to improve the flatness of the upper surface. A flattening process may also be performed.

[0166] Next, a source electrode or a drain electrode of the transistor Tb is formed on the insulating film 114. First, an opening is provided in the insulating film 114. Next, A conductive film 133 that will become a plug is deposited so as to fill the gap (FIG. 15(A)).

[0167] Next, the conductive film 133 is planarized so that the surface of the insulating film 114 is exposed. A groove 134 is formed (FIG. 15(B)).

[0168] Next, a semiconductor film that will become the semiconductor film 101a, etc., and a semiconductor film that will become the semiconductor film 101b, etc. are formed on the insulating film 114. The semiconductor films are successively formed without being exposed to the air. It is preferable that the semiconductor film to be the semiconductor film 101a and the semiconductor film to be the semiconductor film 101b are The semiconductor film is formed by sputtering, CVD, MBE, PLD, ALD, etc. Then, the film can be formed.

[0169] The semiconductor film that becomes the semiconductor film 101a and the like and the semiconductor film that becomes the semiconductor film 101b and the like When forming an In-Ga-Zn oxide film by MOCVD, the source gas is For example, trimethylindium, trimethylgallium, dimethylzinc, etc. may be used. The combination of source gases is not limited to the above, and trimethylindium may be replaced with triethylene. In addition, triethylgallium may be used in place of trimethylgallium. Also, diethyl zinc may be used in place of dimethyl zinc.

[0170] After forming the semiconductor film 101a and the semiconductor film 101b, a heat treatment is performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, more preferably 300° C. or higher and 500° C. or lower. At temperatures below ℃, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or The heat treatment may be performed under a pressure condition. In order to compensate for the oxygen released, the reaction may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The heat treatment may be performed immediately after the semiconductor film is formed, or may be performed after processing the semiconductor film to form island-shaped semiconductor layers. The heat treatment may be performed after the insulating film 101a, the semiconductor film 101b, and the like are formed. Oxygen is supplied to the semiconductor film from 114, and oxygen vacancies in the semiconductor film can be reduced.

[0171] After that, a resist mask is formed and unnecessary parts are removed by etching. By removing the resist mask, the stack of island-shaped semiconductor films 101a, 101b, etc. A layer structure is formed (Figure 15(C)).

[0172] When the semiconductor film is etched, part of the insulating film 114 is etched, and the semiconductor film The insulating film 114 in the region not covered by the semiconductor film 101a, the semiconductor film 101b, etc. becomes thinner. Therefore, in order to prevent the insulating film 114 from being lost by the etching, the insulating film 114 is preliminarily formed to a predetermined thickness. It is preferable to form the

[0173] Thereafter, a conductive film that will become the conductive films 204a and 204b is formed. Electroplating method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE The resist mask can be formed by a method such as a photoresist mask, an ALD method, or a PLD method. and removing unnecessary portions of the conductive film that will become the conductive films 204a and 204b by etching. After that, the resist mask is removed, and the conductive film 204a, the conductive film 204b, etc. are formed ( Figure 15(D)).

[0174] Here, when the conductive film is etched, the semiconductor film 101b and the upper part of the insulating film 114 are The portions not overlapping with the conductive film 204a and the conductive film 204b are etched, and the portions are thinned. Therefore, the thickness of the semiconductor film or the like that becomes the semiconductor film 101b is reduced by etching. It is preferable to form the hole to be thick in advance, taking into consideration the depth to which the hole will be formed.

[0175] Next, the gate insulating film 202 and the semiconductor film 101c are formed. After the semiconductor film 101c is formed, a resist mask is formed and the gate insulating film is formed by etching. Next, a conductive film that becomes a gate electrode 203 may be formed by processing the conductive film 202 and the semiconductor film 101c. After that, a resist mask is formed, and the conductive film is processed by etching to form a gate. A transistor T b is formed (Figure 16(A)).

[0176] The semiconductor film that becomes the semiconductor film 101c is formed by sputtering, CVD, MBE or P The film may be formed by using the LD method, the ALD method, or the like.

[0177] As the semiconductor film that becomes the semiconductor film 101c, an In-Ga-Zn oxide film is formed by MOCV. When forming a film by the D method, trimethylindium and trimethylgallium are used as raw material gases. and dimethyl zinc. The combination of the raw material gases is not limited to the above. Alternatively, triethylindium or the like may be used in place of trimethylindium. Instead of methylgallium, triethylgallium or the like may be used. Alternatively, diethyl zinc or the like may be used.

[0178] Although not shown in FIGS. 8 to 11, the insulating film 212 and the An insulating film 213 may be formed (FIG. 16(B)).

[0179] The insulating film 212 is formed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, P It can be formed by using methods such as ECVD, MBE, ALD, or PLD. After the insulating film 212 is formed, heat treatment is preferably performed. In this way, oxygen is supplied to the semiconductor film 101b from the insulating film 114 and the like, and the In addition, the insulating film 212 may have a stacked structure of two or more layers. In that case, for example, the insulating film 212 is made to have a two-layer laminate structure, and the lower layer is made of, for example, silicon oxide. Silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0180] The insulating film 213 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon oxide. Silicon, Aluminum Oxide, Aluminum Oxynitride, Aluminum Oxide Nitride, Aluminum Nitride The material may be a multilayer or single layer.

[0181] Next, an insulating film 216 is formed on the insulating film 213. The insulating film 216 is, for example, a silicon oxide film. Silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, etc. may be used. The insulating film 216 is formed as a single layer by, for example, a sputtering method, a CVD method (thermal CVD method, M OCVD, PECVD, etc.), MBE, ALD, PLD, etc. In addition, when an organic insulating material such as an organic resin is used as the insulating film 216, In this case, the insulating film 216 may be formed by using a coating method such as a spin coat method. After the formation of the insulating film, it is preferable to perform a flattening process on the upper surface.

[0182] Next, the insulating film 216, the insulating film 213, the insulating film 212, the gate insulating film 202 and the semiconductor film Openings are provided in the 101 etc., and plugs 141, 142, and 143 are inserted into the openings. A conductive film such as 143 is formed, and a planarization process is performed so that the surface of the insulating film 216 is exposed. Then, plugs 141, 142, 143, etc. are formed (FIG. 16(C)).

[0183] Next, a conductive film is formed on the insulating film 216 and the plugs 141, etc., and a mask is formed to perform etching. Then, the conductive films 151, 152, 153, etc. are formed. Then, the insulating film 115 is formed. The insulating film 115 can function as an insulating film for the capacitive element Ca. Materials that can be used for the insulating film 115 are the same as those described for the gate insulating film 102, for example. Please refer to the following.

[0184] Next, a conductive film 155 and the like are formed over the insulating film 115. For the materials and the like that can be used, the description of the conductive film 105 may be referred to. A child Ca can be formed (Figure 17(B)).

[0185] Next, an insulating film 156 is formed on the conductive film 155 and the insulating film 115. The upper surface of the insulating film 156 may be planarized. For the insulating film 156, refer to the description of the insulating film 216. Next, a conductive film 105 or the like is formed on the insulating film 156. Next, an insulating film 114 is formed. Next, openings are provided in the insulating film 156 and the insulating film 114, and a conductive film is formed so as to fill the openings, and the surface of the conductive film is planarized so that the insulating film 114 is exposed, and plugs 144, plugs 145, etc. are formed (FIG. 17(C)).

[0186] Next, a transistor Ta or the like is formed (see FIG. 18).

[0187] For the formation of the transistor Ta, refer to the description of the transistor Tb. Also, as shown in FIG. 18, the transistor Ta included in the memory cell MC_1 and the transistor Tb included in the memory cell M C_2 can be formed in the same process.

[0188] By repeating the above steps, the memory cell array 300 shown in FIG. 9 can be fabricated.

[0189] As described above, the configurations and methods shown in the present embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0190] (Embodiment 2) Referring to FIGS. 19 to 21, in the present embodiment, a configuration example of a circuit that can be used in a circuit system according to an aspect of the present invention will be described in detail.

[0191] <CMOS Circuit> The circuit 2011 shown in FIG. 19(A) includes a p-channel transistor 2200 and an n-channel ​​​A so-called 1-channel transistor 2100 is connected in series and the gates of the transistors are connected together. The device structure of the circuit 2011 is shown in Fig. 19(B). An example of the structure is shown below.

[0192] 19B is a cross-sectional view showing a configuration example of the circuit 2011. The circuit 2011 is 01, a transistor 2200, a transistor 2100, a wiring 2202, and a plug 2 203, a wiring 2206, a wiring 2205, an element isolation layer 2204, and an insulating film 2207. The transistor 2200 has a source region or a drain region. An impurity region 2001 functioning as a drain region, a gate electrode 2003, and a gate insulating film 2004 and a sidewall insulating layer 2005.

[0193] The circuit 2011 shown in FIG. 19B includes a transistor 2 using a first semiconductor material in the lower portion. 200 and a transistor 2100 using a second semiconductor material on the top. In FIG. 19(B), a transistor 2100 using the second semiconductor material is The OS transistor shown in is used. The transistor to the left of the dashed line is 2100 and 2200 in the channel length direction. The right side is the transistor 210. 1 and 2200 are cross-sectional views in the channel width direction of the transistors 2200 and 2200. As shown in the figure, two types of transistors are By stacking transistors, the area occupied by the circuit is reduced, allowing multiple circuits to be arranged more densely. can be placed.

[0194] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (strained silicon) (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum The second semiconductor is a gallium arsenide, indium phosphide, gallium nitride, organic semiconductor, etc. The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0195] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors can be used, and it is sufficient to use an appropriate transistor depending on the circuit. In the circuit 2011 of (A), the transistor 2200 is a p-channel type.

[0196] In addition, as shown in FIG. 19C, an impurity region 2002 is provided in a transistor 2200. The impurity region 2002 may be a lightly doped drain (LDD). The impurity concentration of the impurity region 2001 is The gate electrode 2003 and the sidewall insulating layer 2005 are used as a mask. By using this, the impurity region 2001 and the impurity region 2002 can be formed in a self-aligned manner. In particular, when the transistor 2200 is an n-channel type, the deterioration caused by hot carriers is likely to occur. In order to suppress this, it is preferable to provide an impurity region 2002 .

[0197] The transistor 2200 may be a transistor having silicide (salicide). Alternatively, a transistor without the sidewall insulating layer 2005 may be used. ) the resistance of the source region and the drain region can be reduced, and the semiconductor device In addition, because it can operate at a low voltage, it reduces the power consumption of the semiconductor device. It is possible to do so.

[0198] FIG. 19B illustrates a structure in which a backgate electrode is provided in the transistor 2100. However, a configuration without a back gate electrode may also be used.

[0199] The substrate 2201 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a multi-crystal Semiconductor substrates made of crystalline semiconductors, compound semiconductor substrates made of silicon germanium, and SOI (Sil A semiconductor substrate can be used. The transistor formed by using this structure can easily operate at high speed. When a single crystal silicon substrate is used, an impurity element that imparts n-type conductivity to a part of the substrate 2201 is added. The n-type well is formed by doping, and a p-type transistor is inserted in the n-type well region. It is also possible to form the n-type impurity element. As an impurity element to give p-type conductivity, boron (B) or the like can be used. There can be.

[0200] The substrate 2201 may be a conductive substrate or an insulating substrate on which a semiconductor film is provided. The conductive substrate may be a metal substrate, a stainless steel substrate, or a stainless steel foil. substrates with tungsten, substrates with tungsten foil, etc. The insulating substrate may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a flexible substrate, Examples include laminated films, paper containing fibrous materials, and base films. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or silicon. An example of a flexible substrate is polyethylene terephthalate. (PET), polyethylene naphthalate (PEN), polyethersulfone (PES) Examples of materials that can be used include plastics such as acrylic and other flexible synthetic resins. Examples of laminated films include polypropylene, polyester, polyvinyl fluoride, and Examples of the base film include polyester and polyamide. , polyimide, aramid, epoxy, inorganic vapor deposition film, or paper.

[0201] Note that a semiconductor element is formed using a certain substrate, and then the semiconductor element is transferred to another substrate. Examples of the substrate onto which the semiconductor element is transferred include the above-mentioned substrates, as well as paper substrates, Cellophane substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate , Fabric substrates (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester ) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc. ), leather substrate, or rubber substrate. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacture of durable devices, It is possible to impart thermal resistance, reduce weight, or reduce thickness.

[0202] The transistor 2200 is isolated from other elements formed on the substrate 2201 by an element isolation layer 2204. The element isolation layer 2204 is made of aluminum oxide, aluminum oxynitride, etc. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Insulators containing one or more selected from the group consisting of neodymium oxide, hafnium oxide, and tantalum oxide. It can be used.

[0203] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 is converted into silicon dams. This has the effect of terminating the Gring bonds and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 2 Hydrogen in the insulating film provided near the semiconductor film of 100 generates carriers in the oxide semiconductor. This may be one of the factors that cause the transistor 2100 to become less reliable. Therefore, an oxide film is formed on the upper layer of the transistor 2200 using a silicon-based semiconductor material. When the transistor 2100 using a nitride semiconductor is stacked, hydrogen diffusion between the transistors can occur. It is particularly effective to provide the insulating film 2207 having the function of preventing diffusion. 07, the reliability of the transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, the reliability of the system can be improved.

[0204] The insulating film 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0205] In addition, a transistor 2100 including an oxide semiconductor film is formed on the transistor 2100 so as to cover the transistor 2100. An insulating film 2208 having a function of preventing hydrogen diffusion can be formed on the transistor 2100. It is preferable that the insulating film 2208 be made of a material similar to that of the insulating film 2207. In particular, it is preferable to use aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, etc. High blocking effect prevents impurities and oxygen from passing through the membrane Therefore, an aluminum oxide film is used as the insulating film 2208 covering the transistor 2100. By using the above, it is possible to prevent oxygen from being released from the oxide semiconductor film included in the transistor 2100. Furthermore, water and hydrogen can be prevented from entering the oxide semiconductor film.

[0206] The plug 2203 is made of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au ), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Ni Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (C o) Low-resistance materials, or alloys, or compounds that contain these as their main components It is preferable to use a single layer or a multilayer of conductive films that have both heat resistance and conductivity. It is preferable to use a high melting point material such as tin or molybdenum. It is preferable to form the wire from a low-resistance conductive material such as copper. Furthermore, a Cu-Mn alloy is used. When the material is heated, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide suppresses the diffusion of Cu. This is preferable because it has a function of controlling the

[0207] Wiring 2202 and wiring 2205 are made of copper (Cu), tungsten (W), molybdenum (Mo ), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt (Co) low resistance material, its alloy, or its main component It is preferable to use a single layer or a multilayer of a conductive film containing a compound having a high heat resistance and electrical conductivity. It is preferable to use a high melting point material such as tungsten or molybdenum. It is preferable to form the insulating layer from a low-resistance conductive material such as aluminum or copper. When an alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, and the manganese oxide becomes C This is preferable since it has the function of suppressing the diffusion of u.

[0208] The wiring 2206 is made of the same material as the source electrode or drain electrode of the transistor 2100. It can be formed.

[0209] In addition, in Fig. 19(B) and (C), no symbols or hatching patterns are given. The dark regions represent regions made of insulating materials. These regions include aluminum oxide, Aluminum oxide nitride, magnesium oxide, silicon oxide, silicon oxynitride, nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide Select from zinc oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The insulating material may include one or more of the following: polyimide resin, Polyamide resin, acrylic resin, siloxane resin, epoxy resin, phenolic resin, etc. A synthetic resin can also be used. This is described later in Figs. 20(B), (C) and Fig. 21( The same is true for B).

[0210] By appropriately connecting the electrodes of the transistor 2100 and the transistor 2200, various It is possible to configure such a circuit. Other examples are shown in Figures 20 and 21.

[0211] <Analog switch> The circuit 2012 shown in FIG. 20A includes a transistor 2100 and a transistor 2200. The circuit configuration is such that the source and drain of each are connected, and they function as so-called analog switches. FIG. 20B is a cross-sectional view showing an example of a device structure of the circuit 2012. The transistor 2200 shown in FIG. 19(B) is a planar transistor. However, transistor 2200 can be a variety of types of transistors. For example, FIN type, TRI-GATE type and other three-dimensional structures A transistor or the like can be used. Such an example is shown in FIG.

[0212] As shown in FIG. 20(B), an insulating film 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a protrusion (also called a fin) with a thin tip. An insulating film may be provided on the semiconductor substrate when the protrusions are formed. It acts as a mask to prevent the substrate 2211 from being etched. The protrusion does not have to have a narrow tip. For example, the protrusion may be a substantially rectangular parallelepiped protrusion. The protrusion may have a thick tip. 14 is provided on which a gate electrode 2213 is provided. In the semiconductor device 1, an impurity region 2215 functioning as a source region or a drain region is formed. As shown in FIG. 20C, an impurity region 2216 may be provided. 2216 functions as an LDD region or an extension region.

[0213] <Memory circuit> By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written will be described. do.

[0214] The circuit 2013 shown in FIG. 21A includes a transistor 2100 using a second semiconductor material. The transistor 2200 includes a first semiconductor material and a capacitor 2300. The circuit 2013 has a circuit configuration similar to that of the memory circuit 25 in FIG. Therefore, the description of the memory circuit 25 is used to describe the configuration of the circuit 2013. In the example of 1(A), the transistor 2200 is an n-channel type.

[0215] The transistor 2100 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The off-state current of the transistor 2100 is small, so that the transistor 2100 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. It is possible to provide a semiconductor device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This allows for a sufficient reduction in power consumption.

[0216] In addition, the transistor 2100 may be any of the transistors described in Embodiment 1. This provides excellent subthreshold characteristics and enables the fabrication of miniaturized transistors. In addition, the switching speed is fast, allowing high-speed operation. The present invention relates to a transistor using single crystal silicon or the like as a semiconductor material other than an oxide semiconductor. By combining these, miniaturized transistors and high-speed operation are possible. A semiconductor device can be realized, and high-speed write and read operations can be achieved.

[0217] FIG. 21B shows an example of a device structure of the circuit 2013. The transistor 2200 may be an n-channel or p-channel type. In the case of a channel type, the impurity region 2002 may or may not be provided. Alternatively, the transistor 2100 may not include a backgate electrode.

[0218] In the example of FIG. 19 to FIG. 21, the substrate 2201 and the semiconductor substrate 2211 are made of bulk materials. However, one embodiment of the present invention is not limited to this. For example, an SOI substrate may also be used. Cut.

[0219] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0220] (Embodiment 3) In this embodiment, an example of a circuit that can be used in a circuit system of one embodiment of the present invention will be described. This will be explained using Figure 22.

[0221] A transistor that uses an oxide semiconductor in the active layer or a transistor that uses silicon in the active layer. Examples of circuits using transistors are shown in Figs. 22(a) to 22(i). Transistors using nitride semiconductors are called OS transistors, and silicon is used for the active layer. A p-channel Si transistor is called a p-channel Si transistor. A Si transistor is called a n-channel Si transistor, and an n-channel Si transistor is called an n-Si transistor. Note that the conductivity type of the OS transistor is n-channel unless otherwise specified. For convenience, in FIG. 22, p-channel transistors are designated as PMOS, and n-channel transistors are designated as PMOS. It is described as transistor NMOS.

[0222] The aim is to develop an OS transistor that is easy to manufacture, has a high integration density, and has a small short channel effect. To take advantage of the lithography, the channel length of the OS transistor must be greater than or equal to 1 nm and less than 100 nm. It is preferable that the thickness of the Si tran be 5 nm or more and 60 nm or less. In order to form the OS transistor on the same substrate, a Si transistor is required. The channel length is preferably 1 nm or more and less than 100 nm. Alternatively, the channel length is , more preferably 5 nm or more and 60 nm or less, or 5 nm or more and 30 nm or less.

[0223] The circuit shown in FIG. 22(a) and FIG. 22(b) includes a transistor 700, e.g., a switch. The transistor 700 functions as a transistor circuit. The transistor 700 shown has a first gate (top gate, or front gate) and A dual-gate OS transistor having a second gate (back gate) By separately controlling the first gate and the second gate, the on-characteristics and the off-characteristics are improved. Good is possible.

[0224] The circuit shown in FIG. 22(c) includes a transistor 700, a transistor 701, and a node F By holding a potential at the node FN, the same as the memory circuit 25 (FIG. 2A) can be realized. In the example of FIG. 22(c), the transistor 70 The transistor 701 may be a p-Si transistor. , an n-Si transistor or an OS transistor may be used.

[0225] The circuit shown in FIG. 22(d) includes a transistor 700, a transistor 701, and a capacitor element 22(d) includes a memory circuit 25 (FIG. 2( The circuit configuration is the same as A) and can function as a memory circuit. The transistor 700 is a dual-gate OS transistor. It may be a p-Si transistor, an n-Si transistor, or an OS transistor. If p-Si transistors are used, the data input sequence is the same as that shown in Figure 5. This differs from the chart.

[0226] In the circuits of FIG. 22(c) and FIG. 22(d), the transistors 700 and 701 are OS transistors. In the case of a photoresist, the substrate does not need to be a silicon substrate, and can be a transparent substrate such as glass or quartz glass. It becomes possible to use a transparent substrate, a metal substrate, or the like.

[0227] In miniaturization, n-channel transistors have to be fabricated using LDD and distortion, and p-channel transistors have to be fabricated using OS transistors require more complicated processes than transistors. Therefore, the circuits in Fig. 22(c) and Fig. 22(d) do not require the complicated process of The transistor 701 is a p-Si transistor, and the transistor 700 is an OS transistor. This makes it possible to simplify the manufacturing process.

[0228] OS transistors do not require high-temperature processes at temperatures above 900°C, making them superior to Si transistors. OS transistors are more suitable for integration than other semiconductor elements. By applying OS transistors to circuits, elements can be integrated three-dimensionally. In other words, the OS transistor can provide a highly integrated semiconductor device. Since it can be formed at a lower temperature than Si transistors, OS By stacking transistors, it is possible to provide a highly reliable and high-performance semiconductor device. It is Noh.

[0229] The circuit of FIG. 22(e) is a modification of FIG. 22(d), in which instead of the transistor 701, , a transistor 702 and a transistor 703 are electrically connected in series. For example, , the first terminal of transistor 702 is connected to a high power supply potential (V DD ) is given to the wiring or electrode The second terminal of the transistor 703 is electrically connected to the ground potential (GND). The transistor 700 is a dual-gate OS transistor 701 is a p-Si transistor, and transistor 703 is an n-Si transistor. Transistors 702 and 703 are C It constitutes a MOS inverter circuit. The transistor 700 is fabricated using a low-temperature process. This is highly compatible with the manufacturing process of general silicon transistors, It is easy to form transistor 700 on transistor 702 and transistor 703. .

[0230] FIG. 22(f) shows an example of a CMOS inverter circuit. Transistor 700 is an OS transistor. transistor 701 is a p-Si transistor, and transistor 702 is a p-Si transistor. The fabrication of 0 can be performed at low temperatures, which is the same as the manufacturing process for general silicon transistors. Since the matching is also high, it is easy to form the transistor 700 on the transistor 702. It is.

[0231] The circuit shown in FIG. 22(g) includes a transistor 700, a transistor 701, and a transistor The transistor 701 and the transistor 704 are connected to a diode 706 and a node FN. The gate of the transistor 701 is electrically connected to the transistor 704. The input terminal of the diode 706 is electrically connected to the input terminal of the diode 706 via the resistor 700. an input terminal of a node 706, a gate of a transistor 700, a first terminal of a transistor 701, and the second terminal of the transistor 704 are connected to different wiring or voltage sources, not shown. The transistor 700, the transistor 701, and the transistor The circuit formed by the transistor 704, the diode 706, and the node FN is similar to that shown in FIG. The input terminal of the diode 706 and the The data corresponding to the potential between the output terminal and the diode can be held at the node FN. By using a photodiode as 706, it can function as a sensor element. In this case, the circuit shown in FIG. 22(g) can function as an optical sensor circuit. A potential corresponding to the photocurrent flowing through the photodiode (diode 706) is held at the FN. It is possible to do so.

[0232] The sensor element applied to the circuit shown in FIG. 22(g) is not limited to an optical sensor element. For example, the sensor elements can be force, displacement, position, Speed, acceleration, angular velocity, rotation speed, distance, light (e.g. visible light, infrared), electromagnetic waves (e.g. , EEG), magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, Measure or detect flow rate, humidity, gradient, vibration, or odor, and output the results as a voltage signal. An element that can convert a signal into a current signal is used. For example, a photodiode Instead of (706), a temperature sensor element is used that has two resistor elements with different temperature characteristics connected in series. A child may be born.

[0233] In the circuit diagram of FIG. 22(g), transistor 700 is an OS transistor. The transistor 701 and the transistor 704 may be p-Si transistors or nS The diode 706 may be an i-transistor or an OS transistor. A photodiode using silicon may be used. If 04 is a Si transistor, the transistor 700 can be manufactured using a low-temperature process. This is highly compatible with the manufacturing process of general silicon transistors, so It is easy to form transistor 700 on transistor 701 and transistor 704.

[0234] In the circuit of FIG. 22(g), one of the transistors 701 and 704 When a Si transistor is used in one side and an OS transistor is used in the other side, It is possible to form circuits that combine the high-speed characteristics of the MOSFET with the low leakage characteristics of the OS transistor. It is.

[0235] In the circuit of FIG. 22(g), the transistor 701 and the transistor 704 are O In the case of an S transistor, the process can be further simplified. As shown in Example 3, if the technology node is fine, the OS transistor Since it is possible to obtain frequency characteristics equivalent to those of a Si transistor, even with the above configuration, It is possible to form circuits that combine high speed operation with low leakage characteristics.

[0236] The circuit shown in FIG. 22(h) includes a transistor 700 and a transistor The transistor 700 has a first gate electrically connected to a first terminal. The first terminal is electrically connected to a wiring or electrode (not shown). The first terminal and the second terminal of the transistor 704 may be electrically connected to each other. FIG. 22(h) shows the Enhanced It is possible for the device to function as an inverter circuit of the ement / depletion type. The transistor 700 is a dual-gate OS transistor. By making it variable, it is possible to control the characteristics of the circuit (inverter circuit) shown in Figure 22(h). The transistor 704 may be an OS transistor or an n-Si transistor. It is possible.

[0237] The circuit shown in FIG. 22(i) is similar to the circuit shown in FIG. 22(h) in that it is electrically connected in series. The circuit shown in FIG. 22(i) includes a transistor 700 and a transistor 704. The gate of the transistor 700 is electrically connected to a wiring or electrode (not shown). However, it is different from the circuit in FIG. 22(h). The circuit in FIG. 22(i) is an Enhancement / Enhancement type inverter. The gate potential of the transistor 700 may be fixed or variable. The transistor 704 is an OS transistor or an n-Si transistor. The transistor can be used.

[0238] In FIG. 22(h) and FIG. 22(i), the transistor 704 is a Si transistor. In this case, a transistor 704 is provided on the transistor 704 in the same manner as in the circuit shown in FIG. 700 can be created.

[0239] Note that the OS transistors used in the circuit diagrams of FIGS. A second gate electrode may or may not be provided as required.

[0240] All of the circuits (semiconductor devices) shown in FIG. 22(a) to FIG. 22(i) are fabricated on the same substrate. Therefore, it is possible to mount multiple circuits with different functions and performance on the same board. For example, the circuits shown in Fig. 22(d) and Fig. 22(f) can be fabricated on the same substrate. The semiconductor device manufactured in this manner is shown in FIG. 23(A), and the semiconductor device manufactured in this manner is shown in FIG. 22(d) and FIG. 22(i). FIG. 24A shows a semiconductor device in which a circuit is manufactured over the same substrate.

[0241] FIG. 23A is a cross-sectional view showing an example of the configuration of a semiconductor device. The circuit diagram of FIG. 23(B) is shown in FIG. 22( f), and the circuit diagram in FIG. 23(C) corresponds to the circuit diagram in FIG. 22(d). In the semiconductor device shown in FIG. 3A, a transistor 700 is an OS transistor. In this example, the transistor 701 and the transistor 702 are p-Si transistors. FIG. 23A shows a cross-sectional structure of each transistor in the channel length direction.

[0242] The semiconductor device shown in FIG. 23A includes a transistor 700, a transistor 701, and a transistor A transistor 702, a capacitance element 705, a substrate 730, an element isolation layer 731, and an insulating film 7 32, an insulating film 733, a plug 711, a plug 712, a plug 713, and a plug 7 14, wiring 721, wiring 722, wiring 723, wiring 724, and wiring 74 In FIG. 23(A), a plurality of plates formed in the same layer are Of the plugs, only one plug is labeled with a code, and the other plugs are labeled with a code to avoid confusion. In order to avoid this, the symbols are omitted.

[0243] For details of the substrate 730, refer to the description of the substrate 2201 in FIG. 19B. For details, refer to the element isolation layer 2204 in FIG. 19B. For details of the insulating film 732, refer to 19B. For details of the insulating film 733, refer to the description of the insulating film 2207 in FIG. For details of the plugs 711 to 714, refer to the description of the plug 2208 in FIG. For details of the wirings 721 to 723, refer to the description of the wiring 220 in FIG. Please refer to description 2.

[0244] The wiring 741 functions as a second gate electrode of the transistor 700. The wiring 41 may be formed using the material that can be used for the wirings 721 to 723. In some cases, the wiring 741 may be omitted. The source electrode and the drain electrode can be made of the same material.

[0245] In FIG. 23(A), the regions without symbols and hatching patterns are insulators. These regions include aluminum oxide, aluminum oxide nitride, and nium, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, nitride Silicon, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid containing one or more selected from the group consisting of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Insulators such as polyimide resin, polyamide resin, etc. can be used in this region. , acrylic resin, siloxane resin, epoxy resin, phenolic resin, or other organic resin is used. It is also possible.

[0246] By configuring the semiconductor device as shown in FIG. 23(A), It is possible to fabricate the MOSFET (including the floating node) and its peripheral circuits on the same substrate. Since OS transistors do not require heat treatment at temperatures above 900°C, circuits can be fabricated using lower temperature processes. In addition, miniaturized OS transistors can be fabricated using silicon in the active layer. The frequency characteristics are equivalent to those of n-channel transistors using MOS transistors. CMOS circuits that combine p-Si transistors are capable of high-speed operation.

[0247] FIG. 24(A) is a cross-sectional view showing a configuration example of a semiconductor device, and the circuit shown in FIG. 24(B) is shown on the left side. The circuit diagram of FIG. 24(B) is the same as that of FIG. 22(i). The circuit diagram in FIG. 24(C) corresponds to the circuit diagram in FIG. 22(d). The semiconductor device shown in A) includes a transistor 700, a transistor 701, and a transistor 7 FIG. 24(A) shows the structure of each transistor. FIG.

[0248] The semiconductor device shown in FIG. 24A includes a transistor 700, a transistor 701, and a transistor A transistor 704, a capacitor element 705, a substrate 735, an insulating film 732, and an insulating film 733. , a plug 711, a plug 712, a plug 713, a plug 714, and a wiring 721. , wiring 722, wiring 723, wiring 724, wiring 741, wiring 742, and In FIG. 24A, multiple wirings formed in the same layer are Of the many plugs, only one plug is given a code, and the other plugs are left blank to avoid confusion. To avoid this, the signs are omitted.

[0249] For details of the substrate 735, refer to the description of the substrate 2201 in FIG. Other devices may be formed in the substrate 735. In that case, the surface of the substrate 735 may be flat. It is preferable to perform planarization processing by CMP or the like so as to achieve this.

[0250] For details of the insulating film 732, see the description of the insulating film 2207 in FIG. For details, see the description of the insulating film 2208 in FIG. 19B. For details of 4, refer to the description of the plug 2203 in FIG. 19(B), and for details of the wirings 721 to 723, refer to For details, refer to the description of the wiring 2202 in FIG.

[0251] The wiring 741 functions as a second gate electrode of the transistor 700, and the wiring 742 The wiring 743 serves as a second gate electrode of the transistor 701. The wirings 741 to 743 function as second gate electrodes of the gate electrodes of the gate electrodes 704. The wirings 721 to 723 can be formed using the same material. In some cases, the wirings 741 to 743 may be omitted.

[0252] The wiring 724 is a source electrode or a drain electrode of the transistor 700 and the transistor 704. The insulating layer 14 can be formed of the same material as the insulating electrode.

[0253] In FIG. 24(A), the areas without symbols and hatching patterns are These regions are made of insulating materials. These regions include aluminum oxide, oxide nitride, etc. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide One selected from the group consisting of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Insulators containing the above can be used. Organic resins such as acrylic resin, siloxane resin, epoxy resin, and phenol resin are used. It can also be used.

[0254] By configuring the semiconductor device as shown in FIG. 24(A), It is possible to fabricate the MOSFET (including the floating node) and its peripheral circuits on the same substrate. In addition, OS transistors do not require heat treatment at temperatures above 900°C, so they can be fabricated using lower temperature processes. In addition, OS transistors can be stacked with other semiconductor elements. This allows elements to be arranged three-dimensionally, resulting in the creation of highly integrated semiconductor devices. In addition, miniaturized OS transistors can be fabricated using silicon in the active layer. The frequency characteristics are equivalent to those of the n-channel transistors used in the experiment. The circuit is capable of high speed operation.

[0255] In addition, the channel length dependence of electron mobility in OS transistors is The effect is not as great as the channel length dependence of electron mobility in OS transistors. Even if the channel length is reduced from 10 μm to 100 nm, there is no clear decrease in the field-effect mobility. I can't see the bottom.

[0256] Therefore, when using OS transistors with a channel length of 10 μm or less, The difference in field effect mobility between the Si transistor and the GaN-based transistor is 10 μm or more when the channel length of the transistor is increased. The OS transistor with a channel length of 100 nm or less is When used for a transistor, the thickness is about 1 / 30 of that of a Si transistor, preferably about 1 / 10. More preferably, it is possible to reduce the difference to about one third of the field effect mobility.

[0257] In addition, when an OS transistor is used for a transistor with a channel length of about 100 nm, S It is believed that it is possible to achieve a field effect mobility similar to that of an i-transistor. Therefore, microfabricated OS transistors can achieve switching speeds comparable to those of silicon transistors. , it is possible to realize frequency characteristics.

[0258] In addition, the OS transistor has a characteristic of having a low off-state current. In the circuit, the capacitance required to hold the charge can be reduced due to the low off-current. Cut.

[0259] The configuration of this embodiment can be appropriately combined with other embodiments and examples. .

[0260] (Embodiment 4) In this embodiment, a memory device such as the memory cell array 300 exemplified in the above embodiment is Here, the memory device is a row selection device connected to a memory cell array. The pixel may include a pixel select driver, a column select driver, an A / D converter, and the like.

[0261] The RF device in this embodiment has a memory circuit therein, and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF devices can identify objects by reading their individual information. It can be used for individual authentication systems that distinguish between people. To achieve this, extremely high reliability is required.

[0262] 25 is a block diagram showing a configuration example of an RF device. 800 includes an antenna 804, a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation It includes a circuit 808 , a logic circuit 809 , a memory circuit 810 , and a ROM 811 .

[0263] The reverse current in the transistor exhibiting the rectification effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of achieving this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. Electromagnetic coupling method, electromagnetic induction method that communicates by induced electromagnetic fields, radio wave method that communicates using radio waves The RF device 800 shown in this embodiment can be used in any of these three ways. It is also possible to use it for.

[0264] Next, the configuration of each circuit will be described. The antenna 804 is connected to the communication device 801 (interrogator, reader). The antenna 802 connected to the The rectifier circuit 805 receives a radio signal through the antenna 804. The input AC signal generated by the capacitor is rectified, for example, by half-wave double voltage rectification, and then output to the capacitor in the downstream. This is a circuit that generates an input potential by smoothing the rectified signal using a quantum element. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. A switch circuit is a circuit that operates when the amplitude of the input AC signal is large and the internally generated voltage is large, and when the This is a circuit that controls the power so that it is not input to the subsequent circuit.

[0265] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0266] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0267] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0268] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0269] Here, the memory circuit described in the above embodiment can be applied to the memory circuit 810. The memory circuit according to one embodiment of the present invention can retain data even when power is cut off. Therefore, the memory circuit according to one embodiment of the present invention can be suitably used in an RF device. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance when reading and writing data. In addition, it prevents malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0270] The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to each RF device produced, This means that unique numbers can only be assigned to products that have been shipped, and the unique numbers of the products will be discontinuous after shipment. This makes it easier to manage customers' accounts after products are shipped.

[0271] Next, an example of how to use the RF device will be described with reference to FIG. The applications are wide-ranging, but examples include banknotes, coins, securities, bearer bonds, certificates (driving licenses, etc.) Licenses and resident's cards, etc., Fig. 26(A)), packaging containers (wrapping paper, bottles, etc., Fig. 26(C)), Recording media (DVDs, video tapes, etc., Fig. 26(B)), vehicles (bicycles, etc., Fig. 26(D) )), personal belongings (bags, glasses, etc.), food, plants, animals, the human body, clothing, daily necessities, Medical products including medicines and drugs, or electronic devices (liquid crystal display devices, EL display devices, televisions, etc.) Equipment, or mobile phones) or tags attached to each item (Figure 26(E, 26(F)) and can be used.

[0272] The RF device 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. For example, in a book, the sensor is embedded in the paper and fixed to the packaging made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The F Device 4000 is small, thin, and lightweight, so even after it is fixed to an article, it remains attached to the article. It does not impair the design of the product itself. It can also be used for banknotes, coins, securities, bearer bonds, Alternatively, the RF device 4000 according to one aspect of the present invention may be provided on a document or the like, By utilizing this authentication function, counterfeiting can be prevented. Also, packaging containers, recording media, personal belongings, food, clothing, daily necessities, or electronic devices. By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, the R according to one aspect of the present invention can be used for vehicles as well. By installing the F device, you can increase security against theft, etc. Cut.

[0273] As described above, the RF device according to one aspect of the present invention can be used for each of the applications described in this embodiment. This reduces the power consumption during operation, including writing and reading information, and therefore the maximum communication distance It is also possible to transmit information for an extremely long time even when the power is cut off. Since the data can be stored for a long period of time, it is also suitable for applications where the frequency of writing and reading is low. can be done.

[0274] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0275] (Embodiment 5) In this embodiment, at least the memory cell array 300 described in the embodiment is included. A CPU including a memory device will be described. The memory device is connected to a memory cell array. It may include a row selection driver, a column selection driver, an A / D converter, and the like.

[0276] FIG. 27 shows at least one of the memory devices described in the above embodiments and other semiconductor devices. FIG. 2 is a block diagram showing a configuration of an example of a CPU used in the control unit.

[0277] The CPU shown in FIG. 27 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 27 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 27 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0278] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0279] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0280] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0281] In the CPU shown in FIG. 27, a register 1196 is provided with a memory cell. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0282] In the CPU shown in FIG. 27, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0283] FIG. 28 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory circuit 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory circuit 1200 may include a diode, a resistor, an inductor, etc., as necessary. The transistor 1209 is an oxide semiconductor. It is preferable that the transistor has a channel formed in the semiconductor layer.

[0284] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory circuit 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0285] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 1203 is The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal The conduction or non-conduction between the two terminals (i.e., the on or off state of the transistor 1213) is selected. The first terminal of the switch 1204 is connected to one of the source and drain terminals of a transistor 1214. The second terminal of the switch 1204 corresponds to the source and drain of the transistor 1214. In response to the other switch 1204, a control signal is input to the gate of a transistor 1214. RD determines whether conduction or non-conduction between the first terminal and the second terminal (i.e., transistor 12 14 on or off state) is selected.

[0286] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (either the source or drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) is connected to the The first terminal of the switch 1204 (either the source or drain of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the drains is electrically connected to a wiring capable of supplying a power supply potential VDD. A second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) and a first terminal of the transistor 1204 (either the source or drain of the transistor 1214); The input terminal of the element 1206 and one of the pair of electrodes of the capacitor element 1207 are electrically connected to each other. Here, the connection point is referred to as node M1. The other of the two may be configured to receive a constant potential. For example, a low power supply potential (G A power supply voltage (such as ND) or a high power supply voltage (such as VDD) can be input to the capacitor. The other of the pair of electrodes 1207 is connected to a wiring (e.g. The other of the pair of electrodes of the capacitance element 1208 is electrically connected to a constant For example, a low power supply potential (GND, etc.) or a high A power supply potential (such as VDD) can be input. The other electrode is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). are connected to the network.

[0287] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0288] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and one of the switches When the first and second terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a conductive state. There is no conduction between them.

[0289] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 28, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and the inverted signal is output via the circuit 1220. and input to the circuit 1201.

[0290] In FIG. 28, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The second terminal ( The signal output from the other of the source and drain of the transistor 1213 is inverted in logic value. For example, the input may be input to the circuit 1201 without being If there is a node that holds a signal with the logic value of the signal input from the input terminal inverted, , from the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) The signal that is output can be input to the node.

[0291] In addition, in FIG. 28, among the transistors used in the memory circuit 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The transistor may be a Si transistor in which a channel is formed in a silicon substrate. All the transistors used in the memory circuit 1200 have channels formed in an oxide semiconductor layer. Alternatively, the memory circuit 1200 may include a transistor 1. In addition to 209, an OS transistor may be included, and the remaining transistors may be oxide semiconductor. A transistor in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than a conductor. It is also possible.

[0292] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. can.

[0293] In the semiconductor device of one embodiment of the present invention, while a power supply voltage is not supplied to the memory circuit 1200, The data stored in the circuit 1201 is transferred to a capacitor 1208 in the circuit 1202. Therefore, it can be retained.

[0294] In addition, the off-state current of an OS transistor is extremely small. The current is higher than the off-current of a transistor whose channel is formed in crystalline silicon. Therefore, by using an OS transistor as the transistor 1209, Even when the power supply voltage is not supplied to the memory circuit 1200, the signal held in the capacitor 1208 is In this way, the memory circuit 1200 can maintain the data even when the supply of the power supply voltage is stopped. It is possible to retain memory contents (data).

[0295] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0296] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory circuit 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0297] Such a memory circuit 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0298] In the present embodiment, the memory circuit 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, It can also be applied to RF devices (Radio Frequency Devices).

[0299] For example, in this specification, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrate, metal substrate, stainless steel substrate, stainless steel foil Substrate with tungsten foil, Tungsten substrate, Substrate with tungsten foil, Flexible substrate, Adhesive There are laminated films, papers containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples of such materials include polyethylene terephthalate (PET), polyethylene Plastics such as polyolefin naphthalate (PEN) and polyethersulfone (PES) One example is synthetic resin such as acrylic. Another example is Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy, and inorganic vapor deposition. Films, papers, etc. In particular, semiconductor substrates, single crystal substrates, and SOI substrates, etc. By manufacturing transistors using this method, there is little variation in characteristics, size, shape, etc. This allows the manufacture of transistors with fewer gates, higher current capability, and smaller size. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated. It is possible to achieve this.

[0300] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic material such as a tungsten film and a silicon oxide film. The structure may be a laminated structure of films or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0301] That is, one substrate is used to form a transistor, and then another substrate is used to form the transistor. The transistor may be transposed and placed on another substrate. As an example, in addition to the substrate on which the above-mentioned transistors can be formed, a paper substrate, a cellophane substrate, etc. Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), There are leather substrates, rubber substrates, etc. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of devices that are not easily damaged, heat resistance It is possible to provide a thinner, lighter, or thinner device.

[0302] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0303] (Embodiment 6) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, An image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, printer-combinations, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 29. .

[0304] The portable game machine shown in FIG. 29A includes a housing 901, a housing 902, a display portion 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 29(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0305] The portable data terminal shown in FIG. 29(B) includes a first housing 911, a second housing 912, a first display unit The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The first display unit 913 and the second display unit 914 may be switched according to the angle between the first display unit 913 and the second display unit 914. At least one of the first display unit 912 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be achieved by touching the display device. The position input function can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0306] The notebook personal computer shown in FIG. 29C includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0307] The electric refrigerator-freezer shown in FIG. 29(D) includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0308] The video camera shown in FIG. 29(E) includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0309] The ordinary automobile shown in FIG. 29(F) includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0310] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0311] (Embodiment 7) In this embodiment, an oxide semiconductor film included in a semiconductor device will be described in detail.

[0312] The oxide semiconductor film is an oxide semiconductor containing indium. When indium is contained, the carrier mobility (electron mobility) is increased. The circuit system of the embodiment includes oxygen, In, Zn, and M (wherein M is Ti, Ga, Y, Zr, It is preferable to use an oxide semiconductor film containing La, Ce, Nd, or Hf. M is, for example, an element having a high bond energy with oxygen. Alternatively, the element M is, for example, an element having a higher energy level than indium. The semiconductor film contains zinc. When the oxide semiconductor contains zinc, it may be easily crystallized.

[0313] In addition, it is preferable to use an oxide having a large energy gap for the oxide semiconductor film. The energy gap of the oxide semiconductor film is, for example, 2.5 eV to 4.2 eV. , preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. Below.

[0314] In addition, when the oxide semiconductor film has a stacked structure, for example, as shown in FIG. Alternatively, the semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c may be stacked.

[0315] The semiconductor film 44a and the semiconductor film 44c contain oxygen other than the oxygen constituting the semiconductor film 44b. The semiconductor film 44b is an oxide semiconductor composed of one or more elements. The semiconductor film 44a and the semiconductor film 44b are made of one or more elements other than oxygen. c is formed, the interface between the semiconductor film 44a and the semiconductor film 44b and the semiconductor film 44b An interface state is unlikely to be formed at the interface between the semiconductor film 44c and the semiconductor film 44c.

[0316] The semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c are made of at least indium. When the semiconductor film 44a is an In-M-Zn oxide, In and When the sum of M is 100 atomic %, In is preferably less than 50 atomic %. M is more than 50 atomic %, and more preferably In is less than 25 atomic %. The content of the In-M-Zn oxide in the semiconductor film 44b is set to be higher than 75 atomic %. When the sum of In and M is 100 atomic %, In is preferably 25 atomic %. mic%, M is less than 75 atomic %, and more preferably In is 34 atomic %. % or more and M is less than 66 atomic %. In the case of Zn oxide, when the sum of In and M is 100 atomic %, preferably In is less than 50 atomic %, M is more than 50 atomic %, and more preferably I n is less than 25 atomic % and M is higher than 75 atomic %. The film 4c may be made of the same oxide as the semiconductor film 44a.

[0317] The semiconductor film 44b is an acid having a larger electron affinity than the semiconductor films 44a and 44c. For example, the semiconductor film 44b is made of a compound having a higher conductivity than the semiconductor film 44a and the semiconductor film 44c. The electron affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less. V or less, more preferably, an oxide having a larger energy than the above by 0.15 eV to 0.4 eV is used. , electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0318] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor film 44c contains indium gallium oxide. The atomic ratio [In / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0319] More preferably, the semiconductor film 44c contains gallium oxide. The semiconductor film 44c can function as a blocking film to prevent indium diffusion. By forming the gallium oxide film on the lower semiconductor film 44b, the insulator film 44a is Therefore, it is possible to eliminate or suppress zinc diffusion.

[0320] When an electric field is applied to the gate electrode of the transistor, the semiconductor film 44a, the semiconductor film 44b, the semiconductor Of the conductive film 44c, a channel is formed in the semiconductor film 44b having a large electron affinity.

[0321] Here, the band structure of the stacked structure of the insulating film and the oxide semiconductor film is shown in FIG. FIG. 30 shows the vacuum level and each film (insulating film 43 , the conduction band minimum of the semiconductor film 44a, the semiconductor film 44b, the semiconductor film 44c, and the insulating film 47) The energy at the top of the valence band (denoted as Ev) and the energy at the top of the valence band (denoted as Ec) are shown.

[0322] In addition, between the semiconductor film 44a and the semiconductor film 44b, In addition, between the semiconductor film 44b and the semiconductor film 44c, In some cases, the semiconductor film 44b and the semiconductor film 44c may have a mixed region. The mixed region is formed at the interface Therefore, the level density of the semiconductor film 44a, the semiconductor film 44b, and the semiconductor film 44c is reduced. In the laminate, the energy changes continuously near each interface (continuous junction). (also called a band structure).

[0323] In FIG. 30, the semiconductor film 44a and the semiconductor film 44c have the same Ec. For example, the semiconductor film 44 is made of a material other than the semiconductor film 44a. The Ec of c may have high energy.

[0324] At this time, the electrons are not in the semiconductor film 44a and the semiconductor film 44c but in the semiconductor film 44 Moves mainly within b.

[0325] As described above, the interface state density at the interface between the semiconductor film 44a and the semiconductor film 44b, By lowering the interface state density at the interface between the semiconductor film 44b and the semiconductor film 44c, Therefore, the movement of electrons in the semiconductor film 44b is not hindered, and the on-current of the transistor is reduced. It can be made higher.

[0326] In addition, when the transistor has the s-channel structure described above, the semiconductor film 44b Therefore, the thicker the semiconductor film 44b, the larger the channel region. That is, the thicker the semiconductor film 44b is, the higher the on-state current of the transistor is. For example, it is possible to obtain a thickness of 20 nm or more, preferably 40 nm or more, and more preferably 60 nm or more. More preferably, the semiconductor film 44b may have a region having a thickness of 100 nm or more. However, since this may reduce the productivity of semiconductor devices, A semiconductor having a region preferably having a thickness of 200 nm or less, more preferably 150 nm or less. This may be called film 44b.

[0327] In order to increase the on-state current of the transistor, the thickness of the semiconductor film 44c is preferably as small as possible. For example, it is preferably less than 10 nm, more preferably 5 nm or less, and even more preferably 3 nm or less. On the other hand, the semiconductor film 44c may have a channel shape. The semiconductor film 44b is formed by adding elements other than oxygen (hydrogen, silicon) that compose the adjacent insulator. The semiconductor film 44c has a function of blocking the intrusion of For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the semiconductor film 44c has a region having a thickness of 2 nm or more. In order to suppress outward diffusion of oxygen released from the insulating film 43, the semiconductor film 44c is It is preferable that the material has oxygen blocking properties.

[0328] In order to increase reliability, the semiconductor film 44a is thick and the semiconductor film 44c is thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. The semiconductor film 44a may have a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor film 44a, the interface between the adjacent insulating film and the semiconductor film 44a The distance from the semiconductor film 44b where the channel is formed can be increased. For example, the thickness is set to 200 nm or less, preferably 120 nm or less, because the productivity of the device may decrease. If the semiconductor film 44a has a region with a thickness of 80 nm or less, more preferably 80 nm or less, good.

[0329] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove the impurities to obtain a high purity so that the impurities are not included as much as possible.

[0330] Note that the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film reduces the amount of oxygen in the oxide semiconductor film. Therefore, when the oxide semiconductor film is subjected to a dehydration treatment (dehydrogenation treatment), the amount of oxygen vacancies increases. In order to compensate for oxygen vacancies increased by the above-mentioned treatment, oxygen is added to the oxide semiconductor film. In this specification and the like, the treatment of adding oxygen to an oxide semiconductor film is preferably Alternatively, the amount of oxygen contained in the oxide semiconductor film may be higher than the stoichiometric composition. This treatment is sometimes referred to as peroxygen treatment.

[0331] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 This means that the above is the case.

[0332] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film has an extremely excellent For example, when a transistor using an oxide semiconductor film is The drain current in the MOSFET state is 1×10 at room temperature (approximately 25°C). -18 A or less, preferably 1×10 -21 A or less, more preferably 1×10 -24 A or less, or 1x at 85°C 10 -15 A or less, preferably 1×10 -18 A or less, more preferably 1×10 -21 A or less. Note that the off state of a transistor means that the transistor is an n-channel type transistor. In the case of a transistor, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. If the gate voltage is more than 1V, 2V, or 3V less than the threshold voltage, the transistor The starter is turned off.

[0333] Next, the structure of the oxide semiconductor will be described.

[0334] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0335] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0336] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0337] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0338] <caac-os> First, let me explain about CAAC-OS.

[0339] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0340] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0341] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0342] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 43(A) is shown in Figure 43(B). From Figure 43(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0343] As shown in FIG. 43(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of each pellet is about 1 nm to 3 nm, and the size of each pellet is about 1 nm to 3 nm. It can be seen that the size of the gap caused by the inclination is about 0.8 nm. The pellets can also be called nanocrystals (nc). AAC-OS, CANC(C-Axis Aligned nanocrystals) ) can also be referred to as an oxide semiconductor.

[0344] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 43(D)). The inclination between the pellets observed in FIG. 43(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0345] FIG. 44(A) shows the C The s-corrected high-resolution TEM images are shown for regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 44(B), Fig. 44(C), and Fig. 44(D), respectively. As shown in Figure 44(D), Figure 44(B), Figure 44(C) and Figure 44(D) show that the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0346] Next, C was analyzed by X-ray diffraction (XRD). AAC-OS will be explained. For example, InGaZnO 4 CAAC-O When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 45(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. ZnO 4 Since the crystal orientation of CAAC-OS is attributed to the (009) plane of the crystal, it is considered that the crystal orientation of CAAC-OS is c-axis oriented. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0347] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0348] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I nGaZnO 4 In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a (φ scan) is performed, no clear peak appears as shown in FIG. In contrast, InGaZnO 4 In the case of a single crystal oxide semiconductor, 2θ is fixed to about 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 45(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0349] Next, we will explain the CAAC-OS analyzed by electron diffraction. ZnO 4 For CAAC-OS with a crystal of 300 nm, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO 4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 6(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 46(B) is made of InGaZnO 4 The (010) face of the crystal This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0350] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0351] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0352] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0353] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is set to 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly pure intrinsic or substantially highly pure oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0354] <nc-os> Next, we will explain nc-OS.

[0355] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In some cases, the nanocrystals are not clearly visible in the pellets of CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is referred to as the pellet. There is a chance to call.

[0356] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0357] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0358] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0359] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0360] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0361] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0362] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0363] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0364] The determination of which part is regarded as one crystal part can be made as follows. For example, , InGaZnO 4 The unit cell of the crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the InGaZnO 4 The crystal part of The lattice fringes can be seen as 4 This corresponds to the ab plane of the crystal.

[0365] Figure 47 shows an example of investigating the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in Figure 47, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 47, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0366] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0367] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0368] For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], a single crystal InGaZnO having a rhombohedral crystal structure 4 has a density of 6.357 g / cm 3 . Thus, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Further, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0369] Note that there may be cases where single crystals of the same composition do not exist. In such cases, by combining single crystals with different compositions in any ratio, it is possible to estimate the density corresponding to a single crystal in a desired composition. The density corresponding to a single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

[0370] As described above, the oxide semiconductor has various structures, each having various characteristics. Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0371] <Film Formation Methods for CAAC-OS and nc-OS> Next, an example of a film formation method for CAAC-OS will be described.

[0372] FIG. 48(A) is a schematic diagram of the inside of the film formation chamber. CAAC-OS is formed by sputtering. The film can be formed in this manner.

[0373] As shown in FIG. 48(A), the substrate 5220 and the target 5230 are arranged to face each other. Between the substrate 5220 and the target 5230 there is a plasma 5240. In addition, a heating mechanism 5260 is provided below the substrate 5220. The get 5230 is bonded to the backing plate. A plurality of magnets are disposed in positions facing the target 5230. The sputtering method that uses a magnetic field to increase the deposition rate is called magnetron sputtering. It is called.

[0374] The distance d between the substrate 5220 and the target 5230 (target-substrate distance (TS distance) The distance is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or oxygen 5 volumes). % or more), and the pressure is 0.01 Pa to 100 Pa, preferably The pressure is controlled to be 0.1 Pa or more and 10 Pa or less. By applying a voltage, a discharge starts and plasma 5240 is observed. A high-density plasma region is formed near the nozzle 5230 by the magnetic field. In the region, the deposition gas is ionized to generate ions 5201. The ions 5201 are For example, the oxygen cation (O + ) and argon cations (Ar + ) etc.

[0375] The target 5230 has a polycrystalline structure having a plurality of crystal grains, and As an example, FIG. 49 shows a target 5230 having an InMZn O 4 (Element M is, for example, Ga or Sn) crystal structure. Note that FIG. 49 shows the crystal structure of InMZnO when viewed from the vertical direction 4 This is the crystal structure of InMZnO 4 With crystals of The oxygen atoms have negative charges, which creates a repulsive force between two adjacent M-Zn-O layers. Therefore, InMZnO 4 The crystals are between two adjacent M-Zn-O layers. It has a cleavage plane at

[0376] Ions 5201 generated in the high-density plasma region are attracted to the target 5230 by the electric field. The cleavage plane is then accelerated and collides with the target 5230. At this time, flat or planar particles are generated from the cleavage plane. Pellets 5200, which are pellet-shaped sputtered particles, are peeled off (see FIG. 48(A)).

[0377] The pellet 5200 is the portion sandwiched between the two cleavage planes shown in FIG. When only the 5200 is extracted, its cross section is as shown in Figure 48(B), and its top surface is as shown in Figure 48(C). ) The pellet 5200 is formed by the impact of the ion 5201. The structure may be distorted due to the peeling of pellet 5200. Particles 5203 are also ejected from the get 5230. Particles 5203 can be a single atom or a Therefore, the particle 5203 is called an atomic part. They can also be called icles.

[0378] The pellet 5200 is a flat or pellet-shaped pellet having a triangular, e.g., equilateral, plane. The pellet 5200 is a sputtered particle having a hexagonal, for example, a regular hexagonal plane. The sputtered particles are in the form of a plate or pellet. However, the shape of the pellet 5200 is not limited to a triangle or a hexagon, for example, it may be a shape made up of multiple triangles. For example, a quadrilateral (such as a rhombus) is made up of two triangles (such as an equilateral triangle). ) in some cases.

[0379] The thickness of the pellet 5200 is determined depending on the type of deposition gas. For example, 5200 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5200 has a width of 1 nm or more and 3 nm or less, preferably The thickness is 1.2 nm to 2.5 nm. For example, a target having an In-M-Zn oxide The ion 5201 is bombarded with the conductor 5230. As a result, the M-Zn-O layer, the In-O layer, and The pellet 5200 having three layers, the M-Zn-O layer, and the M-Zn-O layer, is peeled off. As the target 5230 peels off, the particle 5203 is also ejected from the target 5230.

[0380] As the pellet 5200 passes through the plasma 5240, the surface becomes negatively or positively charged. For example, the pellet 5200 may be in the plasma 5240. 2- negative charge from As a result, the oxygen atoms on the surface of the pellet 5200 may become negatively charged. In addition, when the pellet 5200 passes through the plasma 5240, the pellet 5200 may be mixed with the plasma 52 It may grow by combining with indium, element M, zinc, or oxygen in 40. .

[0381] The pellets 5200 and particles 5203 that have passed through the plasma 5240 are Some of the particles 5203 reach the surface because of their small mass. It may be discharged to the outside.

[0382] Next, the deposition of pellets 5200 and particles 5203 on the surface of the substrate 5220 is This will be explained with reference to FIG.

[0383] First, the first pellet 5200 is deposited on the substrate 5220. Since the film has a flat surface, it is deposited with the flat surface facing the surface of the substrate 5220 (see FIG. 50(A)). At this time, the charge on the surface of the pellet 5200 facing the substrate 5220 is discharged through the substrate 5220. do.

[0384] Next, the second pellet 5200 reaches the substrate 5220. Since the surface of the first pellet 5200 and the surface of the second pellet 5200 are charged, A repulsive force is generated (see Figure 50(B)).

[0385] As a result, the second pellet 5200 avoids the first pellet 5200 and falls on the substrate 5 The particles are deposited at a location slightly away from the surface of 220 (see Figure 50(C)). By repeating this process, On the surface of the substrate 5220, countless pellets 5200 are deposited to a thickness equivalent to one layer. Between the pellets 5200, there is a pile of pellets 5200. There will be areas where this is not the case.

[0386] Next, the particle 5203 reaches the surface of the substrate 5220 (see FIG. 50(D)).

[0387] Particles 5203 cannot accumulate in active areas such as the surface of pellet 5200. Therefore, the pellets 5200 are deposited so as to fill in the areas where the pellets 5200 are not deposited. The particles 5203 grow laterally between the pellets 5200 (also called lateral growth). In this way, the pellets 5200 are connected to each other. Particles 5203 are deposited until the area is filled. This mechanism is the deposition mechanism of the ALD method. Similar to a rhythm.

[0388] There are several possible mechanisms by which the particles 5203 grow laterally between the pellets 5200. For example, as shown in FIG. 50(E), the first M-Zn-O layer is connected to the side of the In this case, after the first M-Zn-O layer is formed, the In-O The first M-Zn-O layer is then connected to the second M-Zn-O layer (first mechanism).

[0389] Alternatively, for example, as shown in FIG. 51(A), first, a layer of M-Zn-O is formed on one side of the first layer. Next, one of the In-O layers is bonded to the In-O particles 5203 as shown in FIG. One particle 5203 is bonded to each surface. Next, the second layer M- In some cases, one particle 5203 is bonded to one side of the Zn-O layer to form a connection (see Fig. Mechanism 2).

[0390] In addition, Figure 51 (A), Figure 51 (B) and Figure 51 (C) occur simultaneously and are connected. In some cases (third mechanism).

[0391] As described above, the mechanism of lateral growth of the particles 5203 between the pellets 5200 However, other mechanisms may also be involved in the mechanism of permeability. There is also a possibility that particles 5203 may grow laterally between the nuclei 5200.

[0392] Therefore, even if multiple pellets 5200 are facing in different directions, The particles 5203 grow laterally and fill the gaps between the pellets 5200, forming a crystal. The formation of grain boundaries is suppressed. In addition, the particles 5203 smoothly connect the pellets 5200. In order to bind the molecules together, a crystal structure different from either single crystal or polycrystal is formed. A crystal structure having distortion between small crystal regions (pellets 5200) is formed. The regions between the crystalline regions are distorted crystalline regions, and therefore these regions are referred to as amorphous structures. I don't think it's appropriate to call him that.

[0393] When the particles 5203 have filled the gaps between the pellets 5200, the gap becomes as thick as the pellets 5200. A first layer having a thickness of 1.0 mm is formed. A new pellet 5200 is placed on the first layer. Then, a second layer is formed. This process is repeated to form a stack. A thin film structure having the following structure is formed (see FIG. 48(D)).

[0394] The deposition of the pellets 5200 also changes depending on the surface temperature of the substrate 5220. For example, if the surface temperature of the substrate 5220 is high, the pellet 5200 may be heated to the surface of the substrate 5220. As a result, pellet 5200 and another pellet 5200 However, the proportion of connections not via the particle 5203 increases, resulting in highly oriented CAAC-OS. The surface temperature of the substrate 5220 during the formation of the CAAC-OS film is 100° C. or higher and 500° C. or lower. ° C. or less, preferably 140° C. or more and less than 450° C., and more preferably 170° C. or more and 400° C. Therefore, when a large-area substrate of the 8th generation or later is used as the substrate 5220, It can be seen that almost no warping or the like occurs.

[0395] On the other hand, when the surface temperature of the substrate 5220 is low, the pellet 5200 is mixed with the surface of the substrate 5220. As a result, pellets 5200 do not pile up on each other. In the case of nc-OS, the pellet 520 Because 0 is negatively charged, pellets 5200 may accumulate at regular intervals. Therefore, although the orientation is low, the amorphous acid has a slight regularity. It has a denser structure than nitride semiconductors.

[0396] In addition, in CAAC-OS, the gaps between the pellets are extremely small, Large pellets of one type may be formed. The inside of one large pellet has a single crystal structure. For example, the size of the pellet is 10 nm to 200 nm, 15 It may be between 20 nm and 50 nm, or between 20 nm and 50 nm.

[0397] According to the above model, when the pellet 5200 is deposited on the surface of the substrate 5220, It is possible to form a CAAC-OS film even if the surface on which the film is to be formed does not have a crystalline structure. This indicates that the growth mechanism is different from epitaxial growth. CAAC-OS and nc-OS can be formed into uniform films even on large glass substrates. For example, when the structure of the surface (formation surface) of the substrate 5220 is an amorphous structure (e.g., amorphous It is possible to form a CAAC-OS film even on a substrate made of silicon oxide.

[0398] In addition, even if the surface of the substrate 5220 on which the film is to be formed is uneven, the film is formed according to the shape of the uneven surface. It can be seen that let 5200 is arranged.

[0399] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination. EXAMPLES

[0400] In this example, an OS transistor was fabricated and its cutoff frequency was measured. The cutoff frequency was measured as a function of the channel length of the transistor. Figure 31 shows the measurement results.

[0401] The fabricated OS transistor has the same device structure as the transistor TR1 shown in Figure 12. The gate insulating film 102 was formed using a silicon oxynitride film having a thickness of 10 nm. The gate electrode 104a and the conductive film 104b are formed of a 10 nm tungsten film. was formed of a laminated film of a titanium nitride film having a thickness of 10 nm and a tungsten film having a thickness of 10 nm. The back gate electrode (conductive film 105) is not provided. The semiconductor film is made of three layers of In-Ga-Zn oxide films. The second layer is In-Ga-Zn The n-oxide film is formed by heating the substrate while sputtering in order to have a crystal part oriented along the c-axis. The film was formed using a silicon wafer as the substrate.

[0402] OS transistors with channel lengths L of 60 nm, 100 nm, 180 nm, and 350 nm The frequency characteristics of each OS transistor were measured using a network analyzer. The cutoff frequency of each transistor was calculated. The number of transistors measured for each channel length L was 1. The value is 0.

[0403] From the measurement results in Figure 31, the cutoff frequency is estimated to be about 2 GHz when the channel length L is 60 nm. It has been shown that miniaturized OS transistors have excellent frequency characteristics. EXAMPLES

[0404] A circuit system according to one embodiment of the present invention was manufactured and various evaluations were performed. This article explains:

[0405] An OS transistor corresponding to the transistor TR1 shown in FIG. 12 was fabricated, and its electrical characteristics was evaluated.

[0406] The fabricated OS transistor has a channel length L / channel width W=60 / 60 nm. The back gate electrode was formed of a tungsten film having a thickness of 50 nm. The insulating film is a 100 nm thick silicon oxynitride film and a 50 nm thick aluminum oxide film. The oxide semiconductor film had a stacked structure of a 50-nm-thick silicon oxide film. A 20 nm thick In-Ga-Zn oxide (In:Ga:Zn=1:3:4 [atomic %]) A 15-nm-thick In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic %]) , and a 5-nm-thick In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic %]) The source and drain electrodes were made of tungsten films with a thickness of 20 nm. The gate insulating film was a silicon oxynitride film with a thickness of 10 nm. The structure is a laminate of a titanium nitride film with a thickness of 10 nm and a tungsten film with a thickness of 10 nm. .

[0407] FIG. 32 shows the Id-Vg (drain current-gate current) curve of the OS transistor fabricated in this example. In FIG. 32, the vertical axis is Id (drain current) and the horizontal axis is Vg ( The gate voltage is 0.1V and the drain voltage is 1.8V. No potential was applied to the back gate electrode, i.e., the measurement was performed in a floating state. Figure 2 shows data for 13 transistors on the same substrate, and also shows data for Vd=0.1V. The data for Vd = 1.8 V is shown overlapping the data for Id = 1.8 V. From the Id-Vg characteristics shown in Figure 32, It was confirmed that the OS transistor of this example had good transistor characteristics. .

[0408] Next, a circuit having an OS transistor with a device structure similar to that of the measurement target in FIG. 32 was fabricated. The circuit diagram of the circuit that was fabricated is shown in FIG. 33(A). The configuration is the same as that of the memory circuit 25 in FIG. 2(A) shown in the first embodiment. The transistor M2 and the capacitance element Cs.

[0409] FIG. 33(B) shows the layout of the circuit, and FIG. 33(C) shows the optical FIG. 33(C) shows an optical micrograph of an area corresponding to area 3000 in FIG. 33(B). The optical microscope photograph shown in Figure 33(C) shows that the desired circuit was fabricated. It was confirmed that this was the case.

[0410] In the fabricated circuit, transistor M1 is an OS transistor with W / L=60 / 60 nm. The transistor M1 is an OS transistor with W / L=60 / 60 nm. Here, two types of circuits were fabricated, one with a capacitance of 1 fF and the other with a capacitance of 3 fF. The former is referred to as a memory circuit Mem1, and the latter is referred to as a memory circuit Mem2.

[0411] The write operation of the fabricated memory circuits Mem1 and Mem2 was evaluated. FIG. 34 is a timing chart of a write operation. This corresponds to the operation of charging the capacitance element Cs (node ​​FN). A voltage of 1.1 V was applied to the wire WBL as a timing signal. A pulse of 3 V was also applied to the wire WWL. A signal was applied to make the transistor M1 conductive. The potential of the wiring SL was set to 0 V. Time T write is when the voltage of node FN is increased to 90% of the voltage of wiring WBL. In the operation example shown in FIG. write The potential of node FN is 0V. This is the time it takes for the potential of the wiring WBL to reach 1 V (approximately 90% of the potential of the wiring WBL, 1.1 V).

[0412] FIG. 35 shows the measurement results of the voltage of the node FN versus the write time. FIG. 35(A) shows the measurement results of the memory circuit Mem1, and FIG. 35(B) shows the measurement results of the memory circuit Mem2. The number of measurements was five for each. The voltage at node FN flows to the wiring RBL during the write operation. The current flowing through the wiring RBL was measured by measuring the drain current of the transistor M2. The voltage at node FN corresponds to the gate voltage of transistor M2. From the measured current value and the previously acquired Id-Vg characteristics of the transistor M2, The voltage of the FN terminal is calculated by applying 3V to the wire WWL. is applied.

[0413] The measurement results in Figure 35(A) and (B) show that the capacitance element Cs can be charged to 90% in an extremely short time. This shows that data can be written in an extremely short time. In (A), when the capacitance of the capacitance element Cs is 1 fF, the potential of the node FN is It is possible to increase the voltage from 0V to 1V. If the capacitance of the capacitance element Cs is 3 fF, the potential of the node FN is changed from 0 V to 1 V within 5 nsec. This shows that it is possible to increase

[0414] Next, the write time of the memory circuits (Mem1, Mem2) and the write transistor The relationship with mobility will be explained.

[0415] FIG. 36 shows the capacitance of the capacitance element Cs of the memory circuits (Mem1, Mem2) and the write time. The measured values ​​in FIG. 36 are values ​​obtained from the measurement results in FIG. 35. 6 shows the average write times of the five memory circuits Mem1 and the average write times of the five memory circuits Mem2. The average write time is shown for each of the memory circuits Mem1 and Mem2. The three curves in Figure 36 are the calculation results. The solid line indicates the operating environment at room temperature. This is the calculation result of the writing time at (27°C) (Calculation result 1). This is the result of increasing the mobility of the transistor M1 by a factor of 1 at room temperature (27°C). The dashed line shows the calculation results when the mobility of transistor M1 at room temperature (27°C) is doubled. (Calculation result 2), and the dotted line is the calculation result when the mobility is tripled (Calculation result 3). be.

[0416] From the calculation results shown in FIG. 36, the mobility of the transistor M1 can be increased by 1, 2, or 3 times. As a result, it was estimated that the writing time would be reduced. Also, the average value of the actually measured writing time substantially overlaps with the calculation result when the mobility is tripled. When the capacitance element Cs is 1 fF, the actually measured value was less than 5 nsec.

[0417] As described above, it was shown that the circuit fabricated in this embodiment can be applied to high-speed, low-power LSIs.

Embodiment

[0418] In this embodiment, an OS transistor (hereinafter sometimes referred to as "CAAC-OS FET") in which a semiconductor region is formed of a CAAC-OS film was fabricated, and the DC characteristics and RF characteristics of the CAAC-OS FE T were measured. Also, a memory circuit was prototyped using the CAAC-OS FET, and its operation was verified. Details are described below.

[0419] <Fabrication of CAAC-OS FET> The prototyped CAAC-OS FET had a channel length L of 60 nm and a channel width W of 60 nm. The CAAC-OS FET had the same device structure as the transistor prototyped in Example 1 and was fabricated by the same process. An underlying insulating film was formed on the silicon wafer surface, and the CAAC-OS FET was formed on the underlying insulating film. The equivalent film thickness of the underlying insulating film in terms of silicon oxide film was 390 nm. Also, the equivalent film thickness of the gate insulating film was 11 nm. The semiconductor film of the prototyped CAAC-OS FET was formed of a three-layer In-Ga-Z n oxide film. The second layer of In-Ga-Zn oxide film was formed by a sputtering apparatus while heating the silicon wafer so as to have a crystal part oriented in the c-axis direction.

[0420] The electrical characteristics of the fabricated CAAC-OS FET were measured. The measurement results are shown in FIGS. 37 to 39. The measurement data in FIGS. 37 to 39 are those of a group of 5,000 CAAC-OS FETs connected electrically in parallel. Each CAAC-OS FET has L = 60 nm and W = 60 nm. That is, FIGS. 37 to 39 show the electrical characteristics of a CAAC-OS FET with W / L = 300 μm / 60 nm.

[0421] <DC Characteristics> FIG. 37(A) shows the drain current-gate voltage (Id-Vg) characteristics of a CAAC-OS FET with W / L = 300 μm / 60 nm, and FIG. 37(B) shows the drain current-drain voltage (Id-Vd) characteristics. The on-current Ion at Vg = 2.2 V and Vd = 1.0 V is 2.87 mA, and the S value (subthreshold swing value) is 0.09 V / dec. The off-current is below the measurement lower limit of 1×10 A, which indicates the characteristic of extremely low leakage current of the CAAC-OS FET. -13

[0422] FIG. 38 shows the transconductance g characteristics of a CAAC-OS FET with W / L = 300 μm / 60 nm. m The maximum values of g at drain voltages Vd of 0.1 V, 1.0 V, 2.0 V, 3.0 V, 4 .0 V are 0.4 mS, 3.9 mS, 6.5 mS, 8.0 m m S, 9.3 mS, respectively. The gate voltages Vg at which gm is maximum are 1.90 V , 2.20 V, 2.35 V, 2.65 V, 2.85 V, respectively.

[0423] <RF Characteristics> A CAAC-OS FET with W / L = 300 μm / 60 nm (W / L = 60 nm / 60 n Performed S-parameter measurements on 5,000 CAAC-OS FETs of m and obtained RF gain ( current gain |H21| and maximum unidirectional power gain Ug), and derived the parameter cutoff frequency ( f T ) and the maximum oscillation frequency (f max ).

[0424] Fig. 39 shows the RF gain (|H21|, Ug) versus frequency. Vd = 1.0 V, V g = 2.2 V. Fig. 39 shows that f T and f max are both 1.9 GHz, as shown. These values are after de-embedding using open and short calibration. edding.

[0425] Fig. 40 shows the drain voltage Vd dependence of f T and f max . f and f T are plotted under the voltage conditions where gm shown in Fig. 38 is at its maximum max value. At drain voltages Vd of 0 .1 V, 1.0 V, 2.0 V, 3.0 V, 4.0 V, f T is 0.2 GH z, 1.9 GHz, 3.4 GHz, 4.7 GHz, 5.6 GHz respectively, and f max is respectively 0.2 GHz, 1.9 GHz, 3.3 GHz, 4.2 GHz, 4.8 GHz . Fig. 40 shows that both f T and f max increase as Vd increases.

[0426] <Possibility of Application of CAAC-OS FET to LSI> Fabricated a circuit with a CAAC-OS FET and passive elements and verified the application of the CAAC-OS FET to LS I. Here, as an example, the verification results of the memory circuit shown in Fig. 41 are The memory circuit shown in FIG. 41 has a circuit configuration similar to that of the memory circuit 25 shown in FIG. The memory cell has a write transistor MW, a read transistor MR, and a capacitance element Cs. The write transistor MW and the read transistor MR are W / L = 60 nm / 60 The load capacitance C of node FN is load is 1.0fF, Two types of memory circuits were fabricated, one with a load capacitance of 0.01 fF and the other with a load capacitance of 0.01 fF. lo ad is the sum of the capacitance element Cs and the parasitic capacitance.

[0427] The write time of the memory circuit shown in Figure 41 was measured. The measurement results are shown in Figure 42. The relationship between the load capacitance of the memory circuit and the write time is shown below. The measurement method is shown below.

[0428] In the initial state, the potential of node IN is set to 0.0V, and the potential of node OSG is set to 3.0V. This sets the potential of node FN to 0.0V, the potential of node OSG to -1.0V, Apply 1.1V to node IN. Apply a pulse (-1.0V to 3.0V) to node OSG. The drain current of the read transistor MR (the current flowing between node S and node D) The current is measured from the Id-Vg characteristics of the read transistor MR that were measured in advance. The potential of node FN was estimated. This measurement was performed by changing the pulse width applied to node OSG. The pulse width is the time during which a potential of 3.0 V is applied to the node OSG. The write time is the pulse width at which the potential of FN becomes 1.0V (90% of the potential of node IN, 1.1V). The solid line in FIG. 42 shows the calculation results. load When the capacitance is 3.0fF, the write time is 4.0nsec, and when it is 1.0fF, , it shows that the write time is 2.0 nsec.

[0429] <Summary> In this example, a CAAC-OS FET with W / L=60 nm / 60 nm was fabricated, and The characteristics and RF characteristics were measured. At W=300μm, the measurement limit (1×10 -13 A) Below at off-state current, S value of 0.09V / dec, Vg=2.2V, Vd=1.0V. 9GHz f T , 1.9GHz f max The write speed of the memory circuit is , 4.0nsec when the load capacitance of the floating node is 3.0fF, 2.0 It was nsec.

[0430] CAAC-OS FET with L=60nm is expected to be applied to LSIs such as low-power memory devices. In addition, the RF characteristics of transistors will improve as a result of miniaturization. This is well known for CAAC-O, which has a technology node smaller than 60 nm. S FETs can achieve higher frequency f T , f max This means that the present embodiment By miniaturizing CAAC-OS FETs, microwave integrated circuits in the GHz frequency band can be realized. It was shown that application to the MIC is possible. [Explanation of symbols]

[0431] 10 Circuit System 12 Memory Cell Array 14 Peripheral circuits 21 Transistor 22 Transistor 23 Capacitive element 24 Transistor 25 Memory circuit 26 Memory circuit 27 Memory circuit 31 Substrate 32 Conductive Film 33 Insulating film 34 Semiconductor Film 34a Semiconductor film 34b Semiconductor film 34c Semiconductor film 35 Conductive Film 36 Conductive Film 37 Insulating Film 38 Conductive Film 42 Conductive Film 43 Insulating Film 44 Semiconductor Film 44a Semiconductor film 44b Semiconductor film 44c Semiconductor film 45 Conductive Film 46 Conductive Film 47 Insulating Film 48 Conductive Film 100 Substrates 101 Semiconductor film 101a Semiconductor film 101b Semiconductor film 101c Semiconductor film 102 Gate insulating film 103 Gate electrode 104a Conductive film 104b Conductive film 105 Conductive film 114 Insulating film 115 Insulating film 116 Insulating film 118a Plug 118b Plug 133 Conductive Film 134 Plug 141 Plug 142 Plug 143 Plug 144 Plug 145 Plug 151 Conductive film 152 Conductive Film 153 Conductive Film 155 Conductive Film 156 Insulating Film 171a Low resistance region 171b Low resistance region 202 Gate insulating film 203 Gate electrode 204a Conductive film 204b Conductive film 205 Conductive Film 212 Insulating film 213 Insulating film 216 Insulating film 291 layers 292 layers 293 layers 294 layers 295 layers 296 layers 297 layers 300 Memory Cell Array 700 Transistors 701 Transistor 702 Transistor 703 Transistor 704 Transistor 705 Capacitive element 706 Diode 711 Plug 712 Plug 713 Plug 714 Plug 721 Wiring 722 Wiring 723 Wiring 724 Wiring 730 Substrate 731 Element Isolation Layer 732 Insulating film 733 Insulating Film 735 Substrate 741 Wiring 742 Wiring 743 Wiring 800 RF Devices 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 Case 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 Memory circuit 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2001 Impurity region 2002 Impurity region 2003 Gate electrode 2004 Gate insulating film 2005 Sidewall insulation layer 2011 Circuit 2012 Circuit 2013 Circuit 2100 Transistor 2200 Transistor 2201 Board 2202 Wiring 2203 Plug 2204 Element isolation layer 2205 Wiring 2206 Wiring 2207 Insulating film 2208 Insulating film 2211 Semiconductor substrate 2212 Insulating film 2213 Gate electrode 2214 Gate insulating film 2215 Impurity region 2216 Impurity region 2300 Capacitive element 3000 area 4000 RF Devices 5100 pellets 5120 Circuit Board 5161 area 5200 pellets 5201 AEON 5203 particles 5220 PCB 5230 Target 5240 Plasma 5260 Heating mechanism

Claims

1. A first circuit and a second circuit are included, each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a first electrode of the capacitance element electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; having each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitance element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

2. A first circuit and a second circuit are included, each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a first electrode of the capacitance element electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; a second insulating film having a region located above the sixth conductive film; a seventh conductive film having a region located above the second insulating film and electrically connected to the first conductive film; having each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitance element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

3. A first circuit and a second circuit are included, each of the first circuit and the second circuit includes a first transistor, a second transistor, and a capacitance element; one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor; the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor; a first electrode of the capacitance element electrically connected to a gate of the first transistor, a first semiconductor film having a channel region of the first transistor; a first conductive film having a region in contact with an upper surface of the first semiconductor film; a second conductive film having a region in contact with an upper surface of the first semiconductor film; a third conductive film having a region located above the first semiconductor film and functioning as one electrode of the capacitor; a fourth conductive film having a region located above the third conductive film and functioning as the other electrode of the capacitor; a first insulating film having a region located above the fourth conductive film; a second semiconductor film having a region located above the first insulating film and having a channel region of the second transistor; a fifth conductive film having a region in contact with an upper surface of the second semiconductor film and electrically connected to the third conductive film; a sixth conductive film having a region located above the second semiconductor film and functioning as a gate of the second transistor; a second insulating film having a region located above the sixth conductive film; a seventh conductive film having a region located above the second insulating film and electrically connected to the first conductive film; an eighth conductive film electrically connected to the second conductive film; having each of the seventh conductive film and the eighth conductive film has a region in contact with an upper surface of the second insulating film; each of the third conductive film and the fourth conductive film overlaps with the first semiconductor film; the first circuit and the second circuit share one of the second conductive films; the first transistor has a function of causing a current to flow between the first conductive film and the second conductive film in accordance with an amount of charge held in the capacitance element when the first conductive film and the second conductive film are electrically connected at least through a channel formation region of the first transistor; Semiconductor device.

4. In any one of claims 1 to 3, the second semiconductor film includes an oxide semiconductor; Semiconductor device.

Images