Semiconductor device

Abstract

To provide a semiconductor device capable of detecting a void with a high accuracy.SOLUTION: A semiconductor device according to the present disclosure, comprises: a mounting substrate that includes a first surface and a second surface; a semiconductor substrate that includes a third surface and a fourth surface, and is flip-chip mounted onto the mounting substrate so that the third surface is opposite to the second surface; a capacitor in which a first electrode is provided to the second surface of the mounting substrate, and a second electrode is provided to the second surface of the mounting substrate or the third surface of the semiconductor substrate; a conductive first pillar that is extended from the first electrode of the capacitor; a conductive second pillar that is extended from the second electrode of the capacitor; and a mold that fills the second surface of the mounting substrate and the third surface of the semiconductor substrate.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a mounting evaluation device capable of measuring the dielectric constant of an underfill formed in the gap between a mounting evaluation chip and a mounting evaluation board. This mounting evaluation device is provided with a measuring capacitance unit formed of a pair of electrode patterns arranged on the underside of the mounting evaluation chip to measure capacitance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-205178 A Summary of the Invention [Problem to be solved by the invention]

[0004] There is a semiconductor device in which a microwave or millimeter wave band MMIC (Monolithic Microwave Integrated Circuit) is flip-chip mounted on a mounting substrate having a plurality of electrodes on the back side. The distance between the MMIC and the mounting substrate is, for example, about 50 to 100 μm. In such a structure, the mold cannot be filled in a part of the narrow area between the MMIC and the mounting substrate, and voids may occur locally. Voids are likely to occur, for example, in a case where a mold sealing flow without an underfill process is adopted from the viewpoint of reducing the number of processes and reducing costs. In general, the mold filling conditions are optimized in advance and set to conditions that do not cause voids. However, voids may occur due to variations in materials or devices, unexpected factors, etc., during repeated production of a large number of products.

[0005] The mounting evaluation device in Patent Document 1 detects voids in the underfill by verifying the amount of change in capacitance. However, even though the capacitor is covered with a mold, if a void occurs between the MMIC and the mounting board, it is difficult to detect the void.

[0006] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device capable of detecting voids with high accuracy. [Means for solving the problem]

[0007] A semiconductor device according to a first disclosure includes a mounting substrate having a first surface and a second surface opposite to the first surface, a semiconductor substrate having a third surface and a fourth surface opposite to the third surface and flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate, a capacitor having a first electrode which is one of a positive electrode and a negative electrode provided on the second surface of the mounting substrate and a second electrode which is the other of the positive electrode and the negative electrode provided on the second surface of the mounting substrate or the third surface of the semiconductor substrate, a conductive first pillar extending from the first electrode of the capacitor toward the semiconductor substrate, a conductive second pillar extending from the second electrode of the capacitor toward the side of the mounting substrate and the semiconductor substrate facing the second electrode, and a mold which fills a space between the second surface of the mounting substrate and the third surface of the semiconductor substrate.

[0008] A semiconductor device according to a second disclosure includes a mounting substrate having a first surface and a second surface opposite to the first surface, a semiconductor substrate having a third surface and a fourth surface opposite to the third surface and flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate, a first pattern provided on the second surface of the mounting substrate, a second pattern provided on the second surface of the mounting substrate, an inductor or a capacitor formed between the first pattern and the second pattern, and a mold filling a space between the second surface of the mounting substrate and the third surface of the semiconductor substrate, wherein at least a portion of the inductor or the capacitor is provided at a height intermediate between the second surface of the mounting substrate and the third surface of the semiconductor substrate in a direction perpendicular to the second surface of the mounting substrate.

[0009] A semiconductor device according to a third disclosure comprises a mounting substrate having a first surface and a second surface opposite to the first surface, a semiconductor substrate having a third surface and a fourth surface opposite to the third surface and flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate, a capacitor or inductor formed on the second surface of the mounting substrate, and a mold filling the space between the second surface of the mounting substrate and the third surface of the semiconductor substrate, and a recess is formed on the second surface of the mounting substrate directly below the capacitor or inductor. Effect of the Invention

[0010] In the semiconductor device according to the first disclosure, the first pillar and the second pillar are provided. Therefore, even if the surface of the mounting substrate is covered with a mold and voids are generated, the voids can be detected. Therefore, the voids can be detected with high accuracy. In the semiconductor device according to the second disclosure, at least a portion of the inductor or capacitor is provided at an intermediate height between the second surface of the mounting substrate and the third surface of the semiconductor substrate. Therefore, even if the surface of the mounting substrate is covered with a mold and voids are generated, the voids can be detected. Therefore, the voids can be detected with high accuracy. In the semiconductor device according to the third disclosure, a recess is formed in the mounting substrate. This makes it possible to prevent a state in which voids occur even though the surface of the mounting substrate is covered with a mold. As a result, it is possible to detect voids with high accuracy. [Brief description of the drawings]

[0011] [Figure 1A] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 1B] FIG. 2 is a plan view of a mounting board according to the first embodiment. [Figure 1C] FIG. 2 is an enlarged view of the capacitor in accordance with the first embodiment. [Diagram 2] 1 is a diagram showing a state in which voids are generated in a semiconductor device according to a first comparative example. FIG. [Figure 3A] FIG. 11 is a cross-sectional view of a semiconductor device according to a second comparative example. [Figure 3B] FIG. 11 is a plan view of a mounting board according to a second comparative example. [Figure 4A] FIG. 13 is a diagram showing a state in which there are no voids. [Figure 4B] FIG. 13 is a diagram illustrating an example of a void. [Figure 4C] FIG. 13 is a diagram illustrating an example of a void. [Figure 5A] FIG. 13 is a diagram illustrating an example of a void. [Figure 5B] FIG. 13 is a diagram illustrating an example of a void. [Figure 5C] FIG. 13 is a diagram illustrating an example of a void. [Figure 6A] 5A to 5C are diagrams illustrating the function of a recess according to the first embodiment. [Figure 6B] 5A to 5C are diagrams illustrating the function of a recess according to the first embodiment. [Figure 6C] 5A to 5C are diagrams illustrating the function of a recess according to the first embodiment. [Figure 6D] 5A to 5C are diagrams illustrating the function of a recess according to the first embodiment. [Figure 7A] This is the calculation result of the S parameters of the capacitor. [Figure 7B] This is the calculation result of the S parameters of the capacitor. [Figure 7C] This is the calculation result of the S parameters of the capacitor. [Figure 8A] 1 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 8B] FIG. 4 is a plan view of a mounting board according to a first modified example of the first embodiment. [Figure 9A] This is the calculation result of the S parameters of the inductor. [Figure 9B] This is the calculation result of the S parameters of the inductor. [Figure 9C] This is the calculation result of the S parameters of the inductor. [Figure 10] 13 is a diagram showing a structure of a pillar according to a second modified example of the first embodiment. FIG. [Figure 11A] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 11B] FIG. 11 is a cross-sectional view taken along the line BB' of the semiconductor device according to the second embodiment. [Figure 11C] FIG. 11 is a cross-sectional view taken along line AA' of a semiconductor device according to a second embodiment. [Figure 12A] These are the calculation results of the S parameters of the inductor and capacitor. [Figure 12B] These are the calculation results of the S parameters of the inductor and capacitor. [Figure 12C] These are the calculation results of the S parameters of the inductor and capacitor. [Figure 13A] These are the calculation results of the S parameters of the inductor and capacitor. [Figure 13B] These are the calculation results of the S parameters of the inductor and capacitor. [Figure 14A] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 14B] FIG. 11 is a cross-sectional view taken along the line CC' of the semiconductor device according to the third embodiment. [Figure 14C] FIG. 11 is a cross-sectional view taken along the line BB' of the semiconductor device according to the third embodiment. [Figure 14D]FIG. 11 is a cross-sectional view taken along the line D-D' of a semiconductor device according to a third embodiment. [Figure 15A] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 15B] FIG. 11 is a cross-sectional view taken along the line CC' of the semiconductor device according to the fourth embodiment. [Figure 15C] FIG. 11 is a cross-sectional view taken along the line BB' of a semiconductor device according to a fourth embodiment. [Figure 15D] FIG. 11 is a cross-sectional view taken along the line AA' of a semiconductor device according to a fourth embodiment. [Figure 16A] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 16B] FIG. 13 is a cross-sectional view taken along the line CC' of a semiconductor device according to a fifth embodiment. [Figure 16C] FIG. 13 is a cross-sectional view taken along the line BB' of a semiconductor device according to a fifth embodiment. [Figure 17A] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 17B] FIG. 21 is a cross-sectional view taken along the line BB' of the semiconductor device according to the sixth embodiment. [Figure 17C] FIG. 21 is a cross-sectional view taken along the line AA' of a semiconductor device according to a sixth embodiment. [Figure 18] FIG. 23 is a plan view of a mounting board according to a modified example of the sixth embodiment. [Figure 19A] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 19B] FIG. 13 is a cross-sectional view taken along the line BB' of a semiconductor device according to a seventh embodiment. [Figure 19C] FIG. 21 is a cross-sectional view taken along the line AA' of a semiconductor device according to a seventh embodiment. [Figure 20] FIG. 23 is a plan view of a mounting board according to a modified example of the seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Semiconductor devices according to the embodiments will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0013] Embodiment 1 FIG. 1A is a cross-sectional view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 includes a mounting substrate 10 and a semiconductor substrate 15 flip-chip mounted on the mounting substrate 10. The mounting substrate 10 has a first surface 11 and a second surface 12 opposite to the first surface 11. The semiconductor substrate 15 has a third surface 13 and a fourth surface 14 opposite to the third surface 13. The third surface 13 of the semiconductor substrate 15 faces the second surface 12 of the mounting substrate 10. The distance between the mounting substrate 10 and the semiconductor substrate 15 is, for example, 50 to 100 μm. The mounting substrate 10 may be a multilayer substrate. The semiconductor substrate 15 is, for example, a microwave band or millimeter wave band MMIC. The space between the second surface 12 of the mounting substrate 10 and the third surface 13 of the semiconductor substrate 15 is filled with a mold, but is omitted in FIG. 1A.

[0014] The mounting substrate 10 and the semiconductor substrate 15 are electrically connected by a connection structure including, for example, an electrode 21, a solder 22, a pillar 23, and an electrode 24. Although one connection structure is shown in FIG. 1A, a plurality of connection structures may be provided between the mounting substrate 10 and the semiconductor substrate 15.

[0015] FIG. 1B is a plan view of the mounting board 10 according to the first embodiment. That is, FIG. 1B is a cross-sectional view taken along line B-B' in FIG. 1A. The semiconductor device 100 includes a capacitor 30 formed on the second surface 12 of the mounting board 10. The capacitor 30 is, for example, an interdigital capacitor. The capacitor 30 has patterns 31 and 32, and wirings 33 and 34 connected to the patterns 31 and 32, respectively. The wiring 33 corresponds to a first electrode, which is one of the positive and negative electrodes of the capacitor 30. The wiring 34 corresponds to a second electrode, which is the other of the positive and negative electrodes of the capacitor 30. In this embodiment, the first electrode and the second electrode of the capacitor 30 are both provided on the second surface 12 of the mounting board 10. As shown in FIG. 1B, the multiple wirings 33 and the multiple wirings 34 are provided alternately. The number of the wirings 33 and the number of the wirings 34 may be one or more.

[0016] The wiring 33 is electrically connected to any of the multiple terminals 17 provided on the first surface 11 of the mounting substrate 10 through the pattern 31 and the via hole 19. The wiring 34 is electrically connected to any of the multiple terminals 17 provided on the first surface 11 of the mounting substrate 10 through the pattern 32 and the via hole 19. The multiple terminals 17, which are back surface electrodes, are input / output ports for electrical signals to the semiconductor device 100, and are terminals for measuring S parameters and the like, which will be described later.

[0017] A recess 18 is formed on the second surface 12 of the mounting substrate 10 directly below the wiring 33 or wiring 34 of the capacitor 30. As shown in Fig. 1B, the recess 18 may be formed longer than the region in which the wirings 33 and 34 are provided in a direction perpendicular to the direction in which the wirings 33 and 34 extend.

[0018] FIG. 1C is an enlarged view of the capacitor 30 according to the first embodiment. The semiconductor device 100 includes a plurality of conductive pillars 40. The plurality of pillars 40 includes a plurality of first pillars 41 and a plurality of second pillars 42. The conductive first pillar 41 extends from the wiring 33 of the capacitor 30 toward the semiconductor substrate 15 facing the wiring 33. The second pillar 42 extends from the wiring 34 of the capacitor 30 toward the semiconductor substrate 15 facing the wiring 34. The plurality of pillars 40 are provided, for example, in a direction perpendicular to the second surface 12 of the mounting substrate 10, up to a position higher than the middle between the second surface 12 of the mounting substrate 10 and the third surface 13 of the semiconductor substrate 15. In other words, when the distance between the mounting substrate 10 and the semiconductor substrate 15 is L1, the pillars 40 are provided up to a position higher than L1 / 2. 1A to 1C, a plurality of first pillars 41 and a plurality of second pillars 42 are provided, but it is sufficient that one or more first pillars 41 and one or more second pillars 42 are provided.

[0019] 2 is a diagram showing a state in which a void B1 occurs in a semiconductor device 101 according to a first comparative example. In the semiconductor device 101, a semiconductor substrate 15 is flip-chip mounted on a mounting substrate 10. A heat sink 82 for heat dissipation is die-bonded to the upper surface of the semiconductor substrate 15 by conductive resin 81 or the like as necessary. The periphery of the mounting substrate 10, the semiconductor substrate 15, and the heat sink 82, and the space between the mounting substrate 10 and the semiconductor substrate 15 are sealed by a mold 80. The upper surface of the mold 80 is ground by back grinding or the like so that the heat sink 82 is exposed from the mold 80. The entire surface other than the surface on which the terminals 17 are provided is covered by a shield 83 made of metal.

[0020] 1A, the mold 80, the heat sink 82, and the shield 83 are omitted, but the mold 80 is also provided in the semiconductor device 100. The semiconductor device 100 may also be provided with a heat sink 82 and a shield 83, if necessary.

[0021] In a semiconductor device 101 as shown in Fig. 2, the mold 80 may not be able to fill a part of the narrow region between the mounting substrate 10 and the semiconductor substrate 15, causing a void B1 to occur locally. In the example of Fig. 2, a void B1 is formed near the center of the semiconductor substrate 15, extending from the second surface 12 to the third surface 13. If moisture precipitates in such a void and vaporizes due to a sudden temperature rise or the like, causing a volume expansion, the mold 80 may burst, crack, or peel off from the mounting substrate 10 or the semiconductor substrate 15. This may cause the product to be destroyed.

[0022] The filling conditions of the mold 80 are optimized so that no voids are generated. However, there is a possibility that voids may occur unexpectedly due to manufacturing variations. In order to detect voids, for example, a sample is taken from the product and the sample is ground to check for the presence or absence of voids. However, such samples are destroyed and cannot be shipped.

[0023] Fig. 3A is a cross-sectional view of a semiconductor device 102 according to a second comparative example. Fig. 3B is a plan view of a mounting substrate 10 according to the second comparative example. In the semiconductor device 102, a capacitor 30 is disposed on a second surface 12 of the mounting substrate 10.

[0024] FIG. 4A is a diagram showing a state where there is no void. FIGS. 4B-C and 5A-C are diagrams for explaining examples of voids. In the state of FIG. 4A, the mold 80 covers the capacitor 30. In the state of FIG. 4B, the capacitor 30 is not covered by the mold 80 because of the presence of the void B2. According to the semiconductor device 102, the presence or absence of the void B2 can be determined by detecting the difference in the capacitance value of the capacitor 30 in these two states from the S parameter or the like. The S parameter can be measured using the terminal 17. Moreover, according to the semiconductor device 102, it is also possible to detect the void B4 generated on the surface of the mounting substrate 10 as shown in FIG. 5A. Moreover, by disposing the capacitor 30 on the semiconductor substrate 15 side, it is also possible to detect the void B5 generated on the surface of the semiconductor substrate 15 as shown in FIG. 5B.

[0025] However, in the semiconductor device 102 according to the comparative example, as shown in Fig. 5C, it is difficult to detect void B6 when void B6 occurs even though capacitor 30 is covered by mold 80. Also, in the state of Fig. 4C, void B3 occurs in a part of capacitor 30, and mold 80 partially covers capacitor 30. In this case, since the difference in capacitance value between the presence and absence of void B3 is small, it may be difficult to detect void B3 only from the difference in S parameters due to measurement variation.

[0026] It is also possible to provide the positive and negative electrodes of the capacitor 30 on the mounting substrate 10 and the semiconductor substrate 15, respectively, and detect the difference in capacitance due to the presence or absence of the void B3 or void B6. However, in this case, the difference in capacitance becomes extremely small, so it may be difficult to detect the voids B3 and B6 only based on the difference in the S parameters, etc., due to measurement variations. In addition, in general, a pattern layout is performed in an MMIC to achieve the intended function. For this reason, when the capacitor 30 is applied to an actual product, it is not always possible to freely arrange a pattern for void detection on the MMIC.

[0027] In particular, in order to increase the filling property of the mold, the surfaces of the mounting substrate 10 and the semiconductor substrate 15 may be subjected to O2 plasma treatment or the like to improve wettability. When such treatment is performed, voids B6 may occur even though the surfaces of the mounting substrate 10 and the semiconductor substrate 15 are covered with the mold 80.

[0028] Next, the effect of the pillar 40 of this embodiment will be described. The semiconductor device 100 of this embodiment is provided with a first pillar 41 and a second pillar 42. Therefore, the capacitance value of the capacitor 30 changes depending on the presence or absence of a void B6 occurring between the mounting substrate 10 and the semiconductor substrate 15. That is, when at least a part of the pillar 40 is covered with the void B6, the capacitance value of the capacitor 30 changes compared to when the void B6 does not exist. Therefore, as shown in FIG. 5C, even in a state in which the void B6 occurs despite the surface of the mounting substrate 10 being covered with the mold 80, the void B6 can be detected by the difference in the S parameter. Therefore, the void can be detected with high accuracy.

[0029] Next, the effect of the recess 18 of this embodiment will be described. FIGS. 6A to 6D are diagrams for explaining the function of the recess 18 according to the first embodiment. FIG. 6A shows a state in which the recess 18 is not formed and the entire capacitor 30 is in contact with the mounting substrate 10. The mounting substrate 10 is a glass epoxy substrate or the like, and has a relative dielectric constant of about 4. In this case, the capacitance of the mounting substrate 10 becomes dominant. Assuming that there is no mold 80, the total capacitance is C, the capacitance of the capacitor 30 is C1, and the capacitance of the pillar 40 is C2. In this case, C=C1+C2...(Formula 1). When the capacitor 30 is in contact with the mounting substrate 10, C1>C2, and C1 becomes dominant in the total capacitance.

[0030] Next, assume that the mold 80 with a relative dielectric constant of 2 to 4 is filled. At this time, the change in C1, whose capacitance value is determined by the dielectric constant of the mounting substrate 10, is small. Also, a change ΔC2 occurs in C2 that is equivalent to the change in the relative dielectric constant. Therefore, the total capacitance is approximately C = C1 + C2 + ΔC2 ... (Equation 2). Since C1 > C2 as described above, the proportion of the increase ΔC2 in C is small.

[0031] FIG. 6B shows a state in which the mounting substrate 10 is dug directly below the capacitor 30 to form a recess 18. In this case, in formula 1, C1 and C2 are both capacitances between metals via air. Therefore, when the mold 80 is filled, changes ΔC1 and ΔC2 equivalent to the change in the relative dielectric constant occur in C1 and C2. The total capacitance is C=C1+ΔC1+C2+ΔC2... (formula 3). The proportion of the increase ΔC1+ΔC2 in C is determined by the relative dielectric constant of the filled mold, and is larger than when the recess 18 is not present.

[0032] In this way, the change in capacitance due to the presence or absence of the void B7 is increased by the recess 18, thereby improving the detection sensitivity. This may enable detection of a small partial void B3 as shown in FIG. 4C.

[0033] Fig. 6C shows a state where voids B8 occur even though recesses 18 are not formed and capacitor 30 is covered with mold 80. In contrast, when recesses 18 are formed as shown in Fig. 6D, mold 80 enters recesses 18, making it difficult for mold 80 to fill between the wiring of capacitor 30. In other words, it is possible to make it difficult for voids to occur even though the surface of mounting substrate 10 is covered with mold 80. As a result, it is possible to ensure the change in capacitance depending on the presence or absence of voids, and voids can be detected with high accuracy.

[0034] 7A to 7C show the calculation results of the S parameters of the capacitor 30. In FIG. 7A to 7C, the change in the insertion loss S21 at 1 GHz when the capacitance value is changed by ±10% is shown. FIG. 7A shows the case of C=0.2 pF, and the insertion loss is 18.08 dB. FIG. 7B shows the case of C=0.18 pF, and the insertion loss is 18.99 dB. FIG. 7C shows the case of C=0.22 pF, and the insertion loss is 17.27 dB. As shown above, it can be seen that the S parameters change with the change in the capacitance value. As a method for determining the presence or absence of a void, a frequency at which the change in the S parameters is significant or an S parameter other than the insertion loss may be selected. As a method for detecting a void, any electrical characteristic evaluation using the capacitor 30 can be adopted.

[0035] As described above, according to the present embodiment, voids can be detected non-destructively and with high accuracy as described above.

[0036] 1A to 1C show an example in which the semiconductor device 100 has both the features of the pillars 40 and the recesses 18. However, as described above, the effect of accurately detecting voids can be obtained by using only one of the pillars 40 or the recesses 18. In other words, the semiconductor device 100 may have only one of the features of the pillars 40 and the recesses 18 depending on the allowable void detection accuracy.

[0037] 8A is a cross-sectional view of a semiconductor device 200 according to a first modified example of the first embodiment. FIG. 8B is a plan view of a mounting substrate 10 according to a first modified example of the first embodiment. In the semiconductor device 200, an inductor 250 is formed on the second surface 12 of the mounting substrate 10 instead of the capacitor 30 and the pillar 40. A recess 18 is formed on the second surface 12 of the mounting substrate 10 directly below the inductor 250. The inductor 250 has an inductor wiring 53 that connects between the patterns 31 and 32. As shown in FIG. 8A, the inductor wiring 53 may be formed on a substrate 55.

[0038] 9A to 9C show the calculation results of the S parameters of the inductor 250. In FIG. 9A to 9C, the change in the return loss S1 at 1 GHz when the inductance value is changed by ±10% is shown. FIG. 9A shows the case of L=1 nH, and the return loss is 24.05 dB. FIG. 9B shows the case of L=0.9 nH, and the return loss is 24.97 dB. FIG. 9C shows the case of L=1.1 nH, and the return loss is 23.23 dB. It can be seen that the S parameters change according to the change in the inductance value. From this result, it can be seen that the presence or absence of a void can be detected by disposing the inductor 250 between the mounting board 10 and the semiconductor substrate 15. The method of determining the presence or absence of a void may select an S parameter other than the frequency or return loss at which the change in the S parameter is significant. Any electrical characteristic evaluation using the inductor 250 can be adopted as the method of detecting a void.

[0039] 8A, the inductor wiring 53 may be formed thick. By forming the inductor wiring 53 thick, for example, a void B6 occurring between the mounting substrate 10 and the semiconductor substrate 15 can be detected. If the distance between the mounting substrate 10 and the semiconductor substrate 15 is L1, the inductor wiring 53 may be provided up to a position of, for example, 0.2×L1 to 0.8×L1. This is because if the inductor wiring 53 is formed too low, the void B6 cannot be detected, and if the inductor wiring 53 is formed too high, it becomes difficult to fill the mold 80.

[0040] As another modification of this embodiment, the wiring 33, 34 of the capacitor 30 may be thickened to adjust the height direction position where the capacitor 30 or the pillar 40 is formed. FIG. 10 is a diagram showing the structure of the pillar 40 according to a second modification of the first embodiment. Each of the first pillar 41 and the second pillar 42 according to the second modification has a pier metal 48 provided on the wiring 33 or the wiring 34, and a pillar part 49 provided on the pier metal 48. In this way, the height of the pillar 40 may be adjusted by arranging the pier metal 48. This makes it possible to detect the void B6 in the middle part between the mounting board 10 and the semiconductor substrate 15. In addition, the capacitor 30 of this embodiment may be replaced with a part whose capacitance changes depending on whether or not there is a mold 80 around it, and a pier metal that adjusts the height of the part.

[0041] These modifications can be appropriately applied to the semiconductor device according to the following embodiments. Note that the semiconductor device according to the following embodiments has many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0042] Embodiment 2 FIG. 11A is a cross-sectional view of the semiconductor device 300 according to the second embodiment. FIG. 11B is a B-B' cross-sectional view of the semiconductor device 300 according to the second embodiment. FIG. 11C is an A-A' cross-sectional view of the semiconductor device according to the second embodiment. The A-A' cross-section corresponds to the bottom surface of the recess 18. As shown in FIG. 11C, the semiconductor device 300 includes an inductor 350 formed on the bottom surface of the recess 18 and connected in parallel with the capacitor 30. The other structures are similar to those of the first embodiment.

[0043] Inductor 350 is, for example, a meander-line type inductor. Inductor 350 has, for example, a substrate 55 and inductor wiring 53 formed on substrate 55. Inductor wiring 53 connects patterns 51 and 52. Pattern 51 is connected to pattern 31 and terminal 17 by via hole 19. Pattern 52 is connected to pattern 32 and terminal 17 by via hole 19.

[0044] In this embodiment, a void can be detected by the change in the resonance frequency of capacitor 30 and inductor 350 due to the presence or absence of a void. In actual operation, the presence or absence of a void is determined by detecting the change in the resonance frequency relative to the resonance frequency when the space between the substrates is completely filled with mold 80, for example.

[0045] 12A-C and 13A-B show the calculation results of the S parameters of the inductor 350 and the capacitor 30. FIGS. 12A-C show the change in the resonant frequency when the capacitance value is changed by ±10%. FIG. 12A shows the case where C=0.2pF and L=1nH, and the resonant frequency is 11.3GHz. FIG. 12B shows the case where C=0.18pF and L=1nH, and the resonant frequency is 11.9GHz. FIG. 12C shows the case where C=0.22pF and L=1nH, and the resonant frequency is 10.7GHz. It can be seen that the resonant frequency changes with the change in the capacitance value.

[0046] Figures 13A-B show the change in resonant frequency when the inductance value is changed by ±10%. Figure 13A shows the case where C=0.2pF, L=0.9nH, and the resonant frequency is 11.9GHz. Figure 13B shows the case where C=0.2pF, L=1.1nH, and the resonant frequency is 10.7GHz. It can be seen that the resonant frequency changes when the inductance value is changed.

[0047] According to this embodiment, by using the resonant frequency, it is possible to further improve the detection sensitivity compared to embodiment 1. According to this embodiment, it is possible to detect even a partial void B3 shown in FIG. 4C, for example.

[0048] In this embodiment, the pillars 40 do not necessarily have to be provided.

[0049] Embodiment 3 FIG. 14A is a cross-sectional view of a semiconductor device 400 according to the third embodiment. FIG. 14B is a CC' cross-sectional view of the semiconductor device 400 according to the third embodiment. That is, FIG. 14B is a view of the semiconductor substrate 15 as viewed from below. FIG. 14C is a BB' cross-sectional view of the semiconductor device according to the third embodiment. FIG. 14D is a DD' cross-sectional view of the semiconductor device according to the third embodiment.

[0050] The semiconductor device 400 includes a capacitor 430. In this embodiment, as shown in Fig. 14C, the pattern 31 and the wiring 33 which is the first electrode of the capacitor 430 are provided on the second surface 12 of the mounting substrate 10. Also, as shown in Fig. 14B, the pattern 432 and the wiring 434 which is the second electrode of the capacitor 430 are provided on the third surface 13 of the semiconductor substrate 15.

[0051] The wiring 434 is connected to the pattern 432. The pattern 432 is connected to the pattern 32 via the pillar 43, solder, etc. The patterns 31 and 32 on the second surface 12 of the mounting substrate 10 are connected to the terminal 17 through the via hole 19, similar to the first embodiment.

[0052] The first pillar 41 extends from the wiring 33 toward the semiconductor substrate 15. The second pillar 42 extends from the wiring 434 toward the mounting substrate 10. By providing the multiple wirings 33 and the multiple wirings 434 alternately in a plan view, the first pillar 41 and the second pillar 42 face each other and are disposed in close proximity to each other, as shown in FIG.

[0053] In the present embodiment, first pillar 41 and second pillar 42 can change the capacitance value of capacitor 430 depending on the presence or absence of void B6 occurring between mounting board 10 and semiconductor substrate 15. Therefore, void B6 can be detected by the difference in S parameter.

[0054] Embodiment 4 FIG. 15A is a cross-sectional view of the semiconductor device 500 according to the fourth embodiment. FIG. 15B is a cross-sectional view of the semiconductor device 500 according to the fourth embodiment along C-C'. FIG. 15C is a cross-sectional view of the semiconductor device 500 according to the fourth embodiment along B-B'. FIG. 15D is a cross-sectional view of the semiconductor device 500 according to the fourth embodiment along A-A'. In the semiconductor device 500, a recess 18 is formed on the second surface 12 of the mounting substrate 10 directly below the wiring 33 of the capacitor 430. In addition, an inductor 350 connected in parallel to the capacitor 430 is formed on the bottom surface of the recess 18. The other structures are the same as those of the third embodiment. In addition, the structure of the inductor 350 is the same as that of the inductor 350 of the second embodiment.

[0055] In the present embodiment, similarly to the second embodiment, the presence or absence of voids can be detected with high accuracy based on changes in the resonance frequency of capacitor 430 and inductor 350.

[0056] Embodiment 5. Fig. 16A is a cross-sectional view of the semiconductor device 600 according to the fifth embodiment. Fig. 16B is a CC' cross-sectional view of the semiconductor device 600 according to the fifth embodiment. Fig. 16C is a BB' cross-sectional view of the semiconductor device 600 according to the fifth embodiment.

[0057] The semiconductor device 600 includes a capacitor 630. In the present embodiment, as in the third embodiment, the wiring 33 which is a first electrode of the capacitor 630 is provided on the second surface 12 of the mounting substrate 10, and the wiring 434 which is a second electrode of the capacitor 630 is provided on the third surface 13 of the semiconductor substrate 15. The present embodiment differs from the third embodiment in that the wirings 33 and the wirings 434 are provided so as to overlap each other in a plan view.

[0058] The multiple pillars 40 include pillars 40a to 40f. The wiring 33 and the wiring 434 overlap in a plan view, so that the pillars 40a to 40f are aligned in a straight line. The pillars 40c and 40e correspond to the first pillars 41 extending from the first electrode of the capacitor 630 toward the semiconductor substrate 15. The pillars 40b and 40d correspond to the second pillars 42 extending from the second electrode of the capacitor 630 toward the mounting substrate 10.

[0059] The pillars 40a and 40f connect the wiring 33 and wiring 434 of the capacitor 630 via solder or the like. The pillars 40a and 40f are provided on both sides of the pillars 40b to 40e, and form an inductor 650 together with the wirings 33 and 434.

[0060] In the present embodiment, similarly to the second embodiment, the presence or absence of a void can be detected with high accuracy by changes in the resonant frequency of the capacitor 630 and the inductor 650. In addition, in the present embodiment, since the inductor 650 is formed using the pillars 40a and 40f, it is possible to detect a void using the resonant frequency even if the recess 18 is not provided.

[0061] In addition, the pillars 40a and 40f may be electrically connected to a ground terminal. This is possible by grounding the terminal 17 connected to the pillars 40a and 40f to the ground. This makes it possible to shift the cavity resonance frequency to a frequency band higher than the frequency band used. This makes it possible to prevent cavity resonance.

[0062] Embodiment 6 Fig. 17A is a cross-sectional view of the semiconductor device 700 according to the sixth embodiment. Fig. 17B is a B-B' cross-sectional view of the semiconductor device 700 according to the sixth embodiment. Fig. 17C is an A-A' cross-sectional view of the semiconductor device 700 according to the sixth embodiment. This embodiment is similar to the first embodiment in that the semiconductor substrate 15 is flip-chip mounted on the mounting substrate 10 and sealed with a mold 80. This embodiment differs from the first embodiment in the structure of the inductor 750.

[0063] Patterns 31 and 32 are provided on the second surface 12 of the mounting substrate 10. As in the first embodiment, the patterns 31 and 32 are connected to the terminal 17 through the via hole 19. An inductor 750 is formed between the patterns 31 and 32. The inductor 750 has an inductor wiring 753. At least a portion of the inductor 750 is provided at an intermediate height between the second surface 12 of the mounting substrate 10 and the third surface 13 of the semiconductor substrate 15 in a direction perpendicular to the second surface 12 of the mounting substrate 10. In other words, when the distance between the mounting substrate 10 and the semiconductor substrate 15 is L1, the inductor 750 is formed to a position higher than L1 / 2.

[0064] Furthermore, on the second surface 12 of the mounting substrate 10, a recess 18 is formed between the patterns 31 and 32. A capacitor 730 connected in parallel to the inductor 750 is formed on the bottom surface of the recess 18. The capacitor 730 is, for example, an interdigital capacitor. The capacitor 730 is provided between the patterns 51 and 52. The pattern 51 is connected to the pattern 31 and the terminal 17 by the via hole 19. The pattern 52 is connected to the pattern 32 and the terminal 17 by the via hole 19.

[0065] In this embodiment, at least a portion of the inductor 750 is provided at a height intermediate between the second surface 12 of the mounting substrate 10 and the third surface 13 of the semiconductor substrate 15. Therefore, even in a state in which the void B6 occurs despite the surface of the mounting substrate 10 being covered with the mold 80, the void B6 can be detected with high accuracy. Furthermore, by connecting the inductor 750 and the capacitor 730 in parallel, the presence or absence of a void can be detected with high accuracy by a change in the resonant frequency. Furthermore, by forming the recess 18, contact between the wiring of the inductor 750 and the capacitor 730 due to the inductor 750 falling, distortion, etc. can be suppressed.

[0066] The capacitor 730 may be a MIM (Metal-Insulator-Metal) capacitor, etc. Also, the recess 18 and the capacitor 730 do not have to be provided.

[0067] Fig. 18 is a plan view of mounting board 10 according to a modification of embodiment 6. Figs. 17A to 17C show an example in which inductor 750 is formed using one inductor wiring 753. However, the present invention is not limited to this example, and inductor 750 may be formed by providing multiple pads 37 on second surface 12 of mounting board 10 and connecting patterns 31 and 32 in series with multiple inductor wirings 754 via the multiple pads 37, as shown in Fig. 18.

[0068] Embodiment 7 Fig. 19A is a cross-sectional view of a semiconductor device 800 according to the seventh embodiment. Fig. 19B is a B-B' cross-sectional view of the semiconductor device 800 according to the seventh embodiment. Fig. 19C is an A-A' cross-sectional view of the semiconductor device 800 according to the seventh embodiment. This embodiment is similar to the first embodiment in that a semiconductor substrate 15 is flip-chip mounted on a mounting substrate 10 and sealed with a mold 80. This embodiment differs from the first embodiment in the structure of a capacitor 830.

[0069] The second surface 12 of the mounting substrate 10 is provided with patterns 31 and 32 and a plurality of wire connection pads 38. As in the first embodiment, the patterns 31 and 32 are connected to the terminal 17 through the via hole 19. A capacitor 830 is formed between the patterns 31 and 32 by a plurality of wires 836. Specifically, the pattern 31 and the wire connection pad 38 are connected by the wire 836, and the pattern 32 and the wire connection pad 38 are connected by the wire 836, thereby forming the capacitor 830. The plurality of wires 836 are arranged close to each other.

[0070] At least a portion of wire 836 of capacitor 830 is provided in a direction perpendicular to second surface 12 of mounting substrate 10, at a height intermediate between second surface 12 of mounting substrate 10 and third surface 13 of semiconductor substrate 15. In other words, when the distance between mounting substrate 10 and semiconductor substrate 15 is L1, capacitor 830 is formed to a position higher than L1 / 2.

[0071] Further, on the second surface 12 of the mounting substrate 10, a recess 18 is formed between the patterns 31 and 32. An inductor 350 connected in parallel to the capacitor 830 is formed on the bottom surface of the recess 18. The inductor 350 is, for example, a meander line type inductor. The inductor 350 has, for example, a substrate 55 and an inductor wiring 53 formed on the substrate 55. The inductor wiring 53 connects the patterns 51 and 52. The pattern 51 is connected to the pattern 31 and the terminal 17 by the via hole 19. The pattern 52 is connected to the pattern 32 and the terminal 17 by the via hole 19.

[0072] In this embodiment, at least a portion of the capacitor 830 is provided at a height intermediate between the second surface 12 of the mounting substrate 10 and the third surface 13 of the semiconductor substrate 15. Therefore, even in a state in which the void B6 occurs despite the surface of the mounting substrate 10 being covered with the mold 80, the void B6 can be detected with high accuracy. Furthermore, by connecting the capacitor 830 and the inductor 350 in parallel, the presence or absence of a void can be detected with high accuracy by the change in the resonant frequency. Furthermore, by forming the recess 18, the contact between the capacitor 830 and the inductor wiring 53 due to the collapse, distortion, etc. of the capacitor 830 can be suppressed.

[0073] Alternatively, the inductor 350 may be a high impedance microstrip line or a spiral inductor, and the recess 18 and the inductor 350 may not be provided.

[0074] 20 is a plan view of mounting substrate 10 according to a modification of Embodiment 7. By changing the layout of wire connection pads 38 on mounting substrate 10, capacitor 830 may be formed with three or more wires 836.

[0075] The technical features described in each embodiment may be used in appropriate combination.

[0076] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a capacitor in which a first electrode, which is one of a positive electrode and a negative electrode, is provided on the second surface of the mounting substrate, and a second electrode, which is the other of the positive electrode and the negative electrode, is provided on the second surface of the mounting substrate or the third surface of the semiconductor substrate; a conductive first pillar extending from the first electrode of the capacitor toward the semiconductor substrate; a conductive second pillar extending from the second electrode of the capacitor toward one of the mounting substrate and the semiconductor substrate facing the second electrode; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; A semiconductor device comprising: (Appendix 2) the second electrode of the capacitor is provided on the second surface of the mounting substrate, the second pillar extends toward the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein a recess is formed on the second surface of the mounting substrate directly below the first electrode or the second electrode of the capacitor. (Appendix 3) 3. The semiconductor device according to claim 2, further comprising an inductor formed on a bottom surface of the recess and connected in parallel with the capacitor. (Appendix 4) the second electrode of the capacitor is provided on the third surface of the semiconductor substrate; the second pillar extends toward the mounting substrate, The semiconductor device according to claim 1, wherein the first pillar and the second pillar face each other. (Appendix 5) a recess is formed on the second surface of the mounting substrate directly below the first electrode of the capacitor, 5. The semiconductor device according to claim 4, further comprising an inductor formed on a bottom surface of the recess and connected in parallel with the capacitor. (Appendix 6) the second electrode of the capacitor is provided on the third surface of the semiconductor substrate; the second pillar extends toward the mounting substrate, a conductive third pillar connecting the first electrode and the second electrode of the capacitor; a conductive fourth pillar connecting the first electrode and the second electrode of the capacitor; Further equipped with The semiconductor device according to claim 1, wherein the third pillar and the fourth pillar are provided on both sides of the first pillar and the second pillar to form an inductor. (Appendix 7) The semiconductor device according to claim 6, wherein the third pillar and the fourth pillar are electrically connected to a ground terminal. (Appendix 8) the first electrode of the capacitor is electrically connected to a first terminal provided on the first surface of the mounting substrate; The semiconductor device according to any one of claims 1 to 7, wherein the second electrode of the capacitor is electrically connected to a second terminal provided on the first surface of the mounting substrate. (Appendix 9) The semiconductor device described in any one of appendix 1 to 8, characterized in that the first pillar has a pier metal provided on the first electrode and a pillar portion provided on the pier metal. (Appendix 10) a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a first pattern provided on the second surface of the mounting substrate; a second pattern provided on the second surface of the mounting substrate; an inductor or a capacitor formed between the first pattern and the second pattern; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; Equipped with A semiconductor device characterized in that at least a portion of the inductor or the capacitor is arranged at an intermediate height between the second surface of the mounting substrate and the third surface of the semiconductor substrate in a direction perpendicular to the second surface of the mounting substrate. (Appendix 11) The inductor is formed between the first pattern and the second pattern, a recess is formed between the first pattern and the second pattern on the second surface of the mounting substrate, 11. The semiconductor device according to claim 10, wherein the capacitor connected in parallel with the inductor is formed on a bottom surface of the recess. (Appendix 12) 11. The semiconductor device according to claim 10, wherein the capacitor is formed between the first pattern and the second pattern by a plurality of wires. (Appendix 13) a recess is formed between the first pattern and the second pattern on the second surface of the mounting substrate, 13. The semiconductor device according to claim 12, wherein the inductor connected in parallel to the capacitor is formed on a bottom surface of the recess. (Appendix 14) a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a capacitor or inductor formed on the second surface of the mounting substrate; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; Equipped with The semiconductor device according to claim 1, wherein a recess is formed on the second surface of the mounting substrate directly below the capacitor or the inductor. (Appendix 15) 15. The semiconductor device according to claim 14, wherein the inductor is formed on the second surface of the mounting substrate. (Appendix 16) the capacitor is formed on the second surface of the mounting substrate, 15. The semiconductor device according to claim 14, further comprising the inductor formed on a bottom surface of the recess and connected in parallel with the capacitor. [Explanation of symbols]

[0077] 10 mounting substrate, 11 first surface, 12 second surface, 13 third surface, 14 fourth surface, 15 semiconductor substrate, 17 terminal, 18 recess, 19 via hole, 21 electrode, 23 pillar, 24 electrode, 30 capacitor, 31 pattern, 32 pattern, 33 wiring, 34 wiring, 37 pad, 38 wire connection pad, 40, 40a to 40f pillar, 41 first pillar, 42 second pillar, 43 pillar, 48 pier metal, 49 pillar portion, 51 pattern, 52 pattern, 53 inductor wiring, 55 substrate, 80 mold, 81 conductive resin, 82 heat sink, 83 shield, 100 semiconductor device, 101 semiconductor device, 102 semiconductor device, 200 semiconductor device, 250 inductor, 300 semiconductor device, 350 inductor, 400 Semiconductor device, 430 capacitor, 432 pattern, 434 wiring, 500 semiconductor device, 600 semiconductor device, 630 capacitor, 650 inductor, 700 semiconductor device, 730 capacitor, 750 inductor, 753 inductor wiring, 754 inductor wiring, 800 semiconductor device, 830 capacitor, 836 wire, B1 to B8 void

Claims

1. a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a capacitor in which a first electrode, which is one of a positive electrode and a negative electrode, is provided on the second surface of the mounting substrate, and a second electrode, which is the other of the positive electrode and the negative electrode, is provided on the second surface of the mounting substrate or the third surface of the semiconductor substrate; a conductive first pillar extending from the first electrode of the capacitor toward the semiconductor substrate; a conductive second pillar extending from the second electrode of the capacitor toward one of the mounting substrate and the semiconductor substrate facing the second electrode; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; A semiconductor device comprising:

2. the second electrode of the capacitor is provided on the second surface of the mounting substrate, the second pillar extends toward the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein a recess is formed on the second surface of the mounting substrate directly below the first electrode or the second electrode of the capacitor.

3. 3. The semiconductor device according to claim 2, further comprising an inductor formed on a bottom surface of the recess and connected in parallel with the capacitor.

4. the second electrode of the capacitor is provided on the third surface of the semiconductor substrate; The second pillar extends toward the mounting substrate, The semiconductor device according to claim 1 , wherein the first pillar and the second pillar face each other.

5. a recess is formed on the second surface of the mounting substrate directly below the first electrode of the capacitor, 5. The semiconductor device according to claim 4, further comprising an inductor formed on a bottom surface of the recess and connected in parallel with the capacitor.

6. the second electrode of the capacitor is provided on the third surface of the semiconductor substrate; The second pillar extends toward the mounting substrate, a conductive third pillar connecting the first electrode and the second electrode of the capacitor; a conductive fourth pillar connecting the first electrode and the second electrode of the capacitor; Further equipped with The semiconductor device according to claim 1 , wherein the third pillar and the fourth pillar are provided on both sides of the first pillar and the second pillar to form an inductor.

7. The semiconductor device according to claim 6 , wherein the third pillar and the fourth pillar are electrically connected to a ground terminal.

8. the first electrode of the capacitor is electrically connected to a first terminal provided on the first surface of the mounting substrate; 8. The semiconductor device according to claim 1, wherein the second electrode of the capacitor is electrically connected to a second terminal provided on the first surface of the mounting substrate.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that the first pillar has a pier metal provided on the first electrode and a pillar portion provided on the pier metal.

10. a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a first pattern provided on the second surface of the mounting substrate; a second pattern provided on the second surface of the mounting substrate; an inductor or a capacitor formed between the first pattern and the second pattern; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; Equipped with A semiconductor device characterized in that at least a portion of the inductor or the capacitor is arranged in a direction perpendicular to the second surface of the mounting substrate, at a height intermediate between the second surface of the mounting substrate and the third surface of the semiconductor substrate.

11. The inductor is formed between the first pattern and the second pattern, a recess is formed between the first pattern and the second pattern on the second surface of the mounting substrate, 11. The semiconductor device according to claim 10, wherein the capacitor connected in parallel to the inductor is formed on a bottom surface of the recess.

12. 11. The semiconductor device according to claim 10, wherein the capacitor is formed between the first pattern and the second pattern by a plurality of wires.

13. a recess is formed between the first pattern and the second pattern on the second surface of the mounting substrate, 13. The semiconductor device according to claim 12, wherein the inductor is connected in parallel to the capacitor and formed on a bottom surface of the recess.

14. a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor substrate having a third surface and a fourth surface opposite to the third surface, the semiconductor substrate being flip-chip mounted on the mounting substrate such that the third surface faces the second surface of the mounting substrate; a capacitor or inductor formed on the second surface of the mounting substrate; a mold that fills a gap between the second surface of the mounting substrate and the third surface of the semiconductor substrate; Equipped with The semiconductor device according to claim 1, wherein a recess is formed on the second surface of the mounting substrate directly below the capacitor or the inductor.

15. The semiconductor device according to claim 14 , wherein the inductor is formed on the second surface of the mounting substrate.

16. the capacitor is formed on the second surface of the mounting substrate; 15. The semiconductor device according to claim 14, further comprising the inductor formed on a bottom surface of the recess and connected in parallel with the capacitor.

Images