Semiconductor circuit structure having direct die heat removal structure

Abstract

To provide a semiconductor circuit structure having a direct die heat removal structure.SOLUTION: A semiconductor circuit structure includes a semiconductor substrate having an initial semiconductor surface, a set of active regions in the semiconductor substrate, and a first shallow trench isolation (STI) region 201 adjacent the set of active regions and extending along a first direction. The first STI region includes a heat extraction layer HHDP, and the material of the heat extraction layer is different from SiO2.SELECTED DRAWING: Figure 8b

Description

Detailed Description of the Invention

[0001] 〔background〕 [Technical field] The present disclosure relates to semiconductor structures, and more particularly to semiconductor circuit structures using direct die cooling techniques. Description of Related Art

[0002] The monolithic integration capability of silicon chips has evolved from GSI (gigascale integration: integrating billions of transistors on a die) to TSI (terascale integration: integrating trillions of transistors on a die), and the operation of such a large number of transistors results in a sharp increase in power consumption. The increased power consumption inversely increases the junction temperature of the transistors and therefore the temperature of the entire chip due to the heat dissipation capability caused by current limitation. Silicon dioxide has a very low thermal conductivity, and silicon itself has a low thermal conductivity. This material and device structural problem causes a negative circular effect. That is, the higher die temperature reduces the speed of the transistors, which inevitably forces the design to increase the power to the circuit to promote the transistor's performance, but this mechanism causes the die temperature to rise so much that the heat dissipation problem worsens. This problem of insufficient heat dissipation, which causes the chip operating temperature to rise, is the worst problem that the entire chip industry needs to solve in order to avoid a major obstacle to the integration of more devices on the die. However, progress in reducing the temperature of GSI chips has not improved at present.

[0003] In fact, as technology nodes are further scaled down, transistor dimensions are forced to become smaller (e.g., minimum feature size is scaled down from 7nm to 5nm to 3nm), the oxide coverage ratio to the total size of the transistor is higher, and the heat dissipation capability of the entire device junction is further concentrated. Many heat dissipation methods have been created, such as covering the entire chip with high heat removal pads outside the chip or circulating liquid cooling outside the packaged chip, but both are very expensive and less efficient in effectively reducing the transistor junction temperature. 〔overview〕

[0004] The present invention focuses on forming heat removal (HR) structures specifically within the semiconductor die in the monolithic process of manufacturing the transistors. Such HR structures are connected across the die as a single component designed to maximize the heat dissipation area. Furthermore, the HR structures can be connected across the entire edge of the die, making it easier to connect to a heat sink outside the semiconductor die, creating a larger heat dissipation path from the die to the environment outside the die and ultimately to the packaged chip. This new HR structure is considered the most proximate path to achieve a highly effective heat dissipation function directly related to the individual transistors. Furthermore, all of these HRs can be connected together across the die as components of an optimized heat dissipation network built within the die.

[0005] An embodiment of the present disclosure provides a semiconductor circuit structure, the semiconductor circuit structure including: a semiconductor substrate having an initial semiconductor surface, a set of active regions in the semiconductor substrate, and a first shallow trench isolation (STI) region adjacent to the set of active regions and extending along a first direction, the first STI region including a heat extraction layer, the material of the heat extraction layer being different from SiO2.

[0006] According to one aspect of the present disclosure, the thermal conductivity of the heat extraction layer is higher than the thermal conductivity of SiO2.

[0007] According to one aspect of the present disclosure, the heat extraction layer is an electrical insulator during operation of the semiconductor circuit structure.

[0008] According to one aspect of the disclosure, the heat extraction layer extends into one of the set of active regions.

[0009] According to one aspect of the disclosure, the heat extraction layer includes a metal layer and a thin insulating layer, the thin insulating layer being between the metal layer and the set of active regions.

[0010] According to one aspect of the present disclosure, the heat extraction layer comprises a composite material.

[0011] According to one embodiment of the present disclosure, the first STI region further includes a SiO2 layer below the heat extraction layer.

[0012] According to one aspect of the present disclosure, the heat extraction layer is in a front-end-of-line (FEOL) region of the semiconductor circuit structure.

[0013] According to one aspect of the present disclosure, the first STI region surrounds the set of active areas.

[0014] According to one aspect of the present disclosure, the heat extraction layer is in the first STI region and below the initial semiconductor surface, the heat extraction layer surrounding the set of active regions.

[0015] According to one aspect of the present disclosure, a preliminary STI region is connected to the first STI region, and the heat extraction layer extends along the first direction to the preliminary STI region.

[0016] According to one aspect of the present disclosure, the preliminary STI region is proximate to a center of the semiconductor substrate or proximate to an edge of the semiconductor substrate.

[0017] According to one aspect of the present disclosure, a heat extraction pad is in the preliminary STI region and the heat extraction layer is connected to the heat extraction pad.

[0018] According to one aspect of the present disclosure, a thermal via is over the preliminary STI region and connects to the heat removal pad within the preliminary STI region.

[0019] According to one aspect of the present disclosure, a heat dissipation plate overlies and is connected to the thermal vias.

[0020] According to one aspect of the present disclosure, a plurality of insulators overlie a set of active areas, and the thermal vias extend through the plurality of insulators and connect to the heat removal pads in the pre-STI regions.

[0021] According to one aspect of the present disclosure, the plurality of insulators and the thermal vias are in a back-end-of-line (BEOL) region of the semiconductor circuit structure.

[0022] According to one aspect of the present disclosure, a through-semiconductor via (TSV) extends from the back surface of the semiconductor substrate to an underside of the heat removal pad in the preliminary STI region, with the back surface facing the initial semiconductor surface.

[0023] According to one aspect of the present disclosure, a heat dissipation plate is provided beneath the back surface of the semiconductor substrate and is connected to the through semiconductor vias.

[0024] According to one aspect of the present disclosure, the first STI region surrounds four sidewalls of one of the set of active areas.

[0025] Another embodiment of the present disclosure comprises a semiconductor substrate having an initial semiconductor surface, a set of transistors formed in the semiconductor substrate, and a composite-material STI region adjacent the set of transistors and extending along a first direction to an edge of the semiconductor substrate, the composite-material STI region being in a front-end-of-line (FEOL) region of the semiconductor circuit structure.

[0026] According to one aspect of the present disclosure, the composite STI region includes a heat extraction layer adjacent to the set of transistors and extending along the first direction to an edge of the semiconductor substrate.

[0027] According to one aspect of the present disclosure, a thermal via is provided above or below the heat removal layer, and the thermal via is connected to the heat removal layer.

[0028] According to one aspect of the present disclosure, a heat sink plate is above or below the semiconductor substrate, and the semiconductor substrate is connected to the thermal vias.

[0029] According to one aspect of the present disclosure, the thermal vias are in a back-end-of-line (BEOL) region of the semiconductor circuit structure.

[0030] Another embodiment of the present disclosure includes a semiconductor substrate having an initial semiconductor surface, a first set of active areas in the semiconductor substrate extending along a first direction, a second set of active areas in the semiconductor substrate extending along the first direction, and a first shallow trench isolation (STI) region between the first set of active areas and the second set of active areas, the first STI region including a heat extraction layer extending along the first direction, the thermal conductivity of the heat extraction layer being greater than the thermal conductivity of SiO2.

[0031] According to one aspect of the present disclosure, the semiconductor circuit structure further comprises a spare STI region separate from the first set of active areas and the second set of active areas, the spare STI region connected to the first STI region and including a heat removal pad within the spare STI region, and the heat removal layer connected to the heat removal pad.

[0032] According to one aspect of the present disclosure, the width of the heat extraction pad is greater than the width of the heat extraction layer.

[0033] These and other embodiments of the present disclosure will be better understood with respect to the following detailed description of non-limiting embodiments, the following description being made with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1a shows a schematic top view of a conventional semiconductor circuit structure having an STI region and an active region, and FIGS. 1b and 1c show a top view of a partial region of FIG. 1a and a cross-sectional view thereof, respectively.

[0035] FIG. 2 (including FIGS. 2a and 2b) shows top and cross-sectional views after active areas and shallow trench isolation (STI) regions have been formed.

[0036] FIG. 3 (including FIGS. 3a and 3b) shows a top view and a cross-sectional view after a protective region of nitride has been formed over the center of the active area.

[0037] FIG. 4 (including FIGS. 4a and 4b) shows top and cross-sectional views after vertical spacers have been formed to cover the exposed silicon sidewalls.

[0038] FIG. 5 (including FIGS. 5a and 5b) shows the top and cross-sectional views after the deep silicon sidewalls are exposed.

[0039] FIG. 6 (including FIGS. 6a, 6b and 6c) shows a top view and two different cross-sectional views after the hollow tunnel region has been formed.

[0040] FIG. 7 (including FIG. 7a and FIG. 7b) shows a top view and a cross-sectional view after the heat-dissipating material has been deposited.

[0041] FIG. 8 (including FIG. 8a and FIG. 8b) shows a top view and a cross-sectional view after the horizontal heat dissipation plates (HHDPs) and vertical heat dissipation columns (VHDCs) have been formed.

[0042] FIG. 9 (including FIGS. 9a and 9b) shows a top view and a cross-sectional view of another embodiment after the HHDP and VHDC have been formed.

[0043] FIG. 10 shows that the HHDP and VHDC are connected and extended to the edge of the chip / die.

[0044] FIG. 11 is a diagram showing a cool transistor according to the present invention.

[0045] Figures 12a and 12b show cross-sectional views of different embodiments of the present invention, and Figure 12c shows that the VHDC of Figure 12b extends to the edge of the chip / die according to another embodiment of the present invention.

[0046] FIG. 13 shows another cool transistor according to FIG. 12b.

[0047] FIG. 14a shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0048] FIG. 14b shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure.

[0049] Figure 15a shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure, while Figures 15b-c show schematic top views of the structure at different stages of a method for manufacturing the semiconductor circuit of Figure 15a.

[0050] 16a-16f show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure.

[0051] Figure 17a shows the temperature distribution of a FinFET established by Sentaurus TCAD.

[0052] FIG. 17b shows the temperature difference versus the thickness of the STI region. Detailed Description

[0053] Various embodiments will now be described in more detail with reference to the accompanying drawings, which are provided for purposes of illustration and description, and not for purposes of limitation. For clarity, components may not be drawn to scale. Additionally, some components and / or reference numerals may be omitted from some drawings. It is contemplated that elements and features of one embodiment may be beneficially incorporated in another embodiment without further description. In the following method for manufacturing a semiconductor device, there may be one or more additional operations between the operations described, and the order of operations may differ. The figures use the same / similar reference numerals to indicate the same / similar elements.

[0054] As used herein and in the appended claims, ordinal numbers such as "first," "second," and the like, to describe elements do not suggest or represent a particular location in the structure, order of arrangement, or order of manufacture. Ordinal numbers are used only to clearly distinguish between multiple elements having the same name. As used herein and in the appended claims, spatial relationship terms such as "on," "above," "over," "upper," "top," "below," "beneath," "under," "lower," "bottom," and the like, may be used to describe the relative spatial or positional relationships between one element and another element as illustrated in the drawings, and these spatial or positional relationships may be direct or indirect unless otherwise specified. Spatial relationship terms are intended to encompass different orientations of the structures in addition to the orientation depicted in the drawings. The structures may be flipped or rotated at various angles, and the spatial relationship descriptions used herein may be interpreted accordingly.

[0055] Additionally, the terms "electrically connected" and "electrically coupled" as used herein and in the claims may refer to ohmic contact between elements, or current passing through elements, or an operative relationship between elements. An operative relationship may mean, for example, that one element is used to drive another element, but no current flows directly between the two elements.

[0056] In a conventional semiconductor circuit structure in a semiconductor substrate, as shown in FIG. 1a, there are many active regions or active areas (AA) where transistors or circuit elements are placed, and there are many shallow trench isolation (STI) regions surrounding those active regions. Furthermore, FIG. 1b and FIG. 1c show the top view and its cross-sectional view of some of the regions in FIG. 1a. Here, before fabricating the transistors, the silicon islands in the active regions are covered by oxide and nitride layers, and all of these layers are deposited on top of the initial semiconductor surface (OSS) of the semiconductor substrate. Nevertheless, the depth of the STI regions extending downward from the OSS is usually 250-300 nm, and the material of the STI regions is generally SiO2, and the thermal conductivity of SiO2 is rather low, 1.3-1.5 W / m×K. Therefore, the STI regions may increase the die temperature and reduce the speed of the transistors. To make matters worse, the STI regions in a semiconductor substrate may occupy more than 40% of the total area of ​​the semiconductor substrate, and these STI regions do not provide any special function other than the insulation purpose.

[0057] Hereinafter, a method for fabricating a heat removal structure in a substrate or die according to an embodiment of the present invention will be described. Please refer to FIG. 2a and FIG. 2b. First, a thin pad oxide layer 101 is thermally grown on the initial semiconductor surface, and then a pad nitride-1 layer 102 is deposited on the thin pad oxide layer 101. Photolithography etching techniques are used to define an active area 103 under the composite layer of pad nitride-1 layer 102 and pad oxide 101, where a transistor body 1031 or a fin structure is located. Outside this active area 103, a concave trench area 104 (depth t1 calculated from OSS is 250-300 nm) is formed, which is connected to the wafer. Next, a thick oxide is deposited, and a chemical mechanical polishing (CMP) technique is used to fabricate a shallow trench isolation (STI) 201 such that the top surface of the shallow trench isolation (STI) 201 is flush with the top surface of the pad nitride-1 layer 102 (here, top view and cross-sectional view are shown in FIG. 2a and FIG. 2b, respectively).

[0058] Next, with reference to Figures 3a and 3b, a pad nitride-2 layer 301 is deposited and a portion of this pad nitride-2 layer 301 is left in the center of the active area 103 using photolithographic mask techniques. Here, a top view is shown in Figure 3a and a cross-sectional view is shown in Figure 3b, respectively. Then, with reference to Figures 4a and 4b (top view and cross-sectional view are shown in Figures 4a and 4b, respectively), the oxide inside the exposed STI region 201 is etched away to a depth of t2 (e.g., 70 nm, or a depth of 100-150 nm). The pad nitride-2 layer 301 and the oxide of the STI region 201 under the pad nitride-2 layer 301 are left intact. Therefore, silicon sidewalls are exposed under the OSS. Then, a thin layer of oxide 401 is grown on these sidewalls using a thermal oxidation process (e.g., about 1.5-3 nm thick). Then, another pad nitride-3 layer 403 is deposited. Anisotropic etching techniques are used to make the pad nitride-3 layer 403 into vertical sidewall spacers. By design and under proper design, the pad nitride-2 layer 301 remains on its plane but is thinned by the anisotropic etching which produces the pad nitride-3 spacers 403.

[0059] See Fig. 5a for a top view and Fig. 5b for a cross-sectional view. Using anisotropic etching techniques, the exposed oxide layer inside most of the STI regions 201 is removed to a thickness t3 of about 8 nm. This results in a flat oxide surface with a distance from the top of the exposed oxide surface to the OSS of about 78 nm (t2+t3). Using an isotropic etching technique, the exposed thin oxide layer 401 is removed to expose the sidewall silicon.

[0060] Please refer to Figures 6a, 6b and 6c. Figure 6a is a top view, Figure 6b is a cross-sectional view along the cutting line 6b-6b' shown in Figure 6a, and Figure 6c is a cross-sectional view along the cutting line 6c-6c' shown in Figure 6a. An isotropic etching technique can be used to remove a portion of the exposed silicon surface, and the etching rate, especially over the (110) crystal orientation, can be optimally adjusted to be much faster than that of the (100). Thus, the silicon layer along the formed exposed region can be removed to form the cavity tunnel region 601, but the removal process can be well controlled to end at a suitable adjustment time to leave the silicon protected by the vertical distance under the pad nitride-3 spacer 403.

[0061] It should be noted that different processes can also be used to achieve similar structures as shown in Figures 6a, 6b and 6c. For example, after creating a structure as shown in Figures 5a and 5b, instead of using the isotropic etching technique described above to remove some of the exposed silicon surface, a thermal oxidation process can be used to grow the exposed silicon areas. Because the exposed silicon areas are somewhat narrow in horizontal distance, an oxide layer (such as thermal oxide) grown below the top surface of the silicon island can quickly fill the horizontal voids and provide a smooth close-up shape. However, the bulk silicon material under the coverage of the pad nitride-3 spacer 403 is sufficiently protected and not over-oxidized to connect the semiconductor body regions of the transistors to the wafer substrate as robust pillar regions. An isotropic etching technique is then used to remove this thermal oxide, resulting in a similar structure as shown in Figures 6a, 6b and 6c.

[0062] See Figure 7a and Figure 7b. An isotropic etching technique is adopted to remove the pad nitride-3 spacer 403. A thermal oxidation process is used to grow a very thin oxide layer 701 (e.g., 1-3 nm) to sufficiently protect the freshly created and exposed silicon surface. Then, select a suitable material with very high thermal conductivity (e.g., boron nitride (BN) is an electrical insulator but has a very high thermal conductivity such as 600 W / m×K compared to 149 W / m×K for silicon material; aluminum nitride (AlN) material has its thermal conductivity as high as 321 W / m×K; or any other material with suitable thermal conductivity, any of these can be referred to as Z material 702). Then, a CVD process is used to fill the void tunnel region 601 created by the above process result. Of course, the voids in the STI region are filled by the BN material (here, the top view and cross-sectional view are shown in Figure 7a and Figure 7b, respectively).

[0063] In another embodiment, the thermal conductivity of the Z material 702 is higher than silicon, higher than silicon nitride, or higher than 10 W / m·K or 30 W / m·K. Of course, other possible materials of the Z material 702 can be graphene or metal, (such as copper, tungsten, or composite metal), and it is better that the tungsten layer can be covered by another barrier TiN layer or suitable layer. If the material of the Z material 702 is metal, there can be a thin insulator such as thermal oxide between the active area and the Z material 702. Furthermore, the material of the Z material 702 can also be a composite material consisting of two or more of the above-mentioned materials. It is clear that the Z material 702 is different from the initial material (SiO2) of the STI region. In another embodiment, the Z material is also different from silicon nitride. The Z material 702 can include a material having a higher thermal conductivity than the initial insulating material (such as oxide) of the STI region, for example, AlN, BN, SiC, Si, deposited diamond, or SiGe.

[0064] Then, the BN or Z material 702 on the pad nitride-1 layer 102 can be removed to a planar shape using a CMP technique, and an anisotropic etching technique can be further used to remove some of the BN or Z material 702 on the STI region 201. The top of the remaining Z material 702 can be aligned with the OSS or can be lower than the OSS. Then, a layer of oxide 801 is deposited on top of the remaining Z material 702, flush with the pad nitride-1 layer 102. After removing the pad nitride-2 layer 301, the silicon surface is covered with the pad nitride-1 layer 102 and the oxide-covered STI region 201. Normal processing can be continued to complete transistors (such as planar transistors, FinFET transistors, or GAA transistors) in the remaining semiconductor active area (see FIG. 8, which shows a top view in 8a and a cross-sectional view in 8b, respectively).

[0065] Some BN or Z material 702 is filled in the cavity tunnel area under the active area (or silicon body area of ​​FinFET / Tri-gate device), so it is named as horizontal heat dissipation plate (HHDP), as shown in FIG. 8. Some Z material 702 is filled in the vertical cavity area of ​​STI, so it is named as vertical heat dissipation column (VHDC). After the transistor is formed in the active area, the source / drain area of ​​the transistor is placed near the HDDP and VHDC, which have a higher thermal conductivity than that of the silicon dioxide (or silicon) material surrounding the transistor in conventional designs. In fact, the hottest area of ​​the transistor during full operation is the center of the p / n junction area between the drain and source areas, which are both connected to the channel area of ​​the transistor respectively, and these HDDP and VHDC structures are very effective in dissipating the heat generated in these p / n junction areas.

[0066] Another possibility is to make HHDP structures with a deep distance from the OSS (initial silicon surface) using a similar method described above. This allows more HHDPs to be increased to expand the heat dissipation area. For example, after the BN material or Z material 702 is completed by the CVD process, anisotropic etching techniques can be used to remove the BN material or Z material 702 that is vertically disposed inside the STI region 201. Then, anisotropic etching techniques can be used to remove or etch downwards the bottom oxide material of the STI region 201 as well (for example, only 20-50 nm thick oxide can be kept in the STI region without damaging the BN material already inserted horizontally into the cavity tunnel region 601). Then, the BN or Z material 702 is deposited twice in the cavities of the STI region, and this two-step process of forming the BN or Z material 702 is performed first for the HHDP and then to optimize the volume of the BN or Z material 702 inside almost all of the STI region (see FIG. 9, with a top view in 9a and a cross-sectional view in 9b, respectively). Of course, before the second deposition of the Z material 702, an additional step of forming a thin vertical insulating layer (similar to the thin oxide layer 401) can also be applied, so that the vertical insulating layer is below the HDP and between the sidewalls of the silicon substrate and the Z material 702.

[0067] Also, note that the STI regions are spread across the entire wafer substrate as shown in FIG. 1a. Since all the HHDP materials are laid under the body regions (or active regions) of the MOSFETs / transistors and connected to all the VHDC materials in the STI regions, the high heat dissipation material network thus constructed acts as a connected heat dissipation sink from the operated PN junctions of the transistors. By designing the Z materials inside the monolithic die and utilizing a normal monolithic processing recipe, all the Z materials can be connected to the edge ring of the chip or die, and then the Z materials 702 inside the STI regions are opened and contacted with their top surfaces. As a result, the Z materials 702 of the entire die can be thermally connected to the outside of the edge of the chip / die, further directly and effectively dissipating heat. Referring to FIG. 10, the bottom diagram of FIG. 10 is a cross-sectional view along the cutting line 10a shown in the top diagram of FIG. 10. Therefore, the VHDC in the STI region (and / or the HHDP in the active region) is a kind of direct die heat removal device ("DDHR"), and the present invention provides a direct die cooling technology ("DDCT") based on the proposed VHDC (and / or HHDP.

[0068] There are many active areas in the semiconductor substrate, and in the present invention, the active area (or active areas) are surrounded by Z material 702. The Z material 702 extends from one active area to another and further to the edge of the chip / die. Each active area may house a circuit element such as a transistor. In another embodiment, the die / chip with the VHDC (and / or HHDP) may be thinned first and then opened to expose the VHDC (and / or HHDP) so that another substrate with thermal vias or heat sink can be connected to the VHDC (and / or HHDP) from the bottom of the die / chip.

[0069] After the structure of the VHDC (and / or HHDP) is completed by a portion of the front-end-of-line (FEOL) process, the remainder of the FEOL foundry process can be used to form the transistors in the active area, as shown in Figure 11. The diffusion regions (or source / drain regions) of the transistors are in contact or nearly in contact with the VHDC (and / or HHDP). Thus, the VHDC (and / or HHDP) can be described as being formed during the FEOL process of the foundry manufacturing process, or within the FEOL region of the semiconductor die.

[0070] In FIG. 11, the transistor comprises a gate structure including a gate metal region 1101 and a Hi-K dielectric 1102. The transistor also comprises a source region 1103 including a lightly doped region extending laterally from a sidewall of the substrate and a heavily doped region extending laterally from a sidewall of the lightly doped region. The lightly doped and heavily doped regions are formed by selective growth methods such as epitaxial growth methods. On top of the source region 1104 is a metal contact 1105 between the gate structure of the transistor and the STI region 801. It is noted that the top surface of the STI region 801 is higher than the OSS (e.g., at the same height as the top surface of the gate structure), and thus the metal contact 1105 is self-aligned with the source region 1103, such that the contact hole is automatically formed without using a photolithography process to form the contact hole. Furthermore, in another embodiment, the metal contact 1105 can be connected not only to the top of the source region 1103, but also to the outermost sidewall of the source region 1103. The transistor also includes a drain region 1104, the structure of which is the same or substantially the same as the source region 1103, and will not be described further. FIG. 11 shows the final transistor structure with HHDP and VHDC microstructures of a novel "cool transistor" (CQT), a term best used to describe one embodiment of the present invention. Such a CQT structure can realize a scale-up (increase in transistor count) and scale-down (reduction in transistor dimensions) strategy from the current GSI (gigascale integration) to the near future TSI (terascale integration) era. The newly created heat dissipation path in the chip or die will directly generate a heating path from the transistor level to the whole die level. There are also designs that can connect the die-level heat dissipation path to the chip-level heat dissipation path, and it is certain that the die and package / heterogeneous integrated module will be an effective heat sink for the chip package and / or heterogeneous integrated module (e.g., via TSV, TIV, etc.) with the current cooling schemes.

[0071] Furthermore, in another embodiment, the step of forming the horizontal heat dissipation plate (HHDP) can be omitted and only the vertical heat dissipation column (VHDC) can be constructed. For example, referring to FIG. 2, the STI region 201 is first etched to expose the sidewalls of the Si substrate so that the remaining depth of the STI material is about 150-200 nm, and then a thin thermal oxide layer 401 is formed along the exposed sidewalls of the Si substrate. Then, the Z material 702 is deposited and etched back to a depth of 100-150 nm to form the VHDC, and an oxide 801 or other insulating material is further deposited on the VHDC as shown in FIG. 12a.

[0072] FIG. 12b shows a cross-sectional view on VHDC in the STI region of another embodiment according to the present invention. The difference between FIG. 12b and FIG. 12b is that most of the SiO2 material in the STI region is replaced by VHDC. Conventionally, the depth of the STI region starting from the initial semiconductor surface (OSS) of the die is 250-300 nm. In FIG. 12b, only 20-50 nm of SiO2 material remains at the bottom of the STI region, while 150-200 nm of SiO2 material remains at the bottom of the STI region shown in FIG. 12a. The more SiO2 is replaced by VHDC, the higher the thermal conductivity of the die structure. Of course, the top of the VHDC can be lower or higher than the OSS. Similarly, the VHDC structure of FIG. 12a or FIG. 12b can also extend along all the STI regions in the semiconductor die, as shown in FIG. 12c, and the bottom view of FIG. 12c is a cross-sectional view along the cutting line 12c shown in the top view of FIG. 12c.

[0073] Figure 13 shows another cool transistor, and the difference between Figure 13 and Figure 11 is that the cool transistor in Figure 13 is based on the VHDC of the STI region shown in Figure 12b. The other description of the cool transistor in Figure 13 is the same as that of the cool transistor in Figure 11, and the details thereof are omitted for brevity.

[0074] As mentioned above, the VHDC or Z material can be made of a single high heat dissipation material or can be made in a composite structure. For example, the VHDC comprises a layer of a first high heat dissipation material (such as BN, AlN, not shown in FIG. 12a or FIG. 12b) and another metal or metal-like column covered with the first high heat dissipation material. The metal-like material of the VHDC does not affect the operation of the transistors in the die / chip because the VHDC is in the STI region and the metal-like material is surrounded by the first high heat dissipation material that is non-conductive during the operation of the transistors in the die / chip (in this situation, the thin thermal oxide layer 401 may be omitted). Of course, both the first high heat dissipation material and the metal or metal-like column may further extend to the edge of the die / chip to form a heat dissipation network as mentioned above. Thus, in the semiconductor structure according to the present invention, there is a composite STI region (including the initial STI material SiO2 and VHDC; including only VHDC, which is a composite material with two different layers) or a heterogeneous STI (HSTI) region.

[0075] Additionally, in one embodiment, all or most of the STI regions of FIG. 1a may be replaced by composite STI regions such that the four sidewalls of the active areas are surrounded by composite STI regions. Such composite STI regions extend from one active area to another and to the edge of the chip / die. In another embodiment, the peripheral boundaries of a first set of active areas are surrounded by composite STI regions that extend to a second set of active areas and to the edge of the chip / die.

[0076] FIG. 14a shows a schematic top view of a semiconductor circuit structure 200 in a substrate according to an embodiment of the present disclosure. The semiconductor circuit structure 200 may be formed in a semiconductor chip or a substrate. FIG. 14a shows more active areas, i.e., active area 220A, STI region 220B, and pad open layer 220C, which may accommodate contact pads of the semiconductor circuit structure 200. Some large STI regions 224-1 to 224-4 of the STI region 220B may be located in corner regions adjacent to the peripheral / edge regions of the semiconductor chip, or in the central spare region of the chip. Large VHDC structures (such as VHDC pads) 209 are disposed within the large STI regions 224-1 to 224-4 and are located below the initial semiconductor surface of the semiconductor substrate. In addition, other thin or long VHDC structures (such as VHDC lines) 205 are located below the initial semiconductor surface of the semiconductor substrate and are formed within those thin or long STI regions 214-1 to 214-4 of the STI region 220B. The VHDC structure 205 and STI regions 214-1 through 214-4 may extend along the X-direction (or along the length of the active area). Additionally, the VHDC structure 205 may extend across more than one active area 220A, for example, the VHDC structure 205 located in the top right portion of FIG. 14a extends from one predefined point adjacent to active area 220A-1 to the large STI region 224-1.

[0077] In FIG. 14a, on one side of the STI region 214-1 is a first set of active regions extending along the x-direction, and on the other side of the STI region 214-1 is a second set of active regions also extending along the x-direction. Thus, the STI region 214-1 is between the first set of active regions and the second set of active regions and extends along the x-direction. Additionally, the VHDC structure 205 in the STI region 214-1 is also between the first set of active regions and the second set of active regions and extends along the x-direction. In one embodiment, the smallest and / or largest width (e.g., along the y-direction) of the VHDC structure 205 between the first set of active regions and the second set of active regions is smaller than the width (e.g., along the y-direction) of the VHDC structure 209 connected to the VHDC structure 205.

[0078] Additionally, each of the STI regions 214-1 through 214-4 may be adjacent to a set of transistors in the active areas 220A, and the large STI region 224-1 may be spaced apart from the set of transistors. The VHDC structure 205 is coupled to or directly connected to the VHDC structure 209.

[0079] The width of the VHDC structure 209 along the Y direction is greater than the width of the VHDC structure 205 along the Y direction. For example, the width of the VHDC structure 209 along the Y direction may be in the range of about 2 μm to 8 μm. The width of the VHDC structure 205 along the Y direction may be in the range of about 10 nm to 100 nm. The area of ​​the VHDC structure 209 is about 4 μm. 2 to about 50 μm 2 The materials of the VHDC structures 205 and 209 may be the same or different.

[0080] The spare or large STI regions 224 can form extra alignment marks for backside through silicon vias (TSVs) or thermal vias that extend from under the large STI regions 224 to the underside of the substrate, as shown in FIG. 14b. The pr thermal vias of those TSVs are directly under the large dimension VHDC pads in the large STI regions 224 and are connected to the large dimension VHDC pads. The area of ​​the spare or large STI regions 224 is large enough to accommodate one or more TSVs or thermal vias therein. Of course, those spare or large STI regions 224 can also form extra alignment marks for upper TSVs or thermal vias that extend from above the large STI regions 224 to the upper side of the substrate. These thermal vias are directly over the large dimension VHDC pads in the spare STI regions and are connected to the large dimension VHDC pads. The TSVs or thermal vias of the present invention can be fabricated by a back-end-of-line (BEOL) foundry process and connected to the large dimension VHDC pads. Thus, TSVs or thermal vias can be described as being formed during the BEOL steps of a foundry manufacturing process or within the BEOL region of a semiconductor die.

[0081] In other embodiments, the VHDC structure may extend along a direction other than the X-direction, as shown in FIG. 15a. FIG. 15a shows a schematic top view of a semiconductor circuit structure 300 according to some embodiments of the present disclosure. Compared with the semiconductor circuit structure 200 shown in FIG. 14a, the semiconductor circuit structure 300 shown in FIG. 15a further includes STI regions 314-1, 314-2, and 314-3 and VHDC structures 305-1, 305-2, and 305-3 extending along the Y-direction. The VHDC structures 305-1, 305-2, and 305-3 are disposed below the initial semiconductor surface of the semiconductor substrate and formed in the STI regions 314-1, 314-2, and 314-3, respectively. The VHDC structures 305-1, 305-2, and 305-3 may be VHDC lines. The VHDC structures 305-1, 305-2, and 305-3 and the STI regions 314-1, 314-2, and 314-3 can extend along the Y direction (or along the width direction of the active area). Furthermore, the VHDC structures 305-1, 305-2, and 305-3 may extend across more than one active area 220A, for example, the VHDC structure 305-1 located in the upper left portion of FIG. 15 extends from one predetermined point adjacent to the active area 220A-2 to the horizontal STI region 214. Each of the STI regions 314-1, 314-2, and 314-3 may be adjacent to a set of transistors in the active area 220A.

[0082] 15a, VHDC structures extending along directions other than the X-direction may be connected (or electrically coupled) to VHDC structures extending along the X-direction and / or to VHDC pads in the large STI region. For example, VHDC structure 305-1 is connected (or electrically coupled) to VHDC structure 205, and VHDC structure 305-2 is connected (or electrically coupled) between these two VHDC structures 205. VHDC structure 305-3 is connected (or electrically coupled) to VHDC pad 209 in the large STI region 224. VHDC structures 305-1, 305-2, and 305-3 may be of similar dimensions and materials as VHDC structure 205.

[0083] The arrangement of VHDC structures / lines extending along the X direction, VHDC structures / lines extending along the Y direction (or a direction other than the X direction), and VHDC pads within the large STI regions provides a VHDC mesh within the chip or semiconductor substrate and below the initial semiconductor surface of the semiconductor substrate (also referred to as "direct die cooling technology"). The VHDC structures extending along the X direction (i.e., horizontal VHDC lines) can be used to connect to the VHDC structures (i.e., VHDC pads) within the large STI regions, and the VHDC structures extending along the Y direction (i.e., vertical VHDC lines) can be used to connect to the VHDC pads or horizontal VHDC lines.

[0084] In some embodiments, VHDC structures extending along a direction other than the X direction, such as VHDC structures 305-1, 305-2 and 305-3 shown in FIG. 15a, can be fabricated through the following steps. FIGS. 15b-c are schematic top views of the structures at different stages of the fabrication method. A pad oxide layer (not shown) and a pad nitride layer 3206 are sequentially deposited on a semiconductor substrate. Then, a temporary active area can be defined first by a photolithography step, and a temporary STI area and a large STI area (shown by dotted lines in FIG. 15b) can be defined outside the temporary active area. Then, a Z material is formed in the temporary STI area and the large STI area. Then, as shown in FIG. 15c, a true active area 150A can be defined by another photolithography step, and the removed temporary active area can be used for the remaining STI area.

[0085] The location, dimensions, and number of VHDC structures are not limited to those shown in FIG. 14 and FIG. 15a. As mentioned above, for heat dissipation applications, the VHDC structure may include (or consist of) high thermal conductivity materials such as tungsten (thermal conductivity about 170 W / m·K), boron nitride (BN, thermal conductivity about 600 W / m·K), aluminum nitride (AlN, thermal conductivity about 321 W / m·K). It is also possible to use other materials with higher thermal conductivity than the initial material (silicon dioxide) of the STI region, such as SiC, SiGe, undoped Si, or deposited diamond. In some embodiments, the VHDC structure may include (or consist of) (or be made of) a composite material including two or more high thermal conductivity materials. In the present invention, a portion of the silicon dioxide in the initial STI region may be replaced with the VHDC structure, thereby improving the heat dissipation capability since the material of the VHDC structure has a higher thermal conductivity than silicon dioxide and / or silicon.

[0086] As shown in FIG. 15a, the VHDC structure used for heat dissipation is separated from some STI regions next to the active area where the transistors are placed by a VHDC pad (e.g., the area of ​​the VHDC pad is about 4 μm 2 to about 50 μm 2 ) is located. In another example, all the VHDC structures can be thermally bonded together. For example, the VHDC structures (i.e., VHDC pads) of the large STI regions can be thermally bonded to the VHDC structures (i.e., VHDC lines) of the STI regions. Furthermore, the large STI regions can be employed to align with one or more thermal vias, as shown in FIG. 14b. Furthermore, all or most of the STI regions in the semiconductor chip (e.g., 60% or more, or 70%-90%) can be filled with the proposed VHDC structures for heat dissipation purposes.

[0087] FIG. 16a shows a schematic cross-sectional view of a semiconductor circuit structure 700 according to some embodiments of the present disclosure. The semiconductor circuit structure 700 includes an upper interconnect structure 440 on a semiconductor substrate 400. The upper interconnect structure 440 includes a contact structure 441, metal layers M1-M3, connecting vias V1 and V2, and a dielectric layer (or a set of insulator layers) 442. The contact structure 441, the metal layers M1-M3, and the connecting vias V1 and V2 are in a dielectric layer 442 that may include multiple dielectric underlayers. The contact structure 441 is between the transistor TS and the metal layer M1. The metal layers M1-M3 are sequentially arranged on the initial semiconductor surface OSS of the semiconductor substrate 400 along the Z direction. The metal layers M1-M3 are vertically spaced apart from each other. The connecting vias V1 and V2 are arranged above the initial semiconductor surface OSS of the semiconductor substrate 400. The connecting via V1 is between the metal layers M1 and M2. The connection via V2 is between the metal layers M2 and M3. The metal layers M1 to M3 and the connection vias V1 and V2 are electrically connected to each other.

[0088] The semiconductor circuit structure 700 further includes a backside TSV 733 located directly below the second VHDC structure 209 (i.e., a VHDC pad including a composite layer as shown in FIG. 16a) in the large STI region 424 and connected to the second VHDC structure 209, a heat dissipation film 734 on the sidewall of the TSV 733, a barrier film or insulating film 735 on the sidewall of the heat dissipation film, a heat dissipation plate 737 located on or near the backside 400b of the semiconductor substrate 400 (or the backside of the chip), and an upper heat dissipation plate 739 above the upper interconnect structure 440. The TSV 733 is used for heat dissipation and can be understood as a (backside) thermal via. The heat dissipation plate 737 can be a heat sink, and its material can be the same as that of the heat dissipation film 734 or the TSV 733. The TSV 733 extends from the lower surface of the second VHDC structure 209 to the backside 400B of the semiconductor substrate 400. The TSVs 733 are connected between the second VHDC structure 209 and the heat dissipation plate 737 to form a heat dissipation path including the second VHDC structure, the TSVs 733 and the heat dissipation plate 737 .

[0089] For heat dissipation, the VHDC structure in this embodiment may include (or be made of) a material with a thermal conductivity higher than that of SiO2. For example, the VHDC structure may include tungsten, copper, BN, AlN, SiC, SiGe, or deposited diamond, undoped Si, or a combination thereof. In some embodiments, the VHDC structure includes an insulating material with a thermal conductivity higher than that of Si. The TSVs 733 include copper, and the heat dissipation film 734 may be BN or AlN.

[0090] Furthermore, the TSV733 is directly connected to the second VHDC structure 209, which in turn is connected to the first VHDC structure 205 (i.e., the VHDC line including the composite layer as shown in FIG. 16a) in the STI isolation 414, and the first VHDC structure 205 can be further connected to the transistor (such as the source / drain region of the transistor) through the corresponding connection plug 431. In this way, the heat generated from the transistor can be dissipated to the TSV733 through the connection plug 431, the first VHDC structure 205, and the second VHDC structure 209. Thus, a VHDC heat dissipation network with high heat dissipation efficiency is provided. In another embodiment, the VHDC structure may be isolated from the transistor, but the heat dissipation purpose can be reached through the VHDC line, the VHDC pad, and the TSV733.

[0091] The VHDC 205, which is in and runs along the STI region 414, can be connected in a self-aligned or self-built manner to the source or drain terminal of the transistor through a connection plug 431, which is in the active area housing the transistor. The connection plug 431 is connected to the sidewall of the VHDC structure.

[0092] The conventional semiconductor circuit structure only includes the upper thermal vias of the upper interconnect structure 440, but does not include the VHDC structure, especially the VHDC pad. Therefore, locating the upper thermal vias is a significant problem. Moreover, the upper thermal vias of the conventional semiconductor circuit structure are only located and insulated in the dielectric layer 442 of the upper interconnect structure 440, and these upper thermal vias are spaced apart from the transistors. Therefore, it is difficult to efficiently dissipate the heat generated from the transistors. However, the semiconductor circuit structure according to the present disclosure provides a large alignment window for the thermal vias through the help of the VHDC pads. Furthermore, with the help of the VHDC structure, the thermal coupling path between the thermal vias and the source / drain terminals of the transistors is shortened. Therefore, the configuration of the present disclosure can efficiently dissipate the heat generated from the transistors.

[0093] 16B shows a schematic cross-sectional view of a semiconductor circuit structure 800 according to some embodiments of the present disclosure. The semiconductor circuit structure 800 includes an upper or top surface thermal via 833 in the dielectric layer 442 of the upper interconnect structure 440. The upper thermal via 833 extends upward from the top surface of the second VHDC structure 209 to the upper heat dissipation plate 739 and penetrates the dielectric layer 442 of the upper interconnect structure 440.

[0094] Thus, the upper thermal via 833 is connected to the second VHDC structure 209 (VHDC pad of the STI insulation 424). Then, the second VHDC structure 209 is connected to the first VHDC structure 205 (i.e., the VHDC line of the STI insulation 414). The first VHDC structure 205 is connected to the transistor (such as the source / drain region of the transistor) through the corresponding connection plug 431. Thus, the upper heat dissipation plate 739, the upper thermal via 833, the first VHDC structure 205 and the second VHDC structure 209 can form a heat dissipation path for the heat generated from the transistor. Thus, the heat generated from the transistor can be dissipated to the upper thermal via 833 through the connection plug 431, the first VHDC structure 205 and the second VHDC structure 209. According to the direct thermal cooling technology of the present invention, a VHDC heat dissipation network with high heat dissipation efficiency is provided. In another embodiment, the VHDC structure 205 (VHDC line of STI isolation 414) may be isolated from the transistor, but the heat dissipation purpose may be achieved. In other embodiments, the upper thermal via 833 may extend from the top surface of the upper interconnect structure 440 to the first VHDC structure 205. Furthermore, the material of the upper thermal via 833 may be a Z material, e.g., copper, which has a higher thermal conductivity than Si or SiO2, and the material of the upper thermal via 833 may be the same or different from the material of the upper heat dissipation plate 739.

[0095] 16c is a schematic cross-sectional view of a semiconductor circuit structure 900 according to some embodiments of the present disclosure. The difference between the semiconductor circuit structure 900 shown in FIG. 16c and the semiconductor circuit structure 800 shown in FIG. 16b is that the semiconductor circuit structure 900 includes an upper heat dissipation film 934 on the sidewall of the upper thermal via 833. The upper heat dissipation film 934 includes (or may be made of) a material having a higher thermal conductivity than Si or SiO2, such as BN or AlN. By configuring the upper heat dissipation film 934 on the upper thermal via 833, the heat dissipation efficiency can be improved.

[0096] In some embodiments, the TSVs 733 shown in FIG. 16a and the upper thermal vias 833 shown in FIG. 16b (or the upper heat dissipation film 934 and the upper thermal vias 833 in FIG. 16c) can be combined together as shown in FIG. 16d. In the semiconductor circuit structure 910 shown in FIG. 16d, some upper thermal vias 833 extend from the top surface of the upper interconnect structure 440 to the second VHDC structure 209 and connect to the upper heat dissipation plate 739. The TSVs 733 (additional thermal vias) extend from the back surface 400B of the semiconductor substrate 400 to the second VHDC structure 209 (or other VHDC structure) and connect to the heat dissipation plate 737 located on or near the back surface 400B of the semiconductor substrate 400. Such a sandwich structure (with an intermediate VHDC structure in the chip, an upper heat dissipation plate connected to the intermediate VHDC structure, and a heat dissipation plate on the back surface of the semiconductor substrate and connected to the intermediate VHDC structure) can significantly improve the heat dissipation capability of the IC chip.

[0097] In advanced 2.5D or 3D packaging structures, or HBM structures, two or more IC / memory chips are stacked together. Thus, any of the structures in Fig. 16a-16d may be used for these IC chips stacked vertically. For example, as shown in Fig. 16e, the VHDC structure in Fig. 16d may be used for both chips C1 and C2 stacked together. In another embodiment, as shown in Fig. 16f, chip C1 (having the VHDC structure in Fig. 16b) may be flipped upside down first and then stacked on top of chip C2 (having the VHDC structure in Fig. 16d). Of course, another interposer (such as a Si interposer or other interposer) may be placed between these two IC chips, and any of the structures in Fig. 16a, 16b, or 16c may be used for the interposer.

[0098] FIG. 17a shows a semiconductor circuit structure including a FinFET transistor and an STI region adjacent to (or surrounding) the FinFET transistor, where a portion of the STI region (shown as a diagonal line) is replaced with a VHDC structure made of tungsten. FIG. 17a further shows the temperature distribution of the FinFET established by the TCAD simulation software Sentaurus. The temperature difference (ΔT) between the peak temperature of the transistor (hot spot region) and the ambient temperature (40° C.) is calculated when a portion of the STI region is replaced with tungsten, as shown in FIG. 17b. The term “full” in FIG. 17b represents that none of the STI regions are replaced with tungsten. The terms “1 nm” to “15 nm” represent the remaining thickness of the STI region that is not replaced with tungsten. It is clear that the smaller the remaining thickness of the STI region is, the smaller the temperature difference between the peak temperature of the transistor and the ambient temperature (improving the heat dissipation performance). Therefore, the present disclosure can effectively reduce the peak temperature of the transistor.

[0099] The present disclosure provides a direct die cooling technology based on composite STI regions (or heat removal structures, e.g., VHDC lines and VHDC pads under the initial semiconductor surface and within the STI regions). Depending on the requirements, several VHDC structures can be connected to the transistors, and the heat removal structures can form a VHDC mesh or heat dissipation network within the chip or semiconductor substrate. This provides greater misalignment tolerance due to the large STI regions with more space to accommodate VHDC pads, shortens the path connecting the backside TSVs to the VHDC mesh, improves IR drop of signal transmission, and enhances heat dissipation.

[0100] It should be noted that the above-mentioned structures and methods are provided for illustration purposes. The present disclosure is not limited to the above-disclosed structures and procedures. Other embodiments having different configurations of known elements are applicable, and the illustrated structures may be adjusted and modified based on the needs of the actual application. Of course, it should be noted that the configurations in the figures are drawn for illustrative purposes only, not for limitation. Thus, it is known to those skilled in the art that the relevant elements and layers in the semiconductor structure, the shape or positional relationship of the elements, and the details of the procedures may be adjusted or modified according to the actual requirements and / or manufacturing stages of the actual application.

[0101] While the present disclosure has been described by way of example and in terms of exemplary embodiments, it is to be understood that the disclosure is not limited thereto. On the contrary, the disclosure is intended to cover various modifications and similar arrangements and procedures. The scope of the appended claims should therefore be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. [Brief description of the drawings]

[0102] [Figure 1a] FIG. 1 shows a schematic top view of a conventional semiconductor circuit structure having an STI region and an active region. [Figure 1b] FIG. 1b shows a top view of a partial area of ​​FIG. [Figure 1c] FIG. 1b shows a cross-sectional view of a partial region of FIG. [Figure 2a] A top view is shown after active areas and shallow trench isolation (STI) regions are formed. [Figure 2b] 3 shows a cross-sectional view after active areas and shallow trench isolation (STI) regions have been formed. [Figure 3a] A top view is shown after a protective region of nitride has been formed over the center of the active area. [Figure 3b] The cross-sectional view is shown after a protective region of nitride has been formed over the center of the active area. [Figure 4a]A top view is shown after vertical spacers are formed to cover the exposed silicon sidewalls. [Figure 4b] A cross-sectional view is shown after vertical spacers are formed covering the exposed silicon sidewalls. [Figure 5a] A top view is shown after the deep silicon sidewalls are exposed. [Figure 5b] A cross-sectional view is shown after the deep silicon sidewalls are exposed. [Figure 6a] A top view is shown after the hollow tunnel regions are formed. [Figure 6b] 1 shows a cross-sectional view after the cavity tunnel regions have been formed. [Figure 6c] 1 shows a cross-sectional view after the cavity tunnel regions have been formed. [Figure 7a] A top view is shown after the heat dissipation material has been deposited. [Figure 7b] 4 shows a cross-sectional view after a high thermal conductivity material has been deposited. [Figure 8a] A top view is shown after the horizontal heat dissipation plate (HHDP) and vertical heat dissipation column (VHDC) are formed. [Figure 8b] 1 shows a cross-sectional view after the horizontal heat dissipation plate (HHDP) and vertical heat dissipation column (VHDC) have been formed. [Figure 9a] 1 illustrates a top view of another embodiment after the HHDP and VHDC have been formed. [Figure 9b] 1 illustrates a cross-sectional view of another embodiment after the HHDP and VHDC are formed. [Figure 10] Shows that the HHDP and VHDC are connected and extend to the edge of the chip / die. [Figure 11] 1 shows a cool transistor according to the present invention. [Figure 12a] 1 shows cross-sectional views of different embodiments of the present invention; [Figure 12b] 1 shows cross-sectional views of different embodiments of the present invention; [Figure 12c] FIG. 12b shows that the VHDC of FIG. 12b extends to the edge of the chip / die, according to another embodiment of the present invention. [Figure 13]Another cool transistor according to FIG. 12b is shown. [Figure 14a] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 14b] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 15a] 1 shows a schematic top view of a semiconductor circuit structure according to some embodiments of the present disclosure. [Figure 15b] 15a-15c show schematic top views of the structure at different stages of a method for manufacturing the semiconductor circuit of FIG. [Figure 15c] 15a-15c show schematic top views of the structure at different stages of a method for manufacturing the semiconductor circuit of FIG. [Figure 16a] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 16b] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 16c] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 16d] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 16e] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Fig. 16f] 1A-1D show schematic cross-sectional views of different semiconductor circuit structures according to some embodiments of the present disclosure. [Figure 17a] The temperature distribution of the FinFET established by Sentaurus TCAD is shown. [Figure 17b] The temperature difference versus thickness of the STI region is shown.

Claims

1. a semiconductor substrate having an initial semiconductor surface; a set of active regions in the semiconductor substrate; a first shallow trench isolation (STI) region adjacent the set of active areas and extending along a first direction; The first STI region includes a heat removal layer, and the material of the heat removal layer is SiO. ２ A semiconductor circuit structure that is different from the above.

2. The thermal conductivity of the heat removal layer is SiO ２ 13. The semiconductor circuit structure of claim 1, wherein the thermal conductivity of the semiconductor circuit structure is greater than or equal to 1000 .mu.m.

3. The semiconductor circuit structure of claim 2 , wherein the heat extraction layer is an electrical insulator during operation of the semiconductor circuit structure.

4. 3. The semiconductor circuit structure of claim 2, wherein the heat extraction layer extends into one of the set of the active areas.

5. 3. The semiconductor circuit structure of claim 2, wherein the heat extraction layer comprises a metal layer and a thin insulating layer, the thin insulating layer being between the metal layer and the set of active areas.

6. The semiconductor circuit structure of claim 2 , wherein the heat extraction layer comprises a composite material.

7. The first STI region is formed of SiO under the heat removal layer. ２ The semiconductor circuit structure of claim 2 further comprising a layer.

8. 2. The semiconductor circuit structure of claim 1, wherein the heat extraction layer is in a front end of the line (FEOL) region of the semiconductor circuit structure.

9. The semiconductor circuit structure of claim 1 , wherein the first STI region surrounds the set of active areas.

10. 10. The semiconductor circuit structure of claim 9, wherein the heat extraction layer is in the first STI region and is located below the initial semiconductor surface, the heat extraction layer surrounding a peripheral boundary of the set of active areas.

11. a spare STI region connected to the first STI region; The semiconductor circuit structure of claim 1 , wherein the heat extraction layer extends along the first direction to the preliminary STI region.

12. The semiconductor circuit structure of claim 11 , wherein the preliminary STI region is proximate to a center of the semiconductor substrate or proximate to an edge of the semiconductor substrate.

13. further comprising a heat removal pad in the pre-STI region; The semiconductor circuit structure of claim 11 , wherein the heat extraction layer is connected to the heat extraction pad.

14. 14. The semiconductor circuit structure of claim 13, further comprising a thermal via disposed over the pre-STI region and connected to the heat removal pad within the pre-STI region.

15. The semiconductor circuit structure of claim 14 , further comprising a heat sink plate disposed above and connected to the thermal vias.

16. a plurality of insulators over the set of active regions; 15. The semiconductor circuit structure of claim 14, wherein the thermal vias extend through the plurality of insulators and connect to the heat removal pads in the pre-STI regions.

17. 20. The semiconductor circuit structure of claim 16, wherein the plurality of insulators and the thermal vias are in a back end of line (BEOL) region of the semiconductor circuit structure.

18. a through semiconductor via (TSV) in the pre-STI region extending from a back surface of the semiconductor substrate to a bottom surface of the heat removal pad; 14. The semiconductor circuit structure of claim 13, wherein the back surface faces the initial semiconductor surface.

19. 20. The semiconductor circuit structure of claim 18, further comprising a heat sink plate disposed beneath the back surface of the semiconductor substrate and connected to the through semiconductor via.

20. 2. The semiconductor circuit structure of claim 1, wherein the first STI region surrounds four sidewalls of one of the set of the active areas.

21. a semiconductor substrate having an initial semiconductor surface; a set of transistors formed in the semiconductor substrate; a composite material STI region adjacent to the set of transistors and extending along a first direction to an edge of the semiconductor substrate; The composite STI region is in a front-end-of-line (FEOL) region of the semiconductor circuit structure.

22. 22. The semiconductor circuit structure of claim 21, wherein the composite STI region comprises a heat extraction layer adjacent the set of transistors and extending along the first direction to an edge of the semiconductor substrate.

23. Further comprising a thermal via provided above or below the heat removal layer; 23. The semiconductor circuit structure of claim 22, wherein the thermal vias are connected to the heat removal layer.

24. Further comprising a heat sink plate above or below the semiconductor substrate; 24. The semiconductor circuit structure of claim 23, wherein the semiconductor substrate is connected to the thermal via.

25. 24. The semiconductor circuit structure of claim 23, wherein the thermal via is in a back end of line (BEOL) region of the semiconductor circuit structure.

26. A semiconductor circuit structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, The first semiconductor chip includes: a first semiconductor substrate having an initial semiconductor surface; a set of first active regions in the first semiconductor substrate; a first extended shallow trench isolation (STI) region in the first semiconductor substrate adjacent the set of first active areas; The first extended STI region includes a first heat extraction layer, and the thermal conductivity of the first heat extraction layer is SiO. ２ The thermal conductivity is higher than that of The second semiconductor chip includes: a second semiconductor substrate having an initial semiconductor surface; a set of second active regions in the second semiconductor substrate; a second extended shallow trench isolation (STI) region in the second semiconductor substrate adjacent the set of second active areas; The second extended STI region includes a second heat extraction layer, the thermal conductivity of the second heat extraction layer being SiO. ２ The thermal conductivity of semiconductor circuit structures is higher than that of

27. a first preliminary STI region in the first semiconductor substrate and connected to the first extended STI region; a first heat removal pad is in the first pre-STI region, the first heat removal layer extends to the first pre-STI region and is connected to the first heat removal pad; a second preliminary STI region in the second semiconductor substrate and connected to the second extended STI region; 27. The semiconductor circuit structure of claim 26, wherein a second heat removal pad is in the second preliminary STI region, and the second heat removal layer extends to the second preliminary STI region and is connected to the second heat removal pad.

28. a first thermal via in the first semiconductor substrate; the first thermal via is connected to the first heat removal pad and extends from the first heat removal pad to a first heat dissipation plate on the first semiconductor substrate; further comprising a second thermal via in the second semiconductor substrate; 30. The semiconductor circuit structure of claim 27, wherein the second thermal via is connected to the second heat removal pad and extends from the second heat removal pad to a second heat sink plate on the second semiconductor substrate.

29. 30. The semiconductor circuit structure of claim 28, wherein the first heat sink plate is connected to the second heat sink plate.

30. a semiconductor substrate having an initial semiconductor surface; an active region in the semiconductor substrate; a first shallow trench isolation (STI) region surrounding four sidewalls of the active area; The first STI region includes a heat extraction layer surrounding four sidewalls of the active region, the thermal conductivity of the heat extraction layer being SiO. ２ The thermal conductivity of semiconductor circuit structures is higher than that of

31. a semiconductor substrate having an initial semiconductor surface; a first set of active regions disposed in the semiconductor substrate and extending along a first direction; a second set of active regions disposed in the semiconductor substrate and extending along the first direction; a first shallow trench isolation (STI) region between the first set of active areas and the second set of active areas, the first shallow trench isolation (STI) region extending along the first direction; The first STI region includes a heat extraction layer extending along the first direction, and the thermal conductivity of the heat extraction layer is SiO ２ A semiconductor circuit structure having a thermal conductivity higher than that of

32. a preliminary STI region spaced apart from the first set of active areas and the second set of active areas; 32. The semiconductor circuit structure of claim 31, wherein the preliminary STI region is connected to the first STI region and includes a heat extraction pad in the preliminary STI region, and the heat extraction layer is connected to the heat extraction pad.

33. 12. The semiconductor circuit structure of claim 11, wherein the width of the heat extraction pad is greater than the width of the heat extraction layer.

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