Storage unit, memory, and manufacturing method of them

Abstract

To reduce an occupied area of a storage unit.SOLUTION: A storage unit contains: a channel layer 400 that forms a reading pipe and a writing pipe of a vertical channel to be laminated; a gate dielectric layer 500; a gate electrode layer 600; and an insulation dielectric layer 800. The channel layer contains a first channel 411 and a second channel 421 that are laminated with an interval. The first channel is positioned to a housing hole 210, and the second channel is at least partially positioned to the housing hole. The gate electrode layer contains a first gate 611 and a second gate 621. The first gate is formed in the first inner hole 412 of the first channel, and is directly or indirectly is connected to the second channel. The second gate is at least partially formed into the second inner hole 422 of the second channel. The gate dielectric layer is formed to between the gate electrode layer and the channel layer, and the insulation dielectric layer is formed on at least between the first channel and the second channel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present application relates to the field of semiconductor technology, and in particular to storage units, memories and methods for manufacturing the same. [Background technology]

[0002] The storage unit of a typical dynamic random access memory (DRAM) is a metal oxide semiconductor (MOS) transistor with a drain connected to a capacitor. This storage unit consumes a large amount of power because it must constantly refresh the charge in the capacitor to prevent data loss, release the charge in the capacitor when reading, and write the data again after reading is complete. On the other hand, the capacitor occupies a large area, making it difficult to miniaturize it.

[0003] Two-transistor capacitorless dynamic random access memory (2T0C) uses two MOS transistors as storage units, with the drain of one transistor connected to the gate of the other transistor, and stores information by using the gate capacitance to store charge and change the transconductance of the transistor.

[0004] Existing dynamic random access memories based on 2T0C memory units are usually connected by two horizontal channel thin film transistors (TFTs) on the same plane, which occupy a large area and have low integration density. Summary of the Invention [Problem to be solved by the invention]

[0005] The objective of the present application is to provide a storage unit, a memory and a manufacturing method thereof that can reduce the area occupied by the storage unit and improve the integration density of a dynamic random access memory.

[0006] In order to achieve the above object, the present application provides a storage unit, the storage unit being disposed on a separation layer on one side of a substrate, the separation layer including a receiving hole; The storage unit includes: a channel layer including a first channel and a second channel stacked with a space between them, the first channel being located in the receiving hole and the second channel being at least partially located in the receiving hole, the first channel having a first inner hole on a side away from the substrate, and the second channel having a second inner hole on a side away from the substrate; an insulating dielectric layer formed at least between the first channel and the second channel; a gate electrode layer including a first gate and a second gate, the first gate being formed in the first bore and directly or indirectly connected to the second channel, and the second gate being at least partially formed in the second bore; a gate dielectric layer formed between the gate electrode layer and the channel layer.

[0007] Optionally, the storage unit further includes a conductor layer, the conductor layer including a first conductor portion, the first conductor portion being at least partially located between the first gate and the second channel, the first gate and the second channel being indirectly connected via the first conductor portion, and the insulating dielectric layer being disposed surrounding the first conductor portion.

[0008] Optionally, the first conductor portion extends at least partially to the first gate within the first bore.

[0009] Optionally, the height of the top surface of the first conductor portion relative to the substrate is equal to or greater than the height of the insulating dielectric layer relative to the substrate.

[0010] Optionally, the conductor layer further includes a second conductor portion, the second conductor portion being at least partially disposed in the second bore, and the second gate being located between the second conductor portion and the gate dielectric layer.

[0011] Optionally, the storage unit further includes a lead layer, the lead layer including a first lead layer, a second lead layer, and a third lead layer arranged at a distance from each other, the first lead layer including a first drain, the second lead layer including a first source, the third lead layer including a second source, the first drain and the first source both being located outside the accommodating hole and both being connected to the first channel, the second source being located outside the accommodating hole and being connected to the second channel, and the accommodating hole being connected to the first drain through the second source and the first source.

[0012] Optionally, a portion of the first channel near one end of the substrate is buried in the first drain.

[0013] Optionally, the conductor layer and the gate electrode layer are made of different materials.

[0014] Optionally, the isolation layer and the insulating dielectric layer are made of different materials.

[0015] The present application also provides a memory, the memory comprising: A plurality of said storage units; a write word line connected to second gates of a plurality of the storage units; a write bit line connected to second sources of the plurality of said storage units; a read word line connected to first drains of the plurality of storage units; a read bit line connected to the first sources of the plurality of said storage units.

[0016] The present application also provides a method for manufacturing a memory, the method comprising: forming an isolation layer and a lead layer on a substrate, the lead layer including a first lead layer, a second lead layer, and a third lead layer formed sequentially and spaced apart, the first lead layer, the second lead layer, and the third lead layer all being located on the isolation layer, the first lead layer including a first drain and a read word line connected together, the second lead layer including a first source and a read bit line connected together, and the third lead layer including a second source and a write bit line connected together; forming a receiving hole in the isolation layer, the receiving hole passing through the second source and the first source to the first drain; forming a first channel, a first gate dielectric portion, and a first gate in the receiving hole, the first drain and the first source both being connected to the first channel; forming an insulating dielectric layer on at least a side of the first channel away from the substrate; forming a second channel, a second gate dielectric portion, a second gate, and a write word line on a side of the insulating dielectric layer away from the substrate, the second channel, the second gate dielectric portion, and the second gate all being at least partially located in the receiving hole, the first gate being directly or indirectly connected to the second channel, the second source being connected to the second channel, and the write word line being connected to the second gate.

[0017] Optionally, the method for manufacturing the memory includes: sequentially forming a first channel layer, a first gate dielectric layer, a first gate electrode layer, and a first conductor layer on a side of the isolation layer remote from the substrate, the first channel layer, the first gate dielectric layer, the first gate electrode layer, and the first conductor layer all being at least partially located in the receiving hole; removing a portion of the first conductor layer to form a first conductor portion in the receiving hole, and then removing portions of the first channel layer, the first gate dielectric layer and the first gate electrode layer to form the first channel, the first gate dielectric portion and the first gate in the receiving hole, a step in which a height of an upper surface of the first conductor portion relative to the substrate is greater than heights of upper surfaces of the first channel, the first gate dielectric portion and the first gate relative to the substrate; forming an insulating dielectric layer surrounding the first conductor portion on a side of the first channel, the first gate dielectric portion and the first gate away from the substrate, the insulating dielectric layer having a height of a top surface of the insulating dielectric layer relative to the substrate equal to or less than a height of a top surface of the first conductor portion relative to the substrate; and sequentially forming a second channel layer, a second gate dielectric layer, a second gate electrode layer, a second conductor layer, and a fourth lead layer on a side of the isolation layer away from the substrate, the second channel layer, the second gate dielectric layer, the second gate electrode layer, and the second conductor layer all being at least partially located in the receiving hole, and patterning the second channel layer, the second gate dielectric layer, the second gate electrode layer, the second conductor layer, and the fourth lead layer to form the second channel, the second gate dielectric portion, the second gate, the second conductor portion, and the write word line.

[0018] Optionally, a portion of the first channel layer, the first gate dielectric layer, the first gate electrode layer, and the first conductor layer is removed using an isotropic etch such that a height of the first conductor portion is greater than heights of the first channel, the first gate dielectric portion, and the first gate.

[0019] Optionally, when forming the insulating dielectric layer, an insulating dielectric base layer is formed in the receiving hole to cover the first conductor portion, the first channel, and the first gate dielectric portion; An isotropic etch is used to remove portions of the insulating dielectric base layer to form the insulating dielectric layer.

[0020] Optionally, when forming a receiving hole in the separation layer, the receiving hole passing through the second source and the first source to the first drain, the etching depth is greater than the depth of the upper surface of the first drain.

[0021] Optionally, an orthogonal projection of the receiving hole on the substrate is located within an orthogonal projection of the first drain, the first source and the second source on the substrate. Effect of the Invention

[0022] The storage unit, memory and its manufacturing method disclosed in the present application have the following beneficial effects.

[0023] In the present application, the storage unit includes source and drain electrodes, a channel layer, a gate dielectric layer, and a gate electrode layer, the channel layer includes a first channel and a second channel stacked at an interval, the first channel is located in the receiving hole, the second channel is at least partially located in the receiving hole, the gate electrode layer includes a first gate and a second gate, the first gate is formed in the first inner hole of the first channel, the second gate is at least partially formed in the second inner hole of the second channel, and the gate dielectric layer is formed between the gate electrode layer and the channel layer. The source and drain electrodes, the channel layer, the gate dielectric layer, and the gate electrode layer form a stacked vertical channel read tube and write tube, and the channels of the read tube and write tube are located in the same receiving hole, and compared with the storage unit connected by two horizontal channel thin film transistors on the same plane, the area occupied by the storage unit is reduced and the integration density of the transistors is increased.

[0024] Additional features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. [Brief description of the drawings]

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative efforts. [Figure 1] 2 is a schematic cross-sectional view of a storage unit in the X direction according to the first embodiment of the present application. FIG. [Diagram 2] 2 is a schematic cross-sectional view of a memory unit in the Y direction according to the first embodiment of the present application. FIG. [Diagram 3] FIG. 2 is a schematic diagram showing a circuit configuration of a storage unit in the first embodiment of the present application. [Figure 4] 1 is a schematic diagram showing a circuit configuration of a memory according to a first embodiment of the present application. [Diagram 5] 1 is a flowchart of a method for manufacturing a memory in an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of forming a separation layer and a lead layer in an embodiment of the present application. [Figure 7] 2 is a schematic diagram of an opening in a separation layer in an embodiment of the present application. [Figure 8] FIG. 2 is a schematic diagram of forming a first conductor layer in an embodiment of the present application. [Figure 9] 4 is a schematic diagram showing a process for forming a first conductor portion in an embodiment of the present application. FIG. [Figure 10] FIG. 2 is a schematic diagram of a forming a read tube in an embodiment of the present application. [Figure 11] FIG. 2 is a schematic diagram of forming an insulating dielectric base layer in an embodiment of the present application. [Figure 12] FIG. 2 is a schematic diagram of forming an insulating dielectric layer in an embodiment of the present application. [Figure 13]FIG. 2 is a schematic diagram of forming a fourth lead layer in an embodiment of the present application. [Figure 14] FIG. 2 is a schematic cross-sectional view in the X direction forming a writing tube in an embodiment of the present application. [Figure 15] FIG. 2 is a schematic cross-sectional view in the Y direction forming a writing tube in an embodiment of the present application.

[0027] Explanation of reference symbols: 10 writing tubes, 20 reading tubes; 100 substrate, 200 separation layer, 210 receiving hole; 300 lead layer, 310 first lead layer, 311 first drain, 320 second lead layer, 321 first source, 330 third lead layer, 331 second source, 340 fourth lead layer; 400 channel layer, 410 first channel layer, 411 first channel, 412 first bore, 420 second channel layer, 421 second channel, 422 second bore; 500 gate dielectric layer, 510 first gate dielectric layer, 511 first gate dielectric portion, 520 second gate dielectric layer, 521 second gate dielectric portion; 600 gate electrode layer, 610 first gate electrode layer, 611 first gate, 620 second gate electrode layer, 621 second gate; 700 conductor layer, 710 first conductor layer, 711 first conductor portion, 720 second conductor layer, 721 second conductor portion, 800 insulating dielectric layer, 900 photoresist. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings. However, exemplary embodiments may be embodied in various forms and should not be construed as being limited to the examples set forth herein, but rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0029] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present application. However, one skilled in the art will appreciate that the technical solutions of the present application may be implemented without one or more of the specific details, or may employ other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the present application.

[0030] The present application will be described in more detail below in conjunction with the accompanying drawings and specific examples. It should be noted that the technical features contained in the various embodiments of the present application described below can be combined with each other as long as they are not mutually inconsistent. The embodiments described below with reference to the drawings are illustrative and are intended to explain the present application, and should not be construed as limiting the present application.

[0031] 1 and 2, in this embodiment, the storage unit includes source and drain electrodes, a channel layer 400, a gate dielectric layer 500, a gate electrode layer 600, and an insulating dielectric layer 800. The storage unit is located on an isolation layer 200 on a substrate 100 and is connected to an extension of a lead layer 300.

[0032] The substrate 100 may be any base for mounting a semiconductor integrated circuit known to those skilled in the art, for example, an insulating substrate, a semiconductor substrate, or a composite substrate, and is not limited thereto in the present application. It should be noted that the substrate 100 may be removed after the memory unit is manufactured, and after the memory unit is manufactured and the substrate 100 is removed, its upper or lower surface is bonded to another substrate, such as a peripheral substrate including a peripheral device, a temporary support substrate, or a substrate on which other devices are provided. The relationship between the substrate 100 and the memory unit is not particularly limited in the present application.

[0033] The channel layer 400 includes a first channel 411 and a second channel 421. The first channel 411 and the second channel 421 are stacked with a gap between them. The isolation layer 200 includes a receiving hole 210. The first channel 411 is located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210. The first channel 411 has a first inner hole 412 on a side remote from the substrate 100, and the second channel 421 has a second inner hole 422 on a side remote from the substrate 100.

[0034] The insulating dielectric layer 800 is formed at least between the first channel 411 and the second channel 421. The gate electrode layer 600 includes a first gate 611 and a second gate 621. The first gate 611 is formed in the first bore 412 and is directly or indirectly connected to the second channel 421. The second gate 621 is at least partially formed in the second bore 422. The first gate 611 and the second gate 621 are surrounded by the first channel 411 and the second channel 421, respectively. Thus, the channel width of the transistor is increased, and the read and write current of the transistor is increased. The gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400, and serves to insulate between the gate and the channel. The gate dielectric layer 500 includes a first gate dielectric portion 511 and a second gate dielectric portion 521. The first gate dielectric portion 511 is located between the first channel 411 and the first gate 611 , and the second gate dielectric portion 521 is located between the second channel 421 and the second gate 621 .

[0035] As shown in the embodiment of FIG. 2, the lead layer 300 includes a first lead layer 310, a second lead layer 320, and a third lead layer 330 formed in sequence, and the first lead layer 310, the second lead layer 320, and the third lead layer 330 are all located on the separation layer 200. The source and drain electrodes include a first drain 311, a first source 321, and a second source 331. Any of the source and drain electrodes may be separate from the lead layer, or may be formed integrally with the portion connecting the lead layer 300 and the channel layer 400, i.e., the lead layer 300, and are not particularly limited in the present application. In this embodiment, each of the source and drain electrodes is integrated with the lead layer 300. That is, the first lead layer 310 includes the first drain 311, the second lead layer 320 includes the first source 321, and the third lead layer 320 includes the second source 331. The first drain 311 and the first source 321 are both located outside the accommodating hole 210 and are both connected to the first channel 411, and the second source 331 is located outside the accommodating hole 210 and is connected to the second channel 421.

[0036] The storage unit includes two thin film transistors, which are stacked on a substrate 100. The two thin film transistors are a read tube 20 and a write tube 10, respectively. The read tube 20 includes a first gate 611, a first channel 411, a first drain 311, and a first source 321. The write tube 10 includes a second drain, a second source 331, a second channel 421, and a second gate 621.

[0037] Existing dynamic random access memories based on 2T0C memory units are usually connected by two horizontal channel thin film transistors on the same plane, which occupy a large area and have low memory density.

[0038] In this embodiment, the storage unit includes source and drain electrodes, a channel layer 400, a gate dielectric layer 500, and a gate electrode layer 600. The channel layer 400 includes a first channel 411 and a second channel 421 stacked at a distance from each other. The first channel 411 is located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210. The gate electrode layer 600 includes a first gate 611 and a second gate 621. The first gate 611 is formed in a first inner hole 412 of the first channel 411, and the second gate 621 is formed at least partially in a second inner hole 422 of the second channel 421. The gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400, and the lead layer 300 includes a first drain 311, a first source 321, and a second source 331, the first drain 311 and the first source 321 are all connected around the first channel 411, and the second source 331 is connected around the second channel 421. The source and drain electrodes, the channel layer 400, the gate dielectric layer 500, and the gate electrode layer 600 form stacked vertical channel read tube 20 and write tube 10, and the channels of the read tube 20 and the write tube 10 are located in the same receiving hole 210, which reduces the area occupied by the storage unit and increases the integration density of the transistors compared with the storage unit connected by two horizontal channel thin film transistors on the same plane.

[0039] Moreover, the entirety of the first channel 411 is located in the receiving hole 210, and at least a portion of the second channel 421 is located in the receiving hole 210, and the first channel 411 and the second channel 421 are stacked in the same receiving hole 210. In the process of forming the vertically stacked write tube 10 and read tube 20, the manufacturing process of the memory is simplified and the manufacturing cost of the memory is reduced.

[0040] 1 and 2, the storage unit further includes a conductor layer 700. The conductor layer 700 includes a first conductor portion 711. The first conductor portion 711 is located at least partially between the first gate 611 and the second channel 421. The first gate 611 and the second channel 421 are indirectly connected through the first conductor portion 711.

[0041] The first conductor portion 711 can store or release charge when the write tube 10 is turned on, and the charge stored in the first conductor portion 711 affects the read current of the read tube 20. Therefore, the first conductor portion 711 can be made of a conductive material with strong charge retention ability, such as doped polysilicon, but the present application is not limited thereto as long as the material of the conductor layer 700 can realize charge storage.

[0042] 1 and 2, the insulating dielectric layer 800 is disposed surrounding the first conductor portion 711. The orthogonal projection of the first conductor portion 711 on the substrate 100 is located within the orthogonal projection of the first gate 611 on the substrate 100, and the first gate 611 is located between the first conductor portion 711 and the first gate dielectric portion 511 of the gate dielectric layer 500. That is, the insulating dielectric layer 800 separates the first gate 611, the first gate dielectric portion 511, and the first channel 411 from the second gate 621, the second gate dielectric portion 521, and the second channel 421.

[0043] The insulating dielectric layer 800 is disposed around the first conductor portion 711 and separates the first conductor portion 711 from the first channel 411 to prevent a short circuit between the first conductor portion 711 and the first channel 411, i.e., a short circuit between the gate and the channel of the read tube 20, thereby preventing the read tube from functioning impairing. Referring to Figures 1 and 2, the first conductor portion 711 extends at least partially to the first gate 611 in the first bore 412.

[0044] The first conductor portion 711 is provided in a groove formed in the surface of the first gate 611 away from the first channel 411. The first conductor portion 711 is connected to the second channel 421. Such a design improves the electrical characteristics of the read tube 20 and enhances the performance of the storage unit.

[0045] 1 and 2, the upper surface of first conductor portion 711 is higher than the upper surface of the end portion of first gate 611. First gate 611 and second channel 421 are spaced apart, and first conductor portion 711 is partially located in first inner hole 412 and partially located outside first inner hole 412. First gate 611 and second channel 421 are indirectly connected via first conductor portion 711.

[0046] Since the first gate 611 and the second channel 421 are spaced apart, the first conductor portion 711 is connected to the second channel 421, and the first gate 611 is not connected to the second channel 421, the first gate 611 and the first conductor portion 711 of the reading tube 20 are made of different materials, and the material of the first gate 611 of the reading tube 20 is selected to meet the electrical characteristics of the reading tube 20, and the first conductor portion 711 made of a material with strong charge retention capacity ensures the memory performance of the memory unit.

[0047] 1 and 2, the height of the upper surface of the first conductor portion 711 relative to the substrate 100 is equal to or greater than the height of the upper surface of the insulating dielectric layer 800 relative to the substrate 100.

[0048] The first conductor portion 711 is flush with the insulating dielectric layer 800 or is slightly exposed from the insulating dielectric layer 800, which ensures a reliable connection between the first conductor portion 711 and the second channel 421 and reduces the risk of leakage since the surface of the second channel 421 is relatively flat.

[0049] Referring to Figures 1 and 2, the conductor layer 700 further includes a second conductor portion 721 at least partially disposed in the second inner hole 422, and the second gate 621 is located between the second conductor portion 721 and the second gate dielectric portion 521 of the gate dielectric layer 500.

[0050] A second conductor 721 is provided above the second gate 621, i.e., in a groove formed on the upper surface of the second gate 621. The stack of the second conductor 721 and the second gate 621 is connected to the write word line WWL to improve the electrical connection between the second gate 621 and the write word line WWL. If the write word line WWL is manufactured simultaneously with the second conductor 721 and the second gate 621, the process cost and the difficulty of the process can be reduced, and the impedance of the write word line WWL can be reduced, thereby reducing the signal delay.

[0051] 1 and 3, the second gate 621 of the write tube 10 is connected to the write word line WWL, the second source 331 of the write tube 10 is connected to the write bit line WBL, and the second drain of the write tube 10 is connected to the storage node A. The first gate 611 of the read tube 20 is connected to the storage node A, the first source 321 of the read tube 20 is connected to the read word line RWL, and the first drain 311 of the read tube 20 is connected to the read bit line RBL.

[0052] The connection relationship between the write word line WWL, the write bit line WBL and the write tube 10 can be interchanged, and the connection relationship between the read word line RWL, the read bit line RBL and the read tube 20 can be interchanged. In addition, the operation methods of the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL in the storage operation are also changed accordingly, and are not particularly limited in the present invention.

[0053] The memory unit changes the charge of the gate capacitance of the read tube 20 through the write tube 10, thereby affecting the resistance state between the source and drain of the read tube 20, thereby realizing the distinction between "0" and "1". It can be understood that in this embodiment, the gate capacitance of the read tube 20 is the memory node A.

[0054] The specific storage principle of the storage unit is as follows:

[0055] In the process of writing a "1", the write word line WWL applies a positive voltage (greater than the threshold voltage Vth) to the gate of the write tube 10 to turn on the write tube 10, and the write bit line WBL applies a positive voltage to the source of the write tube 10 to inject charge into the gate capacitance of the read tube 20 (i.e., storage node A in FIG. 3). After the charge is injected, the gate and source voltages of the write tube 10 are removed and the "1" state is stored.

[0056] In the process of reading "1", the read word line RWL applies a read voltage to the source of the read tube 20, and because there is a certain charge on the gate capacitance, the read tube 20 is in a lower resistance state, and the read bit line RBL obtains a larger current, which can be amplified and identified by the peripheral circuit to complete the process of reading "1".

[0057] In the process of writing a "0", the write word line WWL applies a positive voltage (greater than the threshold voltage Vth) to the gate of the write tube 10 to turn on the write tube 10, and the write bit line WBL applies a negative voltage to the source of the write tube 10 to extract charge from the gate capacitance (i.e., the storage node) of the read tube 20. After the charge is extracted, the gate and source voltages of the write tube 10 are removed and the "0" state is stored.

[0058] In the process of reading "0", the read word line RWL applies a read voltage to the source of the read tube 20, and there is no charge on the gate capacitance, so the read tube 20 is in a higher resistance state, and the read bit line RBL obtains a smaller current, which can be amplified and identified by the peripheral circuit to complete the process of reading "0".

[0059] 1 and 2, the first channel 411 is entirely located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210. That is, the second channel 421 may be partially located in the receiving hole 210 and partially extend outside the opening of the receiving hole 210. The orthogonal projection of the first channel 411 on the substrate 100 is located within the orthogonal projection of the second channel 421 on the substrate 100. That is, the area occupied by the first channel 411 is equal to or smaller than the area occupied by the second channel 421. It can be understood that there is no particular relationship between the area occupied by the first channel 411 and the area occupied by the second channel 421, and the present invention is not particularly limited thereto.

[0060] The area occupied by the first channel 411 is equal to or less than the area occupied by the second channel 421, and the read tube 20 and the write tube 10 can be completely overlapped, so that the area occupied by the storage unit can be reduced and the storage density can be improved. Note that, as long as the orthogonal projection of the first channel 411 on the substrate 100 overlaps with the orthogonal projection of the second channel 421 on the substrate 100, the read tube 20 and the write tube 10 can be stacked on each other without completely overlapping, so that the area occupied by the storage unit can be reduced and the storage density can be improved.

[0061] 1 and 2, in one embodiment, the first channel 411 and the second channel 421 are both cylindrical structures, and the first inner hole 412 and the second inner hole 422 are inner holes of the cylindrical structures. The cylindrical portion of the first channel 411 and the cylindrical portion of the second channel 421 are arranged coaxially, and the outer diameter of the cylindrical portion of the first channel 411 and the outer diameter of the cylindrical portion of the second channel 421 are equal.

[0062] The cylindrical portion of the first channel 411 and the cylindrical portion of the second channel 421 are both located in the receiving hole 210 of the separation layer 200, so that in the process of forming the vertically stacked write tube 10 and read tube 20, the manufacturing process of the memory is simplified and the manufacturing cost of the memory is reduced. At the same time, the cylindrical portion of the first channel 411 and the cylindrical portion of the second channel 421 are both located in the receiving hole 210 of the separation layer 200, that is, the main structures of the write tube 10 and the read tube 20 are both located in the receiving hole 210 of the separation layer 200, so that the occupied area of ​​the memory unit can be further reduced and the integration density of the transistors can be improved.

[0063] It should be noted that the second channel 421, the second gate dielectric portion 521, and the second gate 621 may all be located in the receiving hole 210 of the separation layer 200, but are not limited thereto. The second channel 421, the second gate dielectric portion 521, and the second gate 621 may further include a portion located outside the receiving hole 210 according to a specific situation.

[0064] 1 and 2, the lead layer 300 includes a first lead layer 310, a second lead layer 320, and a third lead layer 330 that are spaced apart from each other. The first lead layer 310 includes a first drain 311, the second lead layer 330 includes a first source 321, and the third lead layer 330 includes a second source 331. The first drain 311 and the first source 321 are both located outside the receiving hole 210 and are both connected to the first channel 411, and the second source 331 is located outside the receiving hole 210 and is connected to the second channel 421. The receiving hole 210 is connected to the first drain 311 through the second source 331 and the first source 321.

[0065] That is, the orthogonal projection of the first channel 411 on the substrate 100 is located within the orthogonal projection of the first drain 311 and the first source 321 on the substrate 100, and the orthogonal projection of the second channel 421 on the substrate 100 is located within the orthogonal projection of the second source 331 on the substrate 100. Specifically, the first channel 411 is centrally located with respect to the first drain 311 and the first source 321, and the second channel 421 is centrally located with respect to the second source 331.

[0066] Since the first channel 411 is centrally located relative to the first drain 311 and the first source 321, and the second channel 421 is centrally located relative to the second source 331, the contact area between the channels of the write tube 10 and the read tube 20 and the corresponding source and drain electrodes can be improved, the contact resistance of the source and drain electrodes can be reduced, and the performance of the write tube 10 and the read tube 20 can be improved, thereby improving the performance of the memory unit.

[0067] 1 and 2, the first lead layer 310 intersects with the second lead layer 320, the third lead layer 330 extends in the same direction as the first lead layer 310, and the first channel 411 is formed at the intersection of the first lead layer 310 and the second lead layer 320. Preferably, the orthogonal projection of the first channel 411 on the substrate 100 is located within the orthogonal projection of the intersection of the first lead layer 310 and the second lead layer 320 on the substrate 100.

[0068] 1 and 2, the portion of the first channel 411 close to one end of the substrate 100 is embedded in the first drain 311. That is, the receiving hole 210 of the separation layer 200 partially enters the first drain 311. The portion of the first channel 411 close to one end of the substrate 100 enters the first drain 311, so that the contact area between the first drain 311 and the first channel 411 is increased and the contact resistance is reduced, thereby improving the performance of the readout tube 20. In another embodiment, the connection surface between the portion of the first channel 411 close to one end of the substrate 100 and the first drain 311 is flat, or the portion of the first channel 411 close to one end of the substrate 100 and the first drain 311 are indirectly connected via another component.

[0069] Exemplarily, the substrate 100 may be any base for mounting semiconductor integrated circuits known to those skilled in the art, including, but not limited to, an insulating substrate, a semiconductor substrate, or a composite substrate in the present application. Exemplarily, the substrate 100 may be bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide, or a semiconductor on insulator, etc., in which case the corresponding top semiconductor material is silicon, germanium, silicon germanium, or gallium arsenide, etc.

[0070] The isolation layer 200 is used as an interlayer insulating layer and may be a silicon oxide or low-k material layer to reduce crosstalk. The isolation layer 200 may include an air gap. The isolation layer 200 may be an insulating dielectric material common in the art and is not limited in this application.

[0071] The insulating dielectric layer 800 can be made of an insulating material such as a nitride or an oxynitride, but is not particularly limited in the present invention.

[0072] In some embodiments, the separation layer 200 and the insulating dielectric layer 800 are made of different materials. Since the material of the insulating dielectric layer 800 is different from the material of the separation layer 200, there is an etching selectivity between them, which facilitates the fabrication of the storage unit. The lead layer 300 and the gate electrode layer 600 can be made of metal materials or doped semiconductor materials with good electrical conductivity, where the metal materials include at least one of aluminum (Al), molybdenum (Mo), titanium (Ti), tungsten (W) and alloys thereof. The doped semiconductor materials include doped polysilicon. The gate electrode layer 600 can be made of a specific material according to the electrical property requirements of the write tube 10 and the read tube 20. The lead layer 300 and the gate electrode layer 600 can be made of the same or different metal materials or doped semiconductor materials.

[0073] The first conductor portion 711 can be formed of a conductive material capable of storing electric charges, such as doped polysilicon, but is not limited to this as long as the material of the conductor layer 700 can store electric charges.

[0074] In some embodiments, the conductor layer 700 and the gate electrode layer 600 are made of different materials. Since the conductor layer 700 is made of a different material than the gate electrode layer 600, there is an etch selectivity between them, which facilitates the fabrication of the memory unit.

[0075] The channel layer 400 can be formed of indium gallium zinc oxide (IGZO), and the off-current of a thin film transistor formed of indium gallium zinc oxide is extremely small, and when used in a 2T0C dynamic random access memory, the leakage rate can be significantly reduced. It should be noted that the channel layer 400 can be formed of, but is not limited to, an indium gallium zinc oxide material. The channel layer 400 can also be formed of other metal oxides or semiconductor materials according to specific circumstances.

[0076] The gate dielectric layer 500 may be made of a high-k material or other materials commonly used in the art for gate dielectric layers, such as hafnium dioxide (HfO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), etc.

[0077] The present application also provides a memory including a plurality of storage units connected to each other.

[0078] 1 to 4, the first lead layer 310 includes a first drain 311 and a read word line RWL that are integrally connected, and the first drains 311 of the multiple storage units are connected to and drawn out from the read word line RWL. The second lead layer 320 includes a first source 321 and a read bit line RBL that are integrally connected, and the first sources 321 of the multiple storage units are connected to and drawn out from the read bit line RBL. The third lead layer 330 includes a second source 331 and a write bit line WBL that are integrally connected, and the second sources 331 of the multiple storage units are connected to and drawn out from the write bit line WBL. The memory further includes a fourth lead layer 340 formed on the side of the second conductor portion 721 that is away from the substrate 100. The write word line WWL includes a part of the fourth lead layer 340, and the second gates 621 of the multiple storage units are connected to and drawn out from the write word line WWL. The memory further includes an isolation material layer on the fourth lead layer 340, where the isolation layer 200 is formed by stacking multiple isolation material layers.

[0079] In this embodiment, the memory includes a plurality of storage units connected to each other, each storage unit includes source and drain electrodes, a channel layer 400, a gate dielectric layer 500, and a gate electrode layer 600, the channel layer 400 is formed on one side of the substrate 100, the channel layer 400 includes a first channel 411 and a second channel 421 stacked together, the gate electrode layer 600 includes a first gate 611 and a second gate 621, the first gate 611 is formed in a first inner hole 412 of the first channel 411 and directly connected to the second channel 421. The first and second gate electrodes 621 are directly connected to the first channel 411 or indirectly connected to the second channel 421 through the first conductor portion 711, the second gate 621 is formed at least partially in the second inner hole 422 of the second channel 421, the gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400, the source and drain electrodes include a first drain 311, a first source 321 and a second source 331, the first drain 311 and the first source 321 are both connected to the first channel 411, and the second source 331 is connected to the second channel 421. The source and drain electrodes, the channel layer 400, the gate dielectric layer 500 and the gate electrode layer 600 form a stacked vertical channel read tube 20 and write tube 10, which reduces the area occupied by the storage units and improves the storage density per unit area compared to the storage units connected by two horizontal channel thin film transistors on the same plane.

[0080] The present application also provides a memory manufacturing method, which is used to manufacture the memory disclosed above. As shown in Figures 5 to 15, the memory manufacturing method includes:

[0081] S100: A separation layer 200 and a lead layer 300 are formed on a substrate 100.

[0082] As in the embodiment shown in FIG. 6, the lead layer 300 includes a first lead layer 310, a second lead layer 320, and a third lead layer 330 formed sequentially and spaced apart, the first lead layer 310, the second lead layer 320, and the third lead layer 330 are all located in the separation layer 200, the first lead layer 310 includes a first drain 311 and a read word line RWL that are integrally connected, the second lead layer 320 includes a first source 321 and a read bit line RBL that are integrally connected, and the third lead layer 330 includes a second source 331 and a write bit line WBL that are integrally connected.

[0083] Note that the first lead layer 310 and the second lead layer 320 do not extend in the same direction, i.e., the orthogonal projections of the first lead layer 310 and the second lead layer 320 on the substrate 100 intersect, and the third lead layer 330 extends in the same direction as either of the first lead layer 310 and the second lead layer 320. Preferably, the orthogonal projections of the first lead layer 310 and the second lead layer 320 on the substrate 100 are perpendicular to each other, and the third lead layer 330 extends in the same direction as either of the first lead layer 310 and the second lead layer 320. The orthogonal projection of the third lead layer 330 on the substrate 100 overlaps with the perpendicular intersection of the orthogonal projections of the first lead layer 310 and the second lead layer 320 on the substrate 100.

[0084] S200: In the separation layer 200, a receiving hole 210 is formed, which penetrates the second source 331 and the first source 321 and extends to the first drain 311.

[0085] 7, an orthogonal projection of the receiving hole 210 on the substrate 100 overlaps with a vertical intersection of orthogonal projections of the first lead layer 310 and the second lead layer 320 on the substrate 100. The receiving hole 210 preferably has vertical sidewalls, although it will be understood that the sidewalls of the receiving hole 210 may have a slope angle that does not affect the electrical connection with the source and drain electrodes.

[0086] S300: On the side of the receiving hole 210 away from the substrate 100, the first channel 411, the first gate dielectric portion 511, and the first gate 611 are formed in this order.

[0087] The first drain 311 and the first source 321 are both connected to the first channel 411. The height of the bottom surface of the first gate 611 is at least lower than the lower surface of the second lead layer 320, and preferably lower than the upper surface of the first lead layer 310.

[0088] S400: Form an insulating dielectric layer 800 on at least the side of the first channel 411 away from the substrate 100.

[0089] Referring to FIG. 12, an insulating dielectric layer 800 separates at least the first channel 411 and the second channel 421 .

[0090] S500: On the side of the insulating dielectric layer 800 remote from the substrate 100, the second channel 421, the second gate dielectric portion 521, the second gate 621 and the write word line WWL are formed.

[0091] As in the embodiment shown in Figures 13 to 15, the second channel 421, the second gate dielectric portion 521 and the second gate 621 are all at least partially disposed in the receiving hole 210, the second channel 421 is spaced apart from the first channel 411, the first gate 611 is directly or indirectly connected to the second channel 421, the second source 331 is connected to the second channel 421, and the write word line WWL is connected to the second gate 621.

[0092] The separation layer 200 includes multiple separation material layers, and when forming the separation layer 200, the first lead layer 310, the second lead layer 320, and the third lead layer 330, the first separation material layer, the first lead layer 310, the second separation material layer, the second lead layer 320, the third separation material layer, the third lead layer 330 and the fourth separation material layer are formed in sequence on the substrate 100, and the first lead layer 310, the second lead layer 320, and the third lead layer 330 are separated from each other by the separation layer 200.

[0093] The memory includes a plurality of storage units. The storage units include a read tube 20 and a write tube 10. The read tube 20 includes a first gate 611, a first channel 411, a first drain 311, and a first source 321. The write tube 10 includes a second drain, a second source 331, a second channel 421, and a second gate 621. The plurality of storage units are connected by a read word line RWL, a read bit line RBL, a write bit line WBL, and a write word line WWL.

[0094] The first channel 411 is completely located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210, which can simplify the manufacturing process of the memory in the process of forming the vertically stacked write tube 10 and read tube 20, and reduce the manufacturing cost of the memory. At the same time, since the first channel 411 is completely located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210, and the first channel 411 and the second channel 421 are stacked, the area occupied by the memory unit is reduced, and the memory density is improved.

[0095] As shown in FIGS. 8 to 15, a manufacturing method of a memory includes:

[0096] A first channel layer 410, a first gate dielectric layer 510, a first gate electrode layer 610, and a first conductor layer 710 are sequentially formed on the side of the separation layer 200 away from the substrate 100, and the first channel layer 410, the first gate dielectric layer 510, the first gate electrode layer 610, and the first conductor layer 710 are all at least partially located in the receiving hole 210.

[0097] A portion of the thickness of the first conductor layer 710 is removed from the upper part to form a first conductor portion 711 in the accommodating hole 210, and the surface of the first conductor portion 711 away from the substrate 100 is positioned between the upper surface of the second lead layer 320 and the lower surface of the third lead layer 330.

[0098] Part of the first channel layer 410, the first gate dielectric layer 510 and the first gate electrode layer 610 are removed to form a first channel 411, a first gate dielectric portion 511 and a first gate 611 in the accommodating hole 210, and the height of the upper surface of the first conductor portion 711 relative to the substrate 100 is higher than the height of the upper surfaces of the first channel 411, the first gate 611 and the first gate dielectric portion 511 relative to the substrate 100.

[0099] An insulating dielectric layer 800 surrounding the first conductor portion 711 is formed on end faces of the first channel 411, the first gate 611 and the first gate dielectric portion 511 away from the substrate 100. The height of the upper surface of the insulating dielectric layer 800 relative to the substrate 100 is equal to or lower than the height of the upper surface of the first conductor portion 711 relative to the substrate 100.

[0100] The second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720, and the fourth lead layer 340 are sequentially formed on the side of the reading tube 20 and the insulating dielectric layer 800 away from the substrate 100, and the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, and the second conductor layer 720 are all at least partially located in the receiving hole 210, and the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720, and the fourth lead layer 340 are patterned to form the second channel 421, the second gate dielectric portion 521, the second gate 621, the second conductor portion 721, and the write word line WWL. The second gate 621 and the write word line WWL are connected via the second conductor portion 721.

[0101] When patterning the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340, apply a photoresist 900 on the fourth lead layer 340, and etch the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340 into the isolation layer 200 on the third wiring layer 330, and then remove the residual photoresist 900 and cover with an isolation material layer to form the structure of the memory unit shown in Figures 1 and 2.

[0102] It should be noted that the etching may be stopped at the top surface of the isolation layer 200 or may be over-etched deep into the isolation layer 200 to ensure that the second channel layer 420 is completely etched during the patterning process, thereby reducing the risk of short circuits.

[0103] The first gate 611 and the second channel 421 are spaced apart, and the first conductor portion 711 is connected to the second channel 421, and the first conductor portion 711 can store or release charge when the write tube 10 is turned on, and the charge stored in the first conductor portion 711 affects the read current of the read tube 20.

[0104] It should be noted that the first gate 611 and the second channel 421 are spaced apart from each other, and the first gate 611 and the second channel 421 can be indirectly connected to each other through the first conductor portion 711, but are not limited thereto. The first gate 611 can also extend through the insulating dielectric layer 800 to be directly connected to the second channel 421 according to specific circumstances.

[0105] 8 to 15, the first channel layer 410, the first gate dielectric layer 510, and a portion of the first gate electrode layer 610 are removed by isotropic etching such as dry etching or wet etching, so that the height of the upper surface of the first conductor portion 711 is greater than the heights of the first channel 411, the first gate dielectric portion 511, and the first gate 611. Since the gate electrode layer 600 and the conductor layer 700 are formed of different materials, the first conductor portion 711 is not etched when the first gate electrode layer 610 is etched.

[0106] In addition, in the step of removing a portion of the first channel layer 410, the first gate dielectric layer 510, and the first gate electrode layer 610, each layer may be etched simultaneously or separately, but this is not particularly limited in the present invention.

[0107] By removing the first channel layer 410, the first gate dielectric layer 510, and the first gate electrode layer 610 by etching so that the height of the upper surface of the first conductor portion 711 relative to the substrate 100 is higher than the height of the upper surfaces of the first channel 411, the first gate 611, and the upper ends of the first gate dielectric portion 511, a filling space of the insulating dielectric layer 800 is formed, which avoids a short circuit between the first channel 411, the first gate 611, and the write tube 10 and facilitates a connection between the first conductor portion 711 and the second channel 421. The etching may be, for example, isotropic etching, or may be dry etching or wet etching.

[0108] 8 to 15, when forming the insulating dielectric layer 800, an insulating dielectric base layer is formed at least in the receiving hole 210 to cover the first conductor portion 711, the first channel 411 and the first gate dielectric portion 511. The insulating dielectric base layer is partially located outside the receiving hole 210, and then a part of the insulating dielectric base layer is removed using isotropic dry etching or wet etching to form the insulating dielectric layer 800. The insulating dielectric layer 800 and the separation layer 200 may be formed of different materials to generate etching selectivity so that the wall of the receiving hole 210 is not etched when the insulating dielectric layer 800 is formed.

[0109] First, an insulating dielectric base layer is formed to fill the trench and cover the first conductor portion 711, the first channel 411 and the first gate dielectric portion 511, and then the insulating dielectric base layer is isotropically etched to form the insulating dielectric layer 800. This makes it easy to control the height and shape of the insulating dielectric layer 800.

[0110] 8 to 15, when the receiving hole 210 is formed in the separation layer 200, penetrating the first source 321 and the second source 331 and extending to the first drain 311, the etching depth is greater than the depth of the upper surface of the first drain 311 and less than the depth of the lower surface of the first drain 311. In other words, the receiving hole 210 extends to the first drain 311 but does not penetrate the first drain 311.

[0111] The accommodating hole 210 formed in the separation layer 200 extends to the first drain 311, and a portion of the first channel 411 close to one end of the substrate 100 is embedded in the first drain 311, improving the connection performance between the first drain 311 and the first channel 411 and improving the performance of the reading tube 20.

[0112] 8 to 15, the orthogonal projection of the accommodating hole 210 on the substrate 100 is located within the orthogonal projection of the first drain 311, the first source 321, and the second source 331 on the substrate 100. Specifically, the first channel 411 is located at the center with respect to the first drain 311 and the first source 321, and the second channel 421 is located at the center with respect to the second source 331.

[0113] By having the first channel 411 centrally located relative to the first drain 311 and the first source 321, and the second channel 421 centrally located relative to the second source 331, the performance of the write tube 10 and the read tube 20 can be improved and the performance of the memory unit can be enhanced.

[0114] The terms "first", "second", and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or quantity of the technical features depicted. Thus, a feature defined as "first", "second", and the like may explicitly or implicitly include one or more of that feature. In the description of this application, "plurality" means two or more, unless otherwise expressly limited.

[0115] In this application, unless otherwise expressly stated and limited, the terms "disposition", "connection", etc. should be understood in a broad sense, for example, a fixed connection, a removable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, an indirect connection through an intermediate medium, an internal connection between two elements, or an interaction between two elements. Those skilled in the art will be able to understand the specific meaning of the above terms in this application according to the particular situation.

[0116] In the description of this specification, the description of terms such as "some embodiments," "exemplary," and the like means that the particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. Furthermore, a person skilled in the art may combine different embodiments or examples and features of different embodiments or examples described herein, as long as they are not mutually inconsistent.

[0117] Although the embodiments of the present application have been shown and described above, the above embodiments are illustrative and should not be construed as limitations of the present application. Those skilled in the art can change, modify, substitute and alter the above embodiments within the scope of the present application, and therefore, it is understood that any changes or modifications made in accordance with the claims and descriptions of the present application should all be included within the patent scope of the present application.

Claims

1. A storage unit comprising: a separation layer on one side of the substrate, the separation layer including a receiving hole; The storage unit includes: a channel layer including a first channel and a second channel stacked with a space therebetween, the first channel being located in the receiving hole, the second channel being at least partially located in the receiving hole, the first channel having a first inner hole on a side away from the substrate, and the second channel having a second inner hole on a side away from the substrate; an insulating dielectric layer formed at least between the first channel and the second channel; a gate electrode layer including a first gate and a second gate, the first gate being formed in the first bore and directly or indirectly connected to the second channel, and the second gate being at least partially formed in the second bore; a gate dielectric layer formed between the gate electrode layer and the channel layer. A storage unit characterized by:

2. The storage unit further includes a conductor layer, the conductor layer including a first conductor portion, the first conductor portion being at least partially located between the first gate and the second channel, the first gate and the second channel being indirectly connected through the first conductor portion, and the insulating dielectric layer being disposed surrounding the first conductor portion.

2. The storage unit according to claim 1.

3. The first conductor portion extends at least partially to the first gate within the first bore.

3. The storage unit according to claim 2.

4. The height of the upper surface of the first conductor portion relative to the substrate is equal to or greater than the height of the upper surface of the insulating dielectric layer relative to the substrate.

3. The storage unit according to claim 2.

5. The conductor layer further includes a second conductor portion, the second conductor portion being at least partially disposed in the second bore, and the second gate being located between the second conductor portion and the gate dielectric layer.

3. The storage unit according to claim 2.

6. the storage unit further includes a lead layer, the lead layer including a first lead layer, a second lead layer, and a third lead layer arranged at a distance from each other; The first lead layer includes a first drain, the second lead layer includes a first source, the third lead layer includes a second source, the first drain and the first source are both located outside the receiving hole and are both connected to the first channel, the second source is located outside the receiving hole and is connected to the second channel, and the receiving hole is connected to the first drain through the second source and the first source.

2. The storage unit according to claim 1.

7. A portion of the first channel near one end of the substrate is embedded in the first drain.

7. The storage unit according to claim 6.

8. The conductor layer and the gate electrode layer are made of different materials.

3. The storage unit according to claim 2.

9. The separation layer and the insulating dielectric layer are made of different materials.

2. The storage unit according to claim 1.

10. A plurality of storage units according to any one of claims 1 to 9; a write word line connected to second gates of a plurality of the storage units; a write bit line connected to second sources of a plurality of said storage units; a read word line connected to first drains of the plurality of storage units; a read bit line connected to a first source of a plurality of said storage units; A memory characterized by:

11. A method for manufacturing a memory, comprising the steps of: forming an isolation layer and a lead layer on a substrate, the lead layer including a first lead layer, a second lead layer, and a third lead layer formed sequentially and spaced apart, the first lead layer, the second lead layer, and the third lead layer all being located on the isolation layer, the first lead layer including a first drain and a read word line integrally connected, the second lead layer including a first source and a read bit line integrally connected, and the third lead layer including a second source and a write bit line integrally connected; forming a receiving hole in the isolation layer, the receiving hole passing through the second source and the first source and extending to the first drain; forming a first channel, a first gate dielectric portion, and a first gate in the receiving hole, the first drain and the first source both being connected to the first channel; forming an insulating dielectric layer on at least a side of the first channel away from the substrate; forming a second channel, a second gate dielectric portion, a second gate, and a write word line on a side of the insulating dielectric layer remote from the substrate, the second channel, the second gate dielectric portion, and the second gate all being at least partially located in the receiving hole, the first gate being directly or indirectly connected to the second channel, the second source being connected to the second channel, and the write word line being connected to the second gate. A method for manufacturing a memory comprising the steps of:

12. sequentially forming a first channel layer, a first gate dielectric layer, a first gate electrode layer, and a first conductor layer on a side of the isolation layer remote from the substrate, the first channel layer, the first gate dielectric layer, the first gate electrode layer, and the first conductor layer all being at least partially located in the receiving hole; a step in which a height of an upper surface of the first conductor portion relative to the substrate is greater than a height of upper surfaces of the first channel, the first gate dielectric portion, and the first gate electrode layer; a step in which a height of an upper surface of the first conductor portion relative to the substrate is greater than a height of upper surfaces of the first channel, the first gate dielectric portion, and the first gate electrode layer; forming an insulating dielectric layer surrounding the first conductor portion on a side of the first channel, the first gate dielectric portion and the first gate away from the substrate, the insulating dielectric layer having a height of a top surface of the insulating dielectric layer relative to the substrate equal to or less than a height of a top surface of the first conductor portion relative to the substrate; sequentially forming a second channel layer, a second gate dielectric layer, a second gate electrode layer, a second conductor layer, and a fourth lead layer on a side of the isolation layer away from the substrate, the second channel layer, the second gate dielectric layer, the second gate electrode layer, and the second conductor layer all being at least partially located in the receiving hole, and patterning the second channel layer, the second gate dielectric layer, the second gate electrode layer, the second conductor layer, and the fourth lead layer to form the second channel, the second gate dielectric portion, the second gate, the second conductor portion, and the write word line.

12. The method of claim 11, wherein the memory is formed by a semiconductor device.

13. removing a portion of the first channel layer, the first gate dielectric layer, the first gate electrode layer, and the first conductor layer using isotropic etching so that the height of the top surface of the first conductor portion is greater than the heights of the top surfaces of the first channel, the first gate dielectric portion, and the first gate; 13. The method of claim 12, wherein the memory is formed by a semiconductor device.

14. forming an insulating dielectric base layer in the receiving hole to cover the first conductor portion, the first channel, and the first gate dielectric portion when forming the insulating dielectric layer; Using an isotropic etch, a portion of the insulating dielectric base layer is removed to form the insulating dielectric layer.

13. The method of claim 12, wherein the memory is formed by a semiconductor device.

15. When a receiving hole is formed in the separation layer, the receiving hole passing through the second source and the first source and extending to the first drain, the etching depth is greater than the depth of the upper surface of the first drain.

12. The method of claim 11, wherein the memory is formed by a semiconductor device.

16. An orthogonal projection of the receiving hole on the substrate is located within an orthogonal projection of the first drain, the first source, and the second source on the substrate.

16. The method of claim 15,

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