Detector

Abstract

To detect temperatures in a plurality of positions while suppressing increase of power consumption.SOLUTION: A detector includes: a power source line on which a predetermined power source voltage is applied; an output line to which an output signal is output; a plurality of temperature detection units connected in parallel between the power source line and the output line, the temperature detection units outputting a signal corresponding to a temperature to the output line as the output signal; and a driving unit for driving the temperature detection units in time division.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a detection device. [Background technology]

[0002] Research and development is being conducted on temperature detection devices.

[0003] In this regard, a detection device that detects temperature using a ring oscillator is known (see Non-Patent Document 1). [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] "Temperature Sensor Made of Amorphous Indium-Gallium-Zinc Oxide TFTs", Hoon Jeong, Chung Sik Kong, Sung Wook Chang, Kwon Shik Park, Sang Gul Lee, Yong Min Ha, and Jin Jang, IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 12, DECEMBER 2013. Summary of the Invention

[0005] A detection device according to a first aspect of the present invention comprises a power supply line to which a predetermined power supply voltage is applied, an output line to which an output signal is output, a plurality of temperature detection units connected in parallel between the power supply line and the output line and outputting a signal corresponding to temperature as the output signal to the output line, and a drive unit driving the plurality of temperature detection units in a time-division manner. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of how the detection device 1 is used. [Diagram 2]1 is a diagram showing an example of the configuration of a detection device 1. FIG. [Diagram 3] FIG. 2 is a diagram illustrating an example of a logic circuit showing a ring oscillator RO. [Figure 4] 11 is a diagram showing an example of an output signal output from a ring oscillator RO. FIG. [Diagram 5] FIG. 1 is a diagram illustrating an example of a logic circuit of a CMOS inverter. [Figure 6] FIG. 1 is a diagram showing an example of a logic circuit of an inverter including a diode-connected field effect transistor. [Figure 7] FIG. 1 is a diagram showing an example of a logic circuit of a pseudo-CMOS type inverter. [Figure 8] 3 is a diagram showing an example of the configuration of a drive unit 12 in the detection device 1 shown in FIG. 2. [Figure 9] FIG. 2 is a diagram illustrating an example of a circuit configuration of a flip-flop FF1. [Figure 10] 1 is a diagram showing an example of how each of N flip-flops FF in a shift register SR outputs a drive pulse signal in a time-division manner. [Figure 11] 2 is a diagram showing a specific example of a circuit configuration of the detection device 1. FIG. [Figure 12] 12 is a diagram showing an example of the results of simulating the timing at which each of the four temperature detection units 11 in the detection device 1 shown in FIG. 11 outputs an output signal. FIG. [Figure 13] 3 is a diagram showing another example of the configuration of the detection device 1. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] <Embodiment> Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Here, in the embodiment, a conductor that transmits an electric signal corresponding to DC power or an electric signal corresponding to AC power will be referred to as a transmission line. The transmission line may be, for example, a conductor printed on a substrate, a conductor formed in a linear shape, or another conductor. In addition, in the embodiment, when it is referred to as a voltage, it means a potential difference from a predetermined reference potential, and illustration and description of the reference potential are omitted. Here, the reference potential may be any potential. In the embodiment, as an example, a case where the reference potential is the ground potential will be described. In addition, in the embodiment, for convenience of explanation, a state in which a certain field effect transistor has a current flowing between the drain terminal and the source terminal will be referred to as an on state. In addition, in the embodiment, for convenience of explanation, a state in which a certain field effect transistor has a current not flowing between the drain terminal and the source terminal will be referred to as an off state.

[0008] <Detection device overview> First, an overview of a detection device according to an embodiment will be described.

[0009] The detection device according to the embodiment includes a power line, an output line, a plurality of temperature detection units, and a drive unit. A predetermined power supply voltage is applied to the power line. An output signal is output to the output line. The plurality of temperature detection units are connected in parallel between the power line and the output line. The plurality of temperature detection units output a signal according to temperature as the output signal to the output line. The drive unit drives the plurality of temperature detection units by time division. This allows the detection device to detect temperatures at a plurality of positions while suppressing an increase in power consumption.

[0010] The configuration of the detection device according to the embodiment will be described in detail below.

[0011] <Detection device configuration> The configuration of the detection device according to the embodiment will be described below by taking the detection device 1 as an example.

[0012] FIG. 1 is a diagram showing an example of how a detection device 1 is used.

[0013] The detection device 1 detects the temperature at each of a plurality of mutually different detection positions. In the example shown in FIG. 1, the detection device 1 is buried under a ridge CN, which is one of a plurality of ridges in a field F. As a result, the detection device 1 detects the underground temperature at each of a plurality of detection positions aligned along the ridge CN. The detection device 1 may be configured to be installed on the ground instead of being installed in the ground (i.e., being buried in the ground). In this case, the detection device 1 detects the temperature at each of a plurality of mutually different detection positions on the ground. In addition, some or all of the plurality of detection positions aligned along the ridge CN may be configured to be aligned at equal intervals, or may be configured to be aligned at non-equidistant intervals. In the following, as an example, a case where all of the plurality of detection positions are aligned at equal intervals will be described.

[0014] The detection device 1 is connected to the information processing device 2 so as to be able to communicate with it. The detection device 1 outputs temperature information indicating the underground temperature at each of a plurality of detection positions lined up along the ridge CN to the information processing device 2 in sequence. This allows the information processing device 2 connected to the detection device 1 to identify the underground temperature at each of the plurality of detection positions. As a result, the detection device 1 can cause the information processing device 2 to determine whether or not an abnormality has occurred in the growth of the crops cultivated in the field F.

[0015] The information processing device 2 may be, for example, a notebook PC (Personal Computer), a desktop PC, a tablet PC, a multi-function mobile phone terminal (smartphone), a PDA (Personal Digital Assistant), a workstation, etc., but is not limited thereto. The information processing device 2 supplies a clock signal, a drive pulse signal, a power supply voltage Vdd, a ground voltage (for example, the same potential as the ground potential) Vss, etc. to the detection device 1, and controls the detection device 1. The information processing device 2 acquires temperature information from the detection device 1, and identifies the underground temperature at each of the multiple detection positions based on the acquired temperature information. In this way, the information processing device 2 can determine whether or not an abnormality has occurred in the growth of the crops cultivated in the field F. Note that some or all of the functions of the information processing device 2 may be realized by multiple information processing devices. In this case, the detection device 1 is connected to each of these multiple information processing devices so as to be able to communicate with each other. Also, some or all of the functions of the information processing device 2 may be configured to be provided by the detection device 1. In this case, the detection device 1 further includes a circuit, a member, a device, etc. that realizes some or all of the functions of the information processing device 2.

[0016] Here, FIG. 2 is a diagram showing an example of the configuration of the detection device 1. Note that the arrows shown in FIG. 2 indicate the left and right directions in FIG. 2, respectively. The detection device 1 includes a power line L1, an output line L2, temperature detection units 11, the number of which is the same as the number of detection positions, and a drive unit 12. In the following, as an example, a case where the number of detection positions is N will be described. In this case, the detection device 1 includes N temperature detection units 11. Note that N may be any integer number equal to or greater than 2. In the following, for convenience of explanation, as shown in FIG. 2, each of the N temperature detection units 11 will be described as a temperature detection unit 111 to a temperature detection unit 11N in the order from the left to the right in FIG. 2. Note that in FIG. 2, each of the N temperature detection units 11 is arranged in a straight line from the left to the right. However, this is merely an example. That is, each of the N temperature detection units 11 may be arranged in a line along a curve, in a zigzag pattern, along a circumference, or in another manner.

[0017] The power line L1 is a transmission path connected to the information processing device 2. The power line L1 is, for example, a transmission path printed on a film substrate, but is not limited to this. A predetermined power supply voltage Vdd is applied to the power line L1 from the information processing device 2. The power supply voltage Vdd may be any voltage that can be used as a power supply voltage for driving each of the N temperature detection units 11. Note that the power supply line L1 may be configured to receive the power supply voltage Vdd from a power supply device different from the information processing device 2.

[0018] The output line L2 is a transmission path connected to the information processing device 2. The output line L2 is, for example, a transmission path printed on a film substrate, but is not limited to this. A signal is output from each of the N temperature detection units 11 as an output signal to the output line L2. Here, this output signal is a signal that indicates temperature by frequency, as described later. In addition, the N temperature detection units 11 are driven in a time-division manner by the drive unit 12, as described later. Therefore, an output signal is output from each of the N temperature detection units 11 in a time-division manner to the output line L2. Then, the output signal output from each of the N temperature detection units 11 to the output line L2 is input to the information processing device 2 via the output line L2. This allows the information processing device 2 to identify the temperature at each of the N detection positions.

[0019] The N temperature detection units 11 are connected in parallel between the power supply line L1 and the output line L2. The N temperature detection units 11 output signals corresponding to temperatures to the output line L2. Each of the N temperature detection units 11 includes, for example, a ring oscillator RO that is composed of an odd number of inverters. Note that the state in which a certain temperature detection unit 11 is operating means that the power supply voltage Vdd is being supplied to the temperature detection unit 11 from the power supply line L1.

[0020] As described above, the driving unit 12 drives the N temperature detection units 11 by time division. More specifically, the driving unit 12 drives the temperature detection units 11 one by one in sequence from the temperature detection unit 111 to the temperature detection unit 11N by time division. When driving the n-th temperature detection unit 11n of the N temperature detection units 11, the driving unit 12 stops the temperature detection units 11 other than the temperature detection unit 11n of the N temperature detection units 11. Note that n may be any integer between 1 and N. In other words, the driving unit 12 drives the N temperature detection units 11 one by one in sequence so that the driving times of the N temperature detection units 11 do not overlap. As a result, when detecting the temperature of the n-th detection position of the N detection positions, the detection device 1 can drive only the n-th temperature detection unit 11n of the N temperature detection units 11. As a result, the detection device 1 can suppress an increase in power consumption compared to a case where all of the N temperature detection units 11 are driven each time the temperature of each of the N detection positions is detected. The drive unit 12 is configured to include, for example, a one-hot type shift register SR. In this case, the detection device 1 can share a control line (e.g., a clock line, etc.) that controls the drive unit 12 for the N temperature detection units 11. Note that the shift register SR is omitted in FIG. 2 to simplify the drawing. Also, instead of the shift register SR, the drive unit 12 may be configured to include another circuit that drives the N temperature detection units 11 by time division using another method.

[0021] In addition, in FIG. 2, the driving unit 12 is depicted as not being connected between the N temperature detection units 11 and the power line L1, but it may be connected between the N temperature detection units 11 and the power line L1. In the following, as an example, a case where the driving unit 12 is not connected between the N temperature detection units 11 and the power line L1 as shown in FIG. 2 will be described. In addition, in FIG. 2, the driving unit 12 is depicted as a single member, but it may be composed of a plurality of members. In the following, as an example, a case where the driving unit 12 is composed of a plurality of members will be described.

[0022] Here, a device in which a plurality of temperature detection units are arranged in a straight line, such as the detection device 1, generally tends to have a larger width in the short side direction perpendicular to the longitudinal direction in which the N temperature detection units 11 are arranged. This is because, for example, as the number of temperature detection units increases, the number of output lines drawn from the temperature detection units also increases. In contrast, the detection device 1 has one output line L2. This is because, in the detection device 1, the driving unit 12 drives the N temperature detection units 11 by time division, and the output signals from the N temperature detection units 11 are multiplexed (time division multiplexed) to a smaller number of output lines L2 than the number of the temperature detection units 11. However, when driving the N temperature detection units 11 by time division, if one tries to reduce the width in the short side direction of the detection device 1, it is necessary to reduce the number of control lines (e.g., clock lines, etc.) of a circuit that selects the N temperature detection units 11 one by one (chip select). In contrast, in the detection device 1, the driving unit 12 is configured to include a one-hot type shift register SR, so that the number of control lines of the driving unit 12 that selects and drives the N temperature detection units 11 one by one is reduced (a specific example will be described later). As a result, the detection device 1 can have a smaller width in the short direction. This is important because it leads to suppressing an increase in manufacturing costs. When the driving unit 12 is configured to include a shift register SR, it is possible to output N output signals from the output line L2 in the order in which the N temperature detection units 11 are arranged. This allows the information processing device 2 to easily identify which of the N temperature detection units 11 the output signal input from the output line L2 is output from, even if the output signal does not include identification information that identifies each of the N temperature detection units 11.

[0023] With the above configuration, the detection device 1 can collectively output the output signals output from each of the N temperature detection units 11 arranged in the longitudinal direction from a longitudinal end of the detection device 1. Furthermore, with the above configuration, the detection device 1 can drive the N temperature detection units 11 in a time-division manner, and as a result, it is possible to suppress an increase in power consumption compared to a case in which all of the N temperature detection units 11 are driven each time the temperature of each of the N detection positions is detected.

[0024] Here, the ring oscillator RO included in each of the N temperature detection units 11 will be described. FIG. 3 is a diagram showing an example of a logic circuit showing the ring oscillator RO. In the example shown in FIG. 3, the ring oscillator RO is composed of five inverters. In this example, the output terminal of the ring oscillator RO is connected to the input terminal of one inverter that serves as a pickup circuit. Note that the one inverter that serves as the pickup circuit may be configured to be included in each of the N temperature detection units 11, or may be configured to be connected from the outside to each of the N temperature detection units 11. When a drive pulse signal output from the information processing device 2 is input to the input terminal as an input pulse signal, such a ring oscillator RO outputs an approximately sinusoidal AC signal as an output signal due to the propagation delay of each inverter that constitutes the ring oscillator RO.

[0025] Fig. 4 is a diagram showing an example of an output signal output from the ring oscillator RO. The horizontal axis of the graph shown in Fig. 4 represents elapsed time. The vertical axis of the graph represents the voltage of the output signal output from the ring oscillator RO.

[0026] As shown in FIG. 4, the output signal output from the ring oscillator RO is an AC signal of a substantially sinusoidal wave. The frequency of such an output signal changes according to the power supply voltage Vdd and the ground voltage Vss supplied from the information processing device 2 to each inverter constituting the ring oscillator RO. The frequency of this output signal also changes according to the size of each inverter constituting the ring oscillator RO. The frequency of this output signal also changes according to the number of inverters constituting the ring oscillator RO. And the frequency of this output signal changes according to the temperature of the ring oscillator RO. That is, when the power supply voltage Vdd and the ground voltage Vss supplied to each inverter constituting the ring oscillator RO, the size of each inverter constituting the ring oscillator RO, and the number of inverters constituting the ring oscillator RO are fixed, the frequency of the output signal output from the ring oscillator RO can be one-to-one associated with the temperature of the ring oscillator RO. Therefore, when the information processing device 2 acquires the output signal output from the ring oscillator RO, it can specify the temperature of the ring oscillator RO as the temperature of the detection position where the ring oscillator RO is located based on the frequency of the acquired output signal. In this case, for example, the information processing device 2 stores temperature characteristic information (correspondence information) in which the frequency of the output signal output from the ring oscillator RO corresponds to the temperature of the ring oscillator RO. Note that some or all of the N temperature detection units 11 may be configured to include other elements (i.e., elements whose resistance value changes according to temperature) capable of outputting a voltage signal or a current signal according to temperature as an output signal, instead of the ring oscillator RO. In this case, the information processing device 2 stores, for example, temperature characteristic information in which the magnitude of the voltage or current output as an output signal from the other element corresponds to the temperature of the other element, and the temperature at the detection position can be specified based on this temperature characteristic information and the input output signal. However, if all of the N temperature detection units 11 are configured to include the ring oscillator RO, the detection device 1 can easily discriminate between noise and the output signal.For example, the resistance value of the transmission line extending in the longitudinal direction in the detection device 1 increases as the detection device 1 becomes longer in the longitudinal direction. Therefore, the peak value of the voltage signal or current signal output as an output signal from the other element may change depending on the position of the temperature detection unit 11 in the detection device 1. This is undesirable because it leads to a decrease in the accuracy of temperature detection in the detection device 1. In contrast, when each of the N temperature detection units 11 is configured to include a ring oscillator RO, the output signal can be a signal of a modulation method, for example, a frequency modulation method, which is less affected by the resistance value of the output line L2. As a result, in this case, the detection device 1 can accurately detect the temperature at each of the N detection positions.

[0027] Moreover, the ring oscillator RO can be driven only by the supply of the power supply voltage Vdd from the power supply line L1. Therefore, when each of the N temperature detection units 11 includes the ring oscillator RO, the number of control lines for controlling the N temperature detection units 11 can be reduced. This leads to suppression of an increase in the manufacturing cost of the detection device 1, which is desirable.

[0028] Here, each inverter constituting the ring oscillator RO may be configured to include, for example, a CMOS (Complementary Metal Oxide Semiconductor) type inverter as shown in Fig. 5. Fig. 5 is a diagram showing an example of a logic circuit of a CMOS inverter.

[0029] Furthermore, each inverter constituting the ring oscillator RO may be configured to include an inverter including a diode-connected field effect transistor as shown in Fig. 6. The inverter may also be configured using only p-channel or n-channel transistors. Fig. 6 is a diagram showing an example of a logic circuit of an inverter including a diode-connected field effect transistor.

[0030] Furthermore, each inverter constituting the ring oscillator RO may be configured to include, for example, a pseudo-CMOS type inverter as shown in Fig. 7. Fig. 7 is a diagram showing an example of a logic circuit of a pseudo-CMOS type inverter.

[0031] The field effect transistors included in the inverters shown in each of Figs. 5 to 7 are, for example, thin film transistors (TFTs). The field effect transistors included in the inverters shown in each of Figs. 5 to 7 may be other types of field effect transistors instead of TFTs. However, if the field effect transistors included in the inverters shown in each of Figs. 5 to 7 are TFTs, each of the N temperature detection units 11 can be manufactured by a common manufacturing method (e.g., vacuum deposition) on a film substrate together with the power line L1 and the output line L2. This is useful because it can simplify the manufacturing process of the detection device 1.

[0032] Next, a more detailed configuration example of the driving unit 12 will be described. FIG. 8 is a diagram showing an example of the configuration of the driving unit 12 in the detection device 1 shown in FIG. 2. The arrows in FIG. 8 indicate the left and right directions in FIG. 2, respectively. In the example shown in FIG. 8, the driving unit 12 includes a shift register SR configured with N flip-flops FF connected in a daisy chain. In addition, in this example, the detection device 1 includes a power line L1, an output line L2, N temperature detection units 11, and a shift register SR, as well as three clock signal lines, ie, clock signal lines CK1 to CK3, and a driving pulse line PL connecting adjacent flip-flops FF in the N flip-flops FF. The driving unit 12 may be configured to include other circuits, other members, and the like in addition to the power line L1, the output line L2, N temperature detection units 11, and the shift register SR, as well as the clock signal lines CK1 to CK3 and the driving pulse line PL. Furthermore, the detection device 1 may include a power supply line L1, an output line L2, N temperature detection units 11, a shift register SR, the three clock signal lines, and a drive pulse line PL, as well as other circuits, other members, etc. For ease of explanation, the N flip-flops FF will be referred to as flip-flops FF1 to FFN in the order from left to right in FIG.

[0033] The shift register SR drives the corresponding temperature detection unit 11 based on the clock signal. More specifically, the shift register SR drives the corresponding temperature detection unit 11 based on a drive pulse signal transmitted from the previous stage, and transmits the drive pulse signal to the subsequent stage based on the clock signal. This allows the drive unit 12 to drive the N temperature detection units 11 in a time-division manner by the operation of the shift register SR. The clock signal is supplied to the shift register SR by the information processing device 2, as described above.

[0034] Each of the N flip-flops FF constituting the shift register SR has a pulse input terminal P1, a pulse output terminal P2, a first clock input terminal C1, a second clock input terminal C2, and a ground terminal (not shown). The ground terminal is a terminal to which a ground voltage Vss is supplied from the information processing device 2.

[0035] The pulse input terminal P1 is a terminal to which a drive pulse signal is input as a set pulse signal for the flip-flop FF. For example, when a drive pulse signal is input to the pulse input terminal P1 of the n-th flip-flop FFn among the N flip-flops FF, the flip-flop FFn is set. For example, the drive pulse signal input to the pulse input terminal P1 of the flip-flop FFn is input to the pulse input terminal P1 of the flip-flop FFn as a set pulse signal from the previous stage of the flip-flop FFn. Here, the previous stage of the flip-flop FFn refers to the n-1-th flip-flop FF among the N flip-flops FF. However, the previous stage of the flip-flop FF1 is the information processing device 2.

[0036] The pulse output terminal P2 is a terminal from which a drive pulse signal is output. For example, the drive pulse signal output from the pulse output terminal P2 of the flip-flop FFn is input to the subsequent stage of the flip-flop FFn as a set pulse signal for the subsequent stage of the flip-flop FFn, and is also input to the temperature detection unit 11n as a clock signal indicating the timing for causing the temperature detection unit 11n corresponding to the flip-flop FFn to output an output signal. Here, the subsequent stage of the flip-flop FFn refers to the n+1-th flip-flop FF among the N flip-flops FF. However, the subsequent stage of the flip-flop FFN may or may not be present.

[0037] The first clock input terminal C1 is a terminal to which a clock signal (i.e., an output clock signal) indicating the timing at which the flip-flop FF outputs a drive pulse signal is input. For example, when the flip-flop FFn is set and a clock signal is input to the first clock input terminal C1 of the flip-flop FFn, the flip-flop FFn outputs a drive pulse signal from the pulse output terminal P2 of the flip-flop FFn. Note that when the flip-flop FFn is reset and a clock signal is input to the first clock input terminal C1 of the flip-flop FFn, the flip-flop FFn does nothing.

[0038] The second clock input terminal C2 is a terminal to which a clock signal (i.e., a reset clock signal) that resets the flip-flop FF is input. For example, when the flip-flop FFn is set and a clock signal is input to the second clock input terminal C2 of the flip-flop FFn, the flip-flop FFn is reset. Note that when the flip-flop FFn is reset and a clock signal is input to the second clock input terminal C2 of the flip-flop FFn, the flip-flop FFn does nothing.

[0039] As described above, adjacent flip-flops FF in such N flip-flops FF are connected to each other by a drive pulse line PL. In other words, the N flip-flops FF are daisy-chained via the drive pulse line PL. More specifically, the pulse input terminal P1 of the flip-flop FFn is connected to the pulse output terminal P2 of the previous stage of the flip-flop FFn via the drive pulse line PL. However, the pulse input terminal P1 of the flip-flop FF1 is connected to the pulse output terminal (not shown) of the information processing device 2 via the drive pulse line PL. The pulse output terminal of the information processing device 2 is a terminal from which a drive pulse signal is output, among the terminals of the information processing device 2. In addition, the pulse output terminal P2 of the flip-flop FFn is connected to the pulse input terminal P1 of the next stage of the flip-flop FFn via the drive pulse line PL. In addition, the pulse output terminal P2 of the flip-flop FFn is also connected to the temperature detection unit 11n. In the example shown in FIG. 8, the drive pulse line PL, which connects the pulse output terminal P2 of the flip-flop FFn and the pulse input terminal P1 of the flip-flop FFn+1, is connected to the temperature detection unit 11n, thereby connecting the pulse output terminal P2 of the flip-flop FFn and the temperature detection unit 11n.

[0040] Here, each of the N flip-flops FF is classified into one of three types of flip-flops: a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is a flip-flop FF in which a first clock signal is input to a first clock input terminal C1 and a second clock signal is input to a second clock input terminal C2. The second flip-flop is a flip-flop FF in which a second clock signal is input to a first clock input terminal C1 and a third clock signal is input to a second clock input terminal C2. The third flip-flop is a flip-flop FF in which a third clock signal is input to a first clock input terminal C1 and a first clock signal is input to a second clock input terminal C2.

[0041] The first to third clock signals are clock signals with different phases so that the time periods during which the signal levels are H do not overlap with each other. The first to third clock signals are transmitted from different clock signal lines.

[0042] In the example shown in Fig. 8, the first clock signal is a clock signal transmitted to a clock signal line CK1. That is, the clock signal line CK1 is a transmission path that transmits the first clock signal. Therefore, the first clock input terminal C1 of the first flip-flop is connected to the clock signal line CK1 via the transmission path. In addition, the second clock input terminal C2 of the first flip-flop is connected to the clock signal line CK2 via the transmission path.

[0043] 8, the second clock signal is a clock signal transmitted to a clock signal line CK2. That is, the clock signal line CK2 is a transmission path that transmits the second clock signal. Therefore, the first clock input terminal C1 of the second flip-flop is connected to the clock signal line CK2 via the transmission path. Also, the second clock input terminal C2 of the second flip-flop is connected to the clock signal line CK3 via the transmission path.

[0044] 8, the third clock signal is a clock signal transmitted to a clock signal line CK3. That is, the clock signal line CK3 is a transmission path that transmits the third clock signal. Therefore, the first clock input terminal C1 of the third flip-flop is connected to the clock signal line CK3 via the transmission path. Also, the second clock input terminal C2 of the third flip-flop is connected to the clock signal line CK1 via the transmission path.

[0045] In the shift register SR, the N flip-flops FF are daisy-chained such that the first flip-flop to the third flip-flop are cyclically arranged in the order of the first flip-flop, the second flip-flop, the third flip-flop, and the first flip-flop. In this way, the information processing device 2 can control the drive unit 12 by supplying a drive pulse signal and a first clock signal to a third clock signal to the drive unit 12 such that the N flip-flops FF connected in the daisy chain output drive pulse signals one by one in time division from the flip-flop FF1 to the flip-flop FFN in order.

[0046] The circuit configuration of each of the N flip-flops FF constituting such a shift register SR is, for example, as shown in FIG. 9. FIG. 9 is a diagram showing an example of the circuit configuration of the flip-flop FF1. In the example shown in FIG. 9, the flip-flop FF1 is composed of six field effect transistors, field effect transistors M1 to M6, and one capacitor. In the flip-flop FF1 shown in FIG. 9, when a drive pulse signal is input to the pulse input terminal P1, it is written to the gate of the field effect transistor M5. When a clock signal is input to the first clock input terminal C1 while the gate voltage of the field effect transistor M5 is in a high state, the drive pulse signal is output from the pulse output terminal P2. On the other hand, when a clock signal is input to the second clock input terminal C2, the gate charge of the field effect transistor M5 is discharged and the voltage of the set flip-flop FF1 changes to low. As a result, the flip-flop FF1 is reset. Even if a clock signal is input to the first clock input terminal C1, the reset flip-flop FF1 does not output a drive pulse signal from the pulse output terminal P2 as long as the gate voltage of the field effect transistor M5 is not charged.

[0047] The number of clock lines included in the detection device 1 varies depending on the circuit configuration of each of the N flip-flops FF. The configuration of the detection device 1 including three clock lines as shown in Fig. 8 is merely one example of the configuration of the detection device 1 when the circuit configuration of each of the N flip-flops FF is the circuit configuration shown in Fig. 9. Therefore, the detection device 1 may be configured to include one clock line, two clock lines, or four or more clock lines.

[0048] Here, FIG. 10 is a diagram showing an example of a state in which each of N flip-flops FF in the shift register SR outputs a driving pulse signal in a time-division manner. The horizontal axis of each of the eight timing charts shown in FIG. 10 indicates the elapsed time from the origin. The vertical axis of each of the eight timing charts shown in FIG. 10 indicates the voltage of the signal. In addition, in FIG. 10, as an example, a case where N is 4 will be described. The timing chart TC0 shown in FIG. 10 shows the timing at which the driving pulse signal is output from the information processing device 2. The timing chart TC1 shown in FIG. 10 shows the timing at which the first clock signal is output. The timing chart TC2 shown in FIG. 10 shows the timing at which the second clock signal is output. The timing chart TC3 shown in FIG. 10 shows the timing at which the third clock signal is output. The timing chart TC11 shown in FIG. 10 shows the timing at which the driving pulse signal is output from the flip-flop FF1. The timing chart TC12 shown in FIG. 10 shows the timing at which the driving pulse signal is output from the flip-flop FF2. Timing chart TC13 shown in Fig. 10 shows the timing at which a drive pulse signal is output from flip-flop FF3. Timing chart TC14 shown in Fig. 10 shows the timing at which a drive pulse signal is output from flip-flop FF4.

[0049] As shown in FIG. 10, in the shift register SR, the flip-flop FF1 outputs a drive pulse signal in synchronization with the first clock signal during the period from when the drive pulse signal is output from the information processing device 2 until when the second clock signal is output. Also, in the shift register SR, the flip-flop FF2 outputs a drive pulse signal in synchronization with the second clock signal during the period from when the drive pulse signal is output from the flip-flop FF1 until when the third clock signal is output. Also, in the shift register SR, the flip-flop FF3 outputs a drive pulse signal in synchronization with the third clock signal during the period from when the drive pulse signal is output from the flip-flop FF2 until when the first clock signal is output. Also, in the shift register SR, the flip-flop FF4 outputs a drive pulse signal in synchronization with the first clock signal during the period from when the drive pulse signal is output from the flip-flop FF3 until when the second clock signal is output. Therefore, each of the flip-flops FF1 to FF4 can output the drive pulse signal one by one in a time-division cyclic manner in the order of flip-flop FF1, flip-flop FF2, flip-flop FF3, flip-flop FF4, and flip-flop FF1. In other words, by outputting the drive pulse signal and the first to third clock signals to the drive unit 12, the information processing device 2 can control the drive unit 12 so that the four daisy-chained flip-flops FF output the drive pulse signal one by one in a time-division cyclic manner in the order from flip-flop FF1 to flip-flop FF4.

[0050] Here, when a drive pulse signal is output from the pulse output terminal P2 of the flip-flop FFn, the temperature detection unit 11n corresponding to the flip-flop FFn outputs an output signal from a ring oscillator included in the temperature detection unit 11n until the time indicated by the pulse width of the drive pulse signal has elapsed. In order to realize this, the circuit configuration of the N temperature detection units 11 is, for example, a circuit configuration as shown in FIG. 11. FIG. 11 is a diagram showing a specific example of the circuit configuration of the detection device 1. Note that in FIG. 11, the information processing device 2 is depicted as being divided into two members for the sake of illustration, but the information processing device 2 is not actually divided into two members. Also, in FIG. 11, the case where N is 4 will be described again.

[0051] 11, the information processing device 2 has a power supply terminal PSO, a pulse output terminal SO0, a clock output terminal SO1, a clock output terminal SO2, and a clock output terminal SO3. In this example, the information processing device 2 also has a power supply PS, a signal source S0, a signal source S1, a signal source S2, a signal source S3, and a signal input terminal SI.

[0052] The power supply terminal PSO is a terminal to which the power supply voltage Vdd is supplied from the power supply PS. In other words, the power supply PS is a DC voltage source that supplies the power supply voltage Vdd. The power supply PS may be any DC voltage source capable of supplying the power supply voltage Vdd. The positive terminal of the power supply PS is connected to the power supply terminal PSO via a transmission line. This allows the information processing device 2 to supply the power supply voltage Vdd to the detection device 1 via the power supply terminal PSO.

[0053] The pulse output terminal SO0 is a terminal to which a drive pulse signal is output from the signal source S0. In other words, the signal source S0 is a signal source that outputs a drive pulse signal. The signal source S0 may be any signal source that can output a drive pulse signal. The positive terminal of the signal source S0 is connected to the pulse output terminal SO0 via a transmission line. This allows the information processing device 2 to supply a drive pulse signal to the detection device 1 via the pulse output terminal SO0.

[0054] The clock output terminal SO1 is a terminal at which the first clock signal is output from the signal source S1. In other words, the signal source S1 is a signal source that outputs the first clock signal. The signal source S1 may be any signal source that can output the first clock signal. The positive terminal of the signal source S1 is connected to the clock output terminal SO1 via a transmission line. This allows the information processing device 2 to supply the first clock signal to the detection device 1 via the clock output terminal SO1.

[0055] The clock output terminal SO2 is a terminal at which the second clock signal is output from the signal source S2. In other words, the signal source S2 is a signal source that outputs the second clock signal. The signal source S2 may be any signal source that can output the second clock signal. The positive terminal of the signal source S2 is connected to the clock output terminal SO2 via a transmission line. This allows the information processing device 2 to supply the second clock signal to the detection device 1 via the clock output terminal SO2.

[0056] The clock output terminal SO3 is a terminal at which the third clock signal is output from the signal source S3. In other words, the signal source S3 is a signal source that outputs the third clock signal. The signal source S3 may be any signal source that can output the third clock signal. The positive terminal of the signal source S3 is connected to the clock output terminal SO3 via a transmission line. This allows the information processing device 2 to supply the third clock signal to the detection device 1 via the clock output terminal SO3.

[0057] The signal input terminal SI is a terminal to which the output signals output from the four temperature detection units 11 to the output line L2 are input.

[0058] Here, the power supply terminal PSO is connected to the power supply terminal 11I1 of each of the temperature detection units 111 to 114 via the power supply line L1. Also, the signal input terminal SI is connected to the signal output terminal 11O of each of the temperature detection units 111 to 114 via the output line L2. Here, in the example shown in FIG. 11, the output line L2 is grounded via a capacitor CP1. The capacitor CP1 is a capacitor for removing high-frequency noise. The detection device 1 may or may not include the capacitor CP1 as shown in FIG. 11. Also, the pulse output terminal SO0 is connected to the pulse input terminal P1 of the flip-flop FF1 via the drive pulse line PL. Also, the clock output terminal SO1 is connected to each of the first clock input terminal C1 of the flip-flop FF1 and the second clock input terminal C2 of the flip-flop FF3 via the clock signal line CK1. Moreover, the clock output terminal SO2 is connected to the second clock input terminal C2 of the flip-flop FF1, the first clock input terminal C1 of the flip-flop FF2, and the second clock input terminal C2 of the flip-flop FF4 via a clock signal line CK2. Moreover, the clock output terminal SO3 is connected to the second clock input terminal C2 of the flip-flop FF2 and the first clock input terminal C1 of the flip-flop FF3 via a clock signal line CK3.

[0059] In the example shown in FIG. 11, each of the four temperature detection units 11 includes a first field effect transistor F1 and a second field effect transistor F2, which are chip enable transistors (chip select transistors), along with a ring oscillator RO. In the example, the source terminal of the first field effect transistor F1 in each of the four temperature detection units 11 is connected to a power supply terminal 11I1 via a transmission line. In the example, the gate terminal of the first field effect transistor F1 in each of the four temperature detection units 11 is connected to a signal input terminal 11I2 of the temperature detection unit 11 via a transmission line. In addition, the signal input terminal 11I2 of each of the four temperature detection units 11 is connected to a pulse output terminal P2 of a corresponding flip-flop FF via a transmission line. For example, the signal input terminal 11I2 of the temperature detection unit 111 is connected to a pulse output terminal P2 of a flip-flop FF1, which is the corresponding flip-flop FF, via a transmission line. Also, in this example, in each of the four temperature detection units 11, the drain terminal of the first field effect transistor F1 is connected to the input terminal ROI of the ring oscillator RO via a transmission line. Also, in this example, in each of the four temperature detection units 11, the source terminal of the second field effect transistor F2 is connected to the output terminal ROO of the ring oscillator RO via a transmission line. Also, in this example, in each of the four temperature detection units 11, the gate terminal of the second field effect transistor F2 is connected to the signal input terminal 11I2 of the temperature detection unit 11 together with the gate terminal of the first field effect transistor F1 via a transmission line. Also, in this example, in each of the four temperature detection units 11, the drain terminal of the second field effect transistor F2 is connected to the signal output terminal 11O via a transmission line.

[0060] In the detection device 1 having the circuit configuration shown in FIG. 11, a driving pulse signal is input to each of the four temperature detection units 11 in a time-division manner. Then, in the temperature detection unit 11 to which the driving pulse signal is input among the four temperature detection units 11, the first field effect transistor F1 is turned on and the second field effect transistor F2 is turned on. This is maintained until the time indicated by the pulse width of the driving pulse signal input to the temperature detection unit 11 has elapsed. When the first field effect transistor F1 is in the on state and the second field effect transistor F2 is in the on state, the power supply voltage Vdd is supplied from the power supply PS to the input terminal ROI of the ring oscillator RO of the temperature detection unit 11. As a result, the ring oscillator RO outputs an output signal from the signal output terminal 11O of the temperature detection unit 11 to the output line L2 via the output terminal ROO. After the time indicated by the pulse width of the drive pulse signal input to the temperature detection unit 11 has elapsed, the state of the first field effect transistor F1 becomes OFF again, and the state of the second field effect transistor F2 becomes OFF again. As a result, the output of the output signal from the temperature detection unit 11 stops. Here, as described above, the drive pulse signal is input to each of the four temperature detection units 11 in a time-division manner. This means that each of the four temperature detection units 11 outputs an output signal in a time-division manner. Since the information processing device 2 knows the timing of outputting each of the first clock signal, the second clock signal, and the third clock signal, it can identify which of the four temperature detection units 11 the output signal input from the output line L2 to the information processing device 2 is output from. Therefore, the information processing device 2 can drive the four temperature detection units 11 in a time-division manner so that the drive times do not overlap by the operation of the shift register SR based on the drive pulse signal, the first clock signal, the second clock signal, and the third clock signal output to the detection device 1. That is, the detection device 1 can detect temperatures at four detection positions while suppressing an increase in power consumption.

[0061] In the detection device 1, the temperature detection unit 11 may not include the second field effect transistor F2. However, if the temperature detection unit 11 includes the second field effect transistor F2, the detection device 1 can reduce noise that is superimposed on the output signal output from the output line L2. For this reason, it is desirable for the temperature detection unit 11 to include the second field effect transistor F2.

[0062] FIG. 12 is a diagram showing an example of a result of simulating the timing at which each of the four temperature detection units 11 in the detection device 1 shown in FIG. 11 outputs an output signal. The horizontal axis of each of the four timing charts shown in FIG. 12 indicates the elapsed time from the origin. The vertical axis of each of the four timing charts indicates the voltage of the signal. The timing chart TC21 shown in FIG. 12 shows the timing at which the drive pulse signal is output from the flip-flop FF1 to the temperature detection unit 111 in the simulation. The timing chart TC22 shown in FIG. 12 shows the timing at which the drive pulse signal is output from the flip-flop FF2 to the temperature detection unit 112 in the simulation. The timing chart TC23 shown in FIG. 12 shows the timing at which the drive pulse signal is output from the flip-flop FF3 to the temperature detection unit 113 in the simulation. The timing chart TC24 shown in FIG. 12 shows the timing at which the drive pulse signal is output from the flip-flop FF4 to the temperature detection unit 114 in the simulation. Graph Gh in Fig. 12 shows an example of an output signal input from the output line L2 to the information processing device 2 in a simulation. However, the origin of the horizontal axis of graph Gh coincides with the origin of the horizontal axis of each of the four timing charts. Also, the vertical axis of graph Gh shows the voltage of the output signal.

[0063] By comparing the timing charts TC21 to TC24, it can be seen that in the simulated detection device 1, the driving unit 12 outputs driving pulse signals in a time-division manner from each of the flip-flops FF1 to FF4 of the shift register SR. As a result, output signals are output in a time-division manner from each of the four temperature detection units 11 in the simulation. The graph Gh shows the results. That is, the graph Gh plots the output signals output in a time-division manner from each of the four temperature detection units 11. The output signal SGN1 in the graph Gh is the output signal output from the temperature detection unit 111. The output signal SGN2 in the graph Gh is the output signal output from the temperature detection unit 112. The output signal SGN3 in the graph Gh is the output signal output from the temperature detection unit 113. The output signal SGN4 in the graph Gh is the output signal output from the temperature detection unit 114. In the graph Gh, there is no overlap between the output signals SGN1 to SGN4. That is, this simulation shows that the driving unit 12 of the detection device 1 can drive the four temperature detection units 11 by time division. Here, the four flip-flops FF and the four temperature detection units 11 are each composed of existing elements. Therefore, there is no reason to positively assume that the operation of each of the four flip-flops FF and the four temperature detection units 11 in the simulation does not match the operation of each of the four flip-flops FF and the four temperature detection units 11 in reality. Therefore, it is considered that the driving unit 12 can also drive the four temperature detection units 11 by time division in the actual detection device 1.

[0064] As described above, the detection device 1 includes the power line L1 to which a predetermined power supply voltage Vdd is applied, the output line L2 to which an output signal is output, N temperature detection units 11 connected in parallel between the power line L1 and the output line L2 and outputting a signal according to temperature as an output signal to the output line L2, and the drive unit 12 that drives the N temperature detection units 11 by time division. This allows the detection device 1 to detect temperatures at a plurality of detection positions while suppressing an increase in power consumption.

[0065] <Modifications of the embodiment> The detection device 1 may be composed of a plurality of detachable units. Fig. 13 is a diagram showing another example of the configuration of the detection device 1. In the example shown in Fig. 13, the detection device 1 includes N units U.

[0066] Each of the N units U has a connection part UC1 that connects to the unit U in the previous stage and a connection part UC2 that connects to the unit U in the subsequent stage. However, the unit U closest to the input side (i.e., the flip-flop FF side to which the drive pulse signal is input from the information processing device 2) is connected to the unit U in the previous stage, which is the information processing device 2.

[0067] In the connection unit UC1, a connection terminal for the clock signal line CK1, a connection terminal for the clock signal line CK2, a connection terminal for the clock signal line CK3, a connection terminal for the drive pulse line PL, a connection terminal for the power supply line L1, and a connection terminal for the output line L2 are arranged in a predetermined order. For convenience of explanation, this predetermined order will be referred to as the target order below.

[0068] In addition, the connection part UC2 has a connection terminal of the clock signal line CK1, a connection terminal of the clock signal line CK2, a connection terminal of the clock signal line CK3, a connection terminal of the drive pulse line PL, a connection terminal of the power line L1, and a connection terminal of the output line L2 arranged in symmetrical order. Therefore, the connection part UC2 of a certain unit U can be easily connected to the connection part UC1 of the unit U following the unit U. For example, this allows the connection part UC1 and the connection part UC2 to be configured as connectors that fit together. In this case, the connection part UC1 and the connection part UC2 are configured so that the connection terminal of the clock signal line CK1 in the connection part UC1 is connected to the connection terminal of the clock signal line CK1 in the connection part UC2 by fitting the connection part UC1 to the connection part UC2. In addition, in this case, the connection part UC1 and the connection part UC2 are configured so that the connection terminal of the clock signal line CK2 in the connection part UC1 is connected to the connection terminal of the clock signal line CK2 in the connection part UC2 by fitting the connection part UC1 to the connection part UC2. In this case, the connection parts UC1 and UC2 are configured such that, when the connection parts UC1 and UC2 are fitted together, the connection terminal of the clock signal line CK3 in the connection part UC1 is connected to the connection terminal of the clock signal line CK3 in the connection part UC2. In this case, the connection parts UC1 and UC2 are configured such that, when the connection parts UC1 and UC2 are fitted together, the connection terminal of the drive pulse line PL in the connection part UC1 is connected to the connection terminal of the drive pulse line PL in the connection part UC2. In this case, the connection parts UC1 and UC2 are configured such that, when the connection parts UC1 and UC2 are fitted together, the connection terminal of the power line L1 in the connection part UC1 is connected to the connection terminal of the power line L1 in the connection part UC2. In this case, the connection parts UC1 and UC2 are configured such that, when the connection parts UC1 and UC2 are fitted together, the connection terminal of the output line L2 in the connection part UC1 is connected to the connection terminal of the output line L2 in the connection part UC2. That is, the positional relationship between the six connection terminals in the connection portion UC1 and the positional relationship between the six connection terminals in the connection portion UC2 are mirror images.

[0069] Here, the N units U are classified into three types of units: a first unit U1, a second unit U2, and a third unit U3.

[0070] The first unit U1 is a unit U that includes three clock signal lines, clock signal line CK1 to clock signal line CK3, a drive pulse line PL, a power supply line L1, an output line L2, a first flip-flop, and a temperature detection unit 11 corresponding to the first flip-flop.

[0071] Inside the first unit U1, the connection terminal of the clock signal line CK1 of the connection part UC1 and the connection terminal of the clock signal line CK1 of the connection part UC2 are connected by the clock signal line CK1. Also, inside the first unit U1, the connection terminal of the clock signal line CK2 of the connection part UC1 and the connection terminal of the clock signal line CK2 of the connection part UC2 are connected by the clock signal line CK2. Also, inside the first unit U1, the connection terminal of the clock signal line CK3 of the connection part UC1 and the connection terminal of the clock signal line 3 of the connection part UC2 are connected by the clock signal line CK3. Also, inside the first unit U1, the first clock input terminal C1 of the first flip-flop is connected to the clock signal line CK1 via a transmission line. Also, inside the first unit U1, the second clock input terminal C2 of the first flip-flop is connected to the clock signal line CK2 via a transmission line. In addition, inside the first unit U1, the pulse input terminal P1 of the first flip-flop is connected to the connection terminal of the drive pulse line PL of the connection unit UC1 through the drive pulse line PL. In addition, inside the first unit U1, the pulse output terminal P2 of the first flip-flop is connected to the connection terminal of the drive pulse line PL of the connection unit UC2 through the drive pulse line PL. In addition, inside the first unit U1, the drive pulse line PL is connected to the signal input terminal of the temperature detection unit 11 through a transmission line. In addition, inside the first unit U1, the connection terminal of the power line L1 of the connection unit UC1 and the connection terminal of the power line L1 of the connection unit UC2 are connected by the power line L1. In addition, inside the first unit U1, the power line L1 is connected to the power terminal of the temperature detection unit 11 through the transmission line. In addition, inside the first unit U1, the connection terminal of the output line L2 of the connection unit UC1 and the connection terminal of the output line L2 of the connection unit UC2 are connected by the output line L2. Moreover, inside the first unit U1, the output line L2 is connected to a signal output terminal of the temperature detection section 11 via a transmission line.

[0072] The second unit U2 is a unit U that includes three clock signal lines, clock signal line CK1 to clock signal line CK3, a drive pulse line PL, a power supply line L1, an output line L2, a second flip-flop, and a temperature detection unit 11 corresponding to the second flip-flop.

[0073] Inside the second unit U2, the connection terminal of the clock signal line CK1 of the connection part UC1 and the connection terminal of the clock signal line CK1 of the connection part UC2 are connected by the clock signal line CK1. Inside the second unit U2, the connection terminal of the clock signal line CK2 of the connection part UC1 and the connection terminal of the clock signal line CK2 of the connection part UC2 are connected by the clock signal line CK2. Inside the second unit U2, the connection terminal of the clock signal line CK3 of the connection part UC1 and the connection terminal of the clock signal line 3 of the connection part UC2 are connected by the clock signal line CK3. Inside the second unit U2, the first clock input terminal C1 of the second flip-flop is connected to the clock signal line CK2 via a transmission line. Inside the second unit U2, the second clock input terminal C2 of the second flip-flop is connected to the clock signal line CK3 via a transmission line. In addition, inside the second unit U2, the pulse input terminal P1 of the second flip-flop is connected to the connection terminal of the drive pulse line PL of the connection part UC1 through the drive pulse line PL. In addition, inside the second unit U2, the pulse output terminal P2 of the second flip-flop is connected to the connection terminal of the drive pulse line PL of the connection part UC2 through the drive pulse line PL. In addition, inside the second unit U2, the drive pulse line PL is connected to the signal input terminal of the temperature detection part 11 through a transmission line. In addition, inside the second unit U2, the connection terminal of the power line L1 of the connection part UC1 and the connection terminal of the power line L1 of the connection part UC2 are connected by the power line L1. In addition, inside the second unit U2, the power line L1 is connected to the power terminal of the temperature detection part 11 through the transmission line. In addition, inside the second unit U2, the connection terminal of the output line L2 of the connection part UC1 and the connection terminal of the output line L2 of the connection part UC2 are connected by the output line L2. Moreover, inside the second unit U2, the output line L2 is connected to a signal output terminal of the temperature detection section 11 via a transmission line.

[0074] The third unit U3 is a unit U that includes three clock signal lines, clock signal line CK1 to clock signal line CK3, a drive pulse line PL, a power supply line L1, an output line L2, a third flip-flop, and a temperature detection unit 11 corresponding to the third flip-flop.

[0075] Inside the third unit U3, the connection terminal of the clock signal line CK1 of the connection part UC1 and the connection terminal of the clock signal line CK1 of the connection part UC2 are connected by the clock signal line CK1. Inside the third unit U3, the connection terminal of the clock signal line CK2 of the connection part UC1 and the connection terminal of the clock signal line CK2 of the connection part UC2 are connected by the clock signal line CK2. Inside the third unit U3, the connection terminal of the clock signal line CK3 of the connection part UC1 and the connection terminal of the clock signal line 3 of the connection part UC2 are connected by the clock signal line CK3. Inside the third unit U3, the first clock input terminal C1 of the third flip-flop is connected to the clock signal line CK3 via a transmission line. Inside the third unit U3, the second clock input terminal C2 of the third flip-flop is connected to the clock signal line CK1 via a transmission line. In addition, inside the third unit U3, the pulse input terminal P1 of the third flip-flop is connected to the connection terminal of the drive pulse line PL of the connection part UC1 through the drive pulse line PL. In addition, inside the third unit U3, the pulse output terminal P2 of the third flip-flop is connected to the connection terminal of the drive pulse line PL of the connection part UC2 through the drive pulse line PL. In addition, inside the third unit U3, the drive pulse line PL is connected to the signal input terminal of the temperature detection part 11 through a transmission line. In addition, inside the third unit U3, the connection terminal of the power line L1 of the connection part UC1 and the connection terminal of the power line L1 of the connection part UC2 are connected by the power line L1. In addition, inside the third unit U3, the power line L1 is connected to the power terminal of the temperature detection part 11 through the transmission line. In addition, inside the third unit U3, the connection terminal of the output line L2 of the connection part UC1 and the connection terminal of the output line L2 of the connection part UC2 are connected by the output line L2. Moreover, inside the third unit U3, the output line L2 is connected to a signal output terminal of the temperature detection section 11 via a transmission path.

[0076] Here, in the detection device 1 shown in FIG. 13, the connection part UC2 of the first unit U1 is connected to the connection part UC1 of the second unit U2, the connection part UC2 of the second unit U2 is connected to the connection part UC1 of the third unit U3, and the connection part UC2 of the third unit U3 is connected to the connection part UC1 of the first unit U1, so that the N units U can be daisy-chained so that the first unit U1, the second unit U2, and the third unit U3 are cyclically arranged. The N units U daisy-chained in this manner can be configured as a detection device 1 having the same function as the detection device 1 configured as shown in FIG. 8. In FIG. 13, adjacent units U among the N units U are depicted as being spaced apart. However, adjacent units U among the N units U may or may not be spaced apart. When adjacent units U among the N units U are spaced apart, the terminals of the connection part UC1 and the terminals of the connection part UC2 are connected by, for example, an extension cable or the like. In the example shown in Figure 13, a configuration has been described in which one unit U includes one flip-flop FF and one temperature detection unit 11, but this is not limited to this, and a configuration in which one unit U includes multiple flip-flops FF and multiple temperature detection units 11 may also be used.

[0077] When the detection device 1 has a configuration as shown in FIG. 13, the user of the detection device 1 can daisy-chain the units U according to the number of detection positions. By daisy-chaining the units U as described above, the position at which the temperature detection unit 11 is arranged in the detection device 1 can be adjusted to a desired position, and the number of temperature detection units 11 in the detection device 1 can be adjusted to a desired number. This means that the detection device 1 can improve the user's convenience. Here, such unitization of the detection device 1 can be realized because the output line L2 is multiplexed and the circuit configuration does not change the number of control lines (i.e., clock signal lines, drive pulse lines) in the detection device 1 even if the number of temperature detection units 11 changes in the longitudinal direction of the detection device 1.

[0078] In the example described above, the driving unit 12 drives the multiple temperature detection units 11 in a time-division manner using the shift register SR. However, the driving unit 12 may be configured to drive the multiple temperature detection units 11 in a time-division manner using other circuits, other members, other devices, etc. instead of the shift register SR. For example, the driving unit 12 may include a microcomputer, and the microcomputer may drive the multiple temperature detection units 11 in a time-division manner.

[0079] In the example described above, the temperature detection unit 11 includes the first field effect transistor F1, but may include another switching element such as a bipolar transistor instead of the first field effect transistor F1. In addition, the temperature detection unit 11 includes the first field effect transistor F1, but may be connected to the power supply line L1 via an external first field effect transistor F1 instead of the internal first field effect transistor F1.

[0080] In the example described above, the temperature detection unit 11 includes the second field effect transistor F2, but may include another switching element such as a bipolar transistor instead of the second field effect transistor F2. In addition, the temperature detection unit 11 includes the second field effect transistor F2, but may be connected to the output line L2 via an external second field effect transistor F2 instead of the internal second field effect transistor F2.

[0081] Further, the distance between adjacent temperature detection units 11 among the plurality of temperature detection units 11 described above may be determined in advance, or may be configured to be changeable later by the user, as in the modified example of the embodiment. Note that, as shown in FIG. 1, when the detection device 1 is used in a field F, the distance between adjacent temperature detection units 11 among the plurality of temperature detection units 11 is often, for example, 1 meter or more. For this reason, in such a case, the detection device 1 can be manufactured by roll-to-roll, thereby simplifying the manufacturing process and reducing manufacturing costs. However, in this case, the plurality of temperature detection units 11 are arranged in a substantially straight line.

[0082] Furthermore, the above-described contents may be combined in any manner.

[0083] <Additional Notes> [1] A detection device comprising: a power supply line to which a predetermined power supply voltage is applied; an output line to which an output signal is output; a plurality of temperature detection units connected in parallel between the power supply line and the output line, the temperature detection units outputting a signal corresponding to temperature as the output signal to the output line; and a drive unit driving the plurality of temperature detection units in a time-division manner. [2] The detection device described in [1], wherein when driving a first temperature detection unit among the multiple temperature detection units, the driving unit stops the temperature detection units other than the first temperature detection unit among the multiple temperature detection units. [3] The detection device described in [1] or [2], wherein each of the plurality of temperature detection units is connected to the output line via a switch element that switches a conductive state between the output line and the temperature detection unit. [4] The detection device according to any one of [1] to [3], wherein at least a portion of the plurality of temperature detection units includes a ring oscillator. [5] A detection device described in any one of [1] to [4], comprising a clock signal line, wherein the driving unit includes a shift register that drives the corresponding temperature detection unit based on a clock signal supplied from the clock signal line. [6] A detection device as described in [5], further comprising a drive pulse line for transmitting a drive pulse signal, wherein the shift register drives the corresponding temperature detection unit based on the drive pulse signal transmitted from the previous stage, and transmits the drive pulse signal to the subsequent stage based on the clock signal. [7] A detection device as described in [6], comprising: a first connection section on the input side in which the connection terminal of the clock signal line, the connection terminal of the drive pulse line, the connection terminal of the power supply line, and the connection terminal of the output line are arranged in a predetermined order; and a second connection section on the output side in which the connection terminal of the clock signal line, the connection terminal of the drive pulse line, the connection terminal of the power supply line, and the connection terminal of the output line are arranged in the predetermined order. [8] The detection device described in any one of [1] to [7], wherein the distance between two adjacent temperature detection units in the plurality of temperature detection units is greater than or equal to a predetermined distance. [9] The detection device described in [7], wherein the predetermined distance is 1 meter or more.

[10] The detection device described in any one of [1] to [9], wherein the plurality of temperature detection devices are arranged in a substantially straight line.

[0084] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and may be changed, replaced, deleted, etc. without departing from the gist of the present invention. [Explanation of symbols]

[0085] 1...detection device, 2...information processing device, 3...clock signal line, 11, 11n, 11N...temperature detection unit, 12...drive unit, 111, 112, 113, 114...temperature detection unit, C1...first clock input terminal, C2...second clock input terminal, CK1, CK2, CK3...clock signal line, CN...ridge, CP1...capacitor, F...field, F1...first field effect transistor, F2...second field effect transistor, FF, FF1, FF2, FF3, FF4, FFn, FFN...flip-flop, L1...power line, L2...output line, PL...drive pulse line, PS...power supply, RO...ring oscillator, S0, S1, S2, S3...signal source, SR...shift register, U...unit, U1...first unit, U2...second unit, U3...third unit, UC1, UC2...connection unit

Claims

1. a power supply line to which a predetermined power supply voltage is applied; an output line through which an output signal is output; a plurality of temperature detection units connected in parallel between the power supply line and the output line, the temperature detection units outputting a signal according to a temperature as the output signal to the output line; A drive unit that drives the plurality of temperature detection units in a time division manner; A detection device comprising:

2. When driving a first temperature detection unit among the plurality of temperature detection units, the drive unit stops the temperature detection units other than the first temperature detection unit among the plurality of temperature detection units. The detection device according to claim 1 .

3. Each of the plurality of temperature detection units is connected to the output line via a switch element that switches a conductive state between the temperature detection units and the output line. The detection device according to claim 1 .

4. At least a portion of the plurality of temperature detection units includes a ring oscillator. The detection device according to claim 1 .

5. A clock signal line is provided, the driving unit includes a shift register that drives the corresponding temperature detection unit based on a clock signal supplied from the clock signal line; The detection device according to claim 1 .

6. A driving pulse line for transmitting a driving pulse signal is provided, the shift register drives the corresponding temperature detection unit based on the drive pulse signal transmitted from a previous stage, and transmits the drive pulse signal to a subsequent stage based on the clock signal; 6. The detection device according to claim 5.

7. a first connection portion on an input side in which a connection terminal of the clock signal line, a connection terminal of the drive pulse line, a connection terminal of the power supply line, and a connection terminal of the output line are arranged in a predetermined order; a second connection portion on the output side in which the connection terminal of the clock signal line, the connection terminal of the drive pulse line, the connection terminal of the power supply line, and the connection terminal of the output line are arranged in the predetermined order; The detection device according to claim 6 .

8. A distance between two adjacent temperature detection units among the plurality of temperature detection units is equal to or greater than a predetermined distance. The detection device according to claim 1 .

9. The predetermined distance is equal to or greater than 1 meter.

8. The detection device according to claim 7.

10. The plurality of temperature detection units are arranged in a substantially straight line. The detection device according to claim 1 .

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