Circuit correction method and circuit structure, adopted to pattern deviation

Abstract

To provide a circuit correction method and a circuit structure, which are adopted for a pattern deviation having excellent electric quality by collection of a circuit position and an impedance.SOLUTION: A method contains: a step of installing a chip onto a carrier; a step of performing circuit position collection of a pattern of a re-wiring layer by measuring an off-set amount of the chip, and calculating an impedance difference before and after the correction of the circuit position collection; a step of evaluating a circuit occupation ratio and an impedance change range that require the impedance correction from a pattern of the re-wiring layer on the basis of the impedance difference; a step of determining a plan of a correction position and the circuit occupation ratio, and adjusting the line width, the area, the length, the diagram, or the combination of them of the circuit in the circuit occupation ratio on the basis of the impedance difference; a step of outputting an image file of the pattern obtained by performing the circuit position correction of the re-wiring layer and impedance correction; and a step of forming the re-wiring layer onto a carrier on the basis of the image file, and electrically connecting the re-wiring layer to the chip.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit correction method and a circuit structure, and also to a circuit correction method and a circuit structure that are applied to a pattern misalignment. [Background technology]

[0002] In the chip first chip packaging process, the contact signals cannot be connected accurately due to the misalignment of the chip, so a compensation design of the conductive circuit corresponding to the offset of the chip is performed to ensure accurate connection between the chip and the conductive circuit. However, after the compensation design, the length of the conductor wire changes and the impedance value of the circuit changes, so the electrical quality of the chip package does not match the expected one.

[0003] Meanwhile, in the RDL first (redistribution layer first) chip packaging process, due to the difference in thermal expansion coefficient between dielectric materials and metal materials, different offset situations occur in the circuits on the large board, which causes offsets in all the circuits on each layer. To prevent the chip from being unable to connect to the pads accurately when finally bonding the chip to the redistribution layer, the pad position can be corrected by adjusting the circuit layer. However, after the correction design, the length of the conductor changes and the impedance value of the circuit changes, so the electrical quality of the circuit structure does not match what was expected. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiment of the present invention provides a circuit correction method applied to pattern misalignment, which allows the circuit structure to have excellent electrical quality through circuit position correction and impedance correction.

[0005] Embodiments of the present invention provide a circuit structure with superior electrical qualities. [Means for solving the problem]

[0006] One embodiment of the present invention provides a circuit correction method applicable to pattern deviation, including the steps of: placing at least one chip on a carrier; measuring an offset amount of the chip, performing circuit position correction on a default redistribution layer pattern, and calculating an impedance difference before and after the circuit position correction of the redistribution layer pattern; evaluating a circuit occupancy rate and an impedance change range that require impedance correction among the redistribution layer patterns after the circuit position correction based on the impedance difference; determining a correction position and circuit occupancy plan, and adjusting a line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy based on the impedance difference; outputting an image file of the redistribution layer pattern after the circuit position correction and impedance correction; and forming a redistribution layer on the carrier based on the image file, and electrically connecting the redistribution layer to the chip.

[0007] One embodiment of the present invention provides a circuit correction method applicable to pattern deviation, including the steps of stacking a multi-layer circuit on a carrier; measuring an offset amount of the multi-layer circuit and performing circuit position correction on a default pattern of an upper circuit to be formed on the multi-layer circuit so as to enable normal connection of signals; calculating an impedance difference between the pattern after the circuit position correction of the upper circuit and the default pattern; adjusting the line width, area, length, shape, or a combination thereof of the circuit within the circuit occupancy of the pattern of the upper circuit after the circuit position correction based on the impedance difference to achieve impedance correction; outputting the pattern of the upper circuit after the circuit position correction and impedance correction; and forming the upper circuit on the multi-layer circuit based on the pattern of the upper circuit after the circuit position correction and impedance correction.

[0008] One embodiment of the present invention provides a circuit structure including a carrier, a redistribution layer, and at least one chip. The redistribution layer has a normal circuit and an impedance compensation structure disposed on the carrier and connected to each other, the impedance compensation structure being located in a first region and the normal circuit being located in a second region. Wherein, the impedance compensation structure has a circuit occupancy rate and has a different line width, a different area, a different length, a different shape, or a combination thereof, relative to the normal circuit. The at least one chip is disposed on the carrier and electrically connected to the redistribution layer. Wherein, the impedance of the circuit structure does not change due to the misalignment of the chip. Effect of the Invention

[0009] The circuit correction method applied to the pattern misalignment in the embodiment of the present invention forms a redistribution layer or an upper circuit by circuit position correction and impedance correction, so that a circuit structure with excellent electrical quality can be formed. The circuit structure in the embodiment of the present invention adopts an impedance correction structure, so that the circuit structure has excellent electrical properties. [Brief description of the drawings]

[0010] [Figure 1] 4 is a flowchart of a circuit correction method applied to pattern misalignment in one embodiment of the present invention. [Figure 2A] 2 is a top schematic diagram showing one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2B] 2 is a top schematic diagram showing one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2C] 2 is a top schematic diagram showing one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2D] 2 is a top schematic diagram showing one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Figure 2E]2 is a top schematic diagram showing one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 1. [Diagram 3] FIG. 2D is a curve diagram showing the change in impedance of the circuit of FIG. 2C with line width correction. [Figure 4A] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4B] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4C] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4D] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4E] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4F] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4G] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4H] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4I] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4J] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 4K] 2A-2C are schematic top views of the circuit before and after impedance compensation, illustrating one embodiment of the impedance compensation of FIG. 1; [Figure 5A] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5B] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5C] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5D] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5E] 1A-1C show top schematic views of a circuit structure of one embodiment of the present invention before and after impedance compensation. [Figure 5F] FIG. 2 is a top view schematic diagram of a circuit structure of one embodiment of the present invention after impedance compensation. [Figure 6] 11 is a process flowchart of a circuit correction method applied to pattern misalignment according to another embodiment of the present invention. [Figure 7A] 7 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7B] 7 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7C] 7 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7D] 7 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 6. [Figure 7E] 7 is a schematic top view illustrating one step of a process of a circuit correction method applied to the pattern misalignment of FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 is a flow chart of a circuit correction method applied to a pattern misalignment of one embodiment of the present invention, and FIG. 2A to FIG. 2E are top schematic views for illustrating the process of the circuit correction method applied to the pattern misalignment of FIG. 1. Referring to FIG. 1 and FIG. 2A to FIG. 2E, the circuit correction method applied to the pattern misalignment of this embodiment includes the following steps. First, as shown in FIG. 2A, step S110 is performed to place at least one chip 110 on a carrier 120. For example, the chip 110 is bonded onto the carrier 120. In the bonding process, due to alignment errors and other factors, there may be an offset amount relative to the default position of the chip. Next, as shown in FIG. 2B and FIG. 2C, step S120 is performed to measure the offset amount of the chip 110, perform circuit position correction on the default redistribution layer pattern 200 (shown in FIG. 2B), form the redistribution layer pattern 300 (shown in FIG. 2C) after the circuit position correction, and calculate the impedance difference before and after the circuit position correction of the redistribution layer pattern (that is, the impedance difference between the redistribution layer pattern 200 and the redistribution layer pattern 300). Then, as shown in FIG. 2D, step S130 is executed, and based on this impedance difference, the circuit occupancy rate and impedance change range of the rewiring layer pattern 300 that require impedance correction after the circuit position correction is evaluated. In this embodiment, the circuit occupancy rate of the region A1 is, for example, 20%, the circuit occupancy rate of the region A2 is, for example, 50%, and the circuit occupancy rate of the region A3 is, for example, 10%. Here, the circuit occupancy rate refers to the ratio of the area of ​​the circuit 310 in the region (for example, the region A1, the region A2, or the region A3) where the impedance correction is to be performed to the area of ​​the entire circuit 310 from the contact 301 to the contact 302. Next, a method of the correction position and the circuit occupancy rate is determined (that is, which region of the circuit 310 is adopted to perform the impedance correction and its circuit occupancy rate are determined), and based on the impedance difference, the line width, area, length, shape, or a combination thereof of the circuit 310 in the circuit occupancy rate is adjusted. In this embodiment, for example, a case where the line width of the circuit 310 is adjusted is taken as an example.

[0012] In this embodiment, step S140 is continued to determine whether the line width adjustment range of the impedance compensation is smaller than the auxiliary range of the exposure machine. If the answer is "no," the following step S150 is continued to be executed, and if the answer is "yes," a circuit occupancy rate scheme is reselected. For example, the circuit occupancy rate is reduced (i.e., a smaller circuit occupancy rate is selected). To be more specific, when the exposure machine manufactures a circuit through a photolithography process, there is a detection limit, and if the change in line width is too small, the exposure machine cannot detect it and it becomes impossible to realize. At this time, by reducing the circuit occupancy rate, the degree of line width adjustment corresponding to the impedance difference can be increased, so that the exposure machine can detect it and the auxiliary range can be reached.

[0013] Next, step S150 is performed to output an image file in which the circuit position and impedance of the pattern of the redistribution layer are corrected. Then, as shown in FIG. 2E, step S160 is performed to form the redistribution layer 400 on the carrier 120 based on the image file, and the redistribution layer 400 is electrically connected to the chip 110. Here, as can be seen from the enlarged view of FIG. 2E, the circuit 310 of the redistribution layer 400 has a wider line width.

[0014] FIG. 3 is a curve diagram of the change in impedance of the circuit of FIG. 2C with line width correction. Referring to FIG. 2C, FIG. 2D, and FIG. 3, the impedance value of the circuit 310 of the rewiring layer pattern 300 after the circuit position correction when the impedance correction (e.g., line width correction) has not yet been performed is between about 1.75 and 1.76, which is slightly different from the design value between 1.67 and 1.68. As can be seen from the change curve of FIG. 3, when the line width of the circuit 310 is corrected by 4.4 micrometers, the impedance of the circuit 310 can be returned to the design value. The detection range for the line width correction of the exposure machine is, for example, 2 to 5 micrometers, and 4.4 micrometers is within this range, so the line width correction of 4.4 micrometers fits the auxiliary range of the exposure machine.

[0015] Table 1 below shows some examples of the above circuit occupancy rate schemes (i.e., the correction schemes of Table 1).

[0016] [Table 1]

[0017] For example, in the correction scheme A, when the circuit occupancy is 10% and the absolute value of the impedance difference is 10% or less, the line width or area ratio of the circuit 310 (i.e., the line width correction in Table 1) is adjusted to be greater than 0% and less than 100% in response. Here, the line width correction may be an increase in line width or a decrease in line width. Similarly, when the circuit occupancy is 10% and the absolute value of the impedance difference is greater than 10% and less than 20%, the line width or area ratio of the circuit 310 (i.e., the line width correction in Table 1) is adjusted to be greater than 100% and less than 200% in response. The physical meaning of other situations in Table 1 can be inferred from this. For example, in the correction scheme B, when the circuit occupancy is 20% and the absolute value of the impedance difference is 10% or less, the line width or area ratio (i.e., the line width correction in Table 1) is adjusted to be greater than 0% and less than 50% in response. Other situations and physical meanings of other compensation schemes in Table 1 can be inferred from this. In other embodiments, other compensation schemes may simultaneously select two regions in the circuit 310 with different circuit occupancy rates and perform impedance compensation (e.g., linewidth compensation). For example, two regions in the circuit 310 with circuit occupancy rates of 10% and 20%, respectively, are selected, and impedance compensation (e.g., linewidth compensation) is performed on both of them. In other embodiments, three or more regions in the circuit 310 with different circuit occupancy rates may simultaneously be selected and impedance compensation (e.g., linewidth compensation) is performed.

[0018] In this embodiment, an area (e.g., area A1) in which the line spacing is relatively large in the redistribution layer pattern 300 after the circuit position correction is used as an area for impedance correction. In this embodiment, the chip 110 is a low-frequency signal chip. For example, in one embodiment, the chip 110 is a display panel driving chip, and its frequency is in the range of 1 Hz to 10 kHz. Alternatively, in one embodiment, the chip 110 is a micro light-emitting diode chip.

[0019] The circuit correction method applied to the pattern misalignment of the present embodiment forms the redistribution layer 400 by circuit position correction and impedance correction, so that a circuit structure having excellent electrical quality can be formed. In addition, the circuit correction method applied to the pattern misalignment of the present embodiment is applied to a chip first process.

[0020] 4A to 4K are schematic top views of the circuit before and after impedance correction, showing various embodiments of the impedance correction of FIG. 1. Referring to FIG. 4A, when the impedance of the circuit 310 after the circuit position correction is increased, the impedance can be reduced by increasing the line width of the circuit 310 to form the impedance correction structure 312a. Referring to FIG. 4B, when the impedance of the circuit 310 after the circuit position correction is decreased, the impedance can be increased by bending both sides of the circuit 90 degrees to increase the length of the circuit to form the impedance correction structure 312b. Referring to FIG. 4C, when the impedance of the circuit 310 after the circuit position correction is decreased, the impedance can be increased by bending one side of the circuit 90 degrees to increase the length of the circuit to form the impedance correction structure 312c. Referring to FIG. 4D, when the impedance of the circuit 310 after the circuit position correction is decreased, the impedance can be increased by bending the circuit 45 degrees to increase the length of the circuit to form the impedance correction structure 312d. Referring to Fig. 4E, when the impedance of the circuit 310 after the circuit position correction becomes large, the impedance can be lowered by adding at least one wide block 311e on the circuit, and an impedance compensation structure 312e can be formed. Referring to Fig. 4F, when the impedance of the circuit 310 after the circuit position correction becomes small, the connection between the partial region 311f of the circuit and other regions can be reduced. For example, the impedance can be increased by shrinking the connection portion 313f, and an impedance compensation structure 312f can be formed.

[0021] Referring to FIG. 4G, when the impedance of the circuit 310 after the circuit position correction is reduced, the impedance can be increased by reducing the line width of the circuit to form an impedance compensation structure 312g. Referring to FIG. 4H, when the impedance of the circuit 310 after the circuit position correction is reduced, the impedance can be increased by removing a partial region 311h of the circuit to form an impedance compensation structure 312h. Here, the partial region 311h is, for example, a square region. Referring to FIG. 4I, when the impedance of the circuit 310 after the circuit position correction is reduced, the impedance can be increased by removing a partial region 311i of the circuit to form an impedance compensation structure 312i. Here, the partial region 311i is, for example, a circular region. In other embodiments, the partial region 311i may be a region of another shape. Referring to FIG. 4J, when the impedance of the circuit 310 after the circuit position correction is reduced, the impedance can be increased by removing a partial region 311j of the circuit to form an impedance compensation structure 312j. Here, the partial region 311j is, for example, located on the edge of the circuit, and is, for example, a square region. However, in other embodiments, the partial region 311j may be a region of other shapes. Referring to FIG. 4K, when the impedance of the circuit 310 after the circuit position correction becomes large, a part of the circuit is expanded to form an expanded region 311k, so that the impedance can be reduced and an impedance correction structure 312k can be formed. In other embodiments, the expanded region 311k may be another region that can increase the line width.

[0022] 5A to 5E are schematic top views of circuit structures according to several embodiments of the present invention before and after impedance compensation. First, referring to FIG. 5A, the circuit structure 500 of the present embodiment includes a carrier 120, a redistribution layer 400, and at least one chip 110. The redistribution layer 400 has a normal circuit 314 and at least one impedance compensation structure 312 arranged on the carrier 120 and connected to each other. Here, the impedance compensation structure 312 has a different line width, a different area, a different length, a different shape, or a combination thereof, compared to the normal circuit 314, and FIG. 5A takes the case of a different line width or a different area as an example. In this embodiment, the line width and area of ​​the impedance compensation structure 312 are larger than those of the normal circuit 314, so that the impedance of the circuit can be effectively reduced. The at least one chip 110 is arranged on the carrier 120 and electrically connected to the redistribution layer 400. In this embodiment, the at least one chip 110 is a plurality of chips 110, and can be divided into a driving chip 112 and a micro light-emitting diode chip 114, and the driving chip 112 is used to drive the micro light-emitting diode chip 114 through the redistribution layer 400 to make it emit light.

[0023] In this embodiment, the circuit structure 500 can be fabricated by the circuit compensation method applied to the pattern deviation of Fig. 1. By adopting the impedance compensation structure 312, the circuit structure 500 can have excellent electrical quality.

[0024] The circuit structure 500 can also be applied to a circuit structure as shown in FIG. 2E. The impedance compensation structure 312 is located in a first region (e.g., region A1, A2, or A3 in FIG. 2E), and the normal circuit 314 is located in a second region (e.g., the remaining region other than the first region). The circuit occupancy rate of the impedance compensation structure 312 may be as described in the embodiment of Table 1 above. For example, the circuit structure generated in the compensation scheme A has a circuit occupancy rate of 10%, an absolute value of the impedance difference caused by the chip deviation of the normal circuit 314 of the redistribution layer 400 is less than 10%, and the ratio of the line width change or area change of the impedance compensation structure 312 to the normal circuit 314 is greater than 0% and less than 100%. The circuit structure generated in the compensation scheme B has a circuit occupancy rate of 20%, an absolute value of the impedance difference caused by the chip misalignment of the normal circuit 314 of the redistribution layer 400 is less than 10%, and the ratio of the line width change or area change of the impedance compensation structure 312 to the normal circuit 314 is greater than 0% and less than 50%. The details of the other compensation schemes of the embodiment in Table 1 above can be inferred from this and will not be repeated here.

[0025] Furthermore, in one embodiment, as shown in FIG. 5F, the line spacing D1 of the end E1 where the normal circuit 314 and the impedance compensation structure 312 connect to each other is larger than the average line spacing of the normal circuit 314. For example, the end E1 where the normal circuit 314 and the impedance compensation structure 312 connect to each other is located in an area with a relatively large line spacing (e.g., the line spacing D1 in area A1 of FIG. 5F is larger than the line spacing D2 between the normal circuits 314 in area A2, and the impedance compensation structure 312 is located in area A1). Here, the average line spacing of the normal circuit 314 can be defined as the area of ​​the spacing area between two adjacent normal circuits 314 divided by the total length of one of the two adjacent normal circuits 314.

[0026] The circuit structures 500a-500d of Figures 5B-5E are similar to the circuit structure 500 of Figure 5A, but differ mainly in the impedance compensation structures employed in the redistribution layers, each of which will be described in detail below.

[0027] Referring to Fig. 5B, the redistribution layer 400a of the circuit structure 500a of the present embodiment employs the impedance compensation structure 312j of Fig. 4J to increase the impedance of the circuit. Referring to Fig. 5C, the redistribution layer 400b of the circuit structure 500b of the present embodiment employs the impedance compensation structure 312' to reduce the impedance of the circuit. Here, the impedance compensation structure 312' is similar to the impedance compensation structure 312 of Fig. 5A, but in comparison, the impedance compensation structure 312' has a smaller area and a larger number.

[0028] Referring to Fig. 5D, the redistribution layer 400c of the circuit structure 500c of the present embodiment employs the impedance compensation structure 312c of Fig. 4C to increase the impedance of the circuit. Referring to Fig. 5E, the redistribution layer 400d of the circuit structure 500d of the present embodiment employs a structure similar to Fig. 4F to reduce the connection between the partial region 311f of the circuit and other regions, thereby increasing the impedance and forming the impedance compensation structure 312f'. In other embodiments, the redistribution layer of the circuit structure may employ the impedance compensation structures 312a-312k of Figs. 4A-4K to increase or decrease the impedance.

[0029] FIG. 6 is a flow chart of a circuit correction method applied to the pattern misalignment of another embodiment of the present invention, and FIG. 7A to FIG. 7E are top schematic views for illustrating the process of the circuit correction method applied to the pattern misalignment of FIG. 6. Referring to FIG. 6 and FIG. 7A to FIG. 7E, the circuit correction method applied to the pattern misalignment of this embodiment includes the following steps. First, as shown in FIG. 7A, step S210 is performed to stack a multi-layer circuit 210 on a carrier 120. Here, the multi-layer circuit 210 is, for example, a redistribution layer. In this embodiment, the carrier 120 is, for example, larger in size than the display panel G2.5 generation, for example, the length and width are larger than the size of 370 mm and 470 mm, respectively. That is, the carrier 120 is, for example, a large carrier. In the manufacturing process of the redistribution layer, due to the difference in the thermal expansion coefficient of the dielectric material and the metal material, an offset situation is likely to occur in the circuit on the large carrier, which causes an offset in the circuit of each layer of the multi-layer circuit 210. At this time, step S220 is continued to measure the offset amount of the multi-layer circuit 210, and a circuit position correction is performed on the default pattern 220 of the upper circuit (for example, as shown in FIG. 7B) to be formed on the multi-layer circuit 210. For example, the pattern 320 of the upper circuit is corrected as shown in FIG. 7C so that the signal can be connected normally. Specifically, the circuit correction method applied to the pattern deviation of this embodiment can be applied to the RDL first (redistribution layer first) process. Since the multi-layer circuit 210 already has an offset, when the default pattern 220 of the upper circuit is formed thereon, the pad position 222 of the default pattern 220 of the upper circuit may be offset with respect to the pad default position P1 to which the chip 110 is to be bonded, and the pad position 322 of the pattern 320 of the upper circuit after the circuit position correction is adjusted to match the pad default position P1.

[0030] Next, step S230 is performed to calculate the impedance difference between the pattern 320 (for example, as shown in FIG. 7C) after the circuit position correction of the upper circuit and the default pattern 220 (for example, as shown in FIG. 7B). Then, step S240 is performed to adjust the line width, area, length, shape, or a combination thereof of the circuit in the circuit occupancy of the pattern 320 of the upper circuit after the circuit position correction based on the impedance difference, thereby achieving impedance correction. That is, the pattern 330 of the upper circuit is corrected as shown in FIG. 7C. Here, the method of adjusting the circuit occupancy and the line width, area, length, shape, or a combination thereof may be the same as each of the above-mentioned embodiments, so it will not be described here repeatedly. That is, before the impedance correction, the circuit occupancy and the impedance change range that require impedance correction in the pattern 320 of the upper circuit after the circuit position correction can be evaluated based on the impedance difference. Next, a scheme for the correction position and the circuit occupancy is determined, and the impedance correction is performed. In one embodiment, the area in the pattern 320 of the upper circuit after the circuit position correction where the line spacing is relatively large is used as the area for impedance correction.

[0031] Then, step S250 is executed to determine whether the line width adjustment range of the impedance compensation is smaller than the auxiliary range of the exposure machine. If the answer is "No," the following step S260 is executed continuously. If the answer is "Yes," a scheme for the circuit occupancy rate is reselected. For example, the circuit occupancy rate is reduced (i.e., a smaller circuit occupancy rate is selected). The method for reselecting the scheme for the circuit occupancy rate is the same as that described in the above embodiment, and will not be described again here.

[0032] Next, step S260 is executed to output the upper circuit pattern 330 (for example, as shown in FIG. 7D) after the circuit position correction and the impedance correction are performed. Then, as shown in FIG. 7E, step S270 is executed to form the upper circuit 410 on the multilayer circuit 210 based on the upper circuit pattern 330 after the circuit position correction and the impedance correction are performed.

[0033] In this embodiment, the circuit correction method applied to the pattern misalignment further includes the steps of placing at least one chip 110 on the upper circuit 410 and electrically connecting the chip 110 to the upper circuit 410. The chip 110 is the chip 110 described in the above embodiment, and therefore will not be described again here.

[0034] In the circuit correction method applied to the pattern misalignment of this embodiment, the upper circuit is formed by circuit position correction and impedance correction, so that the circuit structure 500e having excellent electrical quality can be formed.

[0035] As described above, the circuit correction method applied to the pattern misalignment in the embodiment of the present invention forms a redistribution layer or an upper circuit by circuit position correction and impedance correction, so that a circuit structure having excellent electrical quality can be formed. The circuit structure in the embodiment of the present invention adopts an impedance correction structure, so that the circuit structure has excellent electrical characteristics.

[0036] Although the present invention has been disclosed by the above-mentioned embodiments, the present invention is not intended to be limited thereto, and a person having ordinary knowledge in the art may make some modifications and improvements without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention is defined by the claims set forth below. [Industrial Applicability]

[0037] The circuit correction method and circuit structure applied to the pattern misalignment of the present invention can be used in the process and structure of chip packaging. [Explanation of symbols]

[0038] 110 Chips 112 Driving Chip 114 Micro Light Emitting Diode Chip 120 Career 200, 300 Redistribution layer pattern 210 Multilayer circuit 220 Default pattern for upper circuit 222, 322 pad positions 301, 302 Contact 310 Circuit 311e Block 311f, 311h, 311i, 311j partial area 311k Expanded Area 312, 312', 312a, 312b, 312c, 312d, 312e, 312f, 312f', 312g, 312h, 312i, 312j, 312k Impedance compensation structures 313f Connection 314 Normal circuit 320, 330 Upper circuit pattern 400, 400a, 400b, 400c, 400d redistribution layer 410 Upper Circuit 500, 500a, 500b, 500c, 500d, 500e circuit structure A1, A2, A3 area D1, D2 line spacing E1 end P1 Pad default position S110~S160, S210~S270 Step

Claims

1. placing at least one chip on a carrier; measuring an offset amount of the chip, performing a circuit position correction for a default redistribution layer pattern, and calculating an impedance difference before and after the circuit position correction of the redistribution layer pattern; evaluating a circuit occupancy rate and an impedance change range that require impedance correction in the pattern of the rewiring layer after the circuit position correction is performed based on the impedance difference; determining a correction position and circuit occupancy scheme, and adjusting the line width, area, length, shape, or combination thereof of the circuit within the circuit occupancy according to the impedance difference; outputting an image file of the rewiring layer pattern after the circuit position correction and the impedance correction are performed; forming the redistribution layer on the carrier based on the image file, and electrically connecting the redistribution layer to the chip; A circuit correction method applied to a pattern misalignment including:

2. 2. The circuit correction method applied to a circuit pattern misalignment according to claim 1, wherein, when the circuit occupancy rate is 10% and the absolute value of the impedance difference is 10% or less, in response thereto, the ratio of the line width or the area is adjusted to be greater than 0% and less than 100%.

3. 2. The circuit correction method applied to a circuit pattern misalignment according to claim 1, wherein, when the circuit occupancy rate is 20% and the absolute value of the impedance difference is 10% or less, in response thereto, the ratio of the line width or the area is adjusted to be greater than 0% and less than 50%.

4. 2. The circuit correction method applied to a circuit pattern misalignment according to claim 1, wherein a region in which a line spacing is relatively large in the pattern of the rewiring layer after the circuit position correction is used as the region for the impedance correction.

5. 2. The circuit correction method for circuit pattern deviation according to claim 1, further comprising the step of reselecting the circuit occupancy rate scheme in response to an impedance compensation step in which the line width adjustment range is smaller than an exposure machine's compensation range.

6. laminating a multi-layer circuit on a carrier; measuring an offset amount of the multi-layer circuit and performing a circuit position correction with respect to a default pattern of an upper circuit to be formed on the multi-layer circuit so that signals can be connected normally; calculating an impedance difference between a pattern after the circuit position correction of the upper circuit and a default pattern; adjusting a line width, an area, a length, a shape, or a combination thereof of a circuit in a circuit occupancy rate of the pattern of the upper circuit after performing the circuit position correction based on the impedance difference to achieve impedance correction; outputting a pattern of the upper circuit after performing the circuit position correction and the impedance correction; forming the upper circuit on the multilayer circuit based on a pattern of the upper circuit after the circuit position correction and the impedance correction are performed; A circuit correction method applied to a circuit pattern misalignment, comprising:

7. The circuit correction method applied to circuit pattern deviation as claimed in claim 6, further comprising the steps of: placing at least one chip on the upper circuit; and electrically connecting the chip to the upper circuit.

8. a step of evaluating, before the impedance correction, a circuit occupancy rate and a change range of impedance that require impedance correction among the patterns of the upper circuit after the circuit position correction is performed, based on the impedance difference; determining a correction position and a circuit occupancy rate scheme to perform the impedance correction; The circuit correction method applied to a circuit pattern misalignment according to claim 6, further comprising:

9. 9. The circuit correction method applied to a circuit pattern misalignment according to claim 8, further comprising the steps of: adjusting, in response to the circuit occupancy rate being 10% and the absolute value of the impedance difference being 10% or less, a ratio of the line width or the area being greater than 0% and less than 100%.

10. 9. The circuit correction method applied to a circuit pattern misalignment according to claim 8, further comprising the step of adjusting a ratio of the line width or the area to be greater than 0% and less than 50% when the circuit occupancy rate is 20% and the absolute value of the impedance difference is less than 10%.

11. 9. The circuit correction method for circuit pattern deviation according to claim 8, further comprising the step of reselecting the circuit occupancy rate scheme in response to the line width adjustment range of the impedance compensation being smaller than a range that an exposure machine can assist in.

12. 7. The circuit correction method applied to a circuit pattern misalignment according to claim 6, wherein an area in which a line spacing is relatively large in the pattern of the upper circuit after the circuit position correction is used as the area for the impedance correction.

13. Career and a redistribution layer disposed on the carrier and having a normal circuit and an impedance compensation structure connected to each other, the impedance compensation structure being located in a first region and the normal circuit being located in a second region, the impedance compensation structure having a circuit occupancy rate and a different line width, a different area, a different length, a different shape, or a combination thereof, relative to the normal circuit; at least one chip disposed on the carrier and electrically connected to the redistribution layer, such that the impedance of the circuit structure does not change with chip misalignment; A circuit structure comprising:

14. 14. The circuit structure according to claim 13, wherein the chip is a low-frequency signal chip or a display panel driving chip, the frequency of which is in the range of 1 Hz to 10 kHz, or the chip is a micro light-emitting diode chip.

15. 14. The circuit structure according to claim 13, wherein the circuit occupancy rate is 10%, the absolute value of the impedance difference caused by the chip misalignment of the normal circuit of the redistribution layer is 10% or less, and the ratio of the line width change or area change of the impedance compensation structure to the normal circuit is greater than 0% and less than 100%.

16. 14. The circuit structure according to claim 13, wherein the circuit occupancy rate is 20%, the absolute value of the impedance difference caused by the chip misalignment of the normal circuit of the redistribution layer is 10% or less, and the ratio of the line width change or area change of the impedance compensation structure to the normal circuit is greater than 0% and less than 50%.

17. 14. The circuit structure of claim 13, wherein the line spacing at the ends where the normal circuit and the impedance compensation structure connect to each other is greater than the average line spacing of the normal circuit.

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