Inverter device

Abstract

To provide an inverter device which can adjust shunt balance and avoid complication of control.SOLUTION: An inverter device 1 comprises: an inverter unit 2; a measurement unit 3 which measures inverter current; and a control unit 5 which performs PWM control to respective inverter circuits 2-1 to 2-N of the inverter unit 2. The control unit 5 comprises an analog circuit unit and a digital circuit unit. The analog circuit unit includes a pulse generation unit 10 which generates a PWM signal, and the digital circuit unit includes a pulse adjustment unit 20 which performs pulse adjustment processing for increasing and decreasing pulse width of the PWM signal according to a setting parameter, and a parameter correction unit 40 which performs parameter correction processing for fetching a measurement signal of each inverter current from the measurement unit 3, and increasing and decreasing a value of the setting parameter when the measurement signal is out of a setting range.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an inverter device. [Background technology]

[0002] The inverter device is used, for example, in an electromagnet power supply system that supplies an excitation current to an electromagnet. The inverter device includes an inverter circuit and a control unit that controls the inverter circuit. The inverter circuit is configured with four switching elements connected in a bridge configuration so as to operate in four quadrants that are divided by the positive and negative voltages and currents.

[0003] When increasing the excitation current in an electromagnet power supply system, multiple inverter circuits are connected in parallel, and the inverter currents output from each inverter circuit are combined to generate an output current (excitation current). The number of parallel inverter circuits is determined according to the specifications (type, characteristics, etc.) of the switching elements that make up the inverter circuits, the current value of the excitation current, etc.

[0004] An inverter device including multiple inverter circuits connected in parallel is also used in power supply systems other than electromagnet power supply systems, and PWM control is generally used to control the inverter circuits. During PWM control, the control unit generates a deviation signal by comparing a target value of the output current of the inverter device with a measured value of the output current, and generates a PWM signal by comparing the deviation signal with a triangular wave signal, and turns on and off the switching elements of the inverter circuit using the PWM signal.

[0005] When a single PWM signal generated by a control unit is output to multiple inverter circuits via branched wiring, ideally the switching elements of each inverter circuit turn on and off at the same timing, and the inverter currents output from each inverter circuit are equalized. However, in reality, due to the influence of impedance variations due to the wiring route and wiring length after branching, and variations in the characteristics of the switching elements, the on / off timing of the switching elements of each inverter circuit shifts, and the inverter currents output from each inverter circuit become uneven. When the inverter currents become uneven, the load factors of each inverter circuit also become uneven, which may cause variations in the lifespan of parts such as switching elements.

[0006] A method for equalizing the inverter currents, in other words, for adjusting the shunt balance of each inverter circuit, is known to connect resistors (hereinafter, shunt resistors) to the inverter circuits to adjust the shunt balance. However, depending on the degree of shunt balance, a large shunt resistor may be required, and the problem arises that the inverter circuit becomes larger when the shunt resistor is connected. In addition, when connecting a shunt resistor, it is necessary to consider the effects of heat generation, loss, etc. due to the shunt resistor.

[0007] As another method for adjusting the shunt balance, a method in which a PWM signal is corrected by a control unit is known (see, for example, Patent Document 1). In the method described in Patent Document 1, each inverter current is measured by a current transformer, feedback control is performed, and the PWM signal output to each inverter circuit is corrected so that the difference between the measured values ​​(moving average values) of each inverter current becomes small. With this method, the shunt balance can be adjusted without using a shunt resistor.

[0008] However, when the control unit generates a PWM signal by digital control, it is necessary to perform ADC processing to convert an analog signal (current measurement value) into a digital signal, and it is necessary to consider the delay due to the conversion time of ADC processing and the conversion period. In addition, in order to improve the conversion accuracy of ADC processing, high-speed conversion processing and processing for reducing noise (for example, moving average processing) are required. For example, in the method described in Patent Document 1, ADC processing is performed on the current measurement value, and moving average processing is performed, and then a basic PWM signal (PWM signal before current division adjustment) is generated. If the number of times of moving average processing is increased, the effect of noise reduction is improved, but there is a risk that the speed of feedback control cannot be increased. As described above, when a PWM signal before current division adjustment is generated by digital control, it is necessary to consider the delay due to the conversion time of ADC processing, the conversion period, and the conversion accuracy, which causes a problem of complicated control.

[0009] However, when the correction amount of the PWM signal is changed according to the measured value of the inverter current, the current distribution balance may worsen. For example, when the measured value of the inverter current changes abruptly, the correction amount of the PWM signal also changes abruptly, and correcting the PWM signal according to the correction amount worsens the current distribution balance. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2018-133987 A Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inverter device capable of adjusting the current division balance and avoiding the complication of control. [Means for solving the problem]

[0012] In order to solve the above problems, an inverter device according to the present invention comprises: an inverter section including a plurality of inverter circuits connected in parallel, each of the plurality of inverter circuits including at least one switching element; A measurement unit for measuring each inverter current output from each of the inverter circuits; A control unit that performs PWM control on each of the inverter circuits; An inverter device that supplies an output current obtained by combining the inverter currents to a load, The control unit includes an analog circuit unit that performs analog signal processing and a digital circuit unit that performs digital signal processing, The analog circuit unit generates a PWM signal for performing the PWM control, The digital circuit unit includes: a pulse adjustment unit that receives the PWM signal from the analog circuit unit and performs a pulse adjustment process to increase or decrease a pulse width of the PWM signal in accordance with a pre-stored setting parameter; and a parameter correction unit that receives a measurement signal of each inverter current from the measurement unit, and performs a parameter correction process to increase or decrease the value of the setting parameter if the measurement signal is outside a preset range.

[0013] In this configuration, the control unit includes an analog circuit unit that performs analog signal processing and a digital circuit unit that performs digital signal processing, and the digital circuit unit performs pulse adjustment processing to increase or decrease the pulse width of the PWM signal so that each inverter current is equalized, so that the shunt balance of each inverter circuit can be adjusted. In addition, in this configuration, the analog circuit unit generates a PWM signal before the pulse adjustment processing, so there is no need to consider the delay due to the conversion time of the ADC processing, the conversion period, and the conversion accuracy. As a result, in this configuration, it is possible to avoid the complication of control. Furthermore, in this configuration, the parameter correction unit performs parameter correction processing to increase or decrease the value of the setting parameter of the pulse adjustment processing, so that even if there is a change in the inverter unit (e.g., deterioration over time, replacement of a switching element) or a change in the load, the shunt balance can be suitably adjusted.

[0014] In the inverter device, The pulse adjustment unit is The pulse adjustment process is performed based on the increase / decrease width Y determined based on a calculation formula Y=KA×IrefP, where Y is the increase / decrease width of the pulse width during the pulse adjustment process, IrefP is the current current setting value set according to the target value of the output current, and KA is the correction coefficient which is the setting parameter; The parameter correction unit The correction coefficient KA may be increased or decreased during the parameter correction process.

[0015] In the inverter device, The parameter correction unit an ideal value setting unit that sets a current ideal value according to the diversion target value of each of the inverter currents; A conversion unit for converting the measurement signal into a digital signal; The device can be configured to perform a first determination as to whether or not the measurement signal is outside the set range based on the ideal current value and the signal value of the measurement signal that has passed through the conversion unit, and a correction processing unit that performs the parameter correction processing depending on the result of the first determination.

[0016] In the inverter device, The parameter correction unit a mode setting unit that sets a first mode in which the parameter correction process is permitted and a second mode in which the parameter correction process is prohibited; The parameter correction process may be configured to include a cycle setting unit that sets the execution timing of the parameter correction process.

[0017] In the inverter device, The parameter correction unit The parameter correction process may be performed only on the inverter circuit, of which the measurement signal is the furthest from the set range.

[0018] In the inverter device, The parameter correction unit The parameter correction process may be configured to increase or decrease the value of the setting parameter by a minimum value per one parameter correction process. Effect of the Invention

[0019] According to the present invention, it is possible to provide an inverter device capable of adjusting the current division balance and preventing the control from becoming complicated. [Brief description of the drawings]

[0020] [Figure 1] 1 is a diagram showing a configuration of an inverter device according to the present invention; [Diagram 2] FIG. 2 is a block diagram of a control unit (pulse generating unit) of the present invention. [Diagram 3] FIG. 2 is a block diagram of a control unit (pulse adjustment unit) of the present invention. [Figure 4] FIG. 2 is a block diagram of a control unit (pulse output unit) of the present invention. [Diagram 5] FIG. 2 is a block diagram of a control unit (parameter correction unit) of the present invention. [Figure 6] 5 is a diagram showing various signals of a control unit and an output voltage of an inverter circuit. FIG. [Figure 7]1A and 1B are diagrams for explaining a pulse adjustment process, in which (A) shows a case where the pulse width is increased, and (B) shows a case where the pulse width is decreased. [Figure 8] 11A to 11C are diagrams for explaining a parameter correction process in a manual correction mode of the present invention. [Figure 9] FIG. 11 is a diagram for explaining the parameter correction process (in the case of a pulse current) in the automatic correction mode of the present invention. [Figure 10] 11A to 11C are diagrams for explaining the parameter correction process (in the case of DC current) in the automatic correction mode of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an inverter device according to the present invention will now be described with reference to the accompanying drawings.

[0022] 1 shows the configuration of an inverter device 1 according to one embodiment of the present invention. The inverter device 1 includes an inverter section 2, a first measurement section 3 (corresponding to the "measurement section" of the present invention), a second measurement section 4, a control section 5, a pair of first input / output terminals T1, T1', and a pair of second input / output terminals T2, T2'.

[0023] The inverter unit 2 includes N inverter circuits 2-X (X=1, 2, . . . , N) (in this embodiment, N is an integer equal to or greater than 3) connected in parallel. All of the inverter circuits 2-X have the same configuration.

[0024] The inverter circuit 2-X is a full-bridge circuit made up of switching elements U, V, X, and Y. Specifically, the inverter circuit 2-X includes a first leg and a second leg connected in parallel between first input / output terminals T1 and T1', with the switching elements U and X connected in series forming the upper and lower arms of the first leg, and the switching elements V and Y connected in series forming the upper and lower arms of the second leg. The connection point of the switching elements U and X is connected to the second input / output terminal T2, and the connection point of the switching elements V and Y is connected to the second input / output terminal T2'.

[0025] It is preferable that the switching elements U, V, X, and Y are the same type of switching elements. In this embodiment, IGBTs (insulated gate bipolar transistors) are used as the switching elements U, V, X, and Y, but MOSFETs (metal oxide semiconductor field effect transistors) using Si (silicon), SiC (silicon carbide) or GaN (gallium nitride) may be used, or other semiconductor switching elements may be used. Diodes are connected in parallel to the current paths of the switching elements U, V, X, and Y. Each diode may be a parasitic diode of the switching elements U, V, X, and Y, or an external diode independent of the switching elements U, V, X, and Y, or both.

[0026] A DC power supply unit is connected to the first input / output terminals T1 and T1', and a DC voltage is applied to the DC power supply unit. The DC power supply unit is, for example, a bidirectional DC / DC converter circuit, a rectifier circuit, or a capacitor. Since the inverter circuit 2-X operates in four quadrants, in the inverter device 1, DC power is input to the first input / output terminals T1 and T1' and DC power is output from the first input / output terminals T1 and T1'.

[0027] A load is connected to the second input / output terminals T2, T2'. The load is, for example, an electromagnet. For example, an LC filter circuit or an insulating transformer may be provided between the second input / output terminals T2, T2' and the load. Since the inverter circuit 2-X operates in four quadrants, the inverter device 1 can output a current with a desired waveform, such as a pulse current, a pattern current (for example, a current with a stepped waveform), or a direct current, from the second input / output terminals T2, T2'.

[0028] Here, in this embodiment, operation in four quadrants means operation in four quadrants divided by positive and negative voltage and current (for example, the voltage and current at the second input / output terminal T2). That is, under the control of the control unit 5, the inverter circuit 2-X operates in the first quadrant where the voltage is positive and the current is positive, in the second quadrant where the voltage is positive and the current is negative, in the third quadrant where the voltage is negative and the current is negative, and in the fourth quadrant where the voltage is negative and the current is negative.

[0029] The first measurement unit 3 measures the positive and negative inverter currents output from the inverter circuit 2-X. The first measurement unit 3 includes first measurement means 3-X (X=1, 2, . . . , N) the same number as the inverter circuits 2-X (N units). As the first measurement means 3-X, for example, a DCCT or other DC current sensor can be used. The first measurement means 3-X outputs a first measurement signal (analog signal) related to the current value of the inverter current to the control unit 5.

[0030] The second measurement unit 4 measures the output current supplied to the load connected to the second input / output terminals T2, T2'. The output current is a current obtained by combining the inverter currents of the N inverter circuits 2-X. The second measurement unit 4 is provided on the second input / output terminal T2 side of the junction of the inverter currents, and the first measurement means 3-X is provided on the inverter circuit 2-X side of the junction. As the second measurement unit 4, a direct current sensor such as a DCCT can be used, similar to the first measurement means 3-X. The second measurement unit 4 outputs a second measurement signal (analog signal) related to the current value of the output current to the control unit 5.

[0031] The control unit 5 performs PWM control on the inverter circuit 2-X so that the inverter circuit 2-X operates in four quadrants. The control unit 5 includes a pulse generating unit 10, a pulse adjusting unit 20, a pulse output unit 30, and a parameter correcting unit 40. The pulse generating unit 10 and the pulse output unit 30 correspond to the "analog circuit unit" of the present invention and perform analog signal processing. The pulse adjusting unit 20 and the parameter correcting unit 40 correspond to the "digital circuit unit" of the present invention and perform digital signal processing.

[0032] The pulse generating unit 10 generates PWM signals (in this embodiment, a first PWM signal and a second PWM signal) that are the basis for performing PWM control. A block diagram of the pulse generating unit 10 is shown in FIG. 2. The pulse generating unit 10 includes a DAC unit 11, a calculation unit 12, an oscillation unit 13, an inversion unit 14, and a comparison unit 15.

[0033] The DAC unit 11 performs a process of converting a digital signal into an analog signal (DAC process). The DAC unit 11 converts a current setting signal (digital signal) related to the current setting value Iref received from the pulse adjustment unit 20 into an analog signal and outputs it to the calculation unit 12. The current setting value Iref is set according to a target value of the output current. If the target value increases, the current setting value Iref also increases, and if the target value decreases, the current setting value Iref also decreases.

[0034] The calculation unit 12 performs subtraction processing on the input analog signal. The calculation unit 12 receives the current setting signal (analog signal) and the second measurement signal (analog signal) of the second measurement unit 4. The calculation unit 12 generates and outputs a deviation signal obtained by subtracting the current setting signal from the second measurement signal.

[0035] The oscillator 13 is an oscillator that outputs a carrier signal. In this embodiment, the oscillator 13 outputs a triangular wave signal as the carrier signal, but may output a carrier signal other than a triangular wave signal.

[0036] The inverting unit 14 inverts the polarity of the input analog signal and outputs the inverted signal. The deviation signal output from the calculation unit 12 is input to the inverting unit 14, and the inverting unit 14 inverts the polarity of the deviation signal and outputs the deviation signal.

[0037] The comparison unit 15 includes comparators 15A and 15B. The comparators 15A and 15B compare an analog signal input to a non-inverting input terminal with an analog signal input to an inverting input terminal, and output a digital signal that is at a high level when the signal at the non-inverting input terminal is greater than the signal at the inverting input terminal, and is at a low level when the signal at the non-inverting input terminal is equal to or less than the signal at the inverting input terminal. The comparator 15A receives a triangular wave signal at its inverting input terminal and a deviation signal at its non-inverting input terminal, and outputs a first PWM signal (digital signal) according to the magnitude relationship between the two. The comparator 15B receives a deviation signal via the inverting unit 14 at its inverting input terminal and a triangular wave signal at its non-inverting input terminal, and outputs a second PWM signal (digital signal) according to the magnitude relationship between the two. A method for generating the first PWM signal and the second PWM signal will be described later.

[0038] The pulse adjustment unit 20 performs pulse adjustment processing to increase or decrease the pulse width of the PWM signal. The pulse adjustment unit 20 is preferably configured with a PLD (Programmable Logic Device). In this embodiment, the pulse adjustment unit 20 is configured with an FPGA (Field Programmable Gate Array). FIG. 3 shows a block diagram of the pulse adjustment unit 20. The pulse adjustment unit 20 includes a current setting unit 21, an input processing unit 22, an adjustment unit 23, a storage unit 24, and an output processing unit 25.

[0039] The current setting unit 21 sets a current setting value Iref according to a target value of the output current. The target value of the output current may be preset in the current setting unit 21, may be acquired by the current setting unit 21 from a device external to the inverter device 1 through communication, or may be calculated by the current setting unit 21 based on information acquired from the external device.

[0040] The input processing unit 22 includes a first input unit 22A and a second input unit 22B. The first input unit 22A receives a first PWM signal from the comparator 15A. The first input unit 22A performs filtering and clock synchronization on the first PWM signal. Similarly, the second input unit 22B performs filtering and clock synchronization on the second PWM signal. The filtering is a process for removing noise contained in the first PWM signal and the second PWM signal. The clock synchronization is a process for synchronizing the first PWM signal and the second PWM signal with the clock signal of the pulse adjustment unit 20. The frequency of the clock signal can be set to any value in the pulse adjustment unit 20. In this embodiment, the frequency of the clock signal is set to 100 [MHz].

[0041] The adjustment unit 23 includes N first adjustment units GX-1 (X=1, 2, . . ., N) and N second adjustment units GX-2 (X=1, 2, . . ., N). The first adjustment unit GX-1 performs pulse adjustment processing on the first PWM signal input from the first input unit 22A, and outputs the first PWM signal after the pulse adjustment processing. The second adjustment unit GX-2 performs pulse adjustment processing on the second PWM signal input from the second input unit 22B, and outputs the second PWM signal after the pulse adjustment processing. A specific method of the pulse adjustment processing will be described later.

[0042] The storage unit 24 includes N first storage units KX-1 (X=1, 2, . . . , N) and N second storage units KX-2 (X=1, 2, . . . , N). The first storage unit KX-1 stores a correction coefficient Kx-1 (x=1, 2, . . . , N) used in the pulse adjustment process performed by the first adjustment unit GX-1. The second storage unit KX-2 stores a correction coefficient Kx-2 (x=1, 2, . . . , N) used in the pulse adjustment process performed by the second adjustment unit GX-2. The correction coefficient Kx-1 and the correction coefficient Kx-2 are both integers and correspond to the "setting parameters" of the present invention. The values ​​of the correction coefficient Kx-1 and the correction coefficient Kx-2 are updated by the parameter correction process performed by the parameter correction unit 40. The storage unit 24 may be configured to include at least one storage unit, and the at least one storage unit may store the correction coefficients Kx-1 and Kx-2.

[0043] The output processing unit 25 includes N first output units MX-1 (X=1, 2, . . ., N) and N second output units MX-2 (X=1, 2, . . ., N). The first output unit MX-1 performs dead time generation processing and gate signal generation processing on the first PWM signal input from the first adjustment unit GX-1, and generates and outputs a U gate signal and an X gate signal having a predetermined dead time. The second output unit MX-2 performs dead time generation processing and gate signal generation processing on the second PWM signal input from the second adjustment unit GX-2, and generates and outputs a V gate signal and a Y gate signal having a predetermined dead time.

[0044] The pulse output unit 30 outputs U, X, V, and Y gate signals to the control terminals (gates in this embodiment) of the switching elements U, X, V, and Y, respectively. A block diagram of the pulse output unit 30 is shown in FIG. 4. The pulse output unit 30 includes a buffer unit 31 and an insulating unit 32.

[0045] The buffer unit 31 amplifies the signal strength (voltage value) of the U, X, V, and Y gate signals. The buffer unit 31 includes N first buffer units 31u-X (X=1, 2, . . ., N) corresponding to the U gate signal, N second buffer units 31x-X (X=1, 2, . . ., N) corresponding to the X gate signal, N third buffer units 31v-X (X=1, 2, . . ., N) corresponding to the V gate signal, and N fourth buffer units 31y-X (X=1, 2, . . ., N) corresponding to the Y gate signal. The first buffer unit 31u-X, the second buffer unit 31x-X, the third buffer unit 31v-X, and the fourth buffer unit 31y-X have the same configuration, and in this embodiment, are circuits including open-collector transistors.

[0046] The insulating unit 32 outputs the U, X, V, and Y gate signals input from the buffer unit 31 to the gates of the switching elements U, X, V, and Y while isolating the input and output. The insulating unit 32 includes N first insulating units 32u-X (X=1, 2, . . ., N) corresponding to the U gate signal, N second insulating units 32x-X (X=1, 2, . . ., N) corresponding to the X gate signal, N third insulating units 32v-X (X=1, 2, . . ., N) corresponding to the V gate signal, and N fourth insulating units 32y-X (X=1, 2, . . ., N) corresponding to the Y gate signal. The first insulating units 32u-X, the second insulating units 32x-X, the third insulating units 32v-X, and the fourth insulating units 32y-X have the same configuration, and are photocouplers or insulating transformers in this embodiment.

[0047] The parameter correction unit 40 performs a parameter correction process to increase or decrease the values ​​of the setting parameters (correction coefficients Kx-1 and Kx-2). Fig. 5 shows a block diagram of the parameter correction unit 40. The parameter correction unit 40 includes an ideal value setting unit 41, a conversion unit 42, a filter unit 43, a comparison unit 44, a correction processing unit 45, and a correction setting unit 46.

[0048] The ideal value setting unit 41 sets an ideal current value according to a diversion target value of the inverter current. The diversion target value is a value obtained by dividing the target value of the output current by N (the number of inverter circuits 2-X). Based on a current setting signal related to the current setting value Iref input from the pulse adjustment unit 20, the ideal value setting unit 41 calculates an ideal current value Iref / N by dividing the current setting value Iref by N (the number of inverter circuits 2-X), and outputs a signal related to the ideal current value Iref / N to the comparison unit 44.

[0049] The conversion unit 42 includes N ADC units 42-X (X=1, 2, . . . , N). The ADC units 42-X perform a process of converting an analog signal into a digital signal (ADC process). Specifically, the ADC units 42-X convert the first measurement signal (analog signal) of the first measurement means 3-X into a digital signal and output the digital signal to the filter unit 43.

[0050] The filter unit 43 includes N averaging processing units 43-X (X=1, 2, . . . , N). The averaging processing units 43-X perform moving average processing on the signal value of the first measurement signal (digital signal) input from the conversion unit 42, and output the signal value BX (X=1, 2, . . . , N) of the first measurement signal after the moving average processing to the comparison unit 44. Note that the filter unit 43 may be omitted depending on the conversion accuracy of the conversion unit 42.

[0051] The comparison unit 44 includes N signal comparison units 44-X (X=1, 2, . . . , N). The signal comparison unit 44-X calculates a difference IxX (X=1, 2, . . . , N) by subtracting the ideal current value Iref / N from the signal value BX of the first measurement signal, and outputs a signal related to the difference IxX to the correction processing unit 45.

[0052] The correction processing unit 45 performs a correction determination process, a circuit identification process, and a parameter correction process (parameter correction process in the automatic correction mode). The correction processing unit 45 is configured to be able to communicate with an external device (e.g., a computer), and performs a parameter correction process (parameter correction process in the manual correction mode) by receiving an execution command for the parameter correction process from the external device.

[0053] During the correction determination process, the correction processing unit 45 determines whether the difference IxX is within a threshold range between a preset upper threshold and a preset lower threshold. If the difference IxX is within the threshold range, the correction processing unit 45 does not perform the circuit identification process and the parameter correction process. On the other hand, if the difference IxX is outside the threshold range, the correction processing unit 45 performs the circuit identification process and the parameter correction process. The upper threshold and the lower threshold can be set to any value.

[0054] The correction processing unit 45 during the circuit identification process identifies the inverter circuit 2-X with the largest absolute value of the difference IxX among the inverter circuits 2-X with the difference IxX outside the threshold range, and also identifies whether the difference IxX is positive or negative. If there are multiple inverter circuits 2-X with the largest absolute value of the difference IxX, the correction processing unit 45 selects the one with the smallest circuit number. In this embodiment, the inverter circuit 2-1 has the smallest circuit number, and the inverter circuit 2-N has the largest circuit number (i.e., the closer X of the inverter circuit 2-X approaches N, the larger the circuit number). For example, if the inverter circuits 2-2 and 2-3 have the largest absolute value of the difference IxX, the correction processing unit 45 selects the inverter circuit 2-2 with the smallest circuit number.

[0055] The correction processing unit 45 performs a parameter correction process on the inverter circuit 2-X selected in the circuit identification process. The parameter correction process will be described in detail later, but during the parameter correction process, the correction processing unit 45 increases the values ​​of the setting parameters (correction coefficients Kx-1 and Kx-2) by a predetermined value (+1 in this embodiment) or decreases them by a predetermined value (-1 in this embodiment).

[0056] The correction setting unit 46 includes a mode setting unit 47 and a cycle setting unit 48. The mode setting unit 47 sets a first mode that permits the parameter correction process and a second mode that prohibits the parameter correction process. The mode setting unit 47 outputs, for example, a mode signal that goes to high level when the first mode is set and goes to low level when the second mode is set to the correction processing unit 45. The cycle setting unit 48 sets the execution timing of the parameter correction process. The cycle setting unit 48 outputs, for example, a correction timing signal that goes to high level according to the set cycle (or timing) to the correction processing unit 45.

[0057] The correction processing unit 45 performs a correction determination process, a circuit specification process, and a parameter correction process when the mode signal is at a high level and the correction timing signal is at a high level. In this embodiment, when the mode signal is at a high level and the correction timing signal is at a high level, the correction processing unit 45 controls the ADC unit 42-X so that the ADC unit 42-X captures the first measurement signal of the first measuring means 3-X.

[0058] 6 shows various signals of the control unit 5 and the output voltage of the inverter circuit 2-X when the pulse adjustment process is not performed (when the pulse increase / decrease width Y in the pulse adjustment process is 0). Note that the dead time is omitted in FIG.

[0059] 6, the triangular wave signal is a carrier signal output from oscillator 13. The positive deviation signal is a deviation signal output from calculator 12 and input to comparator 15 without passing through inverter 14. On the other hand, the negative deviation signal is a deviation signal output from calculator 12 and input to comparator 15 via inverter 14.

[0060] In the comparison unit 15, the comparator 15A compares the positive deviation signal input to the non-inverting input terminal with the triangular wave signal input to the inverting input terminal, and generates a first PWM signal that is at a high level when the positive deviation signal is greater than the triangular wave signal and at a low level when the positive deviation signal is equal to or less than the triangular wave signal. Meanwhile, the comparator 15B compares the triangular wave signal input to the non-inverting input terminal with the negative deviation signal input to the inverting input terminal, and generates a second PWM signal that is at a high level when the triangular wave signal is greater than the negative deviation signal and at a low level when the triangular wave signal is equal to or less than the negative deviation signal.

[0061] The first output unit MX-1 performs a dead time generation process and a gate signal generation process on the first PWM signal, and generates the first PWM signal as an X gate signal and an inverted signal of the first PWM signal as a U gate signal. That is, the X gate signal and the U gate signal have a phase difference of 180° excluding the dead time. Similarly, the second output unit MX-2 performs a dead time generation process and a gate signal generation process on the second PWM signal, and generates the second PWM signal as a Y gate signal and an inverted signal of the second PWM signal as a V gate signal. That is, the Y gate signal and the V gate signal have a phase difference of 180° excluding the dead time. By inputting such X, U, V, and Y gate signals to the switching elements X, U, V, and Y, the inverter circuit 2-X outputs the output voltage shown in FIG. 6.

[0062] Fig. 7 shows various signals of the control unit 5 and the output voltage of the inverter circuit 2-X when performing pulse adjustment processing. Fig. 7(A) shows pulse adjustment processing for increasing the pulse width, and Fig. 7(B) shows pulse adjustment processing for decreasing the pulse width. In Figs. 7(A) and (B), the triangular wave signal, the positive deviation signal, and the negative deviation signal are the same as in Fig. 6. In Fig. 7 as well, the description of the dead time is omitted.

[0063] The first adjustment unit GX-1 determines Y based on the formula Y=KA×IrefP, where Y is the increase / decrease width of the pulse width of the first PWM signal, IrefP is the current current setting value, and KA is the correction coefficient, and performs pulse adjustment processing. The first adjustment unit GX-1 increases the pulse width when KA is positive, and decreases the pulse width when KA is negative. The correction coefficient KA is the correction coefficient Kx-1 stored in the first storage unit KX-1.

[0064] At the timing of performing the pulse adjustment process, the first adjustment unit GX-1 refers to the first storage unit KX-1 to obtain the correction coefficient KA (=Kx-1), and also refers to the current setting value IrefP to the current setting unit 21 to determine the increase / decrease width Y based on the above formula. If Y is positive, the first adjustment unit GX-1 increases the pulse width of the first PWM signal by Y before outputting it (FIG. 7(A)). If Y is negative, the first adjustment unit GX-1 decreases the pulse width of the first PWM signal by Y before outputting it (FIG. 7(B)).

[0065] The second adjustment unit GX-2 determines Y based on the formula Y=KA×IrefP, where Y is the increase / decrease width of the pulse width of the second PWM signal, IrefP is the current current setting value, and KA is the correction coefficient, and performs pulse adjustment processing. The second adjustment unit GX-2 increases the pulse width when KA is positive, and decreases the pulse width when KA is negative. The correction coefficient KA is the correction coefficient Kx-2 stored in the second storage unit KX-2.

[0066] At the timing of performing the pulse adjustment process, the second adjustment unit GX-2 refers to the second storage unit KX-2 to obtain the correction coefficient KA (=Kx-2), and also refers to the current setting value IrefP to the current setting unit 21 to determine the increase / decrease width Y based on the above formula. If Y is positive, the second adjustment unit GX-2 increases the pulse width of the second PWM signal by Y before outputting it (FIG. 7(A)). If Y is negative, the second adjustment unit GX-2 decreases the pulse width of the second PWM signal by Y before outputting it (FIG. 7(B)).

[0067] As shown in FIG. 7(A), when the pulse widths of the first PWM signal and the second PWM signal are increased by Y through the pulse adjustment process, the pulse width of the output voltage of the inverter circuit 2-X also increases by Y. Accordingly, the inverter current of the inverter circuit 2-X also increases. On the other hand, as shown in FIG. 7(B), when the pulse widths of the first PWM signal and the second PWM signal are decreased by Y through the pulse adjustment process, the pulse width of the output voltage of the inverter circuit 2-X also decreases by Y. Accordingly, the inverter current of the inverter circuit 2-X also decreases.

[0068] In this way, by increasing or decreasing the pulse width of the first PWM signal and the second PWM signal by Y through the pulse adjustment process, the pulse width of the output voltage of the inverter circuit 2-X can be increased or decreased by Y. As a result, the adjustment unit 23 can adjust the shunt balance of the inverter current. In addition, in this embodiment, Y is determined based on the calculation formula Y=KA×IrefP, so that Y is small when the output current is small and Y is large when the output current is large.

[0069] Here, the minimum unit of the increase / decrease width Y is one period of the clock signal of the pulse adjustment unit 20. In this embodiment, since the frequency of the clock signal is 100 [MHz], the minimum value of the increase / decrease width Y is 10 [ns]. That is, when the correction coefficient KA=1 and the current current setting value IrefP is set according to the rated current value of the output current, the increase / decrease width Y is 10 [ns].

[0070] For example, when the correction coefficient KA=10 and the target value of the output current increases from 100 [A] to the rated current value of 1000 [A], the current current setting value IrefP also increases according to the target value. When the target value is 100 [A], the increase / decrease width Y is Y = 10 [ns]. When the target value is 200 A, the increase / decrease width Y is 20 ns. When the target value is 500 [A], the increase / decrease width Y is Y=50 [ns]. When the target value is 1000 [A], the increase / decrease width Y is Y=100 [ns]. Since the minimum value of the increase / decrease width Y is 10 [ns], under the condition of 100 [A]≦target value<200, the increase / decrease width Y is Y=10 [ns].

[0071] Next, the parameter correction process performed by the parameter correction unit 40 will be described. The parameter correction process includes a parameter correction process in a manual correction mode and a parameter correction process in an automatic correction mode. The manual correction mode and the automatic correction mode can be set, for example, by the parameter correction unit 40. The parameter correction process setting of the correction setting unit 46 is the automatic correction mode setting. The manual correction mode and the automatic correction mode differ in the timing and amount of correction at which the parameter correction process is performed, but the other process contents are common to both modes.

[0072] Fig. 8 shows the parameter correction process in the manual correction mode. In the example of Fig. 8, the inverter circuit 2-X outputs a triangular wave pulse current (inverter current) under the control of the control unit 5. In Fig. 8, (A) shows the first shot pulse current, (B) shows the second shot pulse current, and (C) shows the third shot pulse current.

[0073] The "current division target value" in the figure is the value obtained by dividing the target value of the output current by N (the number of inverter circuits 2-X). The "(3-1) measured value" is the current value of the pulse current of the inverter circuit 2-1 measured by the first measuring means 3-1, and the "(3-2) measured value" is the current value of the pulse current of the inverter circuit 2-2 measured by the first measuring means 3-2. The same applies to Figures 9 and 10 described below. Note that, for simplicity of explanation, the following will be described using the inverter circuits 2-1 and 2-2 as examples, but the same applies to the inverter circuits 2-3 and onwards.

[0074] In the manual correction mode, the control unit 5 causes the inverter circuit 2-X to output a first shot of pulse current, and the first measurement unit 3-X measures the first shot of pulse current. The user, for example, uses an external device to compare the measured pulse current with a current division target value, and identifies the inverter circuit 2-X that outputs a pulse current whose difference between the two is outside a predetermined range (i.e., the inverter circuit 2-X is to be subject to parameter correction processing). In FIG. 8(A), the inverter circuit 2-1 and the inverter circuit 2-2 are identified as the inverter circuits 2-X to be subject to parameter correction processing.

[0075] Since the pulse current of the inverter circuit 2-1 is deviated to the positive side with respect to the current division target value, the user inputs a negative value (any value) as the correction coefficient KA using, for example, an external device. The input correction coefficient KA is transmitted to the correction processing unit 45, which performs parameter correction processing to change the correction coefficients K1-1 and K1-2 stored in the first storage unit K1-1 and the second storage unit K1-2 to the input correction coefficient KA.

[0076] Since the pulse current of the inverter circuit 2-2 is deviated to the negative side with respect to the current division target value, the user inputs a positive value (any value) as the correction coefficient KA using, for example, an external device. The input correction coefficient KA is transmitted to the correction processing unit 45, which performs parameter correction processing to change the correction coefficients K2-1 and K2-2 stored in the first storage unit K2-1 and the second storage unit K2-2 to the input correction coefficient KA.

[0077] Next, the control unit 5 causes the inverter circuit 2-X to output a second shot pulse current, and the first measurement means 3-X measures the second shot pulse current. The second shot pulse current is subjected to pulse adjustment processing based on the changed correction coefficient KA. As in the first shot, the user specifies the inverter circuit 2-X for which parameter correction processing is to be performed. In FIG. 8(B), the inverter circuit 2-1 and the inverter circuit 2-2 are specified as the inverter circuit 2-X for which parameter correction processing is to be performed. As in the first shot, the correction coefficient KA input to the external device is transmitted to the correction processing unit 45, and the correction processing unit 45 performs the parameter correction processing.

[0078] Next, the control unit 5 causes the inverter circuit 2-X to output a third shot of pulse current, and the first measurement unit 3-X measures the third shot of pulse current. As shown in Fig. 8(C), when the pulse current is almost equal to the current division target value, the parameter correction process in the manual correction mode is terminated.

[0079] The parameter correction process in the manual correction mode is performed using an external device as described above. Therefore, when the parameter correction unit 40 performs only the parameter correction process in the manual correction mode and does not perform the parameter correction process in the automatic correction mode, the parameter correction unit 40 can be composed of only the correction processing unit 45.

[0080] Next, a description will be given of the parameter correction process in the automatic correction mode performed by the parameter correction unit 40. The flow of the parameter correction process in the automatic correction mode is as follows.

[0081] In the automatic correction mode, the ideal value setting unit 41 outputs the ideal current value Iref / N according to the diversion target value of the inverter current. The conversion unit 42 converts the first measurement signal of the first measurement means 3-X into a digital signal by ADC processing, and the filter unit 43 performs moving average processing on the signal value of the first measurement signal (digital signal) and outputs a signal value BX. The comparison unit 44 calculates a difference IxX by subtracting the ideal current value Iref / N from the signal value BX, and outputs a signal related to the difference IxX to the correction processing unit 45. The correction processing unit 45 performs a correction judgment process, a circuit specification process, and a parameter correction process. In the parameter correction process, the correction processing unit 45 increases the values ​​of the setting parameters (correction coefficients Kx-1 and Kx-2) by +1 or decreases them by -1. This series of processes is performed at the execution timing set by the cycle setting unit 48 when the mode signal of the mode setting unit 47 is at a high level (first mode).

[0082] In this embodiment, the set time of the first mode is a fixed time (arbitrary), so the parameter correction process in the automatic correction mode is terminated once the fixed time has elapsed. However, if the difference IxX is outside the threshold range at the time of termination, when the mode signal of the mode setting unit 47 becomes high level (first mode) after the specified time has elapsed, the parameter correction process in the automatic correction mode is performed again at the execution timing set by the cycle setting unit 48.

[0083] 9, a parameter correction process in the automatic correction mode when the inverter current is a triangular pulse current will be described. Note that the same process is performed even when the inverter current is a pattern current (for example, a current with a stepped waveform).

[0084] At time t1, the inverter circuit 2-X starts outputting a pulse current, the mode signal of the mode setting unit 47 goes to high level (first mode), and at time t2, the correction timing signal of the cycle setting unit 48 goes to high level, causing the conversion unit 42 to take in the first measurement signal of the first measurement means 3-X. At the same timing, the ideal value setting unit 41 calculates and outputs the ideal current value Iref / N based on the current setting value Iref. When the current setting value Iref corresponds to the maximum value of the pulse current (the peak value of the triangular wave pulse current), the ideal value setting unit 41 calculates the ideal current value Iref / N at time t2 from the slope of the pulse current, etc.

[0085] The comparison unit 44 calculates a difference IxX by subtracting the ideal current value Iref / N from the signal value BX, and outputs a signal related to the difference IxX to the correction processing unit 45. The correction processing unit 45 performs a correction determination process, a circuit specification process, and a parameter correction process.

[0086] In the correction determination process, the correction processor 45 performs a first determination as to whether the signal value of the first measurement signal is outside a set range including the diversion target value by determining whether the difference IxX is included in a threshold range between a preset upper threshold and a preset lower threshold. In this embodiment, if the diversion target value is Id [A], the upper threshold corresponds to the upper limit of the set range (Id+Ik) [A], and the lower threshold corresponds to the lower limit of the set range (Id-Ik) [A].

[0087] If all the differences IxX are within the threshold range, the correction processing unit 45 does not perform the circuit identification process and the parameter correction process. On the other hand, if at least one of the differences IxX is outside the threshold range, the correction processing unit 45 performs the circuit identification process and the parameter correction process.

[0088] In the circuit identification process, the correction processing unit 45 identifies the inverter circuit 2-X having the largest absolute value of the difference IxX among the inverter circuits 2-X having the difference IxX outside the threshold range, and also identifies whether the difference IxX is positive or negative.

[0089] In the parameter correction process, the correction processor 45 performs the parameter correction process on the inverter circuit 2-X selected in the circuit identification process. Specifically, when the difference IxX is positive (in the case of the measured value (3-1) in FIG. 9), the correction processor 45 decreases the values ​​of the correction coefficient Kx-1 and the correction coefficient Kx-2 (the correction coefficient K1-1 and the correction coefficient K1-2 in FIG. 9) by -1. On the other hand, when the difference IxX is negative (in the case of the measured value (3-2) in FIG. 9), the correction processor 45 increases the values ​​of the correction coefficient Kx-1 and the correction coefficient Kx-2 (the correction coefficient K2-1 and the correction coefficient K2-2 in FIG. 9) by +1. As described above, the parameter correction process is performed on only one circuit at a time, so that either the inverter circuit 2-1 or the inverter circuit 2-2 is the target of the parameter correction process.

[0090] When the correction coefficients Kx-1 and Kx-2 are changed by the parameter correction process, the adjustment unit 23 performs the pulse adjustment process based on the changed correction coefficients Kx-1 and Kx-2 from the next pulse current output.

[0091] At time t3, the inverter circuit 2-X starts to output a second pulse current, and at time t4, when the correction timing signal goes high, the parameter correction unit 40 performs the above series of processes. That is, the ideal value setting unit 41, the conversion unit 42, the filter unit 43, and the comparison unit 44 perform their respective processes, and the correction processing unit 45 performs the second correction determination process, the circuit identification process, and the parameter correction process.

[0092] Similarly, at time t5, the inverter circuit 2-X starts outputting a third pulse current, and at time t6, when the correction timing signal becomes high level, the parameter correction unit 40 performs the above series of processes. That is, the ideal value setting unit 41, the conversion unit 42, the filter unit 43, and the comparison unit 44 perform their respective processes, and the correction processing unit 45 performs the third correction judgment process, the circuit identification process, and the parameter correction process. The time from time t1 to t2, the time from time t3 to t4, and the time from time t5 to t6 are the same time.

[0093] At time t7, when the mode signal of the mode setting unit 47 becomes low level (second mode), the parameter correction process in the automatic correction mode ends. In this manner, in this embodiment, the pulse current is output multiple times, and the correction coefficients Kx-1 and Kx-2 are increased or decreased by ±1 for each pulse adjustment process, so that the shunt balance can be gradually adjusted and optimized.

[0094] Next, the parameter correction process in the automatic correction mode when the inverter current is a direct current will be described with reference to FIG.

[0095] At time t1, the inverter circuit 2-X starts outputting a pulse current, the mode signal of the mode setting unit 47 goes to high level (first mode), and thereafter the current division target value becomes the rated current value of the inverter circuit 2-X.

[0096] At time t2, when the correction timing signal becomes high level, the parameter correction unit 40 performs a series of processes similar to those in Fig. 9. That is, the ideal value setting unit 41, the conversion unit 42, the filter unit 43, and the comparison unit 44 perform their respective processes. After performing the correction determination process, the correction processing unit 45 increases or decreases the correction coefficients Kx-1 and Kx-2 by ±1 through pulse adjustment processing for one inverter circuit 2-X identified in the circuit identification process. From the point in time when the correction coefficients Kx-1 and Kx-2 are changed, the adjustment unit 23 performs the pulse adjustment processing based on the changed correction coefficients Kx-1 and Kx-2.

[0097] The correction timing signal goes high at a preset cycle (for example, 1 s). In this embodiment, the time between time t2 and time t3 is 1 s. At time t3, the ideal value setting unit 41, the conversion unit 42, the filter unit 43, and the comparison unit 44 perform their respective processes, and the correction processing unit 45 performs the second correction determination process, the circuit identification process, and the parameter correction process. At time t4, when the mode signal goes low (second mode), the parameter correction process in the automatic correction mode ends.

[0098] Thus, in this embodiment, even if the inverter current is a DC current, the current division balance can be gradually adjusted and optimized by increasing or decreasing the correction coefficient Kx-1 and the correction coefficient Kx-2 by ±1 for each pulse adjustment process.

[0099] Ultimately, in the inverter device 1, the pulse generating unit 10 that performs analog processing generates a PWM signal, and the pulse adjusting unit 20 that performs digital processing performs pulse adjustment processing of the PWM signal generated by the pulse generating unit 10. Therefore, in the inverter device 1, it is not necessary to consider the delay due to the conversion time of ADC processing, the conversion period, and the conversion accuracy when generating a PWM signal. As a result, in the inverter device 1, it is possible to avoid complicating the control.

[0100] In the inverter device 1, the parameter correction unit 40 performs a parameter correction process to increase or decrease the values ​​of the setting parameters (correction coefficients Kx-1 and Kx-2) of the pulse adjustment process. Therefore, in the inverter device 1, even if there is a change in the inverter circuit 2-X (e.g., deterioration over time or replacement of a switching element) or a change in the load, the shunt balance can be suitably adjusted.

[0101] In the inverter device 1, ADC processing is performed in the parameter correction process, but the ADC processing in the parameter correction process does not require conversion accuracy as high as the ADC processing performed in conventional inverter devices when generating a PWM signal. Furthermore, in the inverter device 1, the parameter correction process is not performed all the time, but is performed only when the mode signal is at a high level (first mode) and the correction timing signal becomes a high level. Therefore, in the inverter device 1, it is possible to suppress the control from becoming complicated to a certain extent.

[0102] [Variations] Although the embodiment of the inverter device according to the present invention has been described above, the present invention is not limited to the above embodiment.

[0103] The inverter device of the present invention is an inverter device that includes a plurality of inverter circuits connected in parallel, each of the plurality of inverter circuits including at least one switching element, a measurement unit that measures each inverter current output from each inverter circuit, and a control unit that performs PWM control on each inverter circuit, and supplies an output current that is a combination of each inverter current to a load, wherein the control unit includes an analog circuit unit that performs analog signal processing and a digital circuit unit that performs digital signal processing, the analog circuit unit generates a PWM signal for performing PWM control, the digital circuit unit takes in the PWM signal from the analog circuit unit and performs pulse adjustment processing to increase or decrease the pulse width of the PWM signal according to pre-stored setting parameters, and a parameter correction unit that takes in a measurement signal of each inverter current from the measurement unit, and performs parameter correction processing to increase or decrease the value of the setting parameter if the measurement signal is outside a pre-set setting range, so long as the configuration can be changed as appropriate.

[0104] For example, in the above embodiment, in the case of parameter correction processing in the automatic correction mode, the correction coefficients Kx-1 and Kx-2 are increased or decreased only for one inverter circuit 2-X per parameter correction processing, but the correction coefficients Kx-1 and Kx-2 may be increased or decreased for two or more inverter circuits 2-X per parameter correction processing.

[0105] In the above embodiment, in the case of the parameter correction process in the automatic correction mode, the setting parameters (correction coefficients Kx-1 and Kx-2) are increased or decreased by ±1 (minimum value) for each parameter correction process, but the increase or decrease width of the setting parameters can be changed as appropriate. Also, the setting parameters do not necessarily need to be integers, and may be real numbers (for example, integers and decimals).

[0106] The multiple inverter circuits in the present invention refer to two or more inverter circuits. [Explanation of symbols]

[0107] 1. Inverter device 2 Inverter section 3 1st measurement section 4 Second measuring section 5. Control section 10 Pulse Generation Unit 11 DAC section 12 Arithmetic section 13 Oscillator 14 Reversal section 15 Comparison section 20 Pulse adjustment section 21 Current setting section 22 Input Processing Section 23 Adjustment part 24 Memory section 25 Output Processing Section 30 Pulse output section 31 Buffer section 32 Insulation 40 Parameter correction section 41 Ideal value setting section 42 Conversion section 43 Filter section 44 Comparison section 45 Correction processing section 46 Correction setting section 47 Mode setting section 48 Cycle setting section

Claims

1. an inverter section including a plurality of inverter circuits connected in parallel, each of the plurality of inverter circuits including at least one switching element; A measurement unit for measuring each inverter current output from each of the inverter circuits; A control unit that performs PWM control on each of the inverter circuits; An inverter device that supplies an output current obtained by combining the inverter currents to a load, The control unit includes an analog circuit unit that performs analog signal processing and a digital circuit unit that performs digital signal processing, The analog circuit unit generates a PWM signal for performing the PWM control, The digital circuit unit includes: a pulse adjustment unit that receives the PWM signal from the analog circuit unit and performs a pulse adjustment process to increase or decrease a pulse width of the PWM signal in accordance with a pre-stored setting parameter; a parameter correction unit that receives a measurement signal of each of the inverter currents from the measurement unit, and performs a parameter correction process to increase or decrease the value of the setting parameter when the measurement signal is outside a preset range. An inverter device characterized in that

2. The pulse adjustment unit is The pulse adjustment process is performed based on the increase / decrease width Y determined based on a calculation formula of Y=KA×IrefP, where Y is the increase / decrease width of the pulse width during the pulse adjustment process, IrefP is the current current setting value set according to the target value of the output current, and KA is the correction coefficient which is the setting parameter. The parameter correction unit The correction coefficient KA is increased or decreased during the parameter correction process.

2. The inverter device according to claim 1 .

3. The parameter correction unit an ideal value setting unit that sets a current ideal value according to the diversion target value of each of the inverter currents; A conversion unit for converting the measurement signal into a digital signal; a correction processing unit that performs a first determination as to whether or not the measurement signal is outside the set range based on the ideal current value and the signal value of the measurement signal that has passed through the conversion unit, and performs the parameter correction processing in accordance with a result of the first determination.

2. The inverter device according to claim 1 .

4. The parameter correction unit a mode setting unit that sets a first mode in which the parameter correction process is permitted and a second mode in which the parameter correction process is prohibited; A period setting unit that sets the execution timing of the parameter correction process.

4. The inverter device according to claim 3.

5. The parameter correction unit The parameter correction process is performed only on the inverter circuit in which the measurement signal is the furthest from the set range among the inverter circuits.

2. The inverter device according to claim 1 .

6. The parameter correction unit The value of the setting parameter is increased or decreased by a minimum value for each parameter correction process.

2. The inverter device according to claim 1 .

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