Semiconductor device

Abstract

To provide a semiconductor device that is safeguarded against a load short circuit or the like and has a configuration capable of applying negative potential to a gate electrode.SOLUTION: A semiconductor device 1 comprises: an insulated gate 30 with a gate electrode 32, the gate electrode being a semiconductor containing n-type impurity; and an embedded semiconductor layer 50 provided in a contact hole 40a which penetrates through an interlayer insulation film 40, the semiconductor layer 50 including a first embedded semiconductor layer 52 containing p-type impurity and a second embedded semiconductor layer 54 containing the n-type impurity, the first embedded semiconductor layer being in contact with the gate electrode of the insulated gate and being separated from a source electrode 24 by the second embedded semiconductor layer, and the second embedded semiconductor layer being in contact with the source electrode and being separated from the gate electrode of the insulated gate by the first embedded semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] When an overcurrent flows through a semiconductor device due to a load short circuit or the like, the temperature of the semiconductor device rises and the semiconductor device may be damaged. In order to prevent such a situation, a technology is needed to forcibly turn off the semiconductor device when an overcurrent flows through the semiconductor device.

[0003] Patent Document 1 discloses a technique for connecting a pn diode between a gate and a source. The pn diode is formed by forming a contact hole in an interlayer insulating film between a gate electrode and a source electrode, and burying a p-type semiconductor layer in the contact hole. The gate electrode is made of polysilicon containing n-type impurities. Therefore, the gate electrode functions as the cathode of the pn diode, and the p-type semiconductor layer functions as the anode of the pn diode. In the semiconductor device of Patent Document 1, when an overcurrent flows and the temperature rises, a leak current flows in the pn diode. This causes the gate potential to drop, and the semiconductor device is forcibly turned off. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2001-267570 A Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in order to properly turn off a semiconductor device during switching control, it may be desirable to apply a negative potential to the gate electrode. In the semiconductor device of Patent Document 1, when a negative potential is applied to the gate electrode, the pn diode is forward biased and a current may flow from the source electrode to the gate electrode. Such a current may cause the semiconductor device to malfunction. The present specification aims to provide a semiconductor device that is adapted to counter load short circuits and the like and has a configuration that allows a negative potential to be applied to the gate electrode. [Means for solving the problem]

[0006] One embodiment of a semiconductor device (1) disclosed in the present specification includes an insulated gate (30) having a gate electrode (32), the gate electrode being a semiconductor containing a first conductivity type impurity; a pair of main electrodes (22, 24) including a first main electrode (22) and a second main electrode (24), where a current flows from the first main electrode to the second main electrode when an on-voltage is applied to the insulated gate; an interlayer insulating film (40) provided between the gate electrode and the second main electrode of the insulated gate; and a dielectric film (42) penetrating the interlayer insulating film. The semiconductor device may further include a buried semiconductor layer (50) provided in the contact hole (40a) formed in the insulating gate, the buried semiconductor layer (50) including a first buried semiconductor layer (52) containing a second conductive type impurity and a second buried semiconductor layer (54) containing a first conductive type impurity, the first buried semiconductor layer being in contact with the gate electrode of the insulating gate and separated from the second main electrode by the second buried semiconductor layer, and the second buried semiconductor layer being in contact with the second main electrode and separated from the gate electrode of the insulating gate by the first buried semiconductor layer. Here, the type of the semiconductor device is not particularly limited, and may be, for example, a MOSFET or an IGBT. When the semiconductor device is a MOSFET, the first main electrode is a drain electrode, and the second main electrode is a source electrode. When the semiconductor device is an IGBT, the first main electrode is a collector electrode, and the second main electrode is an emitter electrode. The semiconductor device may be a horizontal device in which both of the pair of main electrodes are provided on one of a pair of main surfaces of a semiconductor substrate, or a vertical device in which each of the pair of main electrodes is provided on a separate main surface of the semiconductor substrate. The shape of the insulated gate is not particularly limited, and may be, for example, a planar type or a trench type.

[0007] In the above semiconductor device, a bipolar transistor is formed by a gate electrode of a first conductivity type, a first buried semiconductor layer of a second conductivity type, and a second buried semiconductor layer of the first conductivity type. When an overcurrent flows through the semiconductor device due to a load short circuit or the like and the temperature of the semiconductor device rises, the bipolar transistor operates. As a result, the potential of the gate electrode drops and the semiconductor device is forcibly turned off. Furthermore, in the above semiconductor device, the first buried semiconductor layer is disposed between the gate electrode and the second buried semiconductor layer. As a result, when a negative potential is applied to the gate electrode, either one of the pn junctions between the first buried semiconductor layer and the gate electrode or between the first buried semiconductor layer and the second buried semiconductor layer is reverse biased, and a depletion layer is formed in the pn junction. Therefore, even if a negative potential is applied to the gate electrode, a current is suppressed from flowing from the second main electrode to the gate electrode. In this way, the above semiconductor device has a configuration that is adapted to counter load short circuits and the like and is capable of applying a negative potential to the gate electrode. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a main portion of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 9]1A to 1C are schematic cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] FIG. 1 shows a unit cell of a semiconductor device 1. For the purpose of clarity of illustration, only one of the repeatedly arranged components is labeled with a reference symbol. The semiconductor device 1 is a type of semiconductor device called a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor substrate 10, a drain electrode 22 provided to cover the lower surface of the semiconductor substrate 10, a source electrode 24 provided to cover the upper surface of the semiconductor substrate 10, a trench gate 30 provided in the upper layer of the semiconductor substrate 10, and an interlayer insulating film 40 provided on the semiconductor substrate 10. The drain electrode 22 is an example of a first main electrode, and the source electrode 24 is an example of a second main electrode.

[0010] The material of the semiconductor substrate 10 is not particularly limited, but may be, for example, silicon, silicon carbide, gallium nitride, or gallium oxide. In this example, the material of the semiconductor substrate 10 is silicon carbide. The semiconductor substrate 10 is a n + A drain region 11 of n - A p-type drift region 12, a p-type body region 13, and an n + A source region 14 of p + The semiconductor device has a p-type contact region 15 and a p-type electric field shield region 16 .

[0011] The drain region 11 is disposed in the lower layer of the semiconductor substrate 10, and is disposed at a position exposed on the lower surface of the semiconductor substrate 10. The drain region 11 contains a high concentration of n-type impurities, and is in ohmic contact with a drain electrode 22 that covers the lower surface of the semiconductor substrate 10.

[0012] The drift region 12 is provided on the drain region 11 and separates the drain region 11 from the body region 13. The concentration of n-type impurities contained in the drift region 12 is lower than the concentration of n-type impurities contained in the drain region 11.

[0013] The body region 13 is provided on the drift region 12 and is arranged in the upper layer portion of the semiconductor substrate 10. The body region 13 separates the drift region 12 and the source region 14.

[0014] The source region 14 is provided on the body region 13, and is disposed at a position exposed on the upper surface of the semiconductor substrate 10. The source region 14 is disposed at a position facing a side surface of the trench gate 30. In this example, the source region 14 contacts the side surface of the trench gate 30. The source region 14 contains a high concentration of n-type impurities, and is in ohmic contact with a source electrode 24 that covers the upper surface of the semiconductor substrate 10.

[0015] The contact region 15 is provided on the body region 13, and is disposed at a position exposed on the upper surface of the semiconductor substrate 10. The concentration of p-type impurities contained in the contact region 15 is higher than the concentration of p-type impurities contained in the body region 13. The contact region 15 contains a high concentration of p-type impurities, and is in ohmic contact with a source electrode 24 that covers the upper surface of the semiconductor substrate 10.

[0016] The electric field shield region 16 extends from the lower surface of the body region 13 toward the depth thereof. The electric field shield region 16 is formed deeper than the trench gate 30. In addition, the electric field shield region 16 is disposed away from the side surface of the trench gate 30. Therefore, a part of the drift region 12 is provided between the electric field shield region 16 and the side surface of the trench gate 30. The electric field shield region 16 is provided to alleviate electric field concentration at the bottom of the trench gate 30.

[0017] The trench gate 30 extends from the upper surface of the semiconductor substrate 10 toward the depth thereof, and has a gate electrode 32 and a gate insulating film 34. The trench gate 30 is provided so as to penetrate the source region 14 and the body region 13 and enter a part of the drift region 12. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34. The gate electrode 32 faces a part of the body region 13 (also called a channel region) located between the drift region 12 and the source region 14 via the gate insulating film 34. The gate electrode 32 is made of, but is not limited to, polysilicon containing n-type impurities, for example.

[0018] The semiconductor device 1 further includes a buried semiconductor layer 50. The buried semiconductor layer 50 is provided above the trench gate 30 and buried in a contact hole 40a penetrating the interlayer insulating film 40, and includes a first buried semiconductor layer 52 and a second buried semiconductor layer 54.

[0019] The first buried semiconductor layer 52 is made of, for example, polysilicon containing p-type impurities, although it is not particularly limited thereto. The first buried semiconductor layer 52 is disposed below the contact hole 40a, with its lower surface in contact with the gate electrode 32 and its upper surface in contact with the second buried semiconductor layer 54. The first buried semiconductor layer 52 is separated from the source electrode 24 by the second buried semiconductor layer 54. That is, the first buried semiconductor layer 52 is not in contact with the source electrode 24.

[0020] The second buried semiconductor layer 54 is made of, for example, polysilicon containing n-type impurities, although it is not particularly limited thereto. The second buried semiconductor layer 54 is disposed above the contact hole 40a, with its lower surface in contact with the first buried semiconductor layer 52 and its upper surface in contact with the source electrode 24. The second buried semiconductor layer 54 is separated from the gate electrode 32 by the first buried semiconductor layer 52. That is, the second buried semiconductor layer 54 is not in contact with the gate electrode 32.

[0021] Next, the operation of the semiconductor device 1 will be described. When a voltage that makes the drain electrode 22 positive is applied between the drain electrode 22 and the source electrode 24, and a voltage that makes the gate electrode 32 positive is applied between the gate electrode 32 of the trench gate 30 and the source electrode 24, an inversion layer is formed in a portion of the body region 13 that faces the side surface of the trench gate 30. This allows electrons to flow from the source electrode 24 to the drain electrode 22 via the source region 14, the inversion layer, the drift region 12, and the drain region 11. This allows a current to flow between the drain electrode 22 and the source electrode 24 in the semiconductor device 1, and the semiconductor device 1 can be turned on.

[0022] When a voltage that makes the drain electrode 22 positive is applied between the drain electrode 22 and the source electrode 24, and a voltage that makes the gate electrode 32 negative is applied between the gate electrode 32 and the source electrode 24 of the trench gate 30, an inversion layer is not formed in the portion of the body region 13 that faces the side surface of the trench gate 30. As a result, no current flows between the drain electrode 22 and the source electrode 24, and the semiconductor device 1 can be turned off. In this way, the semiconductor device 1 can perform switching control of the current flowing between the drain electrode 22 and the source electrode 24 based on the voltage applied to the gate electrode 32.

[0023] In the semiconductor device 1, an npn bipolar transistor is formed by the n-type gate electrode 32, the p-type first buried semiconductor layer 52, and the n-type second buried semiconductor layer 54. This npn bipolar transistor is connected between the gate and source of the semiconductor device 1.

[0024] When the semiconductor device 1 is on, for example, if a load short circuit occurs, an overcurrent flows through the semiconductor device 1. When an overcurrent flows through the semiconductor device 1, the temperature of the semiconductor device 1 rises. When the temperature of the semiconductor device 1 rises, the npn bipolar transistor operates and a current flows from the gate electrode 32 to the source electrode 24. This reduces the potential of the gate electrode 32, forcing the semiconductor device 1 to turn off. In this way, the npn bipolar transistor can perform an operation to protect the semiconductor device 1 when, for example, a load short circuit occurs. In particular, the npn bipolar transistor can pass a large current by conductivity modulation, so that the potential of the gate electrode 32 can be sufficiently reduced to turn off the semiconductor device 1. For this reason, the semiconductor device 1 can have a high short circuit resistance.

[0025] Here, let us consider a comparative example in which only a p-type semiconductor layer is provided in the contact hole 40a of the interlayer insulating film 40 instead of the buried semiconductor layer 50. This configuration is an example in which a pn diode is connected between the gate and source, and is the configuration of the conventional example described in the background art. This pn diode can also perform a protection operation of lowering the gate potential by passing a current between the gate and source when an overcurrent flows through the semiconductor device. For example, when the source electrode is made of aluminum, the protection operation needs to be performed at an element temperature (for example, 400°C) lower than the melting point of aluminum (660°C). Although it depends on the area of ​​the pn diode in the element area, the current flowing through the pn diode at an element temperature of 400°C is small. For this reason, in the configuration of the comparative example, the gate potential does not drop below the threshold value, and there is a possibility that the semiconductor device cannot be turned off. On the other hand, in the semiconductor device 1 of this embodiment, an npn bipolar transistor is provided between the gate and source, and a large current can be passed by conductivity modulation, so that the gate potential can be sufficiently lowered.

[0026] The first buried semiconductor layer 52, which corresponds to the base of the npn bipolar transistor, has a width W when measured along the direction connecting the gate electrode 32 and the second buried semiconductor layer 54, i.e., along the thickness direction of the semiconductor substrate 10. The width W is calculated by multiplying the diffusion length L of the n-type impurity in the first buried semiconductor layer 52 by the following formula: n is smaller than the value obtained by dividing by the square root of 2. When this relationship is satisfied, the npn bipolar transistor can operate satisfactorily.

number

[0027] In the semiconductor device 1, during switching control, a voltage is applied between the gate electrode 32 and the source electrode 24 at the on timing so that the gate electrode 32 becomes positive, and a voltage is applied between the gate electrode 32 and the source electrode 24 at the off timing so that the gate electrode 32 becomes negative. During the on timing, the pn junction between the n-type gate electrode 32 and the p-type first buried semiconductor layer 52 becomes reverse biased, and a depletion layer is formed at the pn junction surface, so that a current is suppressed from flowing between the gate and the source. During the off timing, the pn junction between the p-type first buried semiconductor layer 52 and the n-type second buried semiconductor layer 54 becomes reverse biased, and a depletion layer is formed at the pn junction surface, so that a current is suppressed from flowing between the gate and the source. Thus, even if an npn bipolar transistor is connected between the gate and the source in the semiconductor device 1, a current is suppressed from flowing between the gate and the source during switching control, so that switching control is not hindered.

[0028] In the semiconductor device 1, the gate electrode 32 of the trench gate 30, the first buried semiconductor layer 52, and the second buried semiconductor layer 54 constituting the npn bipolar transistor are all formed of polysilicon. Instead of this example, the npn bipolar transistor may be formed of other semiconductor materials. The band gap of a semiconductor material through which a reverse current equivalent to that of polysilicon flows at 400°C is calculated to be 1.518 eV using a theoretical formula relating to the temperature dependence of the reverse current of a pn junction. Therefore, if an npn bipolar transistor is formed using a semiconductor material with a band gap of 1.6 eV or less, a current equivalent to that of an npn bipolar transistor formed using polysilicon flows at 400°C. Therefore, the npn bipolar transistor may be formed using silicon with a band gap of 1.12 eV.

[0029] Next, a process for manufacturing the buried semiconductor layer 50 in the manufacturing method of the semiconductor device 1 will be described. First, as shown in Fig. 2, after various semiconductor regions are formed in the semiconductor substrate 10, a trench 62 is formed, for example, by dry etching, from the upper surface of the semiconductor substrate 10, penetrating the source region 14 and the body region 13 to reach the drift region 12. Next, a silicon oxide film is formed on the upper surface of the semiconductor substrate 10 including the inner wall of the trench 62, for example, by thermal oxidation, to form the gate insulating film 34.

[0030] Next, as shown in FIG. 3, polysilicon containing n-type impurities is grown in the trenches 62 by, for example, epitaxial growth technology to form the gate electrodes 32.

[0031] Next, as shown in FIG. 4, for example, by using an epitaxial growth technique, a first buried semiconductor layer 52 of polysilicon containing p-type impurities and a second buried semiconductor layer 54 of polysilicon containing n-type impurities are grown in sequence on the upper surface of the semiconductor substrate 10 including the upper surface of the trench gate 30.

[0032] Next, as shown in FIG. 5, a portion of the first buried semiconductor layer 52 and the second buried semiconductor layer 54 is removed by, for example, a dry etching technique so that the first buried semiconductor layer 52 and the second buried semiconductor layer 54 in the portion in contact with the gate electrode 32 of the trench gate 30 remain.

[0033] Next, as shown in FIG. 6, the interlayer insulating film 40 is formed on the upper surface of the semiconductor substrate 10 so as to cover the first buried semiconductor layer 52 and the second buried semiconductor layer 54, for example, by using a deposition technique.

[0034] Next, as shown in FIG. 7, the interlayer insulating film 40 is polished by, for example, CMP (Chemical Mechanical Polishing) technology until the second buried semiconductor layer 54 is exposed, and the upper surface of the interlayer insulating film 40 is flattened.

[0035] Next, as shown in FIG. 8, a part of the interlayer insulating film 40 is removed by, for example, dry etching technology so that the source region 14 and the contact region 15 are exposed.

[0036] Next, as shown in FIG. 9, an aluminum film is formed on the semiconductor substrate 10 including the upper surface of the second buried semiconductor layer 54 exposed from the interlayer insulating film 40, for example, by using a deposition technique, to form the source electrode 24.

[0037] Finally, for example, an evaporation technique is used to form an aluminum film on the lower surface of the semiconductor substrate 10, and a drain electrode 22 is formed, thereby completing the semiconductor device 1.

[0038] Although specific examples of the present invention have been described above in detail, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful. [Explanation of symbols]

[0039] 1: semiconductor device, 10: semiconductor substrate, 11: drain region, 12: drift region, 13: body region, 14: source region, 15: contact region, 16: electric field shield region, 22: drain electrode, 24: source electrode, 30: trench gate, 32: gate electrode, 34: gate insulating film, 40: interlayer insulating film, 40a: contact hole, 50: buried semiconductor layer, 52: first buried semiconductor layer, 54: second buried semiconductor layer

Claims

1. A semiconductor device (1), an insulated gate (30) having a gate electrode (32), the gate electrode being a semiconductor containing a first conductivity type impurity; A pair of main electrodes (22, 24) including a first main electrode (22) and a second main electrode (24), in which a current flows from the first main electrode to the second main electrode when an on-voltage is applied to the insulated gate; an interlayer insulating film (40) provided between the gate electrode and the second main electrode of the insulated gate; a buried semiconductor layer (50) provided in a contact hole (40a) penetrating the interlayer insulating film, the buried semiconductor layer including a first buried semiconductor layer (52) containing a second conductive type impurity and a second buried semiconductor layer (54) containing a first conductive type impurity, the first buried semiconductor layer being in contact with the gate electrode of the insulated gate and separated from the second main electrode by the second buried semiconductor layer, and the second buried semiconductor layer being in contact with the second main electrode and separated from the gate electrode of the insulated gate by the first buried semiconductor layer.

2. 2. The semiconductor device according to claim 1, wherein a width of the first buried semiconductor layer measured along a direction connecting the gate electrode of the insulated gate and the second buried semiconductor layer is smaller than a value obtained by dividing a diffusion length of the first conductive type impurity in the first buried semiconductor layer by a square root of 2.

3. the first conductivity type impurity is an n-type impurity, the second conductivity type impurity is a p-type impurity, 3. The semiconductor device according to claim 1, wherein said gate electrode of said insulated gate, said first buried semiconductor layer, and said second buried semiconductor layer constitute an npn bipolar transistor.

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