Switching element

Abstract

To ensure a wide channel and suppress current concentration in the vicinity of each connection region when it is difficult to form a connection region independently for each inter-trench semiconductor layer.SOLUTION: A switching element is configured with a plurality of rows in which connection regions are linearly arranged at intervals along a second direction intersecting with trenches extending in a first direction. An intersection between an inter-trench semiconductor layer and the rows has a connection intersection where the connection region is provided and a non-connection intersection where the connection region is not provided. In each row, a portion where the connection intersection is continuous and a portion where the non-connection intersection is continuous are alternately arranged. Between adjacent rows, the phase of the patterns is shifted in the second direction. At each non-connection intersection, the Chebyshev distance to the connection intersection is 1. At each connection intersection, the Chebyshev distance to the non-connection intersection is 1.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a switching element.

[0002] Patent Document 1 discloses a trench-gate type switching element. In this switching element, multiple p-type deep layers are provided inside an n-type drift layer. In the thickness direction of the semiconductor substrate, each deep layer is disposed below the lower end of the trench. In addition, each deep layer may be disposed in a range including the lower end of the trench in the thickness direction of the semiconductor substrate. In addition, the switching element of Patent Document 1 has multiple p-type connection regions. Each connection region connects each deep layer to a p-type body layer. By providing the deep layers and connection regions in this way, the electric field applied to the gate insulating film covering the lower end of the trench can be suppressed.

[0003] In Patent Document 1, when the semiconductor substrate is viewed from above, the connection regions are distributed and arranged so as to maintain a predetermined interval in the x and y directions. That is, when the semiconductor substrate is viewed from above, the connection regions are distributed and arranged. By distributing the connection regions, a wide channel is ensured.

[0004] Inside the switching element, a diode (so-called body diode) is formed by the interface between the p-type body layer and the n-type drift layer. When the voltage applied to the body diode switches from the forward direction to the reverse direction, a recovery current flows through the switching element, causing a recovery surge. If the density of the connection region is low, as in Patent Document 1, the recovery surge can be suppressed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2022-083790 Summary of the Invention [Problem to be solved by the invention]

[0006] During operation of the switching element, a recovery current or an avalanche current may flow from the drift region to each connection region. In the switching element of Patent Document 1, when a recovery current or an avalanche current flows in the drift region, the current tends to concentrate near each connection region.

[0007] In addition, in Patent Document 1, a connection region is provided independently for each semiconductor layer sandwiched between trenches (hereinafter, sometimes referred to as inter-trench semiconductor layer). However, when the trenches are densely packed, the width of the inter-trench semiconductor layer becomes narrow, making it difficult to form an independent connection region for each inter-trench semiconductor layer.

[0008] In this specification, a technique is proposed for ensuring a wide channel and suppressing current concentration in the vicinity of each connection region when it is difficult to form a connection region independently for each inter-trench semiconductor layer. [Means for solving the problem]

[0009] The switching element disclosed in this specification has a semiconductor substrate, a gate insulating film, a gate electrode, and a source electrode. A plurality of trenches are provided on the upper surface of the semiconductor substrate. Each of the trenches extends linearly in a first direction on the upper surface of the semiconductor substrate. Each of the trenches is arranged at intervals in a second direction intersecting the first direction on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of each of the trenches. The gate electrode is arranged in each of the trenches and is insulated from the semiconductor substrate by the gate insulating film. The source electrode is in contact with the upper surface of the semiconductor substrate. The semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched by the plurality of the trenches. Each of the inter-trench semiconductor layers has an n-type source region in contact with the gate insulating film and the source electrode, and a p-type body region in contact with the gate insulating film below the source region. The semiconductor substrate has a drift region, a plurality of deep regions, and a plurality of connection regions. The drift region is an n-type region that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is in contact with the gate insulating film below the body region in each inter-trench semiconductor layer. The plurality of deep regions are p-type regions that are arranged in a range surrounded by the drift region, spaced apart from the body region and arranged below the body region, and arranged in a range including the lower end of the trench or below the lower end of the trench in the thickness direction of the semiconductor substrate. The plurality of connection regions are p-type regions that connect the body region and the deep region. When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of columns linearly arranged at intervals along the second direction, and the columns are arranged at intervals in the first direction. When the semiconductor substrate is viewed from above, intersections between the plurality of inter-trench semiconductor layers and the plurality of columns include connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided. The connection intersections and the non-connection intersections satisfy the following condition, that is, In each row, the connecting intersections and the non-connecting intersections are arranged in a pattern in which a portion in which a first reference number of the connecting intersections, which is 2 or more, are consecutive and a portion in which a second reference number of the non-connecting intersections, which is 2 or more, are consecutive, are alternately arranged in the second direction. Between adjacent rows, the patterns are out of phase with each other in the second direction. When counting the Chebyshev distance in units of the intersections, the Chebyshev distance of each non-connected intersection to the connected intersection is 1; When counting the Chebyshev distance in units of the intersections, the Chebyshev distance from each connected intersection to the non-connected intersection is 1; The following conditions are met.

[0010] In this switching element, a first reference number (i.e., 2 or more) of connection intersections are continuous in the second direction. That is, the connection intersections are provided across a plurality of inter-trench semiconductor layers. Therefore, even if the width of the inter-trench semiconductor layer is narrow, the connection intersections can be appropriately formed.

[0011] In addition, when the connection intersections are dense, the connection region located at the center of the dense area hardly contributes to the stabilization of the potential of the deep layer. If such a useless connection area exists, the channel is reduced by the amount of the connection area. In contrast, in the switching element disclosed in this specification, when the Chebyshev distance is counted in units of the intersections, the Chebyshev distance from each connection intersection to the non-connection intersection is 1. In other words, the density of the connection intersections is suppressed. Therefore, in this switching element, a wide channel can be secured.

[0012] Furthermore, if there is a non-connection intersection that is extremely far from the connection intersection, the recovery current and the avalanche current are unlikely to flow near the non-connection intersection that is extremely far from the connection intersection. In this case, the density of the recovery current and the avalanche current is high near the connection region. In contrast, in the switching element disclosed in this specification, when the Chebyshev distance is counted in units of intersections, the Chebyshev distance to the connection intersection at each non-connection intersection is 1. In other words, there is no non-connection intersection that is extremely far from the connection intersection. Therefore, in this switching element, current concentration in the vicinity of each connection region is suppressed. [Brief description of the drawings]

[0013] [Figure 1] 1 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a first embodiment. [Diagram 2] 7 is a cross-sectional view showing a vertical section along the y direction at a position including a deep region of the switching element of the first embodiment (the position of line II-II in FIG. 6). [Diagram 3] 8 is a cross-sectional view showing a vertical section along the y direction at a position (position of line III-III in FIG. 6) not including a deep region of the switching element of the first embodiment. FIG. [Figure 4] 7 is a cross-sectional view showing a vertical cross section along the x direction at a position not including a trench of the switching element of the first embodiment (the position of line IV-IV in FIG. 6). [Diagram 5] 7 is a cross-sectional view showing a vertical section along the x direction at a position including a trench of the switching element of the first embodiment (the position of line VV in FIG. 6). FIG. [Figure 6] FIG. 2 is a plan view showing the arrangement of connection intersections of the switching elements according to the first embodiment. [Figure 7] FIG. 3 is a layout diagram of a connection intersection portion according to the first embodiment. [Figure 8] FIG. 4 is a layout diagram of a connection intersection portion according to a first comparative example. [Figure 9] FIG. 11 is a layout diagram of a connection intersection portion according to a second comparative example. [Figure 10] FIG. 11 is a perspective view including a vertical cross section along the x direction and the y direction of a switching element according to a second embodiment. [Figure 11] Plan view showing the arrangement of the connection intersections of the switching element of Example 2. [Figure 12] Perspective view including longitudinal sections of the switching element of Example 3 along the x and y directions. [Figure 13] Plan view showing the arrangement of the connection intersections of the switching element of Example 3. [Figure 14] Perspective view including longitudinal sections of the switching element of Example 4 along the x and y directions. [Figure 15] Plan view showing the arrangement of the connection intersections of the switching element of Example 4. [Figure 16] Perspective view including longitudinal sections of the switching element of Example 5 along the x and y directions. [Figure 17] Layout diagram exemplifying variations in the arrangement of connection intersections satisfying conditions 1 to 4 when A = B. [Figure 18] Layout diagram exemplifying variations in the arrangement of connection intersections satisfying conditions 1 to 4 when A < B. [Figure 19] Layout diagram exemplifying the arrangement of connection intersections satisfying conditions 1 to 4 when A > B. [Figure 20] Layout diagram exemplifying the arrangement of connection intersections when the deviation amount changes.

Mode for Carrying Out the Invention

[0014] In an example of the switching element disclosed in this specification, the second reference number may be equal to or greater than the first reference number.

[0015] According to this configuration, a small number of connection intersections can be efficiently dispersed and arranged.

[0016] In an example of the switching element disclosed in this specification, in each trench-inter semiconductor layer, the connection intersections may not be continuous in the first direction when viewed in units of the intersections.

[0017] According to this configuration, the connection intersections can be arranged more dispersedly.

[0018] In the switching element disclosed in the present specification, in each of the inter-trench semiconductor layers, the number of consecutive connection intersections in the first direction may be 3 or less when viewed in units of the intersections.

[0019] According to this configuration, the connection intersections can be arranged in a more dispersed manner.

[0020] In an example switching element disclosed in the present specification, when the first reference number is expressed by an arbitrary integer A, the second reference number may be 3A. In the plurality of columns, the phase of the pattern may change periodically for every four of the columns. When the four columns are designated in order as a first column, a second column, a third column, and a fourth column, and the amount of phase shift of the pattern is counted in units of the intersections, the amount of shift of the second column relative to the first column may be A, the amount of shift of the third column relative to the first column may be 3A, and the amount of shift of the fourth column relative to the first column may be 2A.

[0021] According to this configuration, the connection intersections can be arranged in a dispersed manner.

[0022] In one example switching element disclosed in this specification, multiple deep regions may extend linearly along the second direction and be spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above.

[0023] In the switching element disclosed in the present specification as an example, a p-type contact region that connects the body region and the source electrode may be provided on an upper portion of each of the connection regions. EXAMPLES

[0024] The switching element 10 of the first embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si and GaN. In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the x-direction on the upper surface 12a. The trenches 14 are arranged at intervals in the y-direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is arranged in each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An interlayer insulating film 20 is arranged in each trench 14. Each interlayer insulating film 20 covers the upper surface of the gate electrode 18.

[0025] As shown in Figures 2 to 5, a source electrode 22 is provided on the upper part of the semiconductor substrate 12. Note that the source electrode 22 is not shown in Figure 1. The source electrode 22 covers the upper surface of the interlayer insulating film 20 and the upper surface 12a of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. A drain electrode 24 is provided on the lower part of the semiconductor substrate 12. The drain electrode 24 covers the lower surface 12b of the semiconductor substrate 12.

[0026] Fig. 6 shows the upper surface 12a of the semiconductor substrate 12. As described above, a plurality of trenches 14 extending linearly in the x direction are arranged at intervals in the y direction on the upper surface 12a. The inter-trench semiconductor layer 30 shown in Fig. 6 shows a semiconductor layer sandwiched between two trenches 14 (i.e., a semiconductor layer arranged between two trenches 14). Each inter-trench semiconductor layer 30 extends linearly in the x direction on the upper surface 12a. Each inter-trench semiconductor layer 30 is arranged at intervals in the y direction on the upper surface 12a.

[0027] As shown in FIG. 1, the semiconductor substrate 12 includes a source region 40, a body region 42, a drift region 44, and a drain region 46.

[0028] The source region 40 is an n-type region having a high n-type impurity concentration. The source region 40 is disposed in the inter-trench semiconductor layer 30. As shown in Figures 2 and 3, the source region 40 contacts the source electrode 22 in the inter-trench semiconductor layer 30. The source region 40 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0029] The body region 42 is a p-type region having a low p-type impurity concentration. The body region 42 is disposed in the inter-trench semiconductor layer 30. As shown in FIGS. 2 and 3, the body region 42 is disposed in the inter-trench semiconductor layer 30, and disposed below the source region 40. The body region 42 contacts the gate insulating film 16 below the source region 40. That is, the body region 42 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of the inter-trench semiconductor layer 30.

[0030] The drift region 44 is an n-type region having a low n-type impurity concentration. As shown in FIGS. 2 and 3, the drift region 44 is distributed across the lower portions of the inter-trench semiconductor layers 30. As shown in FIG. 3, the upper end portion of the drift region 44 extends into each inter-trench semiconductor layer 30. The drift region 44 contacts the body region 42 from the lower side in each inter-trench semiconductor layer 30. The drift region 44 contacts the gate insulating film 16 below the body region 42. That is, the drift region 44 contacts the gate insulating film 16 on the side surfaces of the trenches 14 provided on both sides of each inter-trench semiconductor layer 30.

[0031] The drain region 46 is an n-type region having a high n-type impurity concentration. The n-type impurity concentration of the drain region 46 is higher than the n-type impurity concentration of the drift region 44. As shown in FIGS. 2 to 5, the drain region 46 contacts the drift region 44 from below. The drain region 46 contacts the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.

[0032] The semiconductor substrate 12 has a plurality of p-type deep regions 50. As shown in FIGS. 2 and 4, each deep region 50 is disposed in a range surrounded by the drift region 44. Each deep region 50 is disposed below the body region 42 with a gap therebetween. The drift region 44 is distributed in the gap between each deep region 50 and the body region 42. The dot-hatched region in FIG. 6 indicates the distribution range of the deep regions 50. As shown in FIG. 6, when the semiconductor substrate 12 is viewed from above, each deep region 50 extends linearly in the y direction. When the semiconductor substrate 12 is viewed from above, each deep region 50 is disposed with a gap therebetween in the x direction. As shown in FIGS. 1, 2, and 5, each deep region 50 is disposed in a range including the lower end of the trench 14 in the z direction. Therefore, each deep region 50 contacts the gate insulating film 16 at the lower end of each trench 14.

[0033] As shown in FIG. 1, the semiconductor substrate 12 has a plurality of connection regions 52 and a plurality of contact regions 54. As shown in FIGS. 1, 2, and 4, the connection region 52 is a p-type region that connects the body region 42 and the deep region 50. A plurality of connection regions 52 are provided in each of the inter-trench semiconductor layers 30. The contact region 54 is a p-type region that connects the body region 42 and the source electrode 22. That is, the contact region 54 extends upward from the body region 42 and contacts the source electrode 22 at its upper end. A plurality of contact regions 54 are provided in each of the inter-trench semiconductor layers 30. In this embodiment, the contact region 54 and the connection region 52 extend continuously in the z direction. That is, the contact region 54 is disposed above the connection region 52. The semiconductor substrate 12 has a plurality of sets of the contact region 54 and the deep region 50. Each deep region 50 is connected to the source electrode 22 via the connection region 52 and the contact region 54.

[0034] 6, the hatched region indicates a set of connection region 52 and contact region 54. The set of connection region 52 and contact region 54 is partially provided on the upper part of deep region 50. When semiconductor substrate 12 is viewed from above as shown in FIG. 6, the multiple connection regions 52 are arranged to form multiple rows 53 linearly extending in the y direction. Note that in FIG. 6, rows 53 extending in the y direction overlap with deep region 50. The multiple rows 53 are arranged at intervals in the x direction.

[0035] The intersection 60 shown in FIG. 6 is a portion where the inter-trench semiconductor layer 30 and the row 53 intersect when the semiconductor substrate 12 is viewed from above. In the first embodiment, the intersection 60 coincides with a portion where the inter-trench semiconductor layer 30 and the deep region 50 intersect when the semiconductor substrate 12 is viewed from above. As described above, each inter-trench semiconductor layer 30 extends linearly in the x direction, and each row 53 extends linearly in the y direction. Therefore, when the semiconductor substrate 12 is viewed from above, a plurality of intersections 60 are arranged in a matrix along the x direction and the y direction. As shown in FIG. 6, a set of a connection region 52 and a contact region 54 is provided at a portion of the plurality of intersections 60. As shown in FIGS. 1, 2, and 6, each connection region 52 contacts the gate insulating film 16 on the side surfaces of the trench 14 located on both sides of the intersection 60. In addition, the contact region 54 contacts the gate insulating film 16 on the side surfaces of the trench 14 located on both sides of the intersection 60. Hereinafter, an intersection 60 where a connection region 52 is provided will be referred to as a connection intersection 60a, and an intersection 60 where a connection region 52 is not provided will be referred to as a non-connection intersection 60b.

[0036] FIG. 7 shows an arrangement of the connection intersections 60a and the non-connection intersections 60b. Each cell shown in FIG. 7 shows an intersection 60. In FIG. 7, the cells hatched with diagonal lines show the connection intersections 60a, and the blank cells in FIG. 7 show the non-connection intersections 60b. In FIG. 7, the columns 53 are shown as columns 53a, 53b, 53c, 53d, 53e, 53f, 53g, and 53h from the left. The connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the following conditions 1 to 4.

[0037] (Condition 1) In each column 53, the connecting intersections 60a and the non-connecting intersections 60b are arranged in a repeating pattern in which a portion P1 of consecutive connecting intersections 60a of a first reference number A, which is 2 or greater, and a portion P2 of consecutive non-connecting intersections 60b of a second reference number B, which is 2 or greater, are alternately arranged in the y direction.

[0038] (Condition 2) Between adjacent columns 53, the phase of the repeating patterns is shifted in the y direction.

[0039] (Condition 3) When counting the Chebyshev distance in units of intersections 60, the Chebyshev distance from each non-connected intersection 60b to the connected intersection 60a is 1.

[0040] (Condition 4) When counting the Chebyshev distance in units of intersections 60, the Chebyshev distance from each connected intersection 60a to a non-connected intersection 60b is 1.

[0041] FIG. 7 shows a case where the first reference number A is 2 and the second reference number B is 2. In FIG. 7, the repeating pattern is arranged so that the phase of the repeating pattern is shifted downward by a certain amount as it shifts from the column 53a to the right. Hereinafter, the phase shift amount when the phase of the repeating pattern is shifted downward by a certain amount as it shifts to the right is referred to as the shift amount C. The shift amount C is counted in cell units (i.e., in units of intersections 60). FIG. 7 shows a case where the shift amount C is 2. That is, in column 53b, the phase of the repeating pattern is shifted downward by two cells with respect to column 53a, and in column 53c, the phase of the repeating pattern is shifted downward by two cells with respect to column 53b. In FIG. 7, each non-connection intersection 60b is adjacent to the connection intersection 60a. Therefore, in all non-connection intersections 60b, the Chebyshev distance from the non-connection intersection 60b to the connection intersection 60a is 1. 7, each connection intersection 60a is adjacent to a non-connection intersection 60b. Therefore, the Chebyshev distance from each connection intersection 60a to the non-connection intersection 60b is 1 for all connection intersections 60a.

[0042] The switching element 10 of the first embodiment is a so-called MOSFET (metal-oxide-semiconductor field effect transistor). Normally, a higher potential is applied to the drain electrode 24 than to the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, an inversion layer is formed in the body region 42. In the non-connection intersection 60b, the inversion layer formed in the body region 42 connects the source region 40 and the drift region 44. This turns on the switching element 10, and a current flows from the drain electrode 24 to the source electrode 22. In this way, the inversion layer formed in the non-connection intersection 60b functions as a channel. On the other hand, in the connection intersection 60a, the contact region 54 and the connection region 52 are provided above and below the body region 42. Therefore, in the connection intersection 60a, almost no current flows through the inversion layer formed in the body region 42. That is, the inversion layer formed in the connection intersection 60a does not function as a channel. As described above, when a high potential is applied to the gate electrode 18, the inversion layer formed at the non-connected intersection 60b functions as a channel, turning on the switching element 10.

[0043] When the potential of the gate electrode 18 is lowered to a potential lower than the gate threshold, the inversion layer disappears and the switching element 10 is turned off. When the switching element 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44, and a depletion layer spreads from the body region 42 to the drift region 44. The connection region 52 is provided to stabilize the potential of the deep region 50 with the potential of the body region 42. In other words, since the deep region 50 is connected to the body region 42 by the connection region 52, the potential of the deep region 50 is approximately equal to the potential of the body region 42. Therefore, a reverse voltage is applied to the pn junction at the interface between the deep region 50 and the drift region 44, and a depletion layer spreads from the deep region 50 to the drift region 44. The depletion layer extending from the deep region 50 prevents a high electric field from being applied to the gate insulating film 16 at the lower end of each trench 14.

[0044] A higher potential than that of the drain electrode 24 may be applied to the source electrode 22. In this case, a diode (so-called body diode) formed by a pn junction at the interface between the body region 42 and the drift region 44 turns on, and a current flows from the source electrode 22 to the drain electrode 24. When the body diode is on, holes flow from the body region 42 to the drift region 44, so that many holes exist in the drift region 44. After that, when the potential of the drain electrode 24 becomes higher than the potential of the source electrode 22, the body diode turns off. Then, the holes existing in the drift region 44 flow to the deep region 50 as shown by the arrow 100 in FIG. 2. The holes flowing from the drift region 44 to the deep region 50 flow to the source electrode 22 via the connection region 52 and the contact region 54. The current generated when the body diode turns off in this way is called a recovery current. As shown in FIG. 2, the recovery current flows more easily to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0045] Moreover, an overvoltage may be applied to the switching element 10 in a direction in which the drain electrode 24 has a higher potential than the source electrode 22. In this case, an avalanche current is generated in the drift region 44. The avalanche current flows to the deep region 50 as shown by an arrow 100 in FIG. 2. The avalanche current that flows from the drift region 44 to the deep region 50 flows to the source electrode 22 via the connection region 52 and the contact region 54. As shown in FIG. 2, the avalanche current is more likely to flow to the drift region 44 at the connection intersection 60a where the connection region 52 is provided than at the non-connection intersection 60b where the connection region 52 is not provided.

[0046] As described above, at the connection intersection 60a, the recovery current and the avalanche current flow more easily in the drift region 44 than at the non-connection intersection 60b. At the non-connection intersection 60b, the recovery current and the avalanche current flow less easily the farther the distance to the connection intersection 60a is. If there is a non-connection intersection 60b through which the recovery current and the avalanche current flow less easily, the recovery current and the avalanche current tend to concentrate at the connection intersection 60a.

[0047] FIG. 8 shows the arrangement of the connection intersection 60a and the non-connection intersection 60b of the switching element of the first comparative example. In the arrangement shown in FIG. 8, A=2, B=6, and C=1. In the arrangement of FIG. 8, the Chebyshev distance from the non-connection intersection 60b-1 to the connection intersection 60a is 2. That is, the arrangement of FIG. 8 does not satisfy the above condition 3. In the non-connection intersection 60b-1, which has a long Chebyshev distance to the connection intersection 60a, the recovery current and the avalanche current are extremely unlikely to flow. Therefore, in the arrangement of FIG. 8, the recovery current and the avalanche current are likely to concentrate at the connection intersection 60a. Therefore, the recovery resistance and the avalanche resistance of the switching element of the first comparative example are low. In contrast, in the switching element 10 of the first embodiment, as shown in FIG. 7, the Chebyshev distance to the connection intersection 60a is 1 at all the non-connection intersections 60b. Therefore, in the switching element 10 of the first embodiment, the recovery current and the avalanche current are less likely to concentrate at the connection intersection 60a. Therefore, the switching element 10 of the first embodiment has high recovery resistance and avalanche resistance. Therefore, the structure of the switching element 10 of the first embodiment can achieve higher reliability.

[0048] FIG. 9 shows the arrangement of the connection intersections 60a and non-connection intersections 60b of the switching element of the second comparative example. In the arrangement shown in FIG. 9, A=5, B=4, and C=1. In the arrangement of FIG. 9, the Chebyshev distance from the connection intersections 60a-1 to the non-connection intersections 60b is 2. That is, in FIG. 9, the connection intersections 60a are densely packed, and the connection intersections 60a-1 are present at the center of the dense area. As described above, the connection region 52 (i.e., the connection intersections 60a) are provided to stabilize the potential of the deep region 50 with the potential of the body region 42. In the dense area of ​​the connection intersections 60a, the deep region 50 is connected to the body region 42 by a large number of connection intersections 60a, so the connection intersections 60a-1 present at the center of the dense area hardly contribute to stabilizing the potential of the deep region 50. If such an unnecessary connection intersection 60a-1 exists, the density of the channel decreases, and the on-resistance of the switching element increases. In contrast, in the switching element 10 of the first embodiment, as shown in FIG. 7, the Chebyshev distance to the non-connection intersection 60b is 1 at all the connection intersections 60a. Therefore, in the switching element 10 of the first embodiment, all the connection intersections 60a contribute to stabilizing the potential of the deep region 50, and no unnecessary connection intersections 60a exist. Therefore, it is possible to provide channels at a high density. Therefore, according to the structure of the switching element 10 of the first embodiment, a low on-resistance can be realized.

[0049] In addition, in recent years, the interval between the trenches 14 has become narrower in order to further increase the current density (i.e., channel density) of the switching element. That is, the width of the inter-trench semiconductor layer 30 has become narrower. For this reason, it may be difficult to form the connection region 52 and the contact region 54 for each inter-trench semiconductor layer 30. In contrast, in the first embodiment, the connection intersections 60a are arranged so as to be continuous in the y direction by the first reference number A (i.e., 2 or more), so that the connection region 52 and the contact region 54 can be formed across a plurality of inter-trench semiconductor layers 30. Therefore, even if the width of the inter-trench semiconductor layer 30 is narrow, the connection region 52 and the contact region 54 can be easily formed. For example, even if the width of the inter-trench semiconductor layer 30 is narrow, an ion implantation region (i.e., a region into which ions are implanted to form the connection region 52 and the contact region 54) can be provided across a plurality of inter-trench semiconductor layers 30, so that the width of the ion implantation region can be secured to be wide. Therefore, the width of the opening of the ion implantation mask does not become extremely narrow, and the connection region 52 and the contact region 54 can be easily formed.

[0050] As described above, the switching element of Example 1 can suppress the concentration of recovery current and avalanche current at the connection intersection 60a. Moreover, the switching element of Example 1 can increase the channel density and realize a low on-resistance. Moreover, the structure of the switching element of Example 1 allows the connection region 52 and the contact region 54 to be easily formed even when the interval between the trenches 14 is narrow. EXAMPLES

[0051] 10 and 11 show a switching element 200 according to a second embodiment. In the second embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged below the center of the inter-trench semiconductor layer 30 in the y direction.

[0052] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 11, the connection regions 52 are arranged to form a plurality of rows 53 that extend linearly in the y direction. The rows 53 are arranged at intervals in the x direction.

[0053] As shown in FIG. 11, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. The arrangement of the connection intersections 60a and the non-connection intersections 60b in the second embodiment (i.e., the arrangement in terms of the cell unit) is the same as that in the first embodiment (i.e., FIG. 7). That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 4. Therefore, in the second embodiment, the concentration of the recovery current and the avalanche current can be suppressed while ensuring a wide channel. Also in the second embodiment, the connection region 52 and the contact region 54 can be easily formed when the interval between the trenches 14 is narrow. EXAMPLES

[0054] 12 and 13 show a switching element 300 according to a third embodiment. In the third embodiment, each deep region 50 extends linearly in the x direction. The deep regions 50 are arranged at intervals in the y direction. Each deep region 50 is arranged in the lower part of a trench 14.

[0055] Each deep region 50 is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 13, the connection regions 52 are arranged to form a plurality of rows 53 that extend linearly in the y direction. The rows 53 are arranged at intervals in the x direction.

[0056] As shown in FIG. 13, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. The arrangement of the connection intersections 60a and the non-connection intersections 60b in the third embodiment (i.e., the arrangement in terms of the cell unit) is the same as that in the first embodiment (i.e., FIG. 7). That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 4. Therefore, in the third embodiment as well, it is possible to suppress the concentration of the recovery current and the avalanche current while ensuring a wide channel. Moreover, in the third embodiment as well, it is possible to easily form the connection region 52 and the contact region 54 when the interval between the trenches 14 is narrow. EXAMPLES

[0057] 14 and 15 show a switching element 400 of Example 4. The switching element 400 of Example 4 has two types of deep regions 50x and 50y. Each deep region 50y extends linearly in the y direction. The deep regions 50y are arranged at intervals in the x direction. Each deep region 50y is arranged at a depth including the lower end of the trench 14. Each deep region 50x is arranged below each deep region 50y. Each deep region 50x extends linearly in the x direction. The deep regions 50x are arranged at intervals in the y direction. The upper end of each deep region 50x is arranged at a depth overlapping the lower end of each deep region 50y. Each deep region 50x and each deep region 50y are connected to each other at the intersection.

[0058] Each deep region 50y is connected to the source electrode 22 via a connection region 52 and a contact region 54. As shown in Fig. 15, the connection regions 52 are arranged to form a plurality of rows 53 linearly extending in the y direction. In Fig. 15, the rows 53 extending in the y direction overlap with the deep regions 50y. The rows 53 are arranged at intervals in the x direction.

[0059] As shown in FIG. 15, a set of a connection region 52 and a contact region 54 is provided at some of the multiple intersections 60. The arrangement of the connection intersections 60a and the non-connection intersections 60b in the fourth embodiment (i.e., the arrangement in terms of the cell unit) is the same as that in the first embodiment (i.e., FIG. 7). That is, the connection intersections 60a and the non-connection intersections 60b are arranged so as to satisfy the above-mentioned conditions 1 to 4. Therefore, in the fourth embodiment, it is possible to suppress the concentration of the recovery current and the avalanche current while ensuring a wide channel. Also in the fourth embodiment, it is possible to easily form the connection region 52 and the contact region 54 when the interval between the trenches 14 is narrowed.

[0060] In addition, in the fourth embodiment, the deep regions 50x and 50y extend along the x and y directions. Therefore, the deep regions 50x and 50y in each non-connection intersection 60b are connected to the connection region 52 by a shorter current path. Therefore, the potentials of the deep regions 50x and 50y can be more stabilized.

[0061] In the fourth embodiment described above, the deep region 50y is disposed above the deep region 50x. However, the deep region 50x may be disposed above the deep region 50y. Moreover, the deep region 50x and the deep region 50y may be disposed at the same depth.

[0062] In the above-described first to fourth embodiments, each deep region 50 is disposed at a depth including the lower end of the trench 14. However, each deep region 50 may be disposed below the lower end of the trench 14. For example, in the first embodiment, each deep region 50 may be disposed below the lower end of the trench 14 as shown in FIG.

[0063] In addition, in the above-described Examples 1 to 4, the contact regions 54 are provided above the connection regions 52. However, the positions of the connection regions 52 and the contact regions 54 may be shifted in the x-direction. Furthermore, the number of connection regions 52 and the number of contact regions 54 may be different.

[0064] In the above-mentioned first to fourth embodiments, the connection intersections 60a and the non-connection intersections 60b are arranged as shown in FIG. 7. However, the connection intersections 60a and the non-connection intersections 60b may be arranged in any manner as long as the arrangement satisfies the above-mentioned conditions 1 to 4. FIG. 17 shows an example of an arrangement that satisfies the conditions 1 to 4 when the first reference number A is equal to the second reference number B. FIG. 18 shows an example of an arrangement that satisfies the conditions 1 to 4 when the first reference number A is smaller than the second reference number B. In FIG. 17 and FIG. 18, the horizontal direction is the X direction, the vertical direction is the Y direction, the cells hatched with diagonal lines are the connection intersections 60a, and the blank cells are the non-connection intersections 60b. In addition, FIG. 19 shows an example of an arrangement that satisfies the conditions 1 to 4 when the first reference number A is larger than the second reference number B.

[0065] Furthermore, as illustrated in FIGS. 17 and 18, when the second reference number B is equal to or greater than the first reference number A, the non-connected intersection 60b (i.e., the channel) can be ensured to be wide, and the on-resistance of the switching element can be effectively reduced.

[0066] 17 and 18 (excluding A=4, B=4, and C=1 in FIG. 17), when the number of consecutive connection intersections 60a in the x direction is 3 or less, the concentration of the connection intersections 60a can be more effectively suppressed. Therefore, each connection intersection 60a contributes to stabilizing the potential of the deep region 50, and it is possible to reduce unnecessary connection intersections 60a. Therefore, it is possible to ensure a wide non-connection intersection 60b (i.e., channel), and effectively reduce the on-resistance of the switching element.

[0067] 17 and 18, when (A,B,C) is arranged as (2,2,2), (3,3,3), (4,4,4), (2,4,2), (3,6,3), (3,6,4), (4,8,4), and (4,8,5), there is no point where the connection intersections 60a are continuous in the x direction. As illustrated in these examples, according to the configuration where the connection intersections 60a are not continuous in the x direction, the connection intersections 60a can be arranged in a more dispersed manner, and the concentration of current at the connection intersections 60a can be more effectively suppressed.

[0068] 17, 18, and 19, the phase of the repeating pattern is shifted downward by a fixed amount (i.e., shift amount C) as the column shifts to the right, but the phase shift amount of the repeating pattern does not have to be constant. For example, as shown in FIG. 20, the phase shift amount may change depending on the position. In FIG. 20, the first reference number A is 2, and the second reference number B is 6 (i.e., 3A). Also, the shift amount of column 53b relative to column 53a is 2, the shift amount of column 53c relative to column 53b is 4, and the shift amount of column 53d relative to column 53c is -2. In other words, the shift amount of column 53b relative to column 53a is 2 (i.e., A), the shift amount of column 53c relative to column 53a is 6 (i.e., 3A), and the shift amount of column 53d relative to column 53a is 4 (i.e., 2A). In FIG. 20, the phase shift amount changes with such a period of four columns. By changing the amount of phase shift in this way, it may be possible to more evenly distribute the connection intersections 60a and the non-connection intersections 60b. Even if the first reference number A is different from that in FIG. 20, the second reference number B and each amount of shift can be set at the above ratio.

[0069] In the embodiment, the x direction is an example of the first direction, and the y direction is an example of the second direction.

[0070] The configurations of the techniques disclosed in this specification are listed below. (Configuration 1) A switching element, A semiconductor substrate having a plurality of trenches provided on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart from each other in a second direction intersecting the first direction on the upper surface of the semiconductor substrate; a gate insulating film covering an inner surface of each of the trenches; a gate electrode disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode in contact with the top surface of the semiconductor substrate; having the semiconductor substrate has a plurality of inter-trench semiconductor layers sandwiched between a plurality of the trenches, Each inter-trench semiconductor layer is an n-type source region in contact with the gate insulating film and the source electrode; a p-type body region below the source region and in contact with the gate insulating film; having The semiconductor substrate is an n-type drift region that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and is in contact with the gate insulating film below the body region in each of the inter-trench semiconductor layers; a plurality of p-type deep regions, which are arranged in a range surrounded by the drift region, are arranged below the body region with a gap therebetween, and are arranged in a range including a lower end of the trench or below the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions connecting the body region and the deep region; having When the semiconductor substrate is viewed from above, the connection regions are arranged in a plurality of rows in a linear manner at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections between a plurality of the inter-trench semiconductor layers and a plurality of the columns include connection intersections where the connection regions are provided and non-connection intersections where the connection regions are not provided, The connecting intersections and the non-connecting intersections satisfy the following conditions: In each row, the connecting intersections and the non-connecting intersections are arranged in a pattern in which a portion in which a first reference number of the connecting intersections, which is 2 or more, are consecutive and a portion in which a second reference number of the non-connecting intersections, which is 2 or more, are consecutive, are alternately arranged in the second direction. Between adjacent rows, the patterns are out of phase with each other in the second direction. When counting the Chebyshev distance in units of the intersections, the Chebyshev distance of each non-connected intersection to the connected intersection is 1; When counting the Chebyshev distance in units of the intersections, the Chebyshev distance from each connected intersection to the non-connected intersection is 1; Satisfying the condition that Switching element. (Configuration 2) 2. The switching element of configuration 1, wherein the second reference number is greater than or equal to the first reference number. (Configuration 3) 3. The switching element according to configuration 1 or 2, wherein in each of the inter-trench semiconductor layers, the connection intersections are not continuous in the first direction when viewed in units of the intersections. (Configuration 4) 4. The switching element according to any one of configurations 1 to 3, wherein in each of the inter-trench semiconductor layers, the number of consecutive connection intersections in the first direction is 3 or less when viewed as a unit of the intersections. (Configuration 5) When the first reference number is expressed by an arbitrary integer A, the second reference number is 3A; In the plurality of rows, the phase of the pattern changes periodically every four rows; When the four columns are designated as the first column, the second column, the third column, and the fourth column, and the phase shift amount of the pattern is counted in units of the intersections, the amount of deviation of the second row from the first row is A, the offset of the third row relative to the first row is 3A; The amount of deviation of the fourth row from the first row is 2A. The switching element according to any one of configurations 1 to 4. (Configuration 6) A switching element described in any one of configurations 1 to 5, wherein a plurality of the deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above. (Configuration 7) 7. The switching element according to any one of configurations 1 to 6, wherein a p-type contact region that connects the body region and the source electrode is provided on an upper portion of each of the connection regions.

[0071] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]

[0072] 14: trench, 30: inter-trench semiconductor layer, 50: deep region, 52: connection region, 53: row, 54: contact region, 60a: connection intersection, 60b: non-connection intersection

Claims

1. A switching element, A semiconductor substrate (12) having a plurality of trenches (14) formed on an upper surface of the semiconductor substrate, each of the trenches extending linearly in a first direction on the upper surface of the semiconductor substrate, and each of the trenches being spaced apart in a second direction on the upper surface of the semiconductor substrate that intersects the first direction; a gate insulating film (16) covering the inner surface of each of the trenches; a gate electrode (18) disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; a source electrode (22) in contact with the top surface of the semiconductor substrate; having The semiconductor substrate has a plurality of inter-trench semiconductor layers (30) sandwiched between a plurality of the trenches; Each inter-trench semiconductor layer is an n-type source region (40) in contact with the gate insulating film and the source electrode; a p-type body region (42) below the source region and in contact with the gate insulating film; having The semiconductor substrate is an n-type drift region (44) that is distributed across the lower portions of the plurality of inter-trench semiconductor layers and that contacts the gate insulating film below the body region in each inter-trench semiconductor layer; a plurality of p-type deep regions (50) that are arranged in a range surrounded by the drift region, that are spaced apart from the body region and that are lower than the body region, and that are arranged in a range that includes a lower end of the trench or lower than the lower end of the trench in a thickness direction of the semiconductor substrate; a plurality of p-type connection regions (52) connecting the body region and the deep region; having When the semiconductor substrate is viewed from above, a plurality of rows (53) are configured in which the connection regions are linearly arranged at intervals along the second direction, and the plurality of rows are arranged at intervals in the first direction, When the semiconductor substrate is viewed from above, intersections (60) between the plurality of inter-trench semiconductor layers and the plurality of columns have connection intersections (60a) where the connection regions are provided and non-connection intersections (60b) where the connection regions are not provided, The connecting intersections and the non-connecting intersections satisfy the following conditions: In each row, the connecting intersections and the non-connecting intersections are arranged in a pattern in which a portion in which a first reference number of the connecting intersections, which is 2 or more, are consecutive and a portion in which a second reference number of the non-connecting intersections, which is 2 or more, are consecutive, are alternately arranged in the second direction. Between adjacent rows, the patterns are out of phase in the second direction; When counting the Chebyshev distance in units of the intersections, the Chebyshev distance to the connecting intersection at each non-connecting intersection is 1; When counting the Chebyshev distance in units of the intersections, the Chebyshev distance to the non-connected intersections at each connected intersection is 1; Satisfying the condition that Switching element.

2. The switching element of claim 1 , wherein the second reference number is greater than or equal to the first reference number.

3. The switching element according to claim 1 , wherein in each of the inter-trench semiconductor layers, the connection intersections are not continuous in the first direction when viewed as a unit of the intersections.

4. 3 . The switching element according to claim 1 , wherein in each of the inter-trench semiconductor layers, a number of consecutive connection intersections in the first direction is three or less when viewed as a unit of the intersections.

5. When the first reference number is expressed by an arbitrary integer A, the second reference number is 3A; In the plurality of rows, the phase of the pattern changes periodically every four rows, When the four columns are designated as a first column, a second column, a third column, and a fourth column in order, and the phase shift amount of the pattern is counted in units of the intersections, the amount of deviation of the second row relative to the first row is A, the offset of the third row relative to the first row is 3A; the amount of deviation of the fourth row from the first row is 2A; The switching element according to claim 1 .

6. 3. The switching element of claim 1, wherein the deep regions extend linearly along the second direction and are spaced apart in the first direction so that each deep region extends along a corresponding column when the semiconductor substrate is viewed from above.

7. 3. The switching element according to claim 1, further comprising a p-type contact region (54) provided on an upper portion of each of the connection regions to connect the body region and the source electrode.

Images