Semiconductor device
By employing vertical TFTs with a horizontally positioned second gate on transparent substrates, the challenges of substrate deformation are overcome, allowing for high-performance, low-power digital and analog circuits with compact design.
Patent Information
- Application Number
- JP2023191176
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-10-21
- Publication Date
- 2025-05-02
AI Technical Summary
On transparent substrates like glass or plastic, achieving high performance and integration of transistors through miniaturization is challenging due to substrate deformation, leading to increased circuit area.
The use of vertical thin film transistors (TFTs) with a second gate positioned horizontally to the substrate plane, allowing for control of the threshold voltage and enabling high current driving capability with low operating voltage.
This configuration enables high-speed operation and low power consumption in digital and analog circuits on transparent substrates, while maintaining a compact circuit area.
Smart Images
Figure 2025070906000001_ABST
Abstract
Description
[Technical field]
[0001] In recent years, IoT has been attracting attention. IoT edge devices have a wide range of performance requirements, from devices that occasionally operate at a few MHz to high-performance devices that constantly handle large amounts of digital and analog data.
[0002] In the future, as IoT edge devices become more diverse and multifunctional, there will be a demand to form devices on transparent substrates other than silicon (Si) wafers, such as plastic and glass, depending on the application. In particular, IoT devices formed on plastic are thin and deformable, so they can be attached to anything, such as skin, clothes, bags, and products.
[0003] Ambient electronics, which is expected to become a reality in the next generation, will require high-performance devices that constantly handle digital and analog data on transparent substrates such as glass. [Background technology]
[0004] IoT edge devices on glass or plastic substrates that constantly handle large amounts of digital and analog data require technology that can realize CMOS circuits.
[0005] On the other hand, on transparent substrates such as glass or plastic, it is difficult to achieve high performance and high integration through miniaturization due to substrate deformation during processing. Summary of the Invention [Problem to be solved by the invention]
[0006] Transparent substrates such as glass and plastics are prone to deformation during processing, making it difficult to achieve high performance and high integration of transistors through miniaturization, which has the disadvantage of increasing the circuit area.
[0007] If we can achieve high integration through miniaturization on transparent substrates such as glass or plastic, it will be possible to realize high-performance, highly integrated CMOS circuits that constantly handle large amounts of digital and analog data. [Means for solving the problem]
[0008] Vertical thin-film transistors (TFTs) are introduced to achieve high speed and high integration without increasing the circuit area on glass or plastic substrates.
[0009] In a vertical TFT, the gate length is determined by the size of the step (the length of the side wall 3), so that the gate length can be freely controlled by the film thickness and at the same time, a short gate length can be realized.
[0010] By reducing the gate length, it is possible to obtain a high current driving capability, which makes it possible to increase the speed. However, this structure requires a low threshold voltage (V th ) cannot be controlled.
[0011] To solve this problem, a second gate (2) is provided to th Adds a function to control the above.
[0012] The second gate (2) is characterized by being positioned horizontally to the substrate plane and generally perpendicular to the sidewall.
[0013] Furthermore, the second gate (2) is characterized in that it is made up of one or more gates with an insulating film sandwiched therebetween. Effect of the Invention
[0014] For a thin film transistor (TFT) that uses the sidewall of the step structure as a channel, a first gate (9) is arranged so as to cover the sidewall, and at the same time, a second gate (2) is arranged on the opposite side of the channel from the first gate and is positioned horizontally to the substrate. thBy adding a control function, it becomes possible to achieve a high current driving capability at a low operating voltage.
[0015] This makes it possible to realize high-speed, low-power digital and analog circuits on transparent substrates such as glass and plastic. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] A cross-sectional view of a device for realizing the present invention is shown in Figure 1. The following is an example. It has glass (1) as a substrate, a first gate (9) covering a channel (6) on the sidewall, and a single second gate (2) positioned horizontally relative to the substrate, resulting in a four-terminal structure [drain, source, first gate (9), second gate (2)].
[0017] Mo was sputtered onto a glass substrate (1) to a thickness of 50 nm (Fig. 2), and BG (2) was formed using photolithography and reactive ion etching (RIE) (Fig. 3). Next, using BG (2) as a hard mask, the glass substrate was etched to a depth of 200 nm by reactive ion etching (RIE) to form sidewalls (3) (Fig. 4).
[0018] Next, a 75 nm thick SiO2 film was formed as the BG gate insulating film (4) by plasma enhanced chemical vapor deposition (PECVD) (Fig. 5). Next, a 50 nm thick non-doped amorphous silicon (a-Si) film (5) was formed as the channel layer by plasma enhanced chemical vapor deposition (PECVD) (Fig. 6). The substrate temperatures during film formation were 360°C and 325°C, respectively.
[0019] Next, the non-doped a-Si was crystallized by heat treatment at 580 °C for 8 hours in a nitrogen atmosphere using Ni-based metal-induced crystallization (Ni-MIC), converting it into polycrystalline silicon (poly-Si) (6) (Figure 7).
[0020] Next, phosphorus (P) is injected into the area corresponding to the SD (source, drain) at an acceleration energy of 10 keV and a dose of 3×10 15 cm-2 The ions were implanted at a tilt angle of 45° to prevent ion implantation into the sidewall channel region. Therefore, non-doped poly-Si regions (6) exist in the poly-Si regions near the sidewalls and the bottom of the sidewalls (Fig. 8). As shown in Fig. 1, the top gate (TG) insulating film SiO2 (8) and TG (9) cover this region, so the non-doped poly-Si region (6) corresponds to the channel region in TG operation.
[0021] Next, a TG insulating film SiO2 (8) was formed to a thickness of 50 nm using PECVD (Figure 9). This was followed by activation heat treatment at 500 °C for 6 hours in a nitrogen atmosphere.
[0022] Next, a 40 nm thick Mo film was formed by sputtering, and TG metal (9) was formed by wet etching (Fig. 10). Next, a 200 nm thick SiO2 (10) was deposited as an interlayer insulating film by PECVD (Fig. 11), and then contact holes (11) for SD, TG, and BG were opened by RIE (Fig. 12).
[0023] An electrode (12) is formed by Al (aluminum) sputtering, and finally, hydrogenation is performed at 400°C with stepwise cooling using N2 + H2 gas (Figure 13).
[0024] The maximum temperature in the manufacturing process of this TFT is 580°C, which is lower than the heat-resistant temperature of glass (600°C).
[0025] The crystallization is not limited to Ni-SPC, and crystallization may be performed by a method using an energy beam.
[0026] The energy beam can be a pulsed laser, a continuous wave laser, or rapid thermal annealing (RTA).
[0027] Although Si was used in this embodiment, the semiconductor layer is not limited to Si, and germanium (Ge), oxide semiconductors, compound semiconductors, organic semiconductors, etc. can be used.
[0028] In particular, the present invention can be applied to plastics by using oxide semiconductors, organic semiconductors, Ge, and the like that can form semiconductor thin films at low temperatures.
[0029] In this experiment, fused silica glass was used, but it is also possible to fabricate TFTs using a similar process by using a thick SiO2 film (13) (Figure 14) formed on an Al-free glass substrate.
[0030] FIG. 15 shows a structure in which the second gate is made up of two gates, but the second gate can also be made up of a plurality of gates (two or more).
[0031] FIG. 16 shows the transfer characteristic of the TFT realized in this embodiment. The voltage of the second gate (V c ) causes the current rise voltage (V th ) is seen to have changed. [Brief description of the drawings]
[0032] [Figure 1] Device cross section [Diagram 2] Cross-section of device after formation of second gate (2) [Diagram 3] Cross-section of device after processing the second gate (2) [Figure 4] Cross-section of device after sidewall (3) formation [Diagram 5] Cross-section of device after bottom gate oxide film (4) formation [Figure 6] Cross-section of device after amorphous silicon deposition (5) [Figure 7] Cross-section of the device after crystallization of amorphous silicon to form poly-Si (6) [Figure 8] Cross-section of device after ion implantation (7) [Figure 9] Cross-section of device after top gate oxide film (8) formation [Figure 10] Cross-section of the device after formation of the top gate electrode (9) [Figure 11] Cross-sectional view of the device after the interlayer insulating film (10) is formed [Figure 12] Cross-section of device after contact hole (11) formation [Figure 13] Cross-sectional view of the device after forming the electrode (12) [Figure 14] Cross-sectional view of a glass substrate and a plastic substrate on which a thick oxide film (13) is formed by PECVD, followed by the deposition of a second gate (2). [Figure 15] Cross-sectional view of a device having multiple second gates (2) [Figure 16] Characteristics of the TFT created in this example [Explanation of symbols]
[0033] 1. Glass Substrate 2. Gate 2 3. Side wall 4. Bottom gate oxide (SiO2) 5. Amorphous Silicon (a-Si) 6. Polycrystalline silicon (poly-Si) 7.Ion implantation area 8. Top gate oxide film (SiO2) 9.Top gate electrode 10. Interlayer insulating film (SiO2) 11. Contact Hole 12. Electrode 13. Thick oxide film (SiO2) formed on glass
Claims
1. A semiconductor device comprising a first gate (9) positioned so as to cover a side wall of a thin film transistor (TFT) that uses the side wall of a step structure as a channel, and a second gate (2) on the opposite side of the first gate across the channel (6).
2. 2. The method according to claim 1, wherein the second gate (2) is arranged horizontally with respect to the plane of the substrate and is positioned approximately perpendicular to the sidewall.
3. 3. The second gate (2) is composed of one or more gates with an insulating film sandwiched therebetween.
4. Claims 1 to 3 are characterized in that the first gate and the second gate are operated simultaneously at the same voltage.
5. Claims 1 to 3, characterized in that the first gate and the second gate operate independently.
6. A CMOS circuit comprising a semiconductor device having the features of claims 1 to 5.
7. 7. The semiconductor layer according to any one of claims 1 to 6, characterized in that it is made of a Group IV semiconductor such as silicon or germanium, an oxide semiconductor, a compound semiconductor, an organic semiconductor, or the like.
8. 10. The display device according to claim 1, wherein the display device is formed on a transparent substrate or plastic.