Image sensor and image sensing device including the same

Abstract

To provide an image sensor and an image sensing device in which dark signal non-uniformity is improved by the high dynamic range.SOLUTION: An image sensor includes a pixel array including a plurality of unit pixels, and a driving unit disposed in its periphery and driving the unit pixels. The unit pixel includes a first region including a first transfer transistor TR1 connected to first photodiodes LPD and LPD, and a first contact connected to a first floating diffusion node FD1 and a second floating diffusion node FD2 connected to the first transfer transistor, and a second region including second transfer transistor TR7 connected to second photodiodes SPD and SPD, and a second contact electrically connected to the first contact through a metal wire and a third contact connected to the second transfer transistor and a third floating diffusion node FD3.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an image sensor and an image sensing device including the same, and more particularly to an image sensor having improved dark signal non uniformity (DSNU) in a high dynamic range and an image sensing device including the same. [Background technology]

[0002] An image sensing device is a semiconductor device that converts optical information into an electrical signal. Such image sensing devices include a charge coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device. CMOS image sensors are abbreviated as CIS (CMOS image sensor). The CIS comprises a plurality of pixels arranged two-dimensionally. Each pixel includes, for example, a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

[0003] In recent years, with the development of the computer and communications industries, the demand for improved performance image sensors has increased in a variety of fields, including digital cameras, camcorders, smartphones, game devices, security cameras, medical micro cameras, robots, and vehicles. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor having improved dark signal non uniformity (DSNU) in a high dynamic range and an image sensing device having improved image quality.

[0005] Another object of the present invention is to provide a vehicle equipped with an image sensor having image quality with improved dark signal non uniformity (DSNU) in a high dynamic range. [Means for solving the problem]

[0006] The image sensor according to the present invention, which has been made to achieve the above-mentioned object, comprises a pixel array including a plurality of unit pixels, and a driving unit arranged on a periphery of the pixel array and driving the unit pixels, wherein the unit pixels are characterized in that they include a first region including a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, and a first contact connected to a second floating diffusion node, and a second region including a second photodiode, a second transfer transistor connected to the second photodiode, a second contact electrically connected to the first contact via a connecting metal wiring, and a third contact connected to the second transfer transistor and connected to a third floating diffusion node.

[0007] In order to achieve the above object, an image sensor according to the present invention includes a pixel array including a plurality of unit pixels, and a driving unit for driving the unit pixels, wherein the unit pixels include a first region including a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, a first contact connected to a second floating diffusion node, and a second contact, and a second region including a second photodiode, a second transfer transistor connected to the second photodiode, and a third contact connected to a third floating diffusion node together with the second contact.

[0008] In order to achieve the above object, an image sensing device according to the present invention includes a pixel array including a plurality of unit pixels, and a driving unit arranged around the pixel array and driving the unit pixels, wherein the unit pixels include a first transfer transistor connected between a first photodiode and a first floating diffusion node, a PD switching transistor connected between the first floating diffusion node and a second floating diffusion node and turned on in response to a PD switching control signal, a second transfer transistor connected between a second photodiode and a third floating diffusion node, a metal capacitor connected between the third floating diffusion node and a fourth floating diffusion node, and a capacitor connection transistor connected between the fourth floating diffusion node and a first power supply line and turned on in response to a capacitor connection control signal. Effect of the Invention

[0009] The image sensor and image sensing device including the image sensor according to the present invention include a large photodiode with high sensitivity arranged in a first region and a small photodiode with low sensitivity arranged in a second region, thereby realizing HDR performance while reducing the effects of flicker events. Also, by further including a metal capacitor and storing the charge overflowing from the small photodiode in the metal capacitor, the HDR performance of the image sensor can be improved. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensing device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a top view of a pixel array according to an embodiment of the present invention. [Diagram 3] 2 is a circuit diagram of a unit pixel according to an embodiment of the present invention; [Figure 4] 4 is a signal diagram for explaining the operation of the unit pixel of FIG. 3. [Diagram 5] 2 is a circuit diagram illustrating a unit pixel according to an embodiment of the present invention; [Figure 6] FIG. 6 is a conceptual diagram for explaining the arrangement of unit pixels in FIG. 5. [Figure 7] FIG. 7 is a layout diagram showing the arrangement of unit pixels in FIG. [Figure 8] 2 is a circuit diagram illustrating a unit pixel according to an embodiment of the present invention; [Figure 9] FIG. 9 is a conceptual diagram for explaining the arrangement of unit pixels in FIG. 8. [Figure 10] FIG. 10 is a layout diagram showing the arrangement of unit pixels in FIG. [Figure 11] 1 illustrates a vehicle including an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out the image sensor and the image sensing device including the same according to the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing a schematic configuration of an image sensing device according to an embodiment of the present invention. Referring to FIG. 1, an image sensing device 1 includes an image sensor 100 and an image signal processor 200 .

[0013] The image sensor 100 senses an image of a sensing target using light and generates a pixel signal (SIG_PX). However, the present invention is not limited to the embodiments, and the image sensing device 1 may further include one or more other components. In one embodiment, the generated pixel signal (SIG_PX) may be, for example, a digital signal, although embodiments according to the inventive concept are not limited thereto. Furthermore, the pixel signal (SIG_PX) may include a particular signal voltage or a reset voltage. The pixel signal (SIG_PX) is provided to an image signal processor 200 for processing. The image signal processor 200 receives the pixel signal (SIG_PX) output from the buffer unit 1170 of the image sensor 100, and processes or manipulates the received pixel signal (SIG_PX) so that it can be easily displayed on a display.

[0014] In one embodiment, the image signal processor 200 performs digital binning on the pixel signal (SIG_PX) output from the image sensor 100 . In this case, the pixel signal (SIG_PX) output from the image sensor 100 may be a raw image signal from the pixel array PA without analog binning, or may be a pixel signal (SIG_PX) on which analog binning has already been performed. In one embodiment, the image sensor 100 and image signal processor 200 are located separately from each other as shown. For example, the image sensor 100 is mounted on a first chip, and the image signal processor 200 is mounted on a second chip, and they communicate with each other via a predetermined interface. However, the embodiment is not limited thereto, and the image sensor 100 and the image signal processor 200 may be implemented as a single package, for example, a multi-chip package (MCP).

[0015] The image sensor 100 includes a pixel array PA and a driving section. The driving section is disposed on the periphery of the pixel array and drives each unit pixel. The driving section includes, for example, a controller 1110, a timing generator 1120, a row driver 1130, a read-out circuit 1150, a ramp signal generator 1160, and a buffer section 1170. The controller 1110 controls the overall operation of the image sensor 100 . In particular, the controller 1110 transfers operating signals directly to the timing generator 1120 , the ramp signal generator 1160 , and the buffer unit 1170 .

[0016] The timing generator 1120 generates signals that serve as a reference for the operation timing of various components of the image sensor 100 . An operation timing reference signal generated by the timing generator 1120 is transmitted to the row driver 1130, the readout circuit 1150, the ramp signal generator 1160, and the like. The ramp signal generator 1160 generates and transmits a ramp signal used by the readout circuit 1150 . For example, the readout circuit 1150 may include a correlated double sampler CDS, a comparator, etc., while the ramp signal generator 1160 generates and forwards a ramp signal used by the correlated double sampler CDS, the comparator, etc.

[0017] The buffer unit 1170 includes, for example, a latch unit. The buffer unit 1170 temporarily stores the pixel signal (SIG_PX) to be provided to the outside and transfers the pixel signal (SIG_PX) to an external memory or an external device. The buffer unit 1170 includes a memory such as a DRAM or an SRAM. The pixel array PA senses an external image. The pixel array PA includes a plurality of pixels (or unit pixels). The row driver 1130 selectively activates rows of the pixel array PA. The readout circuit 1150 samples the pixel signal provided by the pixel array PA, compares it with the ramp signal, and then converts the analog image signal (data) into a digital image signal (data) based on the comparison result.

[0018] FIG. 2 is a top view of a pixel array according to an embodiment of the present invention. Referring to FIG. 2, a pixel array PA includes a plurality of unit pixels (UP). For example, a plurality of unit pixels UP are regularly arranged in a first direction X and a second direction Y. Here, the unit pixel UP is a pixel unit that receives light and outputs an image corresponding to one pixel.

[0019] A high dynamic range (HDR) used in an automotive device must meet a minimum of 120dB to 140dB, and in order to meet such a high dynamic range, an image sensor may be implemented as a unit pixel including different types of photodiodes. For example, the unit pixel UP may include at least one large photodiode and at least one small photodiode. The unit pixel UP includes a first region REG1 and a second region REG2 corresponding to a large photodiode and a small photodiode, respectively.

[0020] Here, the first region REG1 and the second region REG2 can be distinguished when viewed from above. The first region REG1 is a first polygon, for example an octagon as shown in the figure, and the second region REG2 is a second polygon, for example a rectangle as shown in the figure, but the embodiment of the present invention is not limited thereto. The first region REG1 and the second region REG2 are in contact with each other. The first region REG1 and the second region REG2 have different sensitivities. For example, the second region REG2 is embodied to have a low sensitivity, and the first region REG1 is embodied to have a higher sensitivity than the second region REG2. According to one embodiment, the area of ​​the first region REG1 is different from the area of ​​the second region REG2. For example, the area of ​​the first region REG1 is larger than the area of ​​the second region REG2. That is, the amount of light incident on the first region REG1 is greater than the amount of light incident on the second region REG2. The unit pixels UP corresponding to the first region REG1 and the second region REG2 convert light to generate electrical signals.

[0021] When implementing High Dynamic Range (HDR) by adjusting the exposure time in an image sensor, the problem of LED flicker mitigation occurs. Since LED light sources used in vehicles and road traffic operate at 90Hz or more and multiple flicker frequencies are mixed, the image sensor sets the time it takes to accumulate charge in the pixels (Effective Integration Time: hereafter referred to as EIT) to be longer than the flicker period of the LED light source to prevent loss in the actually measured signal due to the flicker component in order to remove the mixed flicker components.

[0022] In other words, the image sensor includes a large photodiode with high sensitivity arranged in the first region REG1 and a small photodiode with low sensitivity arranged in the second region REG2, thereby achieving HDR performance while reducing the effects of flicker events. In addition, the image sensor may further include a metal capacitor, and the charge overflowing from the small photodiode may be stored in the metal capacitor, thereby improving the HDR performance of the image sensor. However, when reading a signal from a metal capacitor, charge domain sampling (CDS) is not possible, so leakage current may occur in a switch transistor for the metal capacitor. As the EIT increases, the leakage current between the metal capacitor and the switch transistor increases more, which deteriorates the dark signal non-uniformity (DSNU) and reduces the signal to noise ratio (SNR).

[0023] FIG. 3 is a circuit diagram of a unit pixel according to an embodiment of the present invention. 2 and 3, the pixel circuit of a unit pixel UP constituting the pixel array PA includes a first photodiode LPD, a second photodiode SPD, a plurality of transistors, and a metal capacitor C. The plurality of transistors include transfer transistors (TR1, TR7), a source follower transistor TR2, a selection transistor TR3, a reset transistor TR5, a connection transistor TR6, a PD switching transistor TR4, and a capacitor connection transistor TR8.

[0024] The transfer transistor includes a first transfer transistor TR1 to which a first transfer signal LTG is applied and a second transfer transistor TR7 to which a second transfer signal STG is applied. The first region REG1 includes a first photodiode LPD and a first transfer transistor TR1, and the second region REG2 includes a second photodiode SPD and a second transfer transistor TR7. The first photodiode LPD corresponds to the first photoelectric conversion region (REG1 in FIG. 2), and the second photodiode SPD corresponds to the second photoelectric conversion region (REG2 in FIG. 2). The first photodiode LPD including the first photoelectric conversion region REG1 having a relatively large area in the plan view shown in FIG. 2 is called a large photodiode, and the second photodiode SPD including the second photoelectric conversion region REG2 having a relatively small area is called a small photodiode. The first region REG1 and the second region REG2 share one source follower transistor TR2, one selection transistor TR3, and one reset transistor TR5.

[0025] More specifically, the first transfer transistor TR1 is disposed between the first photodiode LPD and a first node FD1. The first node FD1 is connected to the first floating diffusion region FD1 or is itself the first floating diffusion region FD1. The gate of the first transfer transistor TR1 is connected to a first transfer line and receives a first transfer signal LTG. The source follower transistor TR2 is connected between a first power supply line VDDA providing a first power supply voltage and an output signal line VOUT. The gate of the source follower transistor TR2 is connected to a first node FD1. The selection transistor TR3 is disposed between the source follower transistor TR2 and the output signal line VOUT. The gate of the selection transistor TR3 is connected to the selection line of a corresponding row and receives a selection signal SEL.

[0026] A PD switching transistor TR4 and a reset transistor TR5 are disposed between the first node FD1 and a first power supply line VDDA providing a first power supply voltage. The common node between the PD switching transistor TR4 and the reset transistor TR5 is defined as a second node FD2. The PD switching transistor TR4 is disposed between a first node FD1 and a second node FD2. The gate of the PD switching transistor TR4 is connected to a connection signal line. The PD switching transistor TR4 serves to connect the first node FD1 and the second node FD2 in response to a PD switching control signal DRG provided from a connection signal line. The reset transistor TR5 is disposed between the first power supply line VDDA and the second node FD2. The gate of the reset transistor TR5 is connected to a reset line and receives a reset signal RG.

[0027] A second transfer transistor TR7 and a connection transistor TR6 are disposed between the second photodiode SPD and the second node FD2. The common node between the second transfer transistor TR7 and the connection transistor TR6 is defined as a third node FD3. The second transfer transistor TR7 is connected between the second photodiode SPD and the third node FD3. The third node FD3 is connected to the second node FD2. The gate of the second transfer transistor TR7 is connected to a second transfer line. The second transfer line receives a second transfer signal STG, which is a scan signal different from the first transfer signal LTG of the first transfer line, so that the first transfer transistor TR1 and the second transfer transistor TR7 are turned on and off at different times.

[0028] For example, the first transfer transistor TR1 and the second transfer transistor TR7 are turned on or off independently. However, the present invention is not limited to the embodiment, and the first transfer transistor TR1 and the second transfer transistor TR7 may be turned on or off at the same time. The connection transistor TR6 is disposed between the third node FD3 and the second node FD2. The gate of the connection transistor TR6 is connected to the switch control line. The connection transistor TR6 serves to connect the third node FD3 and the second node FD2 in response to a connection control signal SW.

[0029] According to one embodiment, a metal capacitor C is arranged between the third node FD3 and the fourth node FD4. The capacitor-connecting transistor TR8 is connected between the fourth node FD4 and the first power supply line VDDA. The capacitor connection transistor TR8 stores the charge overflowed from the second photodiode SPD in the metal capacitor C or does not store the charge in response to the capacitor connection signal TSW. However, the present invention is not limited to the embodiments, and for example, according to some embodiments, the capacitor connection transistor TR8 may not store the charge overflowing from the second photodiode SPD in the metal capacitor C in response to the capacitor connection signal TSW. According to one embodiment, the input terminal may further include a power supply connecting transistor TR9 that connects a common node between the first power supply line VDDA and the capacitor connecting transistor TR8 and a common node between the first power supply line VDDA and the reset transistor TR5 in response to a power supply connecting signal DSW.

[0030] FIG. 4 is a signal diagram for explaining the operation of the unit pixel of FIG. FIG. 4 shows the timing of signals applied to a unit pixel UP located in a row that is the target of readout at a corresponding time. At the same time, a signal different from that shown in the figure is applied to pixels UP corresponding to other rows not selected as targets for readout. For example, the signal waveforms shown before and after FIG. 4 are applied to the pixels UP corresponding to other rows not selected as the target for readout.

[0031] The timing diagram of FIG. 4 shows the waveforms of the selection signal SEL, the reset signal RG, the PD switching control signal DRG, the connection control signal SW, the capacitor connection signal TSW, the second transfer signal STG, and the first transfer signal LTG, in that order. Each signal waveform swings between a high voltage level and a low voltage level. In the illustrated embodiment, a high level voltage is described as a turn-on signal that activates the applied transistor, and a low level voltage is described as a turn-off signal that deactivates the applied transistor, but in various embodiments, it may be the other way around, where a high level voltage causes the transistor to be turned off and a low level voltage causes the transistor to be turned on.

[0032] During the time before read-out, in other words, when the selection signal SEL is at a low level, the reset signal RG, the PD switching control signal DRG, and the capacitor connection signal TSW maintain a high level, and the connection control signal SW, the second transfer signal STG, and the first transfer signal LTG maintain a low level. From point R1 to point S1, which corresponds to the first operating period, the selection signal SEL is changed to a high level, so that the reset signal RG and the PD switching control signal DRG are changed from a high level to a low level, a reset operation is performed, and the charge accumulated at the first node FD1 is converted to a first reset voltage via the source follower transistor TR2 and output to the output signal line VOUT.

[0033] In the first operating period, the first transfer signal LTG is toggled from low to high to low. While the first transfer signal LTG maintains a high level, the first transfer transistor TR1 is turned on for a predetermined time and then turned off. While the first transfer transistor TR1 is turned on, the first node FD1 is connected to the first photodiode LPD. As a result, the charge stored in the first photodiode LPD is transferred to the first floating diffusion region FD1. The charge transferred to the first floating diffusion region FD1 is converted to a first signal voltage VS1 by the source follower transistor TR2 and output to the output signal line VOUT.

[0034] Following the first operation, in the second operation section, the second signal operation S2 is performed first, and then the second reset operation R2 is performed. As the PD switching control signal DRG transitions from a low level to a high level as the time point S1 changes to a time point S2, the PD switching transistor TR4 is turned on to connect the first node FD1 and the second node FD2. After time S2, the reset signal RG is toggled from low to high to low levels, and a second reset operation is performed at time R2. The second reset operation resets both the first node FD1 and the second node FD2, which are connected together, and is converted to a second reset voltage VS2 by the source follower transistor TR2 and output to the output signal line VOUT.

[0035] Following the second operation, in the third operation section, a third reset operation R3 is first performed, and then a third signal operation S3 is performed. Between the time points R2 and R3, the connection control signal SW changes from a low level to a high level, the connection transistor TR6 is turned on, the capacitor connection signal TSW changes from a high level to a low level, and the capacitor switch transistor TR8 is turned off. Therefore, the second node FD2, the third node FD3, and the fourth node FD4 are connected to each other, and the fourth node FD4 is disconnected from the first power supply line VDDA.

[0036] As the time passes from time point R3 to time point S3, the second transfer signal STG is toggled from low to high to low. The connection control signal SW is maintained at a high level, and the capacitor connection signal TSW is maintained at a low level. While the second transfer signal STG maintains a high level, the second transfer transistor TR7 is turned on for a predetermined time and then turned off. While the second transfer transistor TR7 is turned on, the third node FD3 is connected to the second photodiode SPD. As a result, the charges stored in the second photodiode SPD are transferred to the floating diffusion region of the third node FD3, the charges stored in the third node FD3 are transferred to the second node FD2 connected by the turned-on connection transistor TR6, and the charges transferred to the second node FD2 are transferred to the first node FD1 via the turned-on switching transistor TR4.

[0037] The charge at the first node FD1 is converted to a third signal voltage VS3 via the source follower transistor TR2 and output. The third signal voltage VS3 does not include an output for the charge stored in the metal capacitor C in a state in which the capacitor-connecting transistor TR8 is turned off. In addition, since the capacitor connecting transistor TR8 connected between the first power supply line VDDA and the fourth node FD4 is turned off in response to the capacitor connecting signal TSW, no leakage current of the charge stored in the metal capacitor C is generated to the first power supply line VDDA or the power supply connecting transistor TR9.

[0038] Following the third operation, in the fourth operation section, a fourth signal operation S4 is performed first, and then a fourth reset operation R4 is performed. As the transition from time S3 to time S4 ​​occurs, the capacitor connection signal TSW transitions from a low level to a high level. As a result, the metal capacitor C is connected to the third node FD3, and the charge overflowing from the third node FD3 is stored in the metal capacitor C. When the connection transistor TR6 is turned on and the switching transistor TR4 is turned on, the first node FD1, the second node FD2, and the third node FD3 are all connected, and the charges stored in the first to third nodes (FD1, FD2, FD3) and the metal capacitor C are converted to a fourth signal voltage VS4 by the source follower transistor TR2 and output.

[0039] As the time passes from S4 to R4, the reset signal RG toggles from low to high to low, while the connection control signal SW, the PD switching control signal DRG, and the capacitor connection signal TSW maintain a high level. The connection transistor TR6, the capacitor connection transistor TR8, and the switching transistor TR4 are turned on by the connection control signal SW, the PD switching control signal DRG, and the capacitor connection signal TSW, thereby connecting the first node FD1, the second node FD2, the third node FD3, and the fourth node FD4. While the reset transistor TR5 is turned on, the first node FD1, the second node FD2, the third node FD3, and the fourth node FD4 are reset based on the first power supply line VDDA, and are converted to a fifth signal voltage VS5 by the source follower transistor TR2 and output.

[0040] After the fourth operation, when the time point R4 has elapsed, the selection signal SEL changes from high to low, and the corresponding pixel UP is deactivated. In summary, the first operation outputs the charge generated in the first photodiode LPD as the first output signal VS1, the second operation turns on the reset transistor TR5 to reset the residual charges accumulated in the first node FD1 and the second node FD2 and output them as the second output signal VS2, and the third operation outputs the charge generated in the second photodiode SPD as the third output signal VS3. The fourth operation is an operation in which the charge generated by the second photodiode SPD and overflowing from the third node FD3 is stored in the metal capacitor C and then output as a fourth output signal VS4, and the fifth operation is an operation in which, when the first to fourth operations are completed, the residual charges of the first to fourth nodes (FD1, FD2, FD3, FD4) and the metal capacitor C are reset and a fifth output signal VS5 is output.

[0041] FIG. 5 is a circuit diagram for explaining a unit pixel according to an embodiment of the present invention, FIG. 6 is a conceptual diagram for explaining the arrangement of the unit pixel of FIG. 5, and FIG. 7 is a layout diagram showing the arrangement of the unit pixel of FIG. 6. According to an embodiment, the first photodiode LPD and the second photodiode SPD of the unit pixel UP are connected to a second node FD2. Therefore, the third node FD3 can be realized with one contact.

[0042] Referring to Figures 5 and 6, the first photodiode LPD, the first transfer transistor TR1, the source follower transistor TR2, the selection transistor TR3, the reset transistor TR5, the PD switching transistor TR4, the capacitor connecting transistor TR8, the power supply connecting transistor TR9, and the first node FD1, the second node FD2, and the fourth node FD4 are arranged in a first region (REG1 in Figure 2). The second photodiode SPD, the second transfer transistor TR7, the connection transistor TR6, the metal capacitor C, and the third node FD3 are disposed in a second region (REG2 in FIG. 2). The boundary between the first region REG1 and the second region REG2 is defined by a front deep trench isolation (FDTI). The unit pixel circuit in FIG. 5 is similar to that described with reference to FIG. 3, and therefore a duplicated description of each component will be omitted.

[0043] Referring to FIG. 6, the second node FD2 is formed by a first contact FD2L formed on the first photodiode LPD side and a second contact FD2S formed on the second photodiode SPD side, and is connected via a connection metal wiring. The second region REG2 is arranged to include a second photodiode SPD, a second transfer transistor TG connected to the second photodiode SPD, a second contact FD2S connected to one end of the gate SW of the connection transistor TR6, and a third contact FD3 corresponding to a third floating diffusion node connected to the other end of the connection transistor SW1. The fourth node FD4 is connected to the third contact FD3 via the metal capacitor C, and the fourth contact corresponding to the fourth node FD4 is disposed outside the second region REG2.

[0044] Referring to FIG. 7, in one embodiment, when a first region REG1 has a hexagonal plane and a second region REG2 is arranged to have a rectangular plane, a unit pixel UP including one first region REG1 and one second region REG2 is regularly arranged as shown in the figure. The first region REG1 and the second region REG2 are separated by a deep trench insulation portion PDI filled with an insulating material. As described in FIG. 6, the first contact FD2L and the fourth contact FD4 are arranged in the first region REG1. The first contact FD2L is disposed at a position adjacent to the second region REG2 belonging to the same unit pixel UP. The first contact FD2L is electrically connected to the second contact FD2S via a connecting metal wiring and is defined as one node FD2.

[0045] According to an embodiment, a portion of the connection metal wiring may be physically connected to the first contact FD2L and the second contact FD2S. According to one embodiment, the first contact FD2L and the second contact FD2S define a second node FD2, so that the first contact FD2L is referred to as a first contact and the second contact FD2S is referred to as a second contact. As described in FIG. 6, in the second region REG2, the gate STG of the second transfer transistor TR7, the second contact FD2S, the third contact FD3, and the gate SW of the connection transistor TR6 are arranged as shown in the figure. The third contact FD3 of the second region REG2 is connected to the fourth contact FD4 via the metal capacitor C, and drains the charge accumulated in the metal capacitor C to the first power supply line VDDA during EIT (Effective Integration Time) when the transfer transistor TR7 is turned off and charge accumulates in the photodiode SPD.

[0046] FIG. 8 is a circuit diagram for explaining a unit pixel according to an embodiment of the present invention, FIG. 9 is a conceptual diagram for explaining the arrangement of the unit pixel of FIG. 8, and FIG. 10 is a layout diagram showing the arrangement of the unit pixel of FIG. 9. According to an embodiment, the first photodiode LPD and the second photodiode SPD of the unit pixel UP are connected to a third node FD3. Therefore, the third node FD3 is realized by two contacts (FD3L, FD3S).

[0047] Referring to Figures 8 and 9, the first photodiode LPD, the first transfer transistor TR1, the source follower transistor TR2, the selection transistor TR3, the reset transistor TR5, the PD switching transistor TR4, the connection transistor TR6, the capacitor connection transistor TR8, the power supply connection transistor TR9, and the first node FD1, the second node FD2, and the fourth node FD4 are arranged in a first region (REG1 in Figure 2). The second photodiode SPD, the second transfer transistor TR7, the metal capacitor C, and the third node FD3 are disposed in a second region (REG2 in FIG. 2). The boundary between the first region REG1 and the second region REG2 is defined by a front deep trench isolation (FDTI). The unit pixel circuit in FIG. 8 is similar to that explained in FIG. 3, and therefore a duplicated explanation of each component will be omitted.

[0048] Referring to FIG. 9, the third node FD3 is formed by a third contact FD3L formed on the first photodiode LPD side and a fourth contact FD3S formed on the second photodiode SPD side, and they are connected via a connection metal wiring. In the first region REG1, the connection transistor SW1, a fifth contact FD2 connected to one end of the connection transistor SW1, and a sixth contact FD3L connected to the other end of the connection transistor SW1 are arranged. The second node FD2 is a fifth contact on the first region (REG1). The sixth contact FD3L is electrically connected to the seventh contact FD3S via a connecting metal wiring and is defined as one node FD3.

[0049] In one embodiment, the first contact FD2L and the second contact FD2S may be a fifth contact FD2. In one embodiment, the sixth contact FD3L and the seventh contact FD3S may be the third contact FD3. In the second region REG2, the second photodiode SPD, the second transfer transistor TG connected to the second photodiode SPD, and the seventh contact FD3S corresponding to the third floating diffusion node are arranged. The fourth node FD4 is connected to the seventh contact FD3S via the metal capacitor C, and the fourth contact corresponding to the fourth node FD4 is disposed outside the second region REG2.

[0050] Referring to FIG. 10, in one embodiment, when a first region REG1 has a hexagonal plane and a second region REG2 is arranged to have a rectangular plane, a unit pixel UP including one first region REG1 and one second region REG2 is regularly arranged as shown in the figure. The first region REG1 and the second region REG2 are separated by a deep trench insulation portion PDI filled with an insulating material. As described with reference to FIG. 9, in the first region REG1, the gate SW of the connection transistor TR6, the gate TSW of the capacitor-connection transistor TR8, the sixth contact FD3L, and the fourth contact FD4 are arranged. The sixth contact FD3L is disposed at a position adjacent to the second region REG2 belonging to the same unit pixel UP. The sixth contact FD3L is disposed between the gate SW of the connection transistor TR6 and the gate TSW of the capacitor-connection transistor TR8.

[0051] As described in FIG. 9, in the second region REG2, the gate STG of the second transfer transistor TR7 and the seventh contact FD3S are arranged as shown in the figure. The seventh contact FD3S of the second region REG2 is connected to the fourth contact FD4 via a metal capacitor C, and drains the charge accumulated in the metal capacitor C to the first power supply line VDDA during EIT (Effective Integration Time) when the second transfer transistor TR7 is turned off and charge accumulates in the photodiode SPD. The gate SW of the connection transistor TR6 is arranged in the first region REG1 rather than in the second region REG2, which provides an advantage in terms of PnR (Place and Routing) in terms of the design area of ​​the second region REG2. For example, the second transfer transistor STG can be realized by a dual transistor.

[0052] FIG. 11 is a diagram illustrating a vehicle including an image sensor according to an embodiment of the present invention. Referring to FIG. 11, a vehicle 300 includes a plurality of electronic control units (ECUs) 310 and a storage device 320. Each electronic control device of the multiple electronic control devices 310 is electrically, mechanically, and communicatively connected to at least one of the multiple devices provided in the vehicle 300, and controls the operation of the at least one device based on any one of the function execution commands. Here, the plurality of devices includes an image sensor 330 for acquiring images required to perform at least one function, and a drive unit 340 for performing at least one function.

[0053] The image sensor 330 may be any of the image sensors according to the various embodiments described above. The image sensor 330 corresponds to an automotive image sensor. The image sensor 330 is an image sensor according to the above-described embodiment, and since there is no leakage current in the switch transistor for the metal capacitor, it is more resistant to dark signal non-uniformity (DSNU) and can provide an improved SNR. The drive unit 340 may include an air conditioner fan and compressor, a ventilation fan, a power plant engine and motor, a steering system motor, a braking system motor and valves, door and tailgate opening and closing devices, and the like. The electronic control devices 310 communicate with the image sensor 330 and the drive unit 340 using at least one of Ethernet, low-voltage differential signaling (LVDS) communication, and LIN (Local Interconnect Network) communication, for example.

[0054] The multiple electronic control devices 310 determine whether or not a function needs to be executed based on information acquired by the image sensor 330, and when it is determined that a function needs to be executed, control the operation of the drive unit 340 that executes the function, and control the amount of operation based on the acquired information. In this case, the electronic control devices 310 store the acquired images in the storage device 320 or read and use the information stored in the storage device 320 . The plurality of electronic control devices 310 control the operation of the driving unit 340 that executes the corresponding function based on a function execution command inputted through the input unit 350, confirm a setting amount corresponding to the information inputted through the input unit 350, and control the operation of the driving unit 340 that executes the corresponding function based on the confirmed setting amount. Each electronic controller 310 may independently control any one of the functions, or may cooperate with other electronic controllers to control any one of the functions.

[0055] For example, the electronic control device of the collision prevention device outputs an alarm sound for collision with the obstacle from a speaker when the distance to the obstacle detected by the distance detection unit is within a reference distance. The electronic control device of the autonomous driving control device works in cooperation with the electronic control device of the vehicle terminal, the electronic control device of the image acquisition unit, and the electronic control device of the collision prevention device to receive navigation information, road image information, and distance information to obstacles, and performs autonomous driving by controlling the power device, braking device, and steering device using the received information.

[0056] A connectivity control unit (CCU) 360 is electrically, mechanically, and communicatively connected to each of the multiple electronic control units 310, and communicates with each of the multiple electronic control units 310. In other words, the connection control device 360 ​​can communicate directly with multiple electronic control devices 310 installed inside the vehicle, can communicate with an external server, and can communicate with an external terminal via an interface. Here, the connection control device 360 ​​communicates with a plurality of electronic control devices 310, and communicates with the server 400 using an antenna (not shown) and RF communication. Moreover, the connection control device 360 ​​communicates with the server 400 via wireless communication.

[0057] In this case, wireless communication between the connection control device 360 ​​and the server 400 can be achieved using various wireless communication methods such as a Wi-Fi module, a WiBro (Wireless broadband) module, GSM (global System for Mobile Communication), CDMA (Code Division Multiple Access), WCDMA (registered trademark) (Wideband Code Division Multiple Access), UMTS (universal mobile telecommunications system), TDMA (Time Division Multiple Access), and LTE (Long Term Evolution).

[0058] The image sensor described above is a type of optical sensor, and the concept of the embodiments of the present invention can be applied to other types of sensors that use semiconductors to detect the amount of incident light, such as fingerprint sensors and distance measurement sensors, in addition to image sensors.

[0059] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0060] 1. Image sensing device 100 Image Sensor 200 Image Signal Processor 300 vehicles 310 Electronic Control Unit (ECU) 320 Storage Devices 330 Image Sensor 340 Drive Unit 350 Input section 360 Connection Control Unit (CCU) 1110 Controller 1120 Timing Generator 1130 Row Driver 1150 Readout circuit 1160 Ramp Signal Generator 1170 Buffer section PA Pixel Array REG1 1st area REG2 2nd area

Claims

1. a pixel array including a plurality of unit pixels; a driving unit arranged around the pixel array and configured to drive the unit pixels; The unit pixel is a first region including a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, and a first contact connected to a second floating diffusion node; a second region including a second photodiode, a second transfer transistor connected to the second photodiode, a second contact electrically connected to the first contact via a connecting metal wiring, and a third contact connected to the second transfer transistor and to a third floating diffusion node.

2. The image sensor of claim 1 , wherein the second region further includes a connection transistor disposed between the second contact and the third contact.

3. The unit pixel is a metal capacitor connected between the third contact and a fourth floating diffusion node; 3. The image sensor of claim 2, further comprising: a capacitor-connected transistor connected between the fourth floating diffusion node and a first power supply line.

4. The drive unit is turning on the capacitor-connected transistor during an effective integration time (EIT) of the second photodiode; 4. The image sensor according to claim 3, wherein the charge stored in the metal capacitor is drained to the first power supply line in response to a reset signal.

5. The first region is a PD switching transistor having one end connected to the second floating diffusion node and turned on in response to a PD switching control signal; a reset transistor connected between the second floating diffusion node and a first power supply line and turned on in response to a reset signal; a source follower transistor having a gate connected to the first floating diffusion node and one end connected to the first power supply line; 2. The image sensor according to claim 1, further comprising: a selection transistor connected between the other end of the source follower transistor and an output signal line, the selection transistor being turned on in response to a selection signal.

6. The image sensor of claim 5 , wherein the first region further comprises a fourth contact coupled to a fourth floating diffusion node.

7. a pixel array including a plurality of unit pixels; a driving unit for driving the unit pixel; The unit pixel is a first region including a first photodiode, a first transfer transistor connected to the first photodiode, a first floating diffusion node connected to the first transfer transistor, a first contact connected to a second floating diffusion node, and a second contact; a second region including a second photodiode, a second transfer transistor connected to the second photodiode, and a third contact connected together with the second contact to a third floating diffusion node.

8. The image sensor of claim 7 , wherein the first region further includes a connection transistor disposed between the first contact and the second contact.

9. The unit pixel is a metal capacitor connected between the third contact and a fourth floating diffusion node; 9. The image sensor of claim 8, further comprising: a capacitor-connected transistor connected between the fourth floating diffusion node and a first power supply line.

10. The drive unit is turning on the capacitor-connected transistor during an effective integration time (EIT) of the second photodiode; 10. The image sensor of claim 9, wherein the charges stored in the third floating diffusion node and the metal capacitor are drained to the first power supply line in response to a reset signal.

11. The first region is a PD switching transistor having one end connected to the second floating diffusion node and turned on in response to a PD switching control signal; a reset transistor connected between the second floating diffusion node and a first power supply line and turned on in response to a reset signal; a source follower transistor having a gate connected to the first floating diffusion node and one end connected to the first power supply line; 9. The image sensor of claim 8, further comprising: a selection transistor connected between the other end of the source follower transistor and an output signal line, the selection transistor being turned on in response to a selection signal.

12. The image sensor of claim 11 , wherein the first region further comprises a fourth contact coupled to a fourth floating diffusion node.

13. 8. The image sensor of claim 7, wherein the second transfer transistor is implemented as a dual transfer transistor.

14. a pixel array including a plurality of unit pixels; a driving unit arranged around the pixel array and configured to drive the unit pixels; The unit pixel is a first transfer transistor connected between the first photodiode and the first floating diffusion node; a PD switching transistor connected between the first floating diffusion node and the second floating diffusion node and turned on in response to a PD switching control signal; a second transfer transistor connected between the second photodiode and the third floating diffusion node; a metal capacitor connected between the third floating diffusion node and a fourth floating diffusion node; a capacitor connection transistor connected between the fourth floating diffusion node and a first power supply line, the capacitor connection transistor being turned on in response to a capacitor connection control signal.

15. The unit pixel is a source follower transistor having a gate connected to the first floating diffusion node and one end connected to the first power supply line; a reset transistor connected between the second floating diffusion node and a first power supply line and turned on in response to a reset signal; 15. The image sensing device of claim 14, further comprising: a selection transistor that is turned on in response to a selection signal to output an output signal corresponding to a signal at the other end of the source follower transistor to an output signal line.

16. The drive unit is During an effective integration time (EIT) of the second photodiode, the connection transistor is turned on and the capacitor connection transistor is turned off to accumulate charges in the third floating diffusion node; 16. The image sensing device of claim 15, wherein the capacitor connection transistor is turned on while maintaining the connection transistor turned on, and charges stored in the third floating diffusion node and the metal capacitor are converted through the source follower transistor to output an output signal to an output signal line.

17. 17. The image sensing device of claim 16, wherein the driving unit turns on the capacitor connecting transistor and the reset transistor, respectively, to drain charges stored in the third floating diffusion node and the metal capacitor to the first power supply line.

18. The unit pixel is a first region including a first contact connected to the first photodiode and the second floating diffusion node; 15. The image sensing device of claim 14, further comprising: a second region including the second photodiode, the second transfer transistor, a second contact electrically connected to the first contact via a first connection metal wiring, and a third contact connected to the third floating diffusion node.

19. The image sensing device of claim 18 , wherein the second region further comprises a connection transistor disposed between the second contact and the third contact.

20. The unit pixel is a first region including the first photodiode, the first floating diffusion node connected to the first transfer transistor, a first contact connected to the second floating diffusion node, and a second contact connected to the third floating diffusion node; 15. The image sensing device of claim 14, further comprising: a second region including the second photodiode, the second transfer transistor connected to the second photodiode, and a third contact electrically connected to the second contact via a first connection metal wiring.

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