Doherty amplifier
The Doherty amplifier's output characteristics are improved by reducing inductance values and maintaining symmetry through a specific configuration of differential amplifiers and a balun on a printed wiring board, addressing the issue of increased inductance due to longer distances in existing designs.
Patent Information
- Application Number
- JP2023182715
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-10-24
- Publication Date
- 2025-05-09
AI Technical Summary
The Doherty amplifier experiences deterioration in output characteristics due to increased inductance values between the peak amplifier's output and the synthesis point, which occurs when the synthesis point is placed on a printed wiring board, leading to longer distances and higher inductance.
A Doherty amplifier configuration that includes a semiconductor device with differential carrier and peak amplifiers and a printed wiring board with a balun to combine the output signals. The semiconductor device has specific terminals connected to the amplifiers and the balun, while the printed wiring board includes specific wirings and metal members to reduce the inductance value and maintain symmetry between the phases.
This configuration effectively suppresses the deterioration of output characteristics by reducing the inductance value and maintaining symmetry between the phases, thereby enhancing the overall performance of the Doherty amplifier.
Smart Images
Figure 2025072153000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates to Doherty amplifiers. [Background technology]
[0002] Doherty amplifiers are known as highly efficient power amplifiers. A Doherty amplifier generally has a configuration in which a carrier amplifier that operates regardless of the power level of an input signal and a peak amplifier that is turned off when the power level of the input signal is low and turned on when the power level of the input signal is high are connected in parallel. In this configuration, when the power level of a high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at the saturated output power level. This allows the Doherty amplifier to improve efficiency compared to normal power amplifiers.
[0003] The following Patent Document 1 describes a Doherty power amplifier in which a carrier amplifier and a peak amplifier are each a differential amplifier, and a phase shifter is provided between the output of the carrier amplifier and the output of the peak amplifier. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] Patent Publication No. 2022-90557 Summary of the Invention [Problem to be solved by the invention]
[0005] Let us consider the case where the Doherty amplifier described in Patent Document 1 is realized. For example, a carrier amplifier and a peak amplifier are formed on a semiconductor device (IC: Integrated Circuit). Then, this semiconductor device is mounted on a printed wiring board (PWB: Printed Wiring Board). In this way, the Doherty amplifier described in Patent Document 1 can be realized as a printed circuit board (PCB: Printed Circuit Board).
[0006] However, if the combining point of the carrier amplifier output and the peak amplifier output is located within the PWB, the distance between the peak amplifier output and the combining point becomes longer and the inductance value between the peak amplifier output and the combining point increases, resulting in degradation of the output characteristics.
[0007] The present disclosure has been made in consideration of the above, and aims to suppress degradation of the output characteristics of a Doherty amplifier. [Means for solving the problem]
[0008] A Doherty amplifier according to one aspect of the present disclosure includes a semiconductor device in which a carrier amplifier and a peak amplifier, each of which is a differential amplifier including a first-phase amplifier and a second-phase amplifier, are formed, and a printed wiring board in which a balun is formed for combining an output signal of the carrier amplifier and an output signal of the peak amplifier. The semiconductor device includes a first terminal electrically connected to an output terminal of the first-phase amplifier of the carrier amplifier, a second terminal electrically connected to an output terminal of the second-phase amplifier of the carrier amplifier, a third terminal electrically connected to the output terminal of the first-phase amplifier of the peak amplifier and electrically connected to one end of the balun, a fourth terminal electrically connected to the output terminal of the second-phase amplifier of the peak amplifier and electrically connected to the other end of the balun, a fifth terminal electrically connected to the output terminal of the first-phase amplifier of the peak amplifier, and a sixth terminal electrically connected to the output terminal of the second-phase amplifier of the peak amplifier. The printed wiring board includes a first wiring and a second wiring. The Doherty amplifier includes a first metal member electrically connecting one end of the first wiring and the first terminal, a second metal member electrically connecting one end of the second wiring and the second terminal, a third metal member electrically connecting the other end of the first wiring and the fifth terminal, and a fourth metal member electrically connecting the other end of the second wiring and the sixth terminal. Effect of the Invention
[0009] According to the present disclosure, it is possible to suppress deterioration of the output characteristics of a Doherty amplifier. [Brief description of the drawings]
[0010] [Figure 1] FIG. 1 is a diagram showing a circuit configuration common to the Doherty amplifiers of the embodiment and the comparative example. [Diagram 2] FIG. 2 is a diagram showing a layout of a Doherty amplifier of the comparative example. [Diagram 3] FIG. 3 is a diagram showing a layout of the Doherty amplifier according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing a layout of the Doherty amplifier according to the first embodiment. [Diagram 5] FIG. 5 is a diagram showing a layout of the Doherty amplifier according to the second embodiment. [Figure 6] FIG. 6 is a diagram showing a layout of the Doherty amplifier according to the second embodiment. [Figure 7] FIG. 7 is a diagram showing a layout of the Doherty amplifier according to the third embodiment. [Figure 8] FIG. 8 is a diagram showing a layout of the Doherty amplifier according to the third embodiment. [Figure 9] FIG. 9 is a diagram showing a layout of the Doherty amplifier according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing a layout of the Doherty amplifier according to the fourth embodiment. [Figure 11] FIG. 11 is a diagram showing a layout of the Doherty amplifier according to the fifth embodiment. [Figure 12] FIG. 12 is a diagram showing a layout of the Doherty amplifier according to the fifth embodiment. [Figure 13] FIG. 13 is a diagram showing a layout of the Doherty amplifier according to the sixth embodiment. [Figure 14] FIG. 14 is a diagram showing a layout of the Doherty amplifier according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.
[0012] <First embodiment> (Circuit configuration common to the embodiment and comparative example) FIG. 1 is a diagram showing a circuit configuration common to the Doherty amplifiers of the embodiment and the comparative example.
[0013] The Doherty amplifier 1 is a differential amplifier. A first phase radio frequency signal RFin1-1 and a second phase radio frequency signal RFin1-2, which are a first differential signal, are input to the Doherty amplifier 1. In addition, a first phase radio frequency signal RFin2-1 and a second phase radio frequency signal RFin2-2, which are a second differential signal, are input to the Doherty amplifier 1. The Doherty amplifier 1 amplifies the first phase radio frequency signal RFin1-1 to the second phase radio frequency signal RFin2-2, and outputs a radio frequency signal RFout.
[0014] The Doherty amplifier 1 includes a carrier amplifier 2, a peaking amplifier 3, a phase shifter 4, and a balun 5.
[0015] Each of the carrier amplifier 2 and the peak amplifier 3 is a differential amplifier. The carrier amplifier 2 includes a first-phase amplifier 2-1 and a second-phase amplifier 2-2. The peak amplifier 3 includes a first-phase amplifier 3-1 and a second-phase amplifier 3-2.
[0016] In the embodiment, the first phase is a negative phase (negative polarity) and the second phase is a positive phase (positive polarity), but the present disclosure is not limited thereto. The first phase may be a positive phase and the second phase may be a negative phase.
[0017] The first-phase amplifier 2-1 of the carrier amplifier 2 includes a transistor Q1. The emitter of the transistor Q1 is electrically connected to a reference potential. The reference potential is exemplified by a ground potential, but the present disclosure is not limited thereto. A first-phase high-frequency signal RFin1-1 and a base bias current (not shown) are input to the base of the transistor Q1. A collector of the transistor Q1 is electrically connected to a power supply potential via a choke coil. The transistor Q1 amplifies the first-phase high-frequency signal RFin1-1 input to the base, and outputs the amplified first-phase high-frequency signal RF1-1 from the collector.
[0018] The second-phase amplifier 2-2 of the carrier amplifier 2 includes a transistor Q2. The emitter of the transistor Q2 is electrically connected to a reference potential. The second-phase high-frequency signal RFin1-2 and a base bias current (not shown) are input to the base of the transistor Q2. The collector of the transistor Q2 is electrically connected to a power supply potential via a choke coil. The transistor Q2 amplifies the second-phase high-frequency signal RFin1-2 input to the base, and outputs the amplified second-phase high-frequency signal RF1-2 from the collector.
[0019] The first-phase amplifier 3-1 of the peak amplifier 3 includes a transistor Q3. The emitter of the transistor Q3 is electrically connected to a reference potential. The first-phase high-frequency signal RFin2-1 and a base bias current (not shown) are input to the base of the transistor Q3. The collector of the transistor Q3 is electrically connected to a power supply potential via a choke coil. The transistor Q3 amplifies the first-phase high-frequency signal RFin2-1 input to the base, and outputs the amplified first-phase high-frequency signal RF2-1 from the collector.
[0020] The second-phase amplifier 3-2 of the peak amplifier 3 includes a transistor Q4. The emitter of the transistor Q4 is electrically connected to a reference potential. The second-phase high-frequency signal RFin2-2 and a base bias current (not shown) are input to the base of the transistor Q4. The collector of the transistor Q4 is electrically connected to a power supply potential via a choke coil. The transistor Q4 amplifies the second-phase high-frequency signal RFin2-2 input to the base, and outputs the amplified second-phase high-frequency signal RF2-2 from the collector.
[0021] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited thereto. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that constitutes a transistor.
[0022] When each transistor is a FET, the source corresponds to the emitter of the bipolar transistor, the gate corresponds to the base of the bipolar transistor, and the drain corresponds to the collector of the bipolar transistor.
[0023] The phase shifter 4 includes an inductor 11 and an inductor 12. The inductor 11 and the inductor 12 can also be realized by a transmission line (for example, a wiring). The phase shifter 4 may further include a capacitor 13.
[0024] When phase shifter 4 includes capacitor 13 , one end of capacitor 13 is electrically connected to one end of inductor 11 , and the other end of capacitor 13 is electrically connected to one end of inductor 12 .
[0025] When phase shifter 4 includes capacitor 13, capacitor 13 may be formed in semiconductor device 31 (described later) or in printed wiring board 32 (described later).
[0026] One end of the inductor 11 is electrically connected to the collector of the transistor Q1. The other end of the inductor 11 is electrically connected to a node N1. The inductor 11 delays the phase of the first phase high frequency signal RF1-1 and outputs it to the node N1.
[0027] One end of the inductor 12 is electrically connected to the collector of the transistor Q2. The other end of the inductor 12 is electrically connected to a node N2. The inductor 12 delays the phase of the second phase high frequency signal RF1-2 and outputs it to the node N2.
[0028] The collector of the transistor Q3 is electrically connected to a node N1. At the node N1, the first phase high frequency signal RF1-1 and the first phase high frequency signal RF2-1 after passing through the phase shifter 4 are superimposed on each other. In other words, the node N1 is a combining point where the first phase high frequency signal RF1-1 and the first phase high frequency signal RF2-1 are combined.
[0029] The collector of the transistor Q4 is electrically connected to a node N2. At the node N2, the second phase high frequency signal RF1-2 and the second phase high frequency signal RF2-2 after passing through the phase shifter 4 are superimposed on each other. In other words, the node N2 is a combining point where the second phase high frequency signal RF1-2 and the second phase high frequency signal RF2-2 are combined.
[0030] The balun 5 includes a first winding 21 and a second winding 22 .
[0031] One end of the first winding 21 is electrically connected to a node N1. The other end of the first winding 21 is electrically connected to a node N2. The second winding 22 is magnetically coupled to the first winding 21. A high frequency signal RFout is output from one end of the second winding 22. The other end of the second winding 22 is electrically connected to a reference potential.
[0032] (Layout of Comparative Example) Fig. 2 is a diagram showing the layout of a Doherty amplifier of a comparative example, Fig. 2 is an explanatory diagram showing a schematic diagram of the connection relationship of wiring and the like when the Doherty amplifier 200 of the comparative example is viewed in a direction parallel to the main surface thereof.
[0033] The Doherty amplifier 200 is a printed circuit board in which a semiconductor device 31 is mounted on a printed wiring board 32. The semiconductor device 31 and the printed wiring board 32 have their main surfaces aligned along the XY plane.
[0034] The semiconductor device 31 includes transistors Q1 to Q4.
[0035] The transistor Q1 and the transistor Q2 are arranged next to each other, taking into consideration the symmetry of inductance. The transistor Q1 and the transistor Q2 are arranged next to each other, meaning that no other transistors are arranged between the transistor Q1 and the transistor Q2, and it does not prevent the presence of elements other than transistors. Similarly, the transistor Q3 and the transistor Q4 are arranged next to each other. The transistor Q2 and the transistor Q3 are arranged next to each other.
[0036] That is, the transistors Q1 to Q4 are arranged in this order on a straight line along the X-axis direction.
[0037] A metal portion 111 is formed on the bottom surface of the semiconductor device 31 (the surface facing the printed wiring board 32, the surface facing the opposite direction to the Z-axis direction, the surface below the paper). The metal portion 111 is exemplified by a land of a metal layer of the semiconductor device 31. The metal portion 111 is electrically connected to the collector of the transistor Q1. A bump 121 is formed on the bottom of the metal portion 111 (the side facing the printed wiring board 32, the side facing the Z-axis direction, the surface below the paper). The bump 121 is electrically connected to the metal portion 111.
[0038] The metal portion 111 corresponds to an example of a "first terminal" in the present disclosure. The bump 121 corresponds to an example of a "first metal member" in the present disclosure.
[0039] A metal portion 112 is formed on the bottom surface of the semiconductor device 31. The metal portion 112 is exemplified by a land of a metal layer of the semiconductor device 31. The metal portion 112 is electrically connected to the collector of the transistor Q2. A bump 122 is formed on the bottom of the metal portion 112. The bump 122 is electrically connected to the metal portion 112.
[0040] The metal portion 112 corresponds to an example of a "second terminal" in the present disclosure. The bump 122 corresponds to an example of a "second metal member" in the present disclosure.
[0041] A metal portion 113 is formed on the bottom surface of the semiconductor device 31. The metal portion 113 is exemplified by a land of a metal layer of the semiconductor device 31. The metal portion 113 is electrically connected to the collector of the transistor Q3. A bump 123 is formed below the metal portion 113. The bump 123 is electrically connected to the metal portion 113.
[0042] Metal portion 113 corresponds to an example of a "third terminal" in the present disclosure.
[0043] A metal portion 114 is formed on the bottom surface of the semiconductor device 31. The metal portion 114 is exemplified by a land of a metal layer of the semiconductor device 31. The metal portion 114 is electrically connected to the collector of the transistor Q4. A bump 124 is formed below the metal portion 114. The bump 124 is electrically connected to the metal portion 114.
[0044] The metal portion 114 corresponds to an example of a "fourth terminal" of the present disclosure.
[0045] Metal portion 111 to metal portion 114 are arranged in this order on a straight line along the X-axis direction. Bumps 121 to 124 are arranged in this order on a straight line along the X-axis direction.
[0046] In this disclosure, each metal portion may be referred to as a metal electrode or an under bump metal (UBM). Each metal portion is formed of a material including at least one of Ti, Cr, Cu, Au, Ni, and Pd, for example.
[0047] In the present disclosure, each bump is, for example, a pillar bump, and is made of, for example, copper (Cu). Each bump may be made of low-resistance metal materials such as aluminum (Al) or gold (Au) in addition to copper. Each bump may be, for example, a solder bump or a stud bump.
[0048] The semiconductor device 31 is electrically connected to the printed wiring board 32 via bumps 121 to 124 .
[0049] Vias 131 to 134 are formed in printed wiring board 32. One end of via 131 is electrically connected to bump 121. One end of via 132 is electrically connected to bump 122. One end of via 133 is electrically connected to bump 123. One end of via 134 is electrically connected to bump 124.
[0050] When capacitor 13 (see FIG. 1) is provided, one end of capacitor 13 is, for example, electrically connected to the other end of via 131. The other end of capacitor 13 is, for example, electrically connected to the other end of via 132. Capacitor 13 may be an SMD (Surface Mount Device) mounted on the surface of printed wiring board 32, or may be formed by two metal layers of printed wiring board 32.
[0051] The other end of the via 133 is electrically connected to one end of the first winding 21 of the balun 5. The other end of the via 134 is electrically connected to the other end of the first winding 21 of the balun 5.
[0052] A wiring 141 is formed on a first metal layer of the printed wiring board 32 (the metal layer closest to the semiconductor device 31, the metal layer furthest in the Z-axis direction, the metal layer at the top of the paper).
[0053] The wiring 141 corresponds to the inductor 11 (see FIG. 1). The wiring 141 corresponds to an example of a "first wiring" in the present disclosure.
[0054] One end of the wiring 141 is electrically connected to the other end of the via 131. The other end of the wiring 141 is electrically connected between one end and the other end of the via 133. The connection point between the wiring 141 and the via 133 is a combination point 211 where the first phase high frequency signal RF1-1 output from the transistor Q1 and the first phase high frequency signal RF2-1 output from the transistor Q3 are combined.
[0055] That is, in the Doherty amplifier 200 , the combining point 211 is provided in the printed wiring board 32 .
[0056] Wiring 142 is formed on a second metal layer of printed wiring board 32 (a metal layer one layer farther from semiconductor device 31 than the first metal layer, a metal layer next to the first metal layer and in the opposite direction to the Z-axis direction, and a metal layer one layer below the first metal layer on the paper).
[0057] The wiring 142 corresponds to the inductor 12 (see FIG. 1). The wiring 142 corresponds to an example of the "second wiring" of the present disclosure.
[0058] One end of the wiring 142 is electrically connected to the other end of the via 132. The other end of the wiring 142 is electrically connected between one end and the other end of the via 134. The connection point between the wiring 142 and the via 134 is a combination point 212 where the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 are combined.
[0059] That is, in the Doherty amplifier 200 , the combining point 212 is provided in the printed wiring board 32 .
[0060] In the Doherty amplifier 200, the longer the distance 221 between the bump 123 and the combining point 211, the larger the inductance value between the collector of the transistor Q3 and the combining point 211. Similarly, the longer the distance 222 between the bump 124 and the combining point 212, the larger the inductance value between the collector of the transistor Q4 and the combining point 212. Since the Doherty amplifier 200 has a large inductance value, the output characteristics are degraded.
[0061] (Layout of the first embodiment) 3 and 4 are diagrams showing the layout of the Doherty amplifier of the first embodiment. Fig. 3 is a schematic plan view of the Doherty amplifier 1A of the first embodiment as viewed from a direction perpendicular to the main surface. Fig. 4 is an explanatory diagram for explaining the connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1A.
[0062] 3 and 4, compared to the Doherty amplifier 200, the Doherty amplifier 1A has a semiconductor device 31A instead of the semiconductor device 31. Also, compared to the Doherty amplifier 200, the Doherty amplifier 1A has a printed wiring board 32A instead of the printed wiring board 32.
[0063] Compared to semiconductor device 31, the underside of semiconductor device 31A (the surface facing printed wiring board 32A, the surface opposite the Z-axis direction, the surface below the paper) further includes metal portion 115 and metal portion 116.
[0064] Metal portion 115 is electrically connected to metal portion 113. That is, metal portion 115 is electrically connected to the collector of transistor Q3. Metal portion 116 is electrically connected to metal portion 114. That is, metal portion 116 is electrically connected to the collector of transistor Q4.
[0065] The metal portion 115 corresponds to an example of a "fifth terminal" in the present disclosure, and the metal portion 116 corresponds to an example of a "sixth terminal" in the present disclosure.
[0066] In the embodiment, each of metal portion 115 and metal portion 116 has a spherical shape, but the present disclosure is not limited to this.
[0067] Metal portion 115 may be formed integrally with metal portion 113. That is, metal portion 115 and metal portion 113 may be configured from a single piece of metal. Metal portion 116 may be formed integrally with metal portion 114. That is, metal portion 116 and metal portion 114 may be configured from a single piece of metal.
[0068] The metal portion 115 is formed on the side of the metal portion 113 opposite to the X-axis direction. In other words, the metal portion 115 is formed on the metal portion 113 on the metal portion 111 side.
[0069] The metal portion 116 is formed on the side of the metal portion 114 opposite to the X-axis direction. In other words, the metal portion 116 is formed on the metal portion 112 side of the metal portion 114.
[0070] Hereinafter, the fact that metal portion 115 is formed on the side opposite to the X-axis direction from metal portion 113, and that metal portion 116 is formed on the side opposite to the X-axis direction from metal portion 114, will be referred to as "metal portion 115 and metal portion 116 are formed in the same direction."
[0071] 4, a bump 125 is formed on the lower part of metal part 115 (the side facing printed wiring board 32A, the side opposite the Z-axis direction, the lower side of the paper). Bump 125 is electrically connected to metal part 115. A bump 126 is formed on the lower part of metal part 116. Bump 126 is electrically connected to metal part 116.
[0072] The bump 125 corresponds to an example of a "third metal member" in the present disclosure. The bump 126 corresponds to an example of a "fourth metal member" in the present disclosure.
[0073] The semiconductor device 31 is electrically connected to the printed wiring board 32A via bumps 121 to 126.
[0074] The first winding 21 of the balun 5 is formed in the first metal layer of the printed wiring board 32A (the metal layer closest to the semiconductor device 31A, the metal layer furthest in the Z-axis direction, and the metal layer at the top of the paper). One end of the first winding 21 is electrically connected to a bump 123. The other end of the first winding 21 is electrically connected to a bump 124. The second winding 22 of the balun 5 is formed in the second metal layer of the printed wiring board 32A (the metal layer one layer farther from the semiconductor device 31A than the first metal layer, the metal layer next to the first metal layer and in the opposite direction to the Z-axis direction, and the metal layer one layer below the first metal layer on the paper).
[0075] The wiring 141 is formed in the second metal layer. The wiring 142 is formed in a third metal layer (a metal layer one layer farther from the semiconductor device 31A than the second metal layer, a metal layer adjacent to the second metal layer and in the opposite direction to the Z-axis direction, and a metal layer one layer below the second metal layer on the paper surface).
[0076] One end of the via 133 is electrically connected to the bump 125. One end of the via 134 is electrically connected to the bump 126.
[0077] The other end of the wiring 141 is electrically connected to the other end of the via 133 .
[0078] As a result, the metal portion 115 serves as a synthesis point between the first phase high frequency signal RF1-1 output from the transistor Q1 and the first phase high frequency signal RF2-1 output from the transistor Q3.
[0079] That is, in the Doherty amplifier 1A, the combining point (metal portion 115) is provided in the semiconductor device 31A.
[0080] The other end of the wiring 142 is electrically connected to the other end of the via 134 .
[0081] As a result, the metal portion 116 serves as a synthesis point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4.
[0082] That is, in the Doherty amplifier 1A, the combining point (metal portion 116) is provided in the semiconductor device 31A.
[0083] (effect) [1] In the Doherty amplifier 1A, the combination point of the first phase radio frequency signal RF1-1 output from the transistor Q1 and the first phase radio frequency signal RF2-1 output from the transistor Q3 is the metal portion 115 in the semiconductor device 31A. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal portion 115) is small.
[0084] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31A. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0085] Therefore, the Doherty amplifier 1A can suppress deterioration of the output characteristics.
[0086] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1A to obtain symmetry between the first and second phases.
[0087] Therefore, the Doherty amplifier 1A can suppress deterioration of the output characteristics.
[0088] [3] The metal portion 115 and the metal portion 116 are formed in the same direction.
[0089] This makes it easier for the Doherty amplifier 1A to achieve symmetry.
[0090] [4] The metal portion 115 and the metal portion 116 are formed in the same direction. This allows the Doherty amplifier 1A to suppress the difference in length between the wiring 141 and the wiring 142. That is, the Doherty amplifier 1A can easily obtain symmetry between the first phase and the second phase.
[0091] Therefore, the Doherty amplifier 1A can suppress deterioration of the output characteristics.
[0092] [5] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. This allows the Doherty amplifier 1A to shorten the wiring 141. Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. This allows the Doherty amplifier 1A to shorten the wiring 142.
[0093] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. Metal portion 116 is formed on the metal portion 112 side of metal portion 114. This allows the circuit of Doherty amplifier 1A to be more compact than when metal portion 115 and metal portion 116 are formed in directions other than the metal portion 111 side and the metal portion 112 side, respectively.
[0094] Therefore, the Doherty amplifier 1A can easily obtain symmetry and suppress deterioration of the output characteristics. Also, the Doherty amplifier 1A can reduce the circuit size.
[0095] <Second embodiment> Fig. 5 and Fig. 6 are diagrams showing the layout of the Doherty amplifier of the second embodiment. Fig. 5 is a schematic plan view of the Doherty amplifier 1B of the second embodiment as viewed from a direction perpendicular to the main surface. Fig. 6 is an explanatory diagram for explaining the connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1B.
[0096] 5 and 6, compared to the Doherty amplifier 1A, the Doherty amplifier 1B has a semiconductor device 31B instead of the semiconductor device 31A. Also, compared to the Doherty amplifier 1A, the Doherty amplifier 1B has a printed wiring board 32B instead of the printed wiring board 32A.
[0097] The transistor Q1 and the transistor Q3 are arranged next to each other. The transistor Q3 and the transistor Q2 are arranged next to each other. The transistor Q2 and the transistor Q4 are arranged next to each other.
[0098] That is, the transistor Q1, the transistor Q3, the transistor Q2, and the transistor Q4 are arranged in this order on a straight line along the X-axis direction.
[0099] The metal portion 111, the metal portion 113, the metal portion 112, and the metal portion 114 are arranged in this order on a straight line along the X-axis direction. The bumps 121, 123, 122, and 124 are arranged in this order on a straight line along the X-axis direction.
[0100] Metal portion 115 is formed on the side opposite to the X-axis direction from metal portion 113. Metal portion 116 is formed on the side opposite to the X-axis direction from metal portion 114.
[0101] In other words, the metal portion 115 and the metal portion 116 are formed in the same direction.
[0102] The first winding 21 of the balun 5 is formed in the first metal layer of the printed wiring board 32B (the metal layer closest to the semiconductor device 31B, the metal layer furthest in the Z-axis direction, and the metal layer at the top of the paper). One end of the first winding 21 is electrically connected to a bump 123. The other end of the first winding 21 is electrically connected to a bump 124. The second winding 22 of the balun 5 is formed in the second metal layer of the printed wiring board 32B (the metal layer one layer farther from the semiconductor device 31B than the first metal layer, the metal layer next to the first metal layer and in the opposite direction to the Z-axis direction, and the metal layer one layer below the first metal layer on the paper).
[0103] The wiring 141 and the wiring 142 are formed in a first metal layer.
[0104] One end of the via 131 is electrically connected to the bump 121. One end of the via 133 is electrically connected to the bump 125.
[0105] One end of the wiring 141 is electrically connected to the other end of the via 131. The other end of the wiring 141 is electrically connected to the other end of the via 133.
[0106] One end of the via 132 is electrically connected to the bump 122. One end of the via 134 is electrically connected to the bump 126.
[0107] One end of the wiring 142 is electrically connected to the other end of the via 132. The other end of the wiring 142 is electrically connected to the other end of the via .
[0108] (effect) [1] In the Doherty amplifier 1B, the combination point of the first phase high frequency signal RF1-1 output from the transistor Q1 and the first phase high frequency signal RF2-1 output from the transistor Q3 is the metal part 115 in the semiconductor device 31B. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal part 115) is small.
[0109] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31B. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0110] Therefore, the Doherty amplifier 1B can suppress deterioration of the output characteristics.
[0111] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1B to obtain symmetry between the first and second phases.
[0112] Therefore, the Doherty amplifier 1B can suppress deterioration of the output characteristics.
[0113] [3] The metal portion 115 and the metal portion 116 are formed in the same direction.
[0114] This allows the Doherty amplifier 1B to have a smaller circuit size than when the metal portion 115 and the metal portion 116 are formed in different directions.
[0115] [4] The metal portion 115 and the metal portion 116 are formed in the same direction. This allows the Doherty amplifier 1B to suppress the difference in length between the wiring 141 and the wiring 142. That is, the Doherty amplifier 1B makes it easier to obtain symmetry between the first phase and the second phase.
[0116] Therefore, the Doherty amplifier 1B can suppress deterioration of the output characteristics.
[0117] [5] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. Metal portion 115 is formed adjacent to metal portion 111. Furthermore, wiring 141 is formed in the first metal layer. This allows Doherty amplifier 1B to shorten wiring 141.
[0118] Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. Metal portion 116 is formed adjacent to metal portion 112. Moreover, wiring 142 is formed in the first metal layer. This allows Doherty amplifier 1B to shorten wiring 142.
[0119] Therefore, the Doherty amplifier 1B can suppress the deterioration of the output characteristics. Also, the Doherty amplifier 1B can reduce the size of the circuit.
[0120] <Third embodiment> 7 and 8 are diagrams showing the layout of a Doherty amplifier according to a third embodiment. Fig. 7 is a schematic plan view of a Doherty amplifier 1C according to the third embodiment as viewed from a direction perpendicular to a main surface of the amplifier. Fig. 8 is an explanatory diagram for explaining a schematic connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1C.
[0121] 7 and 8, compared to the Doherty amplifier 1B, the Doherty amplifier 1C has a semiconductor device 31C instead of the semiconductor device 31B. Also, compared to the Doherty amplifier 1B, the Doherty amplifier 1C has a printed wiring board 32C instead of the printed wiring board 32B.
[0122] The transistor Q1 and the transistor Q3 are arranged next to each other. The transistor Q3 and the transistor Q4 are arranged next to each other. The transistor Q4 and the transistor Q2 are arranged next to each other.
[0123] That is, the transistor Q1, the transistor Q3, the transistor Q4, and the transistor Q2 are arranged in this order on a straight line along the X-axis direction.
[0124] The metal portion 111, the metal portion 113, the metal portion 114, and the metal portion 112 are arranged in this order on a straight line along the X-axis direction. The bumps 121, 123, 124, and 122 are arranged in this order on a straight line along the X-axis direction.
[0125] Metal portion 115 is formed on the side opposite to the X-axis direction of metal portion 113. Metal portion 116 is formed on the X-axis direction side of metal portion 114.
[0126] Hereinafter, the fact that metal part 115 is formed on the side opposite to metal part 113 in the X-axis direction, and that metal part 116 is formed on the X-axis side of metal part 114, will be referred to as "metal part 115 and metal part 116 are formed in opposite directions."
[0127] The first winding 21 of the balun 5 is formed in the first metal layer of the printed wiring board 32C (the metal layer closest to the semiconductor device 31C, the metal layer furthest in the Z-axis direction, and the metal layer at the top of the paper). One end of the first winding 21 is electrically connected to a bump 123. The other end of the first winding 21 is electrically connected to a bump 124. The second winding 22 of the balun 5 is formed in the second metal layer of the printed wiring board 32C (the metal layer one layer farther from the semiconductor device 31C than the first metal layer, the metal layer next to the first metal layer and in the opposite direction to the Z-axis direction, and the metal layer one layer below the first metal layer on the paper).
[0128] The wiring 141 and the wiring 142 are formed in a first metal layer.
[0129] One end of the via 131 is electrically connected to the bump 121. One end of the via 133 is electrically connected to the bump 125.
[0130] One end of the wiring 141 is electrically connected to the other end of the via 131. The other end of the wiring 141 is electrically connected to the other end of the via 133.
[0131] One end of the via 132 is electrically connected to the bump 122. One end of the via 134 is electrically connected to the bump 126.
[0132] One end of the wiring 142 is electrically connected to the other end of the via 132. The other end of the wiring 142 is electrically connected to the other end of the via .
[0133] (effect) [1] In the Doherty amplifier 1C, the combination point of the first phase radio frequency signal RF1-1 output from the transistor Q1 and the first phase radio frequency signal RF2-1 output from the transistor Q3 is the metal portion 115 in the semiconductor device 31C. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal portion 115) is small.
[0134] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31C. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0135] Therefore, the Doherty amplifier 1C can suppress deterioration of the output characteristics.
[0136] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1C to obtain symmetry between the first and second phases.
[0137] Therefore, the Doherty amplifier 1C can suppress deterioration of the output characteristics.
[0138] [3] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. In other words, metal portion 115 is formed next to metal portion 111. Also, wiring 141 is formed in the first metal layer. This allows wiring 141 to be short in the Doherty amplifier 1C.
[0139] Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. In other words, metal portion 116 is formed next to metal portion 112. Moreover, wiring 142 is formed in the first metal layer. This allows the Doherty amplifier 1C to shorten wiring 142.
[0140] Therefore, the Doherty amplifier 1C can suppress the deterioration of the output characteristics and can reduce the circuit size.
[0141] [4] The metal portion 113 and the metal portion 114 are formed next to each other. This enables the Doherty amplifier 1C to shorten the distance between the metal portion 113 and the metal portion 114.
[0142] Therefore, in the Doherty amplifier 1C, the balun 5 can be made smaller, and the circuit can be made smaller.
[0143] <Fourth embodiment> 9 and 10 are diagrams showing the layout of the Doherty amplifier according to the fourth embodiment. Fig. 9 is a schematic plan view of the Doherty amplifier 1D according to the fourth embodiment as viewed from a direction perpendicular to the main surface. Fig. 10 is an explanatory diagram for explaining the connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1D.
[0144] 9 and 10, compared to the Doherty amplifier 1A, the Doherty amplifier 1D has a semiconductor device 31D instead of the semiconductor device 31A. Also, compared to the Doherty amplifier 1A, the Doherty amplifier 1D has a printed wiring board 32D instead of the printed wiring board 32A.
[0145] Compared to the semiconductor device 31A, the semiconductor device 31D does not have the bumps 121 to 126.
[0146] Printed wiring board 32D is different from printed wiring board 32A in that electrodes 161 to 166 are formed on the front surface (the surface facing semiconductor device 31D, the surface in the Z-axis direction).
[0147] The electrodes 161, 162, 165, 163, 166, and 164 are arranged in this order on a straight line along the X-axis direction.
[0148] One end of the via 131 is electrically connected to the electrode 161. One end of the via 132 is electrically connected to the electrode 162. One end of the via 133 is electrically connected to the electrode 165. One end of the via 134 is electrically connected to the electrode 166. One end of the first winding 21 of the balun 5 is electrically connected to the electrode 163. The other end of the first winding 21 of the balun 5 is electrically connected to the electrode 164.
[0149] The metal portion 111 and the electrode 161 are electrically connected via wires 151 and 152. The metal portion 112 and the electrode 162 are electrically connected via wires 153 and 154. The metal portion 115 and the electrode 165 are electrically connected via wire 159. The metal portion 113 and the electrode 163 are electrically connected via wires 155 and 156. The metal portion 116 and the electrode 166 are electrically connected via wire 160. The metal portion 114 and the electrode 164 are electrically connected via wires 157 and 158.
[0150] In the present disclosure, each wire is exemplified by gold (Au).
[0151] (effect) [1] In the Doherty amplifier 1D, the combination point of the first phase radio frequency signal RF1-1 output from the transistor Q1 and the first phase radio frequency signal RF2-1 output from the transistor Q3 is the metal portion 115 in the semiconductor device 31D. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal portion 115) is small.
[0152] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31D. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0153] Therefore, the Doherty amplifier 1D can suppress deterioration of the output characteristics.
[0154] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1D to obtain symmetry between the first and second phases.
[0155] Therefore, the Doherty amplifier 1D can suppress deterioration of the output characteristics.
[0156] [3] The metal portion 115 and the metal portion 116 are formed in the same direction.
[0157] This allows the Doherty amplifier 1D to have a smaller circuit size than when the metal portion 115 and the metal portion 116 are formed in different directions.
[0158] [4] The metal portion 115 and the metal portion 116 are formed in the same direction. This allows the Doherty amplifier 1D to suppress the difference in length between the wiring 141 and the wiring 142. That is, the Doherty amplifier 1D can easily obtain symmetry between the first phase and the second phase.
[0159] Therefore, the Doherty amplifier 1D can suppress deterioration of the output characteristics.
[0160] [5] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. This allows the Doherty amplifier 1D to shorten the wiring 141. Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. This allows the Doherty amplifier 1D to shorten the wiring 142.
[0161] Therefore, the Doherty amplifier 1D can suppress the deterioration of the output characteristics and can reduce the circuit size.
[0162] <Fifth embodiment> Fig. 11 and Fig. 12 are diagrams showing the layout of the Doherty amplifier according to the fifth embodiment. Fig. 11 is a schematic plan view of the Doherty amplifier 1E according to the fifth embodiment as viewed from a direction perpendicular to the main surface. Fig. 12 is an explanatory diagram for explaining the connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1E.
[0163] 11 and 12, compared to the Doherty amplifier 1B, the Doherty amplifier 1E has a semiconductor device 31E instead of the semiconductor device 31B. Also, compared to the Doherty amplifier 1B, the Doherty amplifier 1E has a printed wiring board 32E instead of the printed wiring board 32B.
[0164] Compared to the semiconductor device 31B, the semiconductor device 31E does not have the bumps 121 to 126.
[0165] Printed wiring board 32E is different from printed wiring board 32B in that electrodes 161 to 166 are formed on the front surface (the surface facing semiconductor device 31E, the surface in the Z-axis direction).
[0166] The electrodes 161, 165, 163, 162, 166, and 164 are arranged in this order on a straight line along the X-axis direction.
[0167] One end of the via 131 is electrically connected to the electrode 161. One end of the via 133 is electrically connected to the electrode 165. One end of the via 132 is electrically connected to the electrode 162. One end of the via 134 is electrically connected to the electrode 166. One end of the first winding 21 of the balun 5 is electrically connected to the electrode 163. The other end of the first winding 21 of the balun 5 is electrically connected to the electrode 164.
[0168] The metal portion 111 and the electrode 161 are electrically connected via wires 151 and 152. The metal portion 115 and the electrode 165 are electrically connected via wires 159. The metal portion 113 and the electrode 163 are electrically connected via wires 155 and 156. The metal portion 112 and the electrode 162 are electrically connected via wires 153 and 154. The metal portion 116 and the electrode 166 are electrically connected via wire 160. The metal portion 114 and the electrode 164 are electrically connected via wires 157 and 158.
[0169] (effect) [1] In the Doherty amplifier 1E, the combination point of the first phase radio frequency signal RF1-1 output from the transistor Q1 and the first phase radio frequency signal RF2-1 output from the transistor Q3 is the metal part 115 in the semiconductor device 31E. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal part 115) is small.
[0170] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31E. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0171] Therefore, the Doherty amplifier 1E can suppress deterioration of the output characteristics.
[0172] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1E to obtain symmetry between the first and second phases.
[0173] Therefore, the Doherty amplifier 1E can suppress deterioration of the output characteristics.
[0174] [3] The metal portion 115 and the metal portion 116 are formed in the same direction.
[0175] This allows the Doherty amplifier 1E to have a smaller circuit size than when the metal portion 115 and the metal portion 116 are formed in different directions.
[0176] [4] The metal portion 115 and the metal portion 116 are formed in the same direction. This allows the Doherty amplifier 1E to suppress the difference in length between the wiring 141 and the wiring 142. That is, the Doherty amplifier 1E can easily obtain symmetry between the first phase and the second phase.
[0177] Therefore, the Doherty amplifier 1E can suppress deterioration of the output characteristics.
[0178] [5] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. Metal portion 115 is formed adjacent to metal portion 111. Moreover, wiring 141 is formed in the first metal layer. This allows the Doherty amplifier 1E to shorten wiring 141.
[0179] Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. Metal portion 116 is formed adjacent to metal portion 112. Moreover, wiring 142 is formed in the first metal layer. This allows the Doherty amplifier 1E to shorten wiring 142.
[0180] Therefore, the Doherty amplifier 1E can suppress the deterioration of the output characteristics. Also, the Doherty amplifier 1E can reduce the circuit size.
[0181] Sixth embodiment Fig. 13 and Fig. 14 are diagrams showing the layout of the Doherty amplifier of the sixth embodiment. Fig. 13 is a schematic plan view of the Doherty amplifier 1F of the sixth embodiment as viewed from a direction perpendicular to the main surface. Fig. 14 is an explanatory diagram for explaining the connection relationship of wiring and the like as viewed from a direction parallel to the main surface of the Doherty amplifier 1F.
[0182] 13 and 14, compared to the Doherty amplifier 1C, the Doherty amplifier 1F has a semiconductor device 31F instead of the semiconductor device 31C. Also, compared to the Doherty amplifier 1C, the Doherty amplifier 1F has a printed wiring board 32F instead of the printed wiring board 32C.
[0183] Compared to the semiconductor device 31C, the semiconductor device 31F does not have the bumps 121 to 126.
[0184] Printed wiring board 32F differs from printed wiring board 32C in that electrodes 161 to 166 are formed on the front surface (the surface facing semiconductor device 31F, the surface in the Z-axis direction).
[0185] The electrodes 161, 165, 163, 164, 166 and 162 are arranged in this order on a straight line along the X-axis direction.
[0186] One end of the via 131 is electrically connected to the electrode 161. One end of the via 133 is electrically connected to the electrode 165. One end of the via 134 is electrically connected to the electrode 166. One end of the via 132 is electrically connected to the electrode 162. One end of the first winding 21 of the balun 5 is electrically connected to the electrode 163. The other end of the first winding 21 of the balun 5 is electrically connected to the electrode 164.
[0187] The metal portion 111 and the electrode 161 are electrically connected via wires 151 and 152. The metal portion 115 and the electrode 165 are electrically connected via wires 159. The metal portion 113 and the electrode 163 are electrically connected via wires 155 and 156. The metal portion 114 and the electrode 164 are electrically connected via wires 157 and 158. The metal portion 116 and the electrode 166 are electrically connected via wire 160. The metal portion 112 and the electrode 162 are electrically connected via wires 153 and 154.
[0188] (effect) [1] In the Doherty amplifier 1F, the combination point of the first phase high frequency signal RF1-1 output from the transistor Q1 and the first phase high frequency signal RF2-1 output from the transistor Q3 is the metal part 115 in the semiconductor device 31F. Therefore, the inductance value between the collector of the transistor Q3 and the combination point (metal part 115) is small.
[0189] Similarly, the combination point of the second phase high frequency signal RF1-2 output from the transistor Q2 and the second phase high frequency signal RF2-2 output from the transistor Q4 is the metal portion 116 in the semiconductor device 31F. Therefore, the inductance value between the collector of the transistor Q4 and the combination point (metal portion 116) is small.
[0190] Therefore, the Doherty amplifier 1F can suppress deterioration of the output characteristics.
[0191] [2] The distance between the collector of the transistor Q3 and the junction point (metal portion 115) is approximately the same as the distance between the collector of the transistor Q4 and the junction point (metal portion 116), which makes it easier for the Doherty amplifier 1F to obtain symmetry between the first and second phases.
[0192] Therefore, the Doherty amplifier 1F can suppress deterioration of the output characteristics.
[0193] [3] Metal portion 115 is formed on the metal portion 111 side of metal portion 113. In other words, metal portion 115 is formed next to metal portion 111. Also, wiring 141 is formed in the first metal layer. This allows the Doherty amplifier 1F to shorten wiring 141.
[0194] Moreover, metal portion 116 is formed on the metal portion 112 side of metal portion 114. In other words, metal portion 116 is formed next to metal portion 112. Moreover, wiring 142 is formed in the first metal layer. This allows the Doherty amplifier 1F to shorten wiring 142.
[0195] Therefore, the Doherty amplifier 1F can suppress the deterioration of the output characteristics. Also, the Doherty amplifier 1F can reduce the circuit size.
[0196] [4] The metal portion 113 and the metal portion 114 are formed next to each other. This enables the Doherty amplifier 1F to shorten the distance between the metal portion 113 and the metal portion 114.
[0197] Therefore, in the Doherty amplifier 1F, the balun 5 can be made smaller, and the circuit can be made smaller.
[0198] <Configuration Example of the Present Disclosure> The present disclosure may also have the following configurations.
[0199] (1) a semiconductor device including a carrier amplifier and a peak amplifier, each of which is a differential amplifier including a first phase amplifier and a second phase amplifier; a printed wiring board on which a balun is formed that combines the output signal of the carrier amplifier and the output signal of the peak amplifier; Including, The semiconductor device includes: a first terminal electrically connected to an output terminal of the first phase amplifier of the carrier amplifier; a second terminal electrically connected to an output terminal of the second phase amplifier of the carrier amplifier; a third terminal electrically connected to an output terminal of the first phase amplifier of the peak amplifier and electrically connected to one end of the balun; a fourth terminal electrically connected to the output terminal of the second phase amplifier of the peak amplifier and to the other end of the balun; a fifth terminal electrically connected to the output terminal of the first phase amplifier of the peak amplifier; a sixth terminal electrically connected to the output terminal of the second phase amplifier of the peak amplifier; Including, The printed wiring board comprises: First wiring and second wiring Including, a first metal member electrically connecting one end of the first wiring and the first terminal; a second metal member electrically connecting one end of the second wiring and the second terminal; a third metal member electrically connecting the other end of the first wiring and the fifth terminal; a fourth metal member electrically connecting the other end of the second wiring and the sixth terminal; Including, Doherty amplifier.
[0200] (2) The Doherty amplifier according to (1) above, The fifth terminal is formed on one side of the third terminal, The sixth terminal is formed on the one side of the fourth terminal. Doherty amplifier.
[0201] (3) The Doherty amplifier according to (1) or (2) above, the fifth terminal is formed on the third terminal side of the first terminal, The sixth terminal is formed on the second terminal side of the fourth terminal. Doherty amplifier.
[0202] (4) A Doherty amplifier according to any one of (1) to (3) above, the first phase amplifier of the carrier amplifier and the second phase amplifier of the carrier amplifier are formed adjacent to each other, The first phase amplifier of the peak amplifier and the second phase amplifier of the peak amplifier are formed adjacent to each other. Doherty amplifier.
[0203] (5) A Doherty amplifier according to any one of (1) to (3) above, Each of the first metal member, the second metal member, the third metal member, and the fourth metal member is a bump or a wire. Doherty amplifier.
[0204] The above-described embodiment is for the purpose of facilitating understanding of the present invention, and is not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention.
[0205] (6) The Doherty amplifier according to (1) above, the fifth terminal is formed on a side of the third terminal that is adjacent to the first phase amplifier of the carrier amplifier, The sixth terminal is formed on a second phase amplifier side of the carrier amplifier with respect to the fourth terminal. Doherty amplifier. [Explanation of symbols]
[0206] 1, 1A, 1B, 1C, 1D, 1E, 1F, 200 Doherty Amplifier 2 Carrier Amplifier 2-1, 3-1 Phase 1 amplifier 2-2, 3-2 Phase 2 amplifier 3 Peak Amplifier 4 Phaser 5. Balun 11, 12 Inductors 13 Capacitor 21 Winding No. 1 22 Second Winding 31, 31A, 31B, 31C, 31D, 31E, 31F Semiconductor device 32, 32A, 32B, 32C, 32D, 32E, 32F Printed wiring board 111, 112, 113, 114, 115, 116 Metal section 121, 122, 123, 124, 125, 126 Bump 131, 132, 133, 134 via 141, 142 Wiring 151, 152, 153, 154, 155, 156, 157, 158, 159, 160 Wires 161, 162, 163, 164, 165, 166 electrode Q1, Q2, Q3, Q4 transistors
Claims
1. a semiconductor device including a carrier amplifier and a peak amplifier, each of which is a differential amplifier including a first phase amplifier and a second phase amplifier; a printed wiring board on which a balun is formed that combines the output signal of the carrier amplifier and the output signal of the peak amplifier; Including, The semiconductor device includes: a first terminal electrically connected to an output terminal of the first phase amplifier of the carrier amplifier; a second terminal electrically connected to an output terminal of the second phase amplifier of the carrier amplifier; a third terminal electrically connected to the output terminal of the first phase amplifier of the peak amplifier and to one end of the balun; a fourth terminal electrically connected to the output terminal of the second phase amplifier of the peak amplifier and to the other end of the balun; a fifth terminal electrically connected to the output terminal of the first phase amplifier of the peak amplifier; a sixth terminal electrically connected to the output terminal of the second phase amplifier of the peak amplifier; Including, The printed wiring board comprises: First wiring and second wiring Including, a first metal member electrically connecting one end of the first wiring and the first terminal; a second metal member electrically connecting one end of the second wiring and the second terminal; a third metal member electrically connecting the other end of the first wiring and the fifth terminal; a fourth metal member electrically connecting the other end of the second wiring and the sixth terminal; Including, Doherty amplifier.
2. 2. The Doherty amplifier of claim 1 , The fifth terminal is formed on one side of the third terminal, The sixth terminal is formed on the one side of the fourth terminal. Doherty amplifier.
3. 2. The Doherty amplifier of claim 1 , The fifth terminal is formed on a side of the third terminal that faces the first terminal, The sixth terminal is formed on the second terminal side of the fourth terminal. Doherty amplifier.
4. 4. A Doherty amplifier according to claim 1, further comprising: the first phase amplifier of the carrier amplifier and the second phase amplifier of the carrier amplifier are formed adjacent to each other, The first phase amplifier of the peak amplifier and the second phase amplifier of the peak amplifier are formed adjacent to each other. Doherty amplifier.
5. 4. A Doherty amplifier according to claim 1, further comprising: Each of the first metal member, the second metal member, the third metal member, and the fourth metal member is a bump or a wire. Doherty amplifier.
6. 2. The Doherty amplifier of claim 1 , the fifth terminal is formed on a side of the third terminal that is adjacent to the first phase amplifier of the carrier amplifier, The sixth terminal is formed on a side of the fourth terminal that is adjacent to the second phase amplifier of the carrier amplifier. Doherty amplifier.
Citation Information
Patent Citations
High frequency module and communication device
JP2022090557A