Oscillation circuit

Abstract

To provide an oscillation circuit that shortens a wait time due to a large change in an oscillation frequency immediately after a power supply voltage is turned on and quickly outputs an oscillation signal whose oscillation frequency is stable.SOLUTION: An oscillation circuit 10 comprises: a voltage controlled oscillator 15 that generates a pulsed oscillation signal having a frequency corresponding to a control voltage; a power supply circuit 11 that generates an output voltage corresponding to the frequency of the oscillation signal when a power supply voltage is turned on; an LPF 14 that receives the output voltage of the power supply circuit and generates a control voltage; an enable generation circuit 12 that generates an enable signal during a period when the input voltage to the LPF from the power supply circuit is rising after having lowered than the control voltage immediately after the power supply voltage is turned on; a counter 16 that counts pulses of the oscillation signal in response to the enable signal and generates a mask signal until the count value reaches a prescribed value; and an OR circuit 17 that cuts off output of the oscillation signal while the counter is generating the mask signal and outputs the oscillation signal when the counter stops generating the mask signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an oscillator circuit that waits for oscillation to stabilize when power is turned on. [Background technology]

[0002] Recently, relaxation oscillator circuits that generate an oscillation signal by controlling the charging and discharging of a capacitor using a transistor and an operational amplifier have been used as clock generating circuits for microcomputers and the like.

[0003] For example, Patent Document 1 discloses a relaxation oscillation circuit having an oscillation circuit which increases or decreases the signal levels of first and second oscillation signals in response to transitions in the signal level of a reference clock, a comparison circuit which performs first and second operations of comparing the signal levels of the first and second oscillation signals with a first comparison voltage, respectively, but is turned off outside of these operation periods, and which makes a logical transition of the reference clock based on the results of the first and second operations, and a fixing circuit which fixes the output of the comparison circuit to a predetermined logical value during the off period of the comparison circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-119307 A Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional oscillator circuits such as the relaxation oscillator circuit of Patent Document 1, the desired oscillation frequency is not immediately achieved when the power is turned on, and it takes time for the oscillation frequency to stabilize. For this reason, for example, a configuration has been adopted in which a counter is used to measure the time since the power is turned on, and an oscillation signal is output when it is determined from the counter's count value that the oscillation frequency has reached a stable time.

[0006] However, the large frequency fluctuation that produces the peak at the start of oscillation varies greatly depending on manufacturing variations and operating conditions (power supply voltage, temperature, etc.), so there is a problem that a uniform count value can result in a very long wait time for oscillation to stabilize.

[0007] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide an oscillation circuit capable of shortening the oscillation stabilization wait time due to large fluctuations in the oscillation frequency immediately after power-on, and capable of outputting an oscillation signal with a stabilized oscillation frequency quickly. [Means for solving the problem]

[0008] The oscillation circuit of the present invention is characterized by comprising: a voltage controlled oscillator that generates an oscillation signal of a pulse waveform having a frequency corresponding to a control voltage; a power supply circuit that generates an output voltage corresponding to the frequency of the oscillation signal when a power supply voltage is applied; a low-pass filter that receives the output voltage of the power supply circuit and generates the control voltage; an enable generation circuit that generates an enable signal during a period in which an input voltage from the power supply circuit to the low-pass filter drops below the control voltage immediately after the power supply voltage is applied and then rises; a counter that counts pulses of the oscillation signal in response to the enable signal and generates a mask signal until the count value reaches a predetermined value; and a cutoff circuit that cuts off output of the oscillation signal while the counter is generating the mask signal and outputs the oscillation signal when the counter stops generating the mask signal. Effect of the Invention

[0009] According to the oscillation circuit of the present invention, immediately after the power supply voltage is turned on, the input voltage from the power supply circuit of the low-pass filter falls below the control voltage, and then an enable signal is generated while the input voltage is rising, and in response to the enable signal, the counter begins counting pulses of the oscillation signal. This shortens the oscillation stabilization wait time due to large fluctuations in the oscillation frequency immediately after the power supply voltage is turned on, making it possible to output an oscillation signal with a stable oscillation frequency in a short time after the power supply voltage is turned on. [Brief description of the drawings]

[0010] [Figure 1] 1 is a circuit diagram showing an oscillation circuit according to a first embodiment of the present invention. [Diagram 2] 2 is a waveform diagram showing the operation of the oscillator circuit of FIG. 1. [Diagram 3] FIG. 4 is a circuit diagram showing an oscillator circuit according to a second embodiment of the present invention. [Figure 4] 3 is a waveform diagram showing the operation of the oscillator circuit of FIG. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. EXAMPLES

[0012] 1 shows a circuit diagram of an oscillator circuit according to a first embodiment of the present invention. The oscillator circuit according to the first embodiment is indicated by reference numeral 10 and includes a power supply circuit 11, an enable generating circuit 12, a capacitor 13, an LPF (low-pass filter) 14, a VCO (voltage-controlled oscillator) 15, a counter 16, and an OR circuit 17.

[0013] The power supply circuit 11 has MOS (Metal Oxide Semiconductor) type P-channel transistors TP1 to TP3 (first to third transistors), MOS type N-channel transistors TN1 to TN3 (fourth to sixth transistors), a variable resistor 21, and an SC (Switched Capacitor) resistor 22.

[0014] In the power supply circuit 11, a power supply voltage VDD is supplied to the source of each of the transistors TP1 to TP3. The drain of the transistor TP1 is connected to the drain of the transistor TN1, and is also connected to the gates of each of the transistors TN1 to TN3 via a connection line L2. The drain of the transistor TP2 is connected to the drain of the transistor TN2, and is also connected to the gates of each of the transistors TP1 to TP3. The drain of the transistor TP3 is connected to the drain of the transistor TN3. The drains of the transistors TP3 and TN3 form the output terminal of the power supply circuit 11, and are connected to a connection line L1.

[0015] The source of transistor TN1 is connected to ground. The source of transistor TN2 is connected to ground via a variable resistor 21. The source of transistor TN3 is connected to ground via an SC resistor 22. The SC resistor 22 is a combination circuit of a switch and a capacitor, and acts as a resistor. The SC resistor 22 has a control end, which is connected to the output end of VCO 15. The SC resistor 22 receives the clock signal ck output by VCO 15 as a feedback signal at its control end, and its resistance value corresponds to the frequency of the clock signal ck.

[0016] The enable generation circuit 12 has a MOS type N-channel transistor TN4 (seventh transistor), a capacitor 23, an inverter 24, and a switch 25. The gate of the transistor TN4, which is the input terminal of the enable generation circuit 12, is connected to a connection line L2 of the drains of the transistors TP1 and TN1. The voltage of the connection line L2 is an internal voltage for generating an input voltage Vfin, which is the output voltage of the power supply circuit 11.

[0017] In the enable generation circuit 12, a supply terminal of a power supply voltage VDD is connected to the drain of the transistor TN4 via a capacitor 23 (second capacitor). The source of the transistor TN4 is connected to the ground. In addition, the drain of the transistor TN4 is connected to an inverter 24. The output terminal of the inverter 24 serves as the output terminal of the enable generation circuit 12, and an enable signal cnt_en is output from the output terminal. The output terminal of the enable generation circuit 12 is connected to the enable terminal en of the counter 16.

[0018] A connection line L1 at the output end of the power supply circuit 11 is connected to ground via a first capacitor 13, and is also connected to an LPF 14. The capacitor 13 and the LPF 14 perform a smoothing operation to suppress fluctuations in the output voltage of the power supply circuit 11. A VCO 15 is connected to the output end of the LPF 14, and the LPF 14 supplies the output voltage Vfout to the VCO 15 as a control voltage.

[0019] When the VCO 15 receives the control voltage from the LPF 14, it outputs a clock signal ck, which is an oscillation signal having a pulse waveform with a frequency according to the voltage level of the control voltage.

[0020] The counter 16 is connected to the output terminal of the VCO 15 and receives the output clock signal ck of the VCO 15. An output signal of the enable generation circuit 12 is also supplied to an enable terminal en of the counter 16. The counter 16 generates a high-level mask signal mask in response to the low-level output of the enable generation circuit 12 from the time of power-on. When a high-level enable signal cnt_en is output from the enable generation circuit 12, the counter 16 starts counting pulses of the output clock signal ck of the VCO 15, and when the count value reaches a predetermined value, it stops generating the mask signal mask and goes into a low-level output state.

[0021] The OR circuit 17 is connected to the output terminals of the VCO 15 and the counter 16, and takes the logical OR of the output clock signal ck of the VCO 15 and the output signal of the counter 16. Specifically, the OR circuit 17 is a cutoff circuit, which cuts off the output clock signal ck of the VCO 15 when the output signal ck of the counter 16 is a high-level mask signal, and outputs the output clock signal ck of the VCO 15 as it is as the output signal ckout when the output signal of the counter 16 is a low-level mask signal. The output signal ckout is the output signal of the oscillation circuit 10.

[0022] Next, the operation of the oscillator circuit 10 having such a configuration will be described with reference to the waveform diagram of FIG.

[0023] First, when the power supply voltage VDD is applied to the oscillator circuit 10, a voltage is output from the power supply circuit 11 to the connection line L1. The input voltage Vfin of the LPF 14, which is the voltage of the connection line L1, rises sharply from the time t1 when the power supply voltage VDD starts to be applied, reaches a peak voltage, and then drops sharply. After the steep drop, it gradually rises a little and becomes an almost stable voltage at time t4. In other words, the voltage waveform of the input voltage Vfin immediately after the application of the power supply voltage VDD becomes a steep pulse waveform as shown by characteristic A in FIG. 2.

[0024] Since the LPF 14 integrates the input voltage Vfin, it outputs the low frequency components of the input voltage Vfin. The output voltage Vfout of the LPF 14 draws a pulse voltage waveform that is slightly delayed and has a lower peak voltage than the pulse voltage of characteristic A as shown by characteristic B in Figure 2 immediately after the application of the power supply voltage VDD. The output voltage Vfout of the LPF 14 becomes higher than the input voltage Vfin at time t2, gradually decreases after the peak, and approaches a predetermined stable level earlier than the input voltage Vfin. After that, at time t4, the output voltage Vfout of the LPF 14 becomes almost equal to the input voltage Vfin, which has been gradually increasing slightly.

[0025] The output voltage Vfout of the LPF 14 is supplied to the VCO 15 as a control voltage, so that the VCO 15 starts oscillating according to the output voltage Vfout, and the clock signal ck is output from the VCO 15. The frequency of the clock signal ck from the moment the power supply voltage VDD is turned on fluctuates with a characteristic that has a peak almost similar to the voltage characteristic B in Figure 2, and then stabilizes.

[0026] The output clock signal ck of the VCO 15 is supplied to one input terminal of the OR circuit 17. At the point when the VCO 15 starts oscillating, a high-level mask signal mask is supplied from the counter 16 to the other input terminal of the OR circuit 17, so that the OR circuit 17 is in a state where it blocks the output clock signal ck of the VCO 15.

[0027] On the other hand, the output clock signal ck of the VCO 15 is fed back to the control terminal of the SC resistor 22 of the power supply circuit 11. Here, when the sizes of the transistors TP2 and TP3, and the transistors TN2 and TN3 are equal to each other, the current flowing through the variable resistor 21 and the current flowing through the SC resistor 22 become equal. At this time, the resistance value of the SC resistor 22 changes in response to the frequency of the clock signal ck, and the input voltage Vfin converges so that the resistance value of the variable resistor 21 and the resistance value of the SC resistor 22 become equal to each other. Here, since the frequency of the clock signal ck is determined by the time constant of the resistance value of the variable resistor 21 and the capacitance value of the capacitance included in the SC resistor 23, it is possible to set the frequency of the clock signal ck to a desired frequency by adjusting the resistance value of the variable resistor 21. As a result, the input voltage Vfin, which is the output voltage of the power supply circuit 11, is adjusted so that the frequency of the clock signal ck becomes the desired frequency.

[0028] In the enable signal generation circuit 12, the power supply voltage VDD is applied from time t1 to time t3, so that the power supply voltage VDD is supplied to the inverter 24 via the switch 25 in a conductive state, and the inverter 24 outputs a low level. In other words, the enable signal cnt_en is not output immediately after the power supply voltage VDD is applied to the inverter 24.

[0029] In this state immediately after application of the power supply voltage VDD, when the enable signal cnt_en is not being output, the voltage level of the connection line L2 of the power supply circuit 11 rises, and at time t3, which is earlier than time t4, the switch 25 is put into a non-conducting state, and the voltage level of the connection line L2 becomes high. Time t3 is the time when the frequency of the output clock signal ck of the VCO 15 begins to stabilize. The high level of the connection line L2 is supplied to the gate of the transistor TN4, turning on the transistor TN4. With the transistor TN4 in an on state, the input level of the inverter 24 becomes low, and as shown in FIG. 2, at time t3 the inverter 24 outputs a high level enable signal cnt_en.

[0030] The enable signal cnt_en is supplied to the counter 16, and in response to the enable signal cnt_en, the counter 16 starts counting pulses of the clock signal. At time t5, which is later than time t4, the count value of the counter 16 reaches a predetermined value, and the counter 16 stops generating the mask signal mask and goes into a low-level output state.

[0031] As shown in FIG. 2, when the counter 16 stops generating the mask signal mask, the output clock signal ck of the VCO 15 is output from the OR circuit 17 as the clock signal ckout.

[0032] Thus, in the first embodiment, the counter 16 starts counting from time t3 when the frequency of the output clock signal ck of the VCO 15 starts to stabilize, the output clock signal ck of the VCO 15 is blocked by the OR circuit 17 until just before time t5 when the count value of the counter 16 reaches a predetermined value, and the output clock signal ck of the VCO 15 with a stabilized oscillation frequency is output as the clock signal ckout after time t5. Therefore, the oscillation stabilization wait time due to the large fluctuation accompanying the peak of the oscillation frequency of the VCO 15 immediately after the power supply voltage VDD is turned on is shortened, so that the clock signal ckout with a stabilized oscillation frequency can be output quickly.

[0033] In addition, since the peak of the oscillation frequency of the VCO 15 varies depending on the process finish and the surrounding conditions (ambient temperature, etc.), if the predetermined value is set according to the case where the maximum peak occurs, the masking time may be extended when the peak is lower than the maximum. In anticipation of such a case, it is preferable to set the predetermined value shorter than the case where the masking time is the maximum peak. EXAMPLES

[0034] 3 shows a circuit diagram of an oscillator circuit according to a second embodiment of the present invention. The oscillator circuit according to the second embodiment is designated by reference numeral 20 and includes a power supply circuit 11, a capacitor 13, an LPF 14, a VCO 15, a counter 16, an OR circuit 17, and a comparator 19.

[0035] The power supply circuit 11, the capacitor 13, the LPF 14, the VCO 15, the counter 16, and the OR circuit 17 are the same as those in the oscillator circuit 10 shown in the first embodiment.

[0036] The positive input terminal (+) of the comparator circuit 19 is connected to the output terminal of the LPF 14, and the negative input terminal (-) is connected to the input terminal of the LPF 14, i.e., the connection line L1. The output terminal of the comparator circuit 19 is connected to the enable terminal en of the counter 16. The comparator circuit 19 compares the input voltage Vfin of the LPF 14 with the control voltage Vfout, which is the output voltage of the LPF 14. When the input voltage Vfin+offset voltage Voff of the LPF 14 is higher than the control voltage Vfout (Vfin+Voff>Vfout), the output signal of the comparator circuit 19 becomes high level, and when the input voltage Vfin+offset voltage Voff of the LPF 14 is lower than the output voltage Vfout (Vfin+Voff≦Vfout), the output signal of the comparator circuit 19 becomes low level. The high level output signal of the comparator circuit 19 is the enable signal cnt_en. The offset voltage Voff is a sufficiently low voltage that causes the output signal of the comparator circuit 19 to become high level just before the input voltage Vfin reaches the output voltage Vfout.

[0037] Other configurations of the oscillator circuit 20 are the same as those of the oscillator circuit 10 of the first embodiment except that the oscillator circuit 20 does not have the enable generation circuit 12, so further description here will be omitted.

[0038] Next, the operation of the oscillator circuit 20 having such a configuration will be described with reference to the waveform diagram of FIG.

[0039] First, when the power supply voltage VDD is applied to the oscillator circuit 20, a voltage is output from the power supply circuit 11 to the connection line L1. The input voltage Vfin of the LPF 14, which is the voltage of the connection line L1, rises sharply from the time t11 when the power supply voltage VDD starts to be applied, reaches a peak voltage, and then drops sharply. After the steep drop, it gradually rises a little and becomes an almost stable voltage at time t13. In other words, the voltage waveform of the input voltage Vfin immediately after the application of the power supply voltage VDD becomes a steep pulse waveform as shown by characteristic A in FIG.

[0040] Since the LPF 14 integrates the input voltage Vfin, it outputs the low frequency components of the input voltage Vfin. The output voltage Vfout of the LPF 14 draws a pulse voltage waveform that is slightly delayed and has a lower peak voltage than the pulse voltage of the characteristic A as shown by the characteristic B in FIG. 4 immediately after the application of the power supply voltage VDD. The output voltage Vfout of the LPF 14 becomes higher than the input voltage Vfin at time t12, gradually decreases after the peak, and approaches a predetermined stable level earlier than the input voltage Vfin. After that, at time t13, the output voltage Vfout of the LPF 14 becomes almost equal to the input voltage Vfin, which has been gradually increasing. The operation up to this point is the same as that of the oscillator circuit 10 of the first embodiment.

[0041] The comparator circuit 19 compares the input voltage Vfin of the LPF 14 with the output voltage Vfout of the LPF 14. Therefore, from time t11 when the application of the power supply voltage VDD starts to time t12, the comparator circuit 19 outputs a high-level signal, from time t12 to just before time t13, the comparator circuit 19 outputs a low-level signal, and from time t13 onwards, the comparator circuit 19 outputs a high-level signal.

[0042] The output voltage Vfout of the LPF 14 is supplied to the VCO 15 as a control voltage, so that the VCO 15 starts oscillating according to the output voltage Vfout, and the clock signal ck is output from the VCO 15. The frequency of the clock signal ck from the moment the power supply voltage VDD is turned on fluctuates with a characteristic that has a peak almost similar to the voltage characteristic B in Figure 4, and then stabilizes.

[0043] From time t11 when the power supply voltage VDD starts to be applied to time t12, the high-level output signal of the comparator circuit 19 is the enable signal cnt_en, so the counter 16 starts counting. However, since the period from t11 to t12 is short, the count value of the counter 16 does not reach a predetermined value from 0 during the period from t1 to t2, and the counter 16 generates the mask signal mask.

[0044] The output clock signal ck of the VCO 15 is supplied to one input terminal of the OR circuit 17. At the point when the VCO 15 starts oscillating, the high-level mask signal mask is already being supplied to the other input terminal of the OR circuit 17 from the counter 16, so that the OR circuit 17 is in a state where it blocks the output clock signal ck of the VCO 15.

[0045] From time t12 to just before time t13, the comparator circuit 19 generates a low-level output signal, which stops the counting operation of the counter 16. Therefore, the counter 16 continues to output a high-level mask signal mask to the other input terminal of the OR circuit 17.

[0046] After time t13, the frequency of the output clock signal ck of the VCO 15 starts to stabilize, while the input voltage Vfin of the LPF 14 becomes almost equal to the output voltage Vfout of the LPF 14, and the comparator circuit 19 outputs a high-level enable signal cnt_en. In response to the enable signal cnt_en, the counter 16 starts counting, and the pulses of the output clock signal ck of the VCO 15 are counted, for example, from 0.

[0047] At time t14, the count value of the counter 16 reaches a predetermined value, and the counter 16 stops generating the mask signal mask and goes into a low-level output state.

[0048] As shown in FIG. 4, when the counter 16 stops generating the mask signal mask, the output clock signal ck of the VCO 15 is output from the OR circuit 17 as the clock signal ckout.

[0049] Thus, in the second embodiment, the counter 16 starts counting from time t13 when the frequency of the output clock signal ck of the VCO 15 starts to stabilize, the output clock signal ck of the VCO 15 is blocked by the OR circuit 17 until immediately before time t14 when the count value of the counter 16 reaches a predetermined value, and the output clock signal ck of the VCO 15 with a stabilized oscillation frequency is output as the clock signal ckout after time t14. Therefore, the oscillation stabilization wait time due to the large fluctuation accompanying the peak of the oscillation frequency of the VCO 15 immediately after the power supply voltage VDD is turned on is shortened, and the clock signal ckout with a stabilized oscillation frequency can be output quickly. [Explanation of symbols]

[0050] 10, 20 Oscillator circuit 11 Power supply circuit 12 Enable Generation Circuit 13, 23 Capacitor 14 LPF 15 VCO 16 Counters 17 OR Circuit 19 Comparison circuit 21 Variable resistor 22 SC resistance 24 Inverter TP1~TP3, TN1~TN4 transistors

Claims

1. a voltage controlled oscillator for generating an oscillation signal having a pulse waveform having a frequency according to a control voltage; a power supply circuit that generates an output voltage according to the frequency of the oscillation signal when a power supply voltage is applied; a low-pass filter that receives an output voltage of the power supply circuit and generates the control voltage; an enable generating circuit that generates an enable signal during a period in which an input voltage from the power supply circuit of the low-pass filter falls below the control voltage and then rises above the control voltage immediately after the power supply voltage is turned on; a counter that counts the pulses of the oscillation signal in response to the enable signal and generates a mask signal until the count value reaches a predetermined value; a cutoff circuit that cuts off output of the oscillation signal while the counter is generating a mask signal, and outputs the oscillation signal when the counter stops generating the mask signal.

2. 2. The oscillator circuit according to claim 1, wherein the enable generating circuit generates the enable signal in response to a voltage rise in an internal voltage of the power supply circuit for generating an output voltage of the power supply circuit immediately after the power supply voltage is turned on.

3. 2. The oscillator circuit according to claim 1, wherein the enable generation circuit comprises a comparison circuit that compares an input voltage from the power supply circuit with the control voltage and generates the enable signal immediately before the input voltage from the power supply circuit rises and reaches the control voltage.

4. 2. The oscillator circuit according to claim 1, wherein the enable generating circuit generates the enable signal during the rising period before the input voltage of the low pass filter reaches the control voltage.

5. 2. The oscillation circuit according to claim 1, wherein the cutoff circuit comprises an OR circuit.

6. 2. The oscillator circuit according to claim 1, further comprising a first capacitor connected between a connection line from said power supply circuit to said low-pass filter and ground.

7. the power supply circuit includes first, second and third p-channel transistors, fourth, fifth and sixth n-channel transistors, a variable resistor, and an SC resistor whose resistance value changes according to the frequency of the oscillation signal; 3. The oscillation circuit according to claim 2, wherein the power supply voltage is applied to the sources of the first, second and third transistors, the drains of the first, second and third transistors are connected to the drains of the fourth, fifth and sixth transistors, a connection line of the drains of the second transistor and the fifth transistor is connected to the gates of the first, second and third transistors, a connection line of the drains of the first transistor and the fourth transistor is connected to the gates of the fourth, fifth and sixth transistors, a source of the fourth transistor is connected to ground, a source of the fifth transistor is connected to ground via the variable resistor, a source of the sixth transistor is connected to ground via the SC resistor, a voltage of a connection line of the drains of the third transistor and the sixth transistor is an output voltage of the power supply circuit, and a voltage of a connection line of the drains of the first transistor and the fourth transistor is the internal voltage.

8. the enable generation circuit includes a second capacitor, a seventh n-channel transistor, an inverter, and a switch connected in parallel with the second capacitor; 8. The oscillation circuit according to claim 7, wherein the power supply voltage is applied to the drain of the seventh transistor via a parallel circuit of the second capacitor and the switch, the source of the seventh transistor is connected to ground, and the gate of the seventh transistor is connected to a connection line of the drains of the first transistor and the fourth transistor, and when the switch changes from a conductive state to a non-conductive state and the seventh transistor is turned on, the drain voltage of the seventh transistor is supplied to the inverter, causing the inverter to generate the enable signal.

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