Analog-to-digital converter device and method for operating analog-to-digital converter device

Abstract

To provide an analog-to-digital converter device and a method for operating an analog-to-digital converter device.SOLUTION: There is provided an analog-to-digital converter device designed to form a digital output signal based on an input current. The analog-to-digital converter device includes a first analog-to-digital converter unit of a first type and a second analog-to-digital converter unit of a second type. The first analog-to-digital converter unit is designed to receive the input current, to form a first portion of the digital output signal based on the input current, and to output a first output current to the second analog-to-digital converter unit. The second analog-to-digital converter unit is designed to form a second portion of the digital output signal based on the first output current.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to analog-to-digital converter devices. The present disclosure further relates to a method for operating an analog-to-digital converter device. Summary of the Invention [Means for solving the problem]

[0002] An exemplary embodiment relates to an analog to digital converter device configured to form a digital output signal based on an input current, comprising a first analog to digital converter unit of a first type and a second analog to digital converter unit of a second type, the first analog to digital converter unit configured to receive the input current, form a first portion of the digital output signal based on the input current and output the first output current to the second analog to digital converter unit, the second analog to digital converter unit configured to form a second portion of the digital output signal based on the first output current, thereby enabling in further exemplary embodiments a degree of freedom in providing the analog to digital converter device, e.g. by selection of the first analog to digital converter unit and / or the second analog to digital converter unit.

[0003] In further exemplary embodiments, it is contemplated that a hybrid analog / digital converter device can be provided in which the second type is different from the first type, e.g., the hybrid analog / digital converter device comprises (e.g., first and second) analog / digital converter units of different types.

[0004] In further exemplary embodiments, for example, the first analog / digital converter unit may be optimized for operation with a relatively large input current, and for example the second analog / digital converter unit may be optimized for operation with a relatively small first output current.

[0005] In further exemplary embodiments, the digital output signal may have, for example, M bits, where for example a first portion of the digital output signal has m1 (≧1) bits and for example a second portion of the digital output signal has m2 (≧1) bits. In further exemplary embodiments, m1=m2 may apply. In further exemplary embodiments, m1<m2またはm1> m2 may be applied.

[0006] In a further exemplary embodiment, it is contemplated that the first analog to digital converter unit comprises at least one converter stage, and the at least one converter stage is configured to compare a converter stage input current (e.g., an input current of an analog to digital converter device) supplyable to the at least one converter stage with a converter stage reference current associated with the at least one converter stage, and based on the comparison, a) output a converter stage output current, and / or b) output a digital converter stage output signal.

[0007] In a further exemplary embodiment, it is contemplated that the first analog-to-digital converter unit comprises n (n>1) converter stages, and a first converter stage of the n converter stages is configured to compare a converter stage input current supplyable to the first converter stage with a converter stage reference current associated with the first converter stage, and based on the comparison, a) output the first converter stage output current as an input current for the second converter stage, and / or b) output a first digital converter stage output signal.

[0008] In further exemplary embodiments, e.g. in the case of three or more converter stages, e.g. the second converter stage and / or at least one further converter stage may be configured to compare a converter stage input current supplyable to an associated converter stage with a converter stage reference current associated with the associated converter stage, and based on the comparison: a) output the converter stage output current as an input current for a converter stage subsequent to the associated converter stage, and / or b) output a digital converter stage output signal for the associated converter stage.

[0009] In further exemplary embodiments, it is contemplated that at least one converter stage is configured to compare a converter stage input current with a converter stage reference current, and if the converter stage input current is less than the converter stage reference current, output the converter stage input current as the converter stage output current, and if the converter stage input current is greater than or equal to the converter stage reference current, output a difference between the converter stage input current and the converter stage reference current as the converter stage output current. As a result, in further exemplary embodiments, for example, a binary coding of the first portion of the digital output signal can be obtained.

[0010] In a further exemplary embodiment, it is contemplated that at least one converter stage is configured to compare a converter stage input current with a converter stage reference current, and if the converter stage input current is less than the converter stage reference current, output a difference between the converter stage reference current and the converter stage input current as the converter stage output current, and if the converter stage input current is greater than or equal to the converter stage reference current, output a difference between the converter stage reference current minus the difference between the converter stage input current and the converter stage reference current as the converter stage output current. As a result, in a further exemplary embodiment, for example, a Gray coding of the first portion of the digital output signal can be obtained.

[0011] In a further exemplary embodiment, it is contemplated that the first analog-to-digital converter unit is configured to output a first portion of the digital output signal as a Gray-coded signal, and optionally a transcoding device is provided, the transcoding device being configured to transcode the Gray-coded signal, for example into a binary-coded signal.

[0012] In a further exemplary embodiment, a current mirror device is provided to output the first output current to the second analog / digital converter unit, thereby, in a further exemplary embodiment, it is contemplated that, for example, a suitable current direction of the first output current for the second analog / digital converter unit can be provided.

[0013] In a further exemplary embodiment, it is contemplated that the second analog / digital converter unit is configured to provide a second portion of the digital output signal as a unary coded signal (e.g. according to a thermometer code), and optionally a transcoding device is provided, the transcoding device being configured to transcode the unary coded signal, e.g. into a binary coded signal.

[0014] In a further exemplary embodiment, it is contemplated that the first analog-to-digital converter unit and the second analog-to-digital converter unit are disposed on the same substrate, for example a semiconductor substrate.

[0015] Further exemplary embodiments relate to a computing device for determining, e.g., a scalar product, e.g. a vector matrix multiplier, e.g. a dot product engine, comprising a matrix of elements having controllable electrical resistance and at least one analog-to-digital converter device according to exemplary embodiments.

[0016] A further exemplary embodiment relates to a method for operating an analog to digital converter device configured to form a digital output signal based on an input current, the analog to digital converter device comprising a first analog to digital converter unit of a first type and a second analog to digital converter unit of a second type, the second type being different from the first type, the first analog to digital converter unit receiving the input current and forming a first portion of the digital output signal based on the input current, outputting the first output current to a second analog to digital converter unit, and the second analog to digital converter unit forming the second portion of the digital output signal based on the first output current.

[0017] Further exemplary embodiments relate to the use of an analog to digital converter device according to an embodiment, and / or a computing device according to an embodiment, and / or a method according to an embodiment for at least one of the following elements: a) converting a current to a binary value; b) performing binary coding; and c) providing a fully current-driven, e.g. hybrid, analog to digital converter.

[0018] Further features, possible applications and advantages of the invention will become apparent from the following description of exemplary embodiments of the invention as illustrated in the figures of the drawing, in which all features described or illustrated, individually or in any combination, form the subject of the invention, regardless of their summary or their relationship in the claims, and regardless of their expression or illustration in the text or in the drawings. [Brief description of the drawings]

[0019] [Figure 1] 1 is a simplified schematic block diagram in accordance with an example embodiment; [Diagram 2] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Diagram 3] 1 is a simplified schematic block diagram in accordance with an example embodiment; [Figure 4] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Diagram 5] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Figure 6] 1 is a simplified schematic flow chart according to an exemplary embodiment; [Figure 7] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 8] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 9] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 10] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 11] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 12] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 13] 1 is a schematic diagram illustrating a mode of use according to an exemplary embodiment. [Figure 14] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 15] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 16] FIG. 2 is a simplified schematic circuit diagram according to an example embodiment. [Figure 17] 1 is a simplified schematic timing diagram according to an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] An exemplary embodiment (see Figures 1 and 2) relates to an analog-to-digital converter device 100 configured to form a digital output signal AS-dig based on an input current I_in, the analog-to-digital converter device 100 comprising a first analog-to-digital converter unit 110 of a first type TYP-1 and a second analog-to-digital converter unit 120 of a second type TYP-2, the first analog-to-digital converter unit 110 configured to receive 200 the input current I_in (Figure 2), form 202 a first portion AS-dig-1 of the digital output signal AS-dig based on the input current I_in, and output 204 a first output current I_out-1 (Figure 1) to the second analog-to-digital converter unit 120 (Figure 2), the second analog-to-digital converter unit 120 configured to form 206 a second portion AS-dig-2 of the digital output signal AS-dig based on the first output current I_out-1. This allows for flexibility in providing the analog / digital converter device 100 in further exemplary embodiments, e.g. by selecting the first analog / digital converter unit 110 and / or the second analog / digital converter unit 120.

[0021] In a further exemplary embodiment, the first part AS-dig-1 and the second part AS-dig-2 are combined to produce a digital output signal AS-dig, which may for example be obtained by concatenation of the two parts AS-dig-1, AS-dig-2 when binary coding the respective parts AS-dig-1, AS-dig-2.

[0022] In a further exemplary embodiment (FIG. 1), it is contemplated that the second type TYP-2 is different from the first type TYP-1, e.g., a hybrid analog / digital converter device 100 can be provided that includes (e.g., first and second) analog / digital converter units 110, 120 of different types.

[0023] In a further exemplary embodiment (FIG. 1), for example the first analog / digital converter unit 110 may be optimized for operation with a relatively large input current I_in, and for example the second analog / digital converter unit 120 may be optimized for operation with a relatively small first output current I_out-1.

[0024] In a further exemplary embodiment (FIG. 1), the digital output signal AS-dig may for example have M bits, e.g. a first part AS-dig-1 of the digital output signal AS-dig has m1 (≧1) bits and a second part AS-dig-2 of the digital output signal AS-dig has m2 (≧1) bits. In a further exemplary embodiment, m1=m2 may apply. In a further exemplary embodiment, m1<m2またはm1> m2 may be applied.

[0025] In a further exemplary embodiment (FIG. 3), it is contemplated that the first analog / digital converter unit 110 comprises at least one converter stage 110-1, and the at least one converter stage 110-1 is configured to compare 210 a converter stage input current 110-1-I_in (e.g., the input current I_in of the analog / digital converter device 100; see also FIG. 1) supplyable to the at least one converter stage 110-1 with a converter stage reference current 110-1-I_ref associated with the at least one converter stage 110-1 (see FIG. 4), and based on the comparison 210, a) output 212 a converter stage output current 110-1-I_out, and / or b) output 214 a digital converter stage output signal 110-1-AS.

[0026] In a further exemplary embodiment in which exactly one converter stage 110-1 is provided for the first analog / digital converter unit 110, the converter stage output current 110-1-I_out of the converter stage 110-1 can be output as a first output current I_out-1 to the second analog / digital converter unit 120 (FIG. 1).

[0027] In a further exemplary embodiment in which multiple converter stages 110-1 are provided for the first analog-to-digital converter unit 110, the converter stage output current 110-1-I_out of the converter stage 110-1 can be output to the subsequent converter stage 110-2 as a corresponding input current 110-2-I_in to the second converter stage 110-2, and so on.

[0028] In a further exemplary embodiment (FIG. 3), it is contemplated that the first analog / digital converter unit 110 comprises n (n>1) converter stages 110-1, 110-2, ..., and a first converter stage 110-1 of the n converter stages is configured to compare a converter stage input current 110-1-I_in supplyable to the first converter stage 110-1 with a converter stage reference current 110-1-I_ref associated with the first converter stage 110-1, and based on the comparison, a) output a first converter stage output current 110-1-I_out as an input current 110-2-I_in for the second converter stage 110-2, and / or b) output a first digital converter stage output signal 110-1-AS.

[0029] In a further exemplary embodiment (FIG. 3), e.g. in the case of more than two converter stages, e.g. the second converter stage 110-2 and / or at least one further converter stage may be configured to compare a converter stage input current 110-2-I_in supplyable to the associated converter stage 110-2 with a converter stage reference current 110-2-I_ref associated with the associated converter stage 110-2, and based on the comparison: a) output a converter stage output current 110-2-I_out as an input current for the converter stage subsequent to the associated converter stage, and / or b) output a digital converter stage output signal 110-2-AS for the associated converter stage 110-2.

[0030] In a further exemplary embodiment (FIG. 5), it is contemplated that at least one converter stage 110-1 (FIG. 3) is configured to compare 220 the converter stage input current 110-1-I_in with a converter stage reference current 110-1-I_ref, and if the converter stage input current 110-1-I_in is less than the converter stage reference current 110-1-I_ref, output 222 the converter stage input current 110-1-I_in as the converter stage output current 110-1-I_out, and if the converter stage input current 110-1-I_in is greater than or equal to the converter stage reference current 110-1-I_ref, output 224 a difference 110-1-I_diff (e.g., I_in-I_ref) between the converter stage input current 110-1-I_in and the converter stage reference current 110-1-I_ref as the converter stage output current 110-1-I_out. As a result, in a further exemplary embodiment, a binary coding of the first part AS-dig-1 of the digital output signal AS-dig may for example be obtained, in a further exemplary embodiment, all converter stages 110-1, 110-2, ... may for example be configured to perform such a binary coding.

[0031] Exemplary circuit-technical implementations of converter stages 110-1, 110-2, . . . for eg binary coding according to further exemplary embodiments are further described below with respect to FIGS.

[0032] In a further exemplary embodiment (FIG. 6), at least one converter stage 110-1 compares 230 the converter stage input current 110-1-I_in with a converter stage reference current 110-1-I_ref, and if the converter stage input current 110-1-I_in is less than the converter stage reference current 110-1-I_ref, calculates a difference 110-1-I_diff′ (e.g., by I_ref-I_in) between the converter stage reference current 110-1-I_ref and the converter stage input current 110-1-I_in as the converter stage output current 110- 1-I_out (see also FIG. 3) as the converter stage output current 110-1-I_out (FIG. 6), and if the converter stage input current 110-1-I_in is greater than or equal to the converter stage reference current 110-1-I_ref, output 234 the converter stage output current 110-1-I_diff'' (e.g., by I_ref-(I_in-I_ref)) from the converter stage reference current 110-1-I_ref minus the difference between the converter stage input current 110-1-I_in and the converter stage reference current 110-1-I_ref. As a result, in further exemplary embodiments, for example, a Gray coding of the first portion of the digital output signal can be obtained.

[0033] Exemplary circuit-technical implementations of converter stages 110-1, 110-2, . . . for eg Gray coding according to further exemplary embodiments are further described below with respect to FIGS.

[0034] In a further exemplary embodiment (FIG. 1), it is contemplated that the first analog / digital converter unit 110 is configured to output a first portion AS-dig-1 of the digital output signal AS-dig as a Gray-coded signal, and optionally a transcoding device 130 is provided, the transcoding device 130 being configured to transcode the Gray-coded signal AS-dig-1, for example into a binary-coded signal AS-dig-1′.

[0035] Fig. 7 shows a simplified circuit diagram according to an exemplary embodiment. The analog / digital converter device 100a according to Fig. 7 comprises a first analog / digital converter unit 110a configured to output a first part AS-dig-1 (Fig. 1) of a digital output signal AS-dig as a Gray-coded signal having, for example, three bits o3, o4, o5 in this case, and optionally a transcoding device 130 (see Fig. 8) is provided, which is configured to transcode the Gray-coded signal AS-dig-1 into a binary-coded signal AS-dig-1' having, for example, three bits bit3, bit4, bit5.

[0036] In a further exemplary embodiment (FIG. 7), the analog-to-digital converter device 100a according to FIG. 7 can be supplied with an input current I_in, which may for example be the measured currents Ia, Ib, Ic of the computing device 10 (see FIG. 12 below). The first converter stage 110-1 receives the input current I_in, compares it with a reference current 110-1-I_ref associated with the first converter stage 110-1, and based on the comparison outputs an output current 110-1-I_out, which is for example the difference 110-1-I_diff' or the difference 110-1-I_diff'' according to FIG. 6 depending on the result of the comparison. The output current 110-1-I_out forms an input current for a second converter stage 110-2, which operates similarly to the first converter stage 110-1, but has a separate reference current 110-2-I_ref, e.g., associated with the second converter stage 110-2. The output current 110-2-I_out of the second converter stage 110-2 forms an input current for a third converter stage 110-3, which operates similarly to the first and second converter stages, but has a separate reference current 110-3-I_ref, e.g., associated with the third converter stage 110-3.

[0037] Thus, for example, converter stages 110-1, 110-2, 110-3 each provide one bit of the Gray-coded portion AS-dig-1 (FIG. 1) of the digital output signal AS-dig, with signal o5 of converter stage 110-1 corresponding to the most significant bit MSB.

[0038] Voltage source V11 represents an operating voltage potential for the operating voltage supply of at least some of the components 110a, 120a, for example according to FIG. In further exemplary embodiments, exemplary circuit-technical implementations of the converter stages 110-1, 110-2, 110-3 according to FIG. 7 can be realized, for example, as described in FIGS. 14 and 15, where FIG. 14 shows an exemplary configuration N' for a circuit-technical implementation of a converter stage in a first polarity configuration, type "N", and FIG. 15 shows an exemplary configuration P' for a circuit-technical implementation of a converter stage in a second polarity configuration, type "P".

[0039] In a further exemplary embodiment of the bipolar configuration of the first analog / digital converter unit 110a according to FIG. 7, for example, the first converter stage 110-1 has a second polarity configuration "P", the second converter stage 110-2 has a first polarity configuration "N", and the third converter stage 110-3 has a second polarity configuration "P".

[0040] In a further exemplary embodiment, the bipolar configuration of the first analog-to-digital converter unit 110a requires, for example, a relatively low quiescent current. In further exemplary embodiments, all converter stages of the first analog-to-digital converter unit 110a may also have the same polarity configuration ("N" or "P").

[0041] In a further exemplary embodiment (FIG. 7), each converter stage 110-1, 110-2, 110-3 comprises an input (eg for receiving a respective input current I_in, 110-1-I_out, 110-2-I_out).

[0042] In a further exemplary embodiment (FIG. 7), each converter stage 110-1, 110-2, 110-3 has a first output (e.g., for outputting a respective output current 110-1-I_out, 110-2-I_out, 110-3-I_out, i.e., a residual current, e.g., by exemplary differential generation according to FIG. 5 or 6).

[0043] In a further exemplary embodiment (FIG. 7), each converter stage 110-1, 110-2, 110-3 comprises a second output (eg for outputting a respective digital output signal with bits o5, o4, o3, etc.).

[0044] In a further exemplary embodiment (FIG. 7), a respective reference current 110-1-I_ref, 110-2-I_ref, 110-3-I_ref can be provided to each converter stage 110-1, 110-2, 110-3. In a further exemplary embodiment, at least one reference current source I_ref-SRC can be provided for providing the at least one reference current 110-1-I_ref, 110-2-I_ref, 110-3-I_ref.

[0045] In further exemplary embodiments, the respective reference currents 110-1-I_ref, 110-2-I_ref, 110-3-I_ref may, for example, be the same magnitude or different, for example, based on the respective value settings of the corresponding converter stages 110-1, 110-2, 110-3.

[0046] In a further exemplary embodiment, for example, the reference current 110-1-I_ref for the first converter stage 110-1 may have a first reference current value W_REF-1, the reference current 110-2-I_ref for the second converter stage 110-2 may have a second reference current value W_REF-2=W_REF-1 / 2 that is half as large, and the reference current 110-3-I_ref for the third converter stage 110-3 may have a third reference current value W_REF-3=W_REF-2 / 2 that is half as large.

[0047] In a further exemplary embodiment, the use of the Gray-coded portion AS-dig-1 of the digital output signal AS-dig advantageously requires that the output currents 110-1-I_out, 110-2-I_out, 110-3-I_out of each individual converter stage 110-1, 110-2, 110-3, respectively, do not have jumps in value or sharp edges, which in a further exemplary embodiment may be advantageous for real implementations, for example (e.g. due to a relatively low bandwidth) (see also e.g. FIG. 17).

[0048] FIG. 8 shows a transcoding device 130 configured to transcode the Gray-coded signals o3, o4, o5 (see also FIG. 7) of the first analog-to-digital converter unit 110a into a binary-coded signal (AS-dig-1') having, for example, bits bit3, bit4, bit5.

[0049] The transcoding device 130 according to FIG. 8 comprises several logical elements A1, A2, A3, A4, A5, A6, A7, although in further exemplary embodiments alternative configurations with equivalent functionality are also possible.

[0050] The transcoding device 130 according to FIG. 8 comprises a controllable inverter device 131 configured to output binary coded bits bit0, bit1, bit2 based on a second part AS-dig-2 (FIG. 1) of the digital output signal AS-dig, which can be obtained, for example, in the form of bits o0, o1, o2 by the second analog / digital converter unit 120a according to FIG. 7.

[0051] The inverter device 131 can be advantageously used in further exemplary embodiments, for example when the first analog / digital converter unit 110a performs Gray coding, since in this case the second analog / digital converter unit 120a outputs the correct bit pattern bit0, bit1, bit2 for an input current I_in smaller than the reference current 110-1-I_ref, but outputs an inverted bit pattern for an input current I_in equal to or larger than the reference current 110-1-I_ref, which can be compensated for by the controllable inverter device 131, for example.

[0052] In a further exemplary embodiment (FIG. 7), a current mirror device 140 is provided to output the first output current I_out_1 to the second analog-to-digital converter unit 120a, thereby, in the further exemplary embodiment, it is contemplated that, for example, a suitable current direction of the first output current I_out_1 for the second analog-to-digital converter unit 120a can be provided.

[0053] The reference sign BP1 denotes, by way of example, a first reference potential, for example ground potential, according to a further exemplary embodiment. In a further exemplary embodiment (Figure 7), it is contemplated that the second analog / digital converter unit 120a is configured to provide a second part AS-dig-2 (Figure 1) of the digital output signal AS-dig as a unary coded signal (for example according to a thermometer code), and optionally a transcoding device 130a is provided, which is configured to transcode the unary coded signal AS-dig-2, for example characterized by three bits o0, o1, o2 according to Figure 7, for example into a binary coded signal.

[0054] 9 shows an exemplary circuit-technical implementation of the second analog / digital converter unit 120a according to a further exemplary embodiment, for example as a thermometer-code analog / digital converter unit. The second analog / digital converter unit 120a can be supplied with the first output current I_out-1 provided by the first analog / digital converter unit 110a as an input signal. A number of field-effect transistors (not individually referenced) are connected as shown by way of example to perform a unary coding of the input signal I_out-1 in the sense of a thermometer code, resulting in digital output signals t1', t2', t3', t4', t5', t6', t7' each having one bit.

[0055] Reference numeral 121 denotes an optional conversion of a reference current into a bias voltage for at least some of the field effect transistors according to a further illustrative embodiment. In further exemplary embodiments, the reference currents can be selected separately, e.g. individually, or possibly derived from a reference already used in the circuit. In further exemplary embodiments, this is possible, e.g., if the reference currents are converted into gate voltages, e.g., by connecting the gate of transistor 121 to gate voltages of different references.

[0056] In further exemplary embodiments, the level of the reference current can be selected, for example in conjunction with the design, i.e., for example in conjunction with the gate dimensions of the transistor (e.g., P-channel in FIG. 9), to achieve a desired current sensitivity. If, for example, one wishes to reuse an existing reference current or an existing voltage, in further exemplary embodiments, a fit to the desired conversion range can be achieved, for example, by sizing the transistor 121 in FIG.

[0057] In a further exemplary embodiment, as shown by way of example in FIG. 10, one or more of the digital output signals t1', t2', t3', t4', t5', t6', t7' may be buffered, for example by a buffer circuit 122, respectively.

[0058] The reference BP3 denotes a further operating voltage potential which is for example different from the reference potentials BP1, BP2. Now, it is shown in Fig. 10 how the signal t1' according to Fig. 9 is buffered, resulting in a buffered signal t1. In further exemplary embodiments, one or more further, for example all, output signals t1', t2', t3', t4', t5', t6', t7' can also be buffered using the configuration presented as an example in Fig. 10. In further exemplary embodiments, a corresponding buffer circuit 122 (Fig. 10) can also be directly integrated (not shown), for example in the circuit 120a according to Fig. 9.

[0059] In a further exemplary embodiment, the first analog-to-digital converter unit 110 (FIG. 1) and the second analog-to-digital converter unit 120 may for example be supplied with different operating voltages.

[0060] In a further exemplary embodiment, the first analog-to-digital converter unit 110 (FIG. 1) and the second analog-to-digital converter unit 120 may for example be supplied with different operating voltages.

[0061] In a further exemplary embodiment (FIG. 1), it is contemplated that the first analog-to-digital converter unit 110 and the second analog-to-digital converter unit 120 are disposed on the same substrate, for example a semiconductor substrate.

[0062] Fig. 11 shows in a schematic way an exemplary circuit-technical implementation aspect of a transcoding device 130a configured to transcode (possibly buffered) unary coded signals t1, t2, ..., t7 (e.g. thermometer code) into, for example, a binary coded signal AS-dig-2' (see also the individual bit signals out1, out2, out3 according to Fig. 11, which in a further exemplary embodiment correspond, for example, to the signals o0, o1, o2 according to Fig. 7). The transcoding device 130a comprises, by way of example, the logic elements A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18 as shown in Fig. 11. In further exemplary embodiments, alternative configurations with equivalent functionality can also be provided.

[0063] A further exemplary embodiment (Figure 12) relates to a computing device 10, e.g. for determining a scalar product, e.g. a vector matrix multiplier, e.g. a dot product engine, comprising a matrix M of elements having controllable electrical resistance and at least one analog / digital converter device 100, 100a according to an exemplary embodiment.

[0064] As can be seen from Fig. 12, the analog / digital converter device 100, 100a can be used for example for high side current measurements, i.e. current measurements in potential ranges different from ground potential, where it is useful for example to determine the currents Ia, Ib, Ic. For example, the current Ia according to Fig. 12 can be supplied to the analog / digital converter device 100, 100a as the input current I_in according to Figs.

[0065] A further exemplary embodiment (FIG. 2) relates to a method for operating an analog to digital converter device 100, 100a configured to form a digital output signal AS-dig based on an input current I_in, where the analog to digital converter device comprises a first analog to digital converter unit 110, 110a of a first type and a second analog to digital converter unit 120, 120a of a second type, where the second type is different from the first type, where the first analog to digital converter unit receives 200 the input current (FIG. 2), forms 202 a first portion of the digital output signal based on the input current, outputs 204 the first output current to a second analog to digital converter unit, and where the second analog to digital converter unit forms 206 a second portion of the digital output signal based on the first output current.

[0066] In a further exemplary embodiment, the parts AS-dig-1, AS-dig-2 may possibly be combined into a digital output signal AS-dig, e.g. by concatenation of the parts AS-dig-1, AS-dig-2, possibly after optional transcoding, e.g. into binary code, e.g. taking into account the value settings of the respective bit signals.

[0067] A further exemplary embodiment (FIG. 13) relates to the use 300 of an analog / digital converter device 100, 100a according to an embodiment and / or a computing device 10 according to an embodiment and / or a method according to an embodiment for at least one element of a) converting 301 the current I_in into a binary value AS-dig, b) performing 302 the binary coding, c) providing 303, e.g. a fully current-driven, e.g. hybrid, analog / digital converter 100, 100a.

[0068] FIG. 14 shows an exemplary configuration N′ for a circuit-technical implementation of aspects of the converter stages 110-1, 110-2, 110-3, ... of the first analog / digital converter unit 110, 110a according to a further exemplary embodiment in a first polarity configuration, type “N”.

[0069] In a further exemplary embodiment, the configuration N′ comprises at least one of the following elements: a) a conversion device B1 configured to generate a bias voltage, e.g., a control voltage, based on a reference current, e.g., with respect to a comparator device B2; b) a comparator device B2 configured to compare an input current with a reference current and / or a variable characterizing the input current with a variable characterizing the reference current, e.g., configured to output an output signal based on the comparison; c) a current shunting device B3 configured to at least temporarily shunt the current, e.g., at least temporarily to a first reference potential, e.g., ground potential; d) an inversion device B4 configured to at least easily invert one or the above output signals; e) a first current output device B5 configured to at least temporarily output a first current to a first output, e.g., when the input current is smaller than the reference current; f) a current output device B6 configured to at least temporarily output a second current to a first output, e.g., when the input current is equal to or greater than the reference current.

[0070] In a further exemplary embodiment, the configuration N′ may be used to implement at least one of the converter stages 110-1, 110-2, 110-3 of the first analog / digital converter unit 110, 110a according to a further exemplary embodiment, e.g. to realize aspects of the exemplary flow according to FIG. 5 .

[0071] In a further exemplary embodiment (FIG. 14), the conversion device B1 has at least one transistor, for example a transistor M10, or a series connection of at least two transistors M10, M12. In a further exemplary embodiment, at least one transistor M10, M12 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example an N-channel MOSFET. In a further exemplary embodiment, for example, further transistors described below by way of example can also be configured as MOSFETs (N-channel or P-channel, see circuit symbol in FIG. 14).

[0072] In further exemplary embodiments, the conversion device B1 may comprise at least one further transistor, here for example two MOSFETs M14, M20 in series with the above-mentioned transistors M10, M12, so that in further exemplary embodiments for example a voltage drop can be compensated across at least one further component of the device N'. For example, the MOSFET M20 can compensate for a voltage drop across the MOSFET M22, which will be described in more detail below, and / or the MOSFET M14 can compensate for a voltage drop across the MOSFET M11, which will be described in more detail below.

[0073] In further exemplary embodiments, the conversion device B1 may comprise at least one resistor R3 or (e.g. instead of resistor R3) a diode, e.g. a Schottky diode, in series with, e.g., the above-mentioned transistors M10, M12, so that, in further exemplary embodiments, a voltage difference ("offset") between bias voltages that can be generated by the conversion device B1, e.g. based on a reference current I_ref, e.g. with respect to one or the above-mentioned comparator devices B2, can be generated. The aforementioned offset is thus effective at, e.g., circuit nodes N1, N2.

[0074] Optionally, the transformation device B1 may comprise a first fuse F1, which may be used, for example, for simulation purposes of the configuration N', but which may also be omitted in the actual circuit-technical implementation.

[0075] The optional current source SQ1 represents a reference current I_ref already indicated by the block arrow A3 (e.g. corresponding to the reference current 110-1-I_ref for the first converter stage 110-1 according to FIG. 3), which in a further exemplary embodiment can be supplied to the converter device B1. The optional current source SQ1, like the optional first fuse F1, can be used, for example, for simulation purposes of the configuration N′, and in a further exemplary embodiment can also be omitted, for example with respect to the actual circuit-technical implementation.

[0076] In a further exemplary embodiment, the comparator device B2 may comprise at least one transistor M18, or a series connection of at least two transistors, e.g. MOSFETs M18, M13, which are controllable by a bias voltage, which may be generated, for example, by the conversion device B1.

[0077] In further exemplary embodiments, the comparator device B2 may comprise at least one further transistor M11, for example in series with the above-mentioned transistors M13, M18, thereby making it possible in further exemplary embodiments to compensate for a voltage drop, for example, across at least one further component M16 of the arrangement.

[0078] In a further exemplary embodiment, the comparator device B2 may comprise at least one further transistor M22, for example in series with the abovementioned transistors M18, M13, M11, which is for example a component of a current mirror circuit and copies for example the current I-4 flowing through the comparator device B2, for example the input current I_in (or the input current 110-1-I_in for the first converter stage 110-1 according to FIG. 3), for example for a further component B5 of the configuration N′. Further components of the current mirror circuit comprising the transistor M22 are for example the transistors M23 and / or M28 of the component B5.

[0079] In a further exemplary embodiment, the comparator device B2 may comprise at least one further transistor M34, for example to stabilize the input voltage level. The transistor M34 may be controlled, for example, by an optional voltage source V6. For example, the transistor M34 is connected as a "source follower" (corresponding to an emitter follower for a pnp transistor). The transistor M34 thus tries to keep a fixed voltage level at its source electrode, which in a further exemplary embodiment is also the input of the converter stage. For example, in this case the transistor M34 is conductive when it is drawing current from the current source SQ2 and highly resistive otherwise. This ensures that the voltage level at the current source SQ2 remains approximately constant. This is important, in a further exemplary embodiment, for example for an upstream converter stage, since its current outlet (for example a MOSFET) also depends on the voltage level at the output of this MOSFET.

[0080] Similarly, FIG. 14 also shows a second fuse F2 and a second current source SQ2, both of which in further exemplary embodiments are used, e.g., only for simulation purposes of configuration N′, and which in further exemplary embodiments may be omitted, e.g., in an actual circuit-technical implementation.

[0081] In a further exemplary embodiment, the current shunting device B3 may comprise at least one transistor, for example a MOSFET M7, which at least temporarily shunts the current I-5, for example from the comparator device B2. Optionally, a voltage source V7 is provided for controlling the MOSFET M7. In a further exemplary embodiment, the current shunting device B3 may comprise at least one further transistor, for example a MOSFET M35, which is, for example, a component of a current mirror circuit, for example, copying the current A5 flowing through the current shunting device B3, for example the current A5 shunted from the comparator device B2, for example for a further component B6 of the configuration N'. The further component of the current mirror circuit comprising the transistor M35 is, for example, the transistor M29 and / or M38 of the component B6.

[0082] In a further exemplary embodiment, the inverter device B4 may comprise at least one series connection of two transistors, for example MOSFETs M26, M27 and M1, M2 (for example two MOSFETs per inverter stage). Thus, here, the inverter device B4 comprises two inverter stages, for example for the configuration according to FIG. 14 or for reasons of correctly interpreting the binary output signal out of the device N′.

[0083] In a further exemplary embodiment, the first current output device B5 may comprise a first transistor, e.g., a MOSFET M23, which is a component of a current mirror circuit M22, M23, which for example mirrors the current I-4 of the comparator device B2 to the first current output device B5. In a further exemplary embodiment, the first current output device B5 may comprise a second transistor, e.g., a MOSFET M28, which for example is connected in parallel with the first transistor M23 of the first current output device B5, which similarly mirrors the current I-4 of the comparator device B2 to the first current output device B5, thereby for example doubling the total current mirrored to the first current output device B5.

[0084] In a further exemplary embodiment, the first current output device B5 may comprise a third transistor, e.g., a MOSFET M16, which selectively activates or deactivates the first current output device B5, e.g., based on the output signal out or its preliminary stage out'. In other words, in a further exemplary embodiment, it is controllable based on the signal out' whether the current I-4', which can be mirrored or is mirrored (or multi-mirrored (MOSFET M28) or amplified) from the comparator device B2 by the current mirror M22, M23, should be output by the first current output device B5 as the output current I_out. For example, in a further exemplary embodiment, the first current output device B5 can be activated to output the current I-4' when the binary value "0" is output by the device N'.

[0085] In a further exemplary embodiment, the second current output device B6 may comprise a transistor, for example a MOSFET M29, which is a component of a current mirror circuit M35, M29, which for example mirrors the current I-5 of the current shunting device B3 to the second current output device B6 (see block arrow I-5'). In a further exemplary embodiment, the second current output device B6 may comprise a second transistor, for example a MOSFET M38, which for example is connected in parallel with the first transistor M29 of the second current output device B6, which similarly mirrors the current I-5 of the current shunting device B3 to the second current output device B6, thereby for example doubling the total current I-5' mirrored to the second current output device B6. For example, in a further exemplary embodiment, the second current output device B6 can be activated to output a current I-5' when a binary value "1" is output by the device N'.

[0086] In a further exemplary embodiment, the current source SQ2 supplies an input current for the simulation of the circuit N′ according to Fig. 14, the current source SQ2 being used, for example, only for the individual simulation of the circuit N′. In a further exemplary embodiment with several blocks or stages, the current source SQ2 can for example be omitted and instead a current from, for example, a previous block can be made available.

[0087] Optionally, the configuration N' according to FIG. 14 may comprise a third fuse F3, which can be used, for example, for simulation purposes of the configuration N', but which can also be omitted in the actual circuit technical implementation.

[0088] An optional voltage source V3' can be used, for example, in the simulation of the circuit N' according to FIG. 14, to characterize the input of a subsequent block or stage. Fig. 15 shows an exemplary configuration P' for a circuit-technical implementation of aspects of the converter stages 110-1, 110-2, 110-3, ... of the first analog / digital converter unit 110, 110a according to a further exemplary embodiment for realizing aspects of the exemplary flow according to Fig. 5 in a second polarity configuration, type "P". It should be noted that in a further exemplary embodiment, the polarity configurations "N", "P" according to Figs. 14, 15 are different from the types TYP-1, TYP-2 of the analog / digital converter units 110, 110a, 120, 120a.

[0089] Blocks or components B1', B2', B3', B4', B5', B6' according to FIG. 15 correspond in a further exemplary embodiment to blocks or components B1, B2, B3, B4, B5, B6 according to FIG.

[0090] In further exemplary embodiments, the conversion device B1' comprises at least one transistor M7 or at least two transistors M7, M11 connected in series. In further exemplary embodiments, at least one transistor M7, M11 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), for example a P-channel MOSFET. In further exemplary embodiments, for example, further transistors described below by way of example can also be configured as MOSFETs (N-channel or P-channel, see circuit symbol in FIG. 15).

[0091] In further exemplary embodiments, the conversion device B1′ may comprise at least one further transistor, here for example two MOSFETs M3, M4 in series with the above-mentioned transistors M7, M11, so that in further exemplary embodiments for example a voltage drop can be compensated across at least one further component of the arrangement P′. For example, the MOSFET M4 can compensate for a voltage drop across the MOSFET M9, which will be described in more detail below, and / or the MOSFET M3 can compensate for a voltage drop across the MOSFET M5, which will be described in more detail below.

[0092] In further exemplary embodiments, the conversion device B1' may comprise at least one resistor R1 or a diode (e.g., instead of the resistor R1), e.g., a Schottky diode, in series with, e.g., the above-mentioned transistors M7, M11, so that, in further exemplary embodiments, a voltage difference ("offset") between bias voltages that can be generated by the conversion device B1', e.g., based on the reference current I-6, can be generated, e.g., with respect to one or the above-mentioned comparator device B2'. The aforementioned offset is thus effective, e.g., at the circuit nodes N1', N2'.

[0093] Optionally, the transformation device B1' may comprise a fuse F4, which may be used, for example, for simulation purposes of the configuration P', but which may also be omitted in the actual circuit-technical implementation.

[0094] The optional current source SQ1' represents a reference current I_ref (corresponding for example to the reference current 110-1-I_ref for the first converter stage 110-1 according to FIG. 3) already indicated by the block arrow I-6, which in a further exemplary embodiment can be supplied to the converter device B1'. The optional current source SQ1' can be used, like the optional fuse F4, for example for simulation purposes of the configuration P', and in a further exemplary embodiment can also be omitted, for example with regard to the actual circuit-technical implementation.

[0095] In a further exemplary embodiment, the comparator device B2′ may comprise at least one transistor M2, or at least two transistors, e.g., MOSFETs M2, M16, connected in series, the transistors being controllable by a bias voltage, which may be generated, for example, by a conversion device B1′.

[0096] In further exemplary embodiments, the comparator device B2' may comprise at least one further transistor M9, for example in series with the above-mentioned transistors M2, M16, thereby, in further exemplary embodiments, being able to compensate for a voltage drop, for example, across at least one further component M8 of the apparatus P'.

[0097] In a further exemplary embodiment, the comparator device B2' may comprise at least one further transistor M5, for example in series with the abovementioned transistors M2, M16, M9, which is for example a component of a current mirror circuit, for example copying the current I-7, for example the input current I_in, flowing through the comparator device B2', for example for a further component B5' of the arrangement P+. The further component of the current mirror circuit comprising the transistor M5 is for example the transistor M15 and / or M6 of the component B5'.

[0098] In a further exemplary embodiment, the comparator device B2' may comprise at least one further transistor M9, for example to stabilize the input voltage level. Similarly, FIG. 15 also shows fuse F5 as well as current source SQ2′ and resistor R′, both of which in further exemplary embodiments are used, e.g., only for simulation purposes of configuration P′ and which, in further exemplary embodiments, may be omitted, e.g., in an actual circuit-technical implementation.

[0099] In a further exemplary embodiment, the current shunting device B3' may comprise at least one transistor, for example a MOSFET M1, which at least temporarily shunts the current I-8, for example from the comparator device B2'. Optionally, a voltage source V2' is provided for controlling the MOSFET M1. In a further exemplary embodiment, the current shunting device B3' may comprise at least one further transistor, for example a MOSFET M13, which is, for example, a component of a current mirror circuit, for example, copying the current I-8 flowing through the current shunting device B3', for example the current I-8 shunted from the comparator device B2', for example for a further component B6' of the device. The further component of the current mirror circuit comprising the transistor M1 is, for example, the transistor M10 and / or M11 of the component B6'.

[0100] In a further exemplary embodiment, the inverter device B4' may comprise at least one series connection of two transistors, for example MOSFETs M17, M19, so that now the inverter device B4' comprises an inverter stage, in contrast to the inverter device B4 according to FIG.

[0101] In a further exemplary embodiment, the first current output device B5' according to Fig. 15 may comprise a first transistor, for example a MOSFET M15, which is a component of a current mirror circuit M5, M15, which for example mirrors the current I-7 of the comparator device B2' to the first current output device B5'. In a further exemplary embodiment, the first current output device B5' may comprise a second transistor, for example a MOSFET M6, which is for example connected in parallel to the first transistor M15 of the first current output device B5' and similarly mirrors the current I-7 of the comparator device B2' to the first current output device B5', thereby for example doubling the total current I-7' mirrored to the first current output device B5'.

[0102] In a further exemplary embodiment, the first current output device B5' may comprise a third transistor, e.g., a MOSFET M8, which selectively activates or deactivates the first current output device B5', e.g., based on the output signal out. In other words, in a further exemplary embodiment, based on the signal out, it is possible to control whether the first current output device B5' should output as the output current I_out the current I-7' that can be mirrored or is mirrored (or multiply mirrored (MOSFET M26) or amplified) from the comparator device B2' by the current mirror M5, M15. For example, in a further exemplary embodiment, the first current output device B5' can be activated to output a current A4' when a binary value "0" is output by the device P'.

[0103] In a further exemplary embodiment, the second current output device B6' may comprise a transistor, for example a MOSFET M10, which is a component of a current mirror circuit M10, M13, which for example mirrors the current I-8 of the current shunting device B3' to the second current output device B6' (see block arrow I-8'). In a further exemplary embodiment, the second current output device B6' may comprise a second transistor, for example a MOSFET M14, which for example is connected in parallel with the first transistor M10 of the second current output device B6' and similarly mirrors the current I-8 of the current shunting device B3' to the second current output device B6', thereby for example doubling the total current I-8' mirrored to the second current output device B6'. For example, in a further exemplary embodiment, the second current output device B6' is activatable to output a current I-8' when a binary value "1" is output by the unit P'.

[0104] Optionally, eg for simulation purposes, a resistor R2 can be provided in block B3', which can eg speed up the simulation process and can be omitted in the actual circuit-technical implementation.

[0105] In a further exemplary embodiment, it is contemplated that the device P+ in the second polarity configuration is configured to receive an input current I_in flowing at a second reference potential BP2, e.g. different from the one or above first reference potential BP1, VDD, e.g. an operating voltage potential associated with the operating voltage VDD, and to output an output current I_out to the second reference potential, e.g. the operating voltage potential.

[0106] Optionally, the configuration P' according to FIG. 15 may comprise at least one further fuse F6, F7, which can be used, for example, for simulation purposes of the configuration P', but which can also be omitted in the actual circuit-technical implementation.

[0107] The optional voltage source V3' can be used, for example, in the simulation of the circuit P' according to FIG. 15, to characterize the input of a subsequent block or stage or to show its behavior.

[0108] The manner of operation of component N' according to Fig. 14 will be described below by way of example, which applies analogously to component P' according to Fig. 15. As long as the output signal out is zero, i.e. as long as the input current I_in or I-4 is smaller than the reference current I_ref or I-3, the input current I_in is output as the output current (see for example block 222 according to FIG. 5), which in a further exemplary embodiment is done for example by means of transistors M22, M23.

[0109] In a further exemplary embodiment, the component B5 is deactivated as soon as the output signal out exhibits the value "1" or "high", for example by the transistor M16. Due to the non-zero resistance of the transistor M16 (or its drain-source path) in the switched-on state (RDS_on), a voltage drop occurs in the drain-source path of the transistor M16, which in a further exemplary embodiment can be compensated for, for example by the transistors M11, M14, for example in the converter device B1 and the comparator device B2. In a further exemplary embodiment, the transistors M11, M14 can be operated as resistors, and in a further exemplary embodiment can also be replaced by a resistor, for example having the value RDS_on of the transistor M16. However, in a further exemplary embodiment, MOSFETs are used as the transistors M11, M14, which can contribute to better thermal stability.

[0110] As long as the output signal is 1 (i.e. "high"), i.e. as long as the input current I_in is greater than the reference current I_ref, the reference current I_ref is subtracted from the input current I_in and only the remaining differential current A5' is output as the output current, which can be controlled, for example, by the transistor M7 of the block B3. For example, the transistor M7 is switched on as soon as the potential of its source electrode (and its output or drain electrode) rises. In a further exemplary embodiment, the current I-4 corresponding to the reference current I_ref continues to flow through the comparator device B2, while the current I-5 exceeding the current I-4 is shunted by the transistor M7 of the current shunting device B3. This current A5 is then mirrored by the current mirrors M35, M29 and leaves the circuit N' as the output current I_out.

[0111] In further exemplary embodiments, the transistors M28 and M33 allow amplification, e.g. doubling, of the output current. In further exemplary embodiments, these transistors M28 and M33 can be selectively activated or deactivated, e.g. by at least one fuse F3a, F3b. As a result, in further exemplary embodiments based on the same circuit layout N′, it is possible to efficiently provide both devices with amplified output current (M28 and / or M38 active) and devices with unamplified output current (M28 and / or M38 inactive). In further exemplary embodiments, optional output current amplification can be used for stages or devices farther away from the input, e.g. in a converter stage, e.g. in a series connection, such stages or devices operate at lower current strengths, according to the above-mentioned operating principles according to the exemplary embodiments, e.g. non-zero capacitance of the gate electrode of a real MOSFET affects the associated current signal profile.

[0112] In further exemplary embodiments, for example as an alternative or complement to the second transistor M28, the width of the gate electrode of the main transistor M23 may be increased, for example doubled, to achieve the desired output current amplification.

[0113] In a further exemplary embodiment, the comparator device B2 (FIG. 14) is controlled by the translation device B1, for example by a bias voltage. In a further exemplary embodiment, transistor M12 provides a bias voltage for transistor M13. In a further exemplary embodiment, transistor M10 provides a bias voltage for transistor M18. In a further exemplary embodiment, the bias voltage for transistor M18 is slightly greater than the bias voltage for transistor M13, for example, by between about 20 mV (millivolts) and about 200 mV. This offset can be provided, for example, by optional resistor R3, which in a further exemplary embodiment can also be replaced by a diode, for example a Schottky diode.

[0114] In a further exemplary embodiment, the advantage of the configuration N' according to Fig. 14 described above by way of example is that when the input current I_in reaches the current intensity of the reference current I_ref, the transistor M13 is no longer able to supply the required current intensity, so the potential of the drain electrode of the transistor M13 is raised. As soon as this rise in the potential of the drain electrode of the transistor M13 exceeds the offset across the resistor R3, the transistor M18 thereby starts to turn off, which further accelerates the rise in the potential of the drain electrode of the transistor M13. As a result, in a further exemplary embodiment, a relatively accurate and steep edge can be achieved. According to the applicant's research, this works relatively well in a further exemplary embodiment, especially for currents in the milliampere (mA) range, and in a further exemplary embodiment, for smaller currents, for example in the range of a few nanoamperes (nA), the optional components R3, M10, M18 can be omitted.

[0115] In further exemplary embodiments, the converter device B1 can also be influenced to provide a nominal bias voltage for the comparator device B2 based on, for example, half the reference current I_ref. In further exemplary embodiments, this can be achieved, for example, by changing the dimensions of the gate electrodes of the MOSFETs M12, M10 or the MOSFETs M18, M13. In further exemplary embodiments, for example, the same bias voltage can be used for several units N' or 100, ..., for example of the same A / D converter device and / or of A / D converter devices adjacent to each other, and for example only one reference current I_ref is required.

[0116] In further exemplary embodiments, the device N' or P' can use, for example, an additional current mirror, which increases the electrical energy consumption but allows the current direction of the input current to be adjusted to coincide with the current direction of the output current. In these embodiments, for example, devices with the same polarity configuration N or P, respectively, can be used for the converter device, i.e. for example, several converter stages 110-1, 110-2, 110-3 of the same polarity configuration can be provided. Alternatively, in further exemplary embodiments, it can be envisaged that at least two successive converter stages 110-1, 110-2, for example according to Figs. 14, 15, each have a different polarity configuration P, N, for example several, for example all, respectively successive converter stages have alternating polarity configurations P, N, P, ..., for example the respective polarity configurations corresponding to the position of the respective converter stage in the series circuit. In further exemplary embodiments, this can contribute to reducing the complexity and electrical energy consumption of the individual converter stages (for example with respect to optional additional current mirrors).

[0117] In further exemplary embodiments, device N′ or its inverter device B4 may comprise inverter stages M26, M27 instead of two inverter stages, and in some cases the inverted state of the output signal out′ can be taken into account by the target systems 110-1, 110-2, ... of device N′.

[0118] In further exemplary embodiments, it is also possible to place multiple devices N', P' "on top of each other" with respect to a reference potential, e.g. stack them, e.g. a first device has ground potential as a reference potential and has an operating voltage of e.g. 0.5 volts, a second device has a potential of 0.5 volts (with respect to ground potential) as a reference potential and has an operating voltage of 1.0 volts, and so on. In these embodiments, it may be possible to omit internal current mirrors of the devices, for example, since the output current of each device leaves each device in the same direction as the input current of each device. In other words, in these embodiments, the entire circuit can be powered by the current to be measured or the input current I_in.

[0119] Fig. 16 shows an exemplary configuration K of aspects of the converter stages 110-1, 110-2, ... (Figs. 3, 7) of the first analog / digital converter unit 110, 110a for implementing aspects of the exemplary process according to Fig. 6, where Gray coding is feasible, according to a further exemplary embodiment. Here, two comparator devices 1110-1, 1110-2, for example connected in series with each other, are shown, where the first comparator device 1110-1 can be used for example for the first converter stage 110-1 according to Fig. 3, 7 and the second comparator device 1110-2 can be used for example for the second converter stage 110-2 according to Fig. 3, 7.

[0120] The configuration K according to FIG. 16 can provide an input current as a first input current I_in-1 for the first comparator device 1110-1 (e.g., the input current I_in according to FIG. 1, 3, e.g., the input current 110-1-I_in according to FIG. 3) at the third circuit node 112-1-N3 of the first comparator device 1110-1, and the first comparator device 1110-1 compares the first input current I_in-1 with a first reference current I_ref-1 (e.g., similar to the reference current 110-1-I_ref according to FIG. 3) and provides a potential characterizing the comparison result as an output signal o5 (see also element o5 according to FIG. 7) at its first circuit node 112-1-N1.

[0121] In a further exemplary embodiment (FIG. 16), it is contemplated that the first reference current device 114-1 comprises a transistor 114-1a, e.g., a field effect transistor, with the load path (drain-source path) of the transistor 114-1a being connected between the first circuit node 112-1-N1 of the first comparator device 1110-1 and the first reference potential BP1-1. This allows the first reference current I_ref-1 to be efficiently provided in the further embodiment. In a further exemplary embodiment, the current strength of the first reference current I_ref-1 can be predetermined or influenced by at least one of the following factors: a) control of the transistor 114-1a; b) a dimension of at least one component of the transistor 114-1a, e.g., a gate width in the case of a field effect transistor.

[0122] In a further exemplary embodiment, the transistor 114-1a may be part, eg, an output, of a current mirror device that provides the first reference current I_ref-1. In a further illustrative embodiment (FIG. 16), it is contemplated that the first differential current providing device 115-1 comprises a first transistor 115-1a, e.g., a field effect transistor, and the load path of the first transistor 115-1a is connected between the second circuit node 112-1-N2 of the first comparator device 1110-1 and one or the above first reference potentials BP1-1.

[0123] In a further illustrative embodiment, it is contemplated that the first transistor 115-1a of the first differential current supply device 115-1 is controllable based on the potential of the first circuit node 112-1-N1 of the first comparator device 1110-1, i.e., based on the comparison result of the first comparator device 1110-1.

[0124] For example, the first transistor 115-1a of the first differential current supply device 115-1 may form a current mirror device together with the second transistor 115-1b of the first differential current supply device 115-1, which is controllable, for example, by the third transistor 115-1c of the first differential current supply device 115-1 based on, for example, the potential of the first circuit node 112-1-N1 of the first comparator device 1110-1. In this way, it may be effectively caused that the first transistor 115-1a of the first differential current providing device 115-1 provides the first output current I_out-1 thereafter as soon as the first input current I_in-1 exceeds the first reference current I_ref-1, thus causing a potential change at the first circuit node 112-1-N1.

[0125] By way of example, further aspects of the operation of the comparator device 1110-1 according to FIG. 16 are described below with reference also to the exemplary timing diagram according to FIG. At time t0, the first input current I_in-1 is zero, after time t0, the first input current I_in-1 increases, for example linearly here (see curve K1), until time t1. Curve K2 characterizes the first output current I_out-1 of the first comparator device 1110-1 according to FIG. 16. As can be seen from FIG. 17, the first output current K2 is equal to the first reference current I_ref-1 at time t0 and then decreases linearly to zero until time t01, when the first input current I_in-1 (K1) exceeds the first reference current I_ref-1. The output signal o5 at the first circuit node 112-1-N1 (see curve K3 according to FIG. 17) has a first state, for example logic 1, between t0 and t01, for example based on the first operating voltage potential BP1-1 of the first comparator device.

[0126] As soon as the first input current I_in-1 (K1) exceeds the first reference current I_ref-1 (see time t01 according to FIG. 17), the output signal o5 (K3) goes to a second state, e.g. logic 0, and the first output current I_out-1 (K2) increases correspondingly while the first input current I_in-1 (K1) continues to increase until time t1. It can be seen that even during the state transition of the output signal o5 (K3) (see time t01 for example), no abrupt change in the first output current K2 occurs, and the temporal change in the first output current K2 is based on the temporal change in the first input current K1.

[0127] 16 is in a conducting state during a time period from t0 to t01 and in a blocking state during a time period from t01 to t10. In a further exemplary embodiment, the first differential current providing device 115-1 may provide the first output current I_out-1 while the diode 116-1 is blocking.

[0128] Here, the first comparator device 1110-1 according to Fig. 16 is realized by a p-channel field effect transistor, for example of MOSFET type, and the second comparator device 1110-2 according to Fig. 16 is realized by an n-channel MOSFET. In a further exemplary embodiment, such an alternating implementation of the MOSFETs of the successive comparator devices 1110-1, 1110-2, ... of the configuration K can be advantageous, since it requires fewer components than an embodiment in which all the transistors of the comparator devices 1110-1, 1110-2, ... are of the same type (for example p-type or n-type). Furthermore, it allows to reduce the number of cross-flows between adjacent comparator devices.

[0129] The function of the second comparator device 1110-2 according to FIG. 16 substantially corresponds to the function of the first comparator device 1110-1 according to FIG. 16, with the difference that the MOSFET of the second comparator device 1110-2 is now for example of the n-channel type.

[0130] For example, it is contemplated that the second reference current device 114-2 comprises a transistor 114-2a, e.g., a field effect transistor, with the load path (drain-source path) of the transistor 114-2a being connected between the first circuit node 112-2-N1 of the second comparator device 1110-2 and the first reference potential BP1-2. This can effectively provide the second reference current I_ref-2 in a further exemplary embodiment. In a further exemplary embodiment, the current strength of the second reference current I_ref-2 can be predetermined or influenced by at least one of the following factors: a) control of the transistor 114-2a; b) a dimension of at least one component of the transistor 114-2a, e.g., a gate width in the case of a field effect transistor.

[0131] In a further illustrative embodiment (FIG. 16), it is contemplated that the second differential current providing device 115-2 comprises a first transistor 115-2a, e.g., a field effect transistor, and the load path of the first transistor 115-2a is connected between the second circuit node 112-2-N2 of the second comparator device 1110-2 and one or more first reference potentials BP1-2.

[0132] In a further illustrative embodiment, it is contemplated that the first transistor 115-2a of the second differential current providing device 115-2 is controllable based on the potential of the first circuit node 112-2-N1 of the second comparator device 1110-2, i.e., for example, based on the comparison result of the second comparator device 1110-2 (see output signal o4).

[0133] For example, the first transistor 115-2a of the second differential current providing device 115-2 may form a current mirror device together with the second transistor 115-2b of the second differential current providing device 115-2, which current mirror device is controllable, for example, by the third transistor 115-2c of the second differential current providing device 115-2, for example, based on the potential of the first circuit node 112-2-N1 of the second comparator device 1110-2. In this way, as soon as the second input current I_in-2 exceeds the second reference current I_ref-2, thus causing a potential change at the first circuit node 112-2-N1, it may be effectively caused that the first transistor 115-2a of the second differential current providing device 115-2 provides the second output current I_out-2 thereafter.

[0134] In further exemplary embodiments, the configuration K according to Fig. 16 may comprise, for example, a third comparator device (not shown here), which is designed, for example, similar to the first comparator device 1110-1 and is realized, for example, by a p-channel MOSFET, similar to the first comparator device 1110-1. In further exemplary embodiments, the third comparator device can be used, for example, to realize the third converter stage 110-3 (Fig. 7). In further exemplary embodiments, the configuration K according to Fig. 16 may comprise, for example, a fourth comparator device (not shown here), which is designed, for example, similar to the second comparator device 1110-2 and is realized, for example, by an n-channel MOSFET, similar to the second comparator device 1110-2, and so on, where an alternating implementation of successive comparator devices 1110-1, 1110-2 by MOSFETs of different types (p-channel, n-channel) may be advantageous.

[0135] In a further exemplary embodiment, for example, a first comparator device 1110-1 according to Fig. 16 can be used to realize the first converter stage 110-1 (Fig. 7), a second comparator device 1110-2 according to Fig. 16 can be used to realize the second converter stage 110-2 (Fig. 7), etc. In other words, in a further exemplary embodiment, the configuration K according to Fig. 16 can be used to provide one or more converter stages 110-1, 110-2, ... for the first analog-to-digital converter unit 110, 110a, for example to output a Gray-coded portion AS-dig-1 of the digital output signal AS-dig.

[0136] In further exemplary embodiments, for example alternative circuit technical implementations from at least one of the embodiments described above by way of example may also be provided in the context of inverted circuits, for example in which NMOS elements are replaced by PMOS elements and vice versa, for example upon a change in the allocation of the corresponding reference potentials.

[0137] In further exemplary embodiments, the first analog-to-digital converter unit 110, 110a and / or the second analog-to-digital converter unit 120, 120a may have a different number of stages or bits than those described above as examples.

[0138] In further exemplary embodiments, the circuit technical implementation may also comprise semiconductor elements, for example transistors of types other than the MOSFET type mentioned above by way of example, for example bipolar transistors.

[0139] In further exemplary embodiments, one or more resistors may be provided, for example connected to the gate electrodes of each of the MOSFET transistors, for example to dampen oscillation tendencies. Information about assistance and support The project leading to this application has been funded by the ECSEL (Joint Undertaking) Joint Venture under grant agreement No. 826655. The Joint Undertaking receives support from the European Union's Horizon 2020 research and innovation programme, as well as from Belgium, France, Germany, the Netherlands and Switzerland. [Explanation of symbols]

[0140] AS-dig digital output signal AS-dig-1 1st part AS-dig-1' binary coded signal AS-dig-2 2nd part AS-dig-2' binary coded signal I_in Input current I_out-1 First output current M matrix Ia;Ib;Ic current TYP-1 First Type TYP-2 Second type 10. Computing Devices 100;100a Analog to Digital Converter Device 110 first analog / digital converter unit 110-1, 110-2 Converter Stage 110-1-AS Digital Converter Stage Output Signal 110-1-I_diff The difference between the converter stage input current and the converter stage reference current. 110-1-I_diff' Difference between converter stage reference current and converter stage input current 110-1-I_diff'' Converter stage reference current minus the difference between the converter stage input current and the converter stage reference current 110-1-I_in, 110-2-I_in Converter stage input current 110-1-I_ref Converter stage reference current 110-1-I_out Converter stage output current 120 Second analog / digital converter unit 130, 130a Transcoding Device 140 Current Mirror Device 200 Received 202 Formation of the first part 204 Output 206 Formation of the second part 210 comparison 212 Output 214 Output 220 comparison 222 Output 224 Output 230 comparison 232 Output 234 Output 300 uses 301 Converting current to binary value 302 Binary Coding Execution Providing 303 analog / digital converters 1000 boards

Claims

1. An analog-to-digital converter device (100; 100a) configured to form a digital output signal (AS-dig) based on an input current (I_in), comprising a first analog-to-digital converter unit (110) of a first type (TYP-1) and a second analog-to-digital converter unit (120) of a second type (TYP-2), said first analog-to-digital converter unit (110) receiving (200) said input current (I_in) and forming said digital output signal (AS-dig) based on said input current (I_in). An analog-to-digital converter device (100; 100a) configured to form (202) a first portion (AS-dig-1) of a force signal (AS-dig) and output (204) a first output current (I_out-1) to the second analog-to-digital converter unit (120), the second analog-to-digital converter unit (120) configured to form (206) a second portion (AS-dig-2) of the digital output signal (AS-dig) based on the first output current (I_out-1).

2. An analog-to-digital converter device (100; 100a) according to claim 1, wherein said second type (TYP-2) is different from said first type (TYP-1).

3. 3. An analog to digital converter device (100; 100a) according to claim 1 or 2, wherein the first analog to digital converter unit (110) comprises at least one converter stage (110-1), the at least one converter stage (110-1) configured to compare (210) a converter stage input current (110-1-I_in) supplyable to the at least one converter stage (110-1) with a converter stage reference current (110-1-I_ref) associated with the at least one converter stage (110-1) and to output (212) a converter stage output current (110-1-I_out) and / or b) output (214) a digital converter stage output signal (110-1-AS) based on the comparison (210).

4. The first analog / digital converter unit (110) comprises n (n>1) converter stages (110-1, 110-2, ...), and a first converter stage (110-1) of the n converter stages (110-1, 110-2, ...) is configured to calculate a converter stage input current (110-1-I_in; I_in) that can be supplied to the first converter stage (110-1) based on a converter stage reference current (110-1-I_in; I_in) associated with the first converter stage (110-1).

4. An analog to digital converter device (100; 100a) according to claim 3, configured to compare (210) the first converter stage output current (110-1-I_out) with an input current (110-2-I_in) for the second converter stage (110-2) and / or b) output (214) a first digital converter stage output signal (110-1-AS) based on said comparison (210).

5. The at least one converter stage (110-1) compares (220) the converter stage input current (110-1-I_in) with the converter stage reference current (110-1-I_ref), and outputs (222) the converter stage input current (110-1-I_in) as the converter stage output current (110-1-I_out) if the converter stage input current (110-1-I_in) is less than the converter stage reference current (110-1-I_ref); 5. An analog to digital converter device (100; 100a) according to claim 3 or 4, configured to output (224) a difference (110-1-I_diff) between the converter stage input current (110-1-I_in) and the converter stage reference current (110-1-I_ref) as the converter stage output current (110-1-I_out) when the converter stage input current (110-1-I_in) is greater than or equal to the converter stage reference current (110-1-I_ref).

6. the at least one converter stage (110-1) compares (230) the converter stage input current (110-1-I_in) with the converter stage reference current (110-1-I_ref), and if the converter stage input current (110-1-I_in) is less than the converter stage reference current (110-1-I_ref), outputs (232) a difference (110-1-I_diff') between the converter stage reference current (110-1-I_ref) and the converter stage input current (110-1-I_in) as the converter stage output current (110-1-I_out); and, if the converter stage input current (110-1-I_in) is greater than or equal to the converter stage reference current (110-1-I_ref), output (234) a difference (110-1-I_diff'') obtained by subtracting the difference between the converter stage input current (110-1-I_in) and the converter stage reference current (110-1-I_ref) from the converter stage reference current (110-1-I_ref) as the converter stage output current (110-1-I_out).

7. An analogue / digital converter device (100; 100a) according to any one of claims 1 to 6, wherein the first analogue / digital converter unit (110) is configured to output the first part (AS-dig-1) of the digital output signal (AS-dig) as a Gray coded signal (AS-dig-1), optionally a transcoding device (130) is provided, the transcoding device (130) being configured to transcode the Gray coded signal, for example into a binary coded signal (AS-dig-1').

8. An analogue to digital converter device (100; 100a) according to any one of claims 1 to 7, wherein a current mirror device (140) is provided for outputting the first output current (I_out_1) to the second analogue to digital converter unit (120).

9. An analogue / digital converter device (100; 100a) according to any one of claims 1 to 8, wherein the second analogue / digital converter unit (120) is configured to provide the second part (AS-dig-2) of the digital output signal (AS-dig) as a unary coded signal, and optionally a transcoding device (130a) is provided, the transcoding device (130a) being configured to transcode the unary coded signal (AS-dig-2), for example into a binary coded signal (AS-dig-2').

10. An analog / digital converter device (100; 100a) according to any one of claims 1 to 9, wherein the first analog / digital converter unit (110) and the second analog / digital converter unit (120) are arranged on a same substrate (1000), for example a semiconductor substrate.

11. A computing device (10), e.g. for determining a scalar product, e.g. a vector matrix multiplier, e.g. a dot product engine, comprising a matrix (M) of elements having controllable electrical resistance and at least one analogue / digital converter device (100; 100a) according to any one of the claims 1 to 10.

12. A method for operating an analog / digital converter device (100; 100a) configured to form a digital output signal (AS-dig) based on an input current (I_in), the analog / digital converter device (100; 100a) comprising a first analog / digital converter unit (110) of a first type (TYP-1) and a second analog / digital converter unit (120) of a second type (TYP-2), the second type (TYP-2) being different from the first type (TYP-1) and the first analog / digital converter unit (120) of a second type (TYP-2) being different from the first type (TYP-1). a digital converter unit (110) receives (200) an input current (I_in), forms (202) a first portion (AS-dig-1) of the digital output signal (AS-dig) based on the input current (I_in), and outputs (204) a first output current (I_out-1) to the second analog-to-digital converter unit (120), which forms (206) a second portion (AS-dig-2) of the digital output signal (AS-dig) based on the first output current (I_out-1).

13. Use (300) of an analog / digital converter device (100; 100a) according to any one of claims 1 to 10 and / or a computing device (10) according to claim 11 and / or a method according to claim 12 for at least one of the following elements: a) converting (301) electric currents (Ia; Ib; Ic) into binary values; b) performing binary coding (302); c) providing (303) an analog / digital converter, e.g. fully current-driven, e.g. hybrid.

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