Image sensor and electronic system including the same

Abstract

To provide an image sensor capable of achieving improvements in sensitivity, resolution and product completeness, and an electronic system including the same.SOLUTION: An image sensor 100 includes: a sensor array area SA which includes a plurality of unit pixels PX each including photodiodes PD disposed in a substrate 122 that has a frontside surface 122F and a backside surface 122B, and at least one isolation structure DSA passing through the substrate in a vertical direction with respect to the backside surface so as to isolate the plurality of unit pixels from one another; and a capacitor area CA which is adjacent to the sensor array area in a horizontal direction parallel to the backside surface and which includes at least one capacitor 158 disposed on the frontside surface and at least one dummy isolation structure DSB that passes through the substrate in the vertical direction at a position adjacent to the capacitor. One end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the backside surface of the substrate.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an image sensor and an electronic system including the same, and more particularly to an image sensor including a sensor array region and a capacitor region and an electronic system including the same. [Background technology]

[0002] Image sensors, which capture images and convert them into electrical signals, are used in a variety of fields, such as digital cameras, camcorders, PCS (Personal Communication Systems), game devices, security cameras, and medical micro cameras, due to the development of the computer and communication industries. To realize high-sensitivity image sensors through the high integration and miniaturization of pixel sizes of image sensors, the width of the sensing region limited by the element isolation structure is gradually narrowing. As a result, the density of the element isolation structure is high in the sensor array region including the element isolation structure, while in the peripheral circuit region surrounding the sensor array region, a relatively large difference in polishing speed occurs between the sensor array region and the peripheral circuit region when planarizing the backside surface of the substrate during the manufacturing process of the image sensor due to the absence of the element isolation structure, which makes it easy for process defects to occur in the subsequent photolithography process. Summary of the Invention [Problem to be solved by the invention]

[0003] The technical problem to be solved by the present invention is to provide an image sensor having a structure capable of suppressing process defects due to a step between a sensor array region and a capacitor region by minimizing a polishing rate difference between a sensor array region and a capacitor region adjacent to the sensor array region among a peripheral circuit region surrounding the sensor array region when planarizing a backside surface of a substrate in a manufacturing process of an image sensor.

[0004] Another technical problem to be solved by the present invention is to provide an electronic system including an image sensor having a structure capable of suppressing process defects due to a step between the sensor array region and the capacitor region by minimizing a polishing rate difference between a sensor array region and a capacitor region adjacent to the sensor array region among a peripheral circuit region surrounding the sensor array region when planarizing a backside surface of a substrate in a manufacturing process of an image sensor. [Means for solving the problem]

[0005] According to one aspect of the technical concept of the present invention, an image sensor includes a plurality of unit pixels including a plurality of photodiodes arranged in a substrate having a front side surface and a back side surface; a sensor array region configured to separate each of the plurality of unit pixels and including at least one isolation structure that penetrates the substrate in a vertical direction relative to the back side surface; and a capacitor region adjacent to the sensor array region in a horizontal direction parallel to the back side surface and including at least one capacitor arranged on the front side surface and at least one dummy isolation structure that penetrates the substrate in the vertical direction at a position adjacent to the at least one capacitor, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the back side surface of the substrate, and the at least one isolation structure and the at least one dummy isolation structure each include the same material.

[0006] According to another aspect of the present invention, there is provided an image sensor including: a plurality of unit pixels, each including a plurality of photodiodes, disposed in a substrate having a front side surface and a back side surface; a sensor array region including at least one isolation structure configured to isolate each of the plurality of unit pixels and penetrating the substrate in a direction perpendicular to the back side surface; a pad region surrounding the sensor array region and including a plurality of conductive pads; and a capacitor region disposed between the sensor array region and the pad region, including a plurality of capacitors disposed on the front side surface and at least one dummy isolation structure penetrating the substrate in the vertical direction between two adjacent capacitors selected from the plurality of capacitors, wherein one end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends in the same plane as the back side surface of the substrate, and the at least one isolation structure and the at least one dummy isolation structure include the same material.

[0007] According to yet another aspect of the present invention, there is provided an image sensor comprising: a first semiconductor chip including a logic region including a logic element and a peripheral circuit region including a peripheral circuit; and a second semiconductor chip stacked on the first semiconductor chip to overlap the first semiconductor chip in a vertical direction, the second semiconductor chip including: a substrate having a front side surface and a back side surface; a plurality of unit pixels including a plurality of photodiodes disposed in the substrate; a sensor array region including a plurality of isolation structures configured to isolate each of the unit pixels and penetrating the substrate in a vertical direction relative to the back side surface; and a capacitor region surrounding the sensor array region and including a plurality of capacitors disposed on the front side surface of the substrate and a plurality of dummy isolation structures penetrating the substrate in the vertical direction at positions adjacent to the plurality of capacitors, wherein one end surface of each of the plurality of isolation structures and the plurality of dummy isolation structures extends in the same plane as the back side surface of the substrate, and the plurality of isolation structures and the plurality of dummy isolation structures include the same material.

[0008] According to one aspect of the technical concept of the present invention, an electronic system includes at least one camera module including an image sensor selected from image sensors having the above-mentioned characteristics, and a processor configured to process image data provided by the at least one camera module. Effect of the Invention

[0009] The image sensor according to the technical idea of ​​the present invention can suppress process defects due to a step between the sensor array region and the capacitor region by minimizing the polishing rate difference between the sensor array region and the surrounding capacitor region when planarizing the backside surface of the substrate during the manufacturing process of the image sensor. Therefore, it is possible to prevent a decrease in process efficiency due to a deterioration in depth of focus (DOF) in a photolithography process performed after a process of planarizing the substrate to the backside surface during the manufacturing process of the image sensor, improve productivity in the manufacturing process of the image sensor, and improve the sensitivity and resolution of the image sensor to improve the completeness of the product.

[0010] An electronic system according to the teachings of the present invention may include an image sensor that provides superior sensitivity and resolution, thereby improving operational characteristics and reliability. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic exploded perspective view of an image sensor according to an embodiment of the present invention; [Diagram 2] 1 is a block diagram illustrating a partial configuration of an image sensor according to an embodiment of the present invention; [Diagram 3] 1 is a cross-sectional view illustrating a partial configuration of an image sensor according to an embodiment of the present invention; [Figure 4] 4 is an enlarged cross-sectional view showing a partial area indicated by "EX1" in FIG. 3 rotated 180 degrees on the XY plane. [Figure 5A]11 is a plan view of a portion of a capacitor region included in an image sensor according to another embodiment of the present invention; [Figure 5B] 5B is a cross-sectional view of a partial area of ​​a portion along the cross section line X2-X2' in FIG. 5A. [Figure 6] 13 is a plan view illustrating an image sensor according to still another embodiment of the present invention; FIG. [Figure 7] 13 is a plan view illustrating an image sensor according to still another embodiment of the present invention; FIG. [Figure 8A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an image sensor according to an embodiment of the present invention; [Figure 8B] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an image sensor according to an embodiment of the present invention; [Figure 8C] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method of manufacturing an image sensor according to an embodiment of the present invention; [Figure 9A] FIG. 1 is a block diagram of an electronic system according to an embodiment of the inventive concept. [Figure 9B] FIG. 9B is a detailed block diagram of a camera module included in the electronic system of FIG. 9A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to refer to the same components in the drawings, and duplicated descriptions thereof will be omitted.

[0013] FIG. 1 is a schematic exploded perspective view of an image sensor 100 according to an embodiment of the inventive concept.

[0014] 1, the image sensor 100 includes a first semiconductor chip 110 and a second semiconductor chip 120 that are overlapped in a vertical direction (Z direction). The first semiconductor chip 110 is a logic chip, and the second semiconductor chip 120 is a sensor chip.

[0015] The first semiconductor chip 110 includes a logic region LA including logic elements and a peripheral circuit region PE including peripheral circuits. The logic region LA may be surrounded by the peripheral circuit region PE.

[0016] The second semiconductor chip 120 may be stacked on the first semiconductor chip 110 so as to overlap the first semiconductor chip 110 in the vertical direction (Z direction). The second semiconductor chip 120 includes a sensor array region SA, a capacitor region CA surrounding the sensor array region SA, a pad region PA surrounding the sensor array region SA and the capacitor region CA, and a plurality of through-via regions TVA interposed between the capacitor region CA and the pad region PA. In the second semiconductor chip 120, the capacitor region CA, the plurality of through-via regions TVA, and the pad region PA may form a peripheral circuit region of the second semiconductor chip 120.

[0017] In the second semiconductor chip 120, the sensor array area SA includes an active pixel sensor area APS including active pixels for generating active signals corresponding to wavelengths of external light, and an optical black sensor area OBS including optical black pixels for blocking external light and generating optical black signals. Dummy pixel sensors may be disposed at edge portions of the active pixel sensor area APS close to the optical black sensor area OBS.

[0018] A plurality of capacitors (e.g., capacitor 158 in FIG. 3) may be arranged in the capacitor area CA of the second semiconductor chip 120. The sensor array area SA may be arranged within an area defined by the capacitor area CA. In the second semiconductor chip 120, the capacitor area CA may be arranged closer to the sensor array area SA than the pad area PA. That is, in the horizontal direction (X-direction or Y-direction in FIG. 1), the distance between the capacitor area CA and the sensor array area SA is shorter than the distance between the capacitor area CA and the pad area PA.

[0019] The capacitor region CA may be disposed adjacent to the optical black sensor region OBS and may surround the active pixel sensor region APS and the optical black sensor region OBS at a position separated from the active pixel sensor region APS with the optical black sensor region OBS in between. The capacitor region CA has a rectangular ring shape surrounding the sensor array region SA in a plan view (XY plane in FIG. 1), but according to the technical idea of ​​the present invention, the planar shape of the capacitor region CA is not limited to that illustrated in FIG. 1. For example, the capacitor region CA may be disposed locally or intermittently along the periphery of the optical black sensor region OBS in a region adjacent to the optical black sensor region OBS.

[0020] A plurality of pads 2 may be arranged in the pad area PA of the second semiconductor chip 120. In an exemplary embodiment, the plurality of pads 2 may transmit and receive electrical signals to and from an external device. In another exemplary embodiment, the plurality of pads 2 may serve to transmit a driving power supply, such as a power supply voltage or a ground voltage, supplied from the outside to a circuit within the second semiconductor chip 120.

[0021] A plurality of through vias 4 may be arranged in the plurality of through via areas TVA included in the second semiconductor chip 120. Some of the plurality of through vias 4 may be connected to unit pixels in the sensor array area SA through wiring included in the second semiconductor chip 120. Another portion of the plurality of through vias 4 may serve to connect wiring included in the first semiconductor chip 110 to wiring of the second semiconductor chip 120. Yet another portion of the plurality of through vias 4 may serve to connect wiring included in the first semiconductor chip 110 to logic elements in the logic area LA included in the second semiconductor chip 120.

[0022] FIG. 2 is a block diagram for explaining a partial configuration of the image sensor 100 illustrated in FIG.

[0023] 1 and 2, an image sensor 100 includes a pixel array 10 disposed in a sensor array area SA, and a circuit for controlling the pixel array 10. In an exemplary embodiment, the circuit for controlling the pixel array 10 includes a column driver 20, a row driver 30, a timing controller 40, and a readout circuit 50.

[0024] The image sensor 100 operates according to a control command received from the image processor 70, and may convert light transmitted from an external object into an electrical signal and output the electrical signal to the image processor 70. The image sensor 100 may be a CMOS image sensor.

[0025] The pixel array 10 includes a plurality of unit pixels PX arranged in a two-dimensional array structure in a matrix along a plurality of row lines and a plurality of column lines. The term "unit pixel" used in this specification is also simply referred to as pixel.

[0026] Each of the unit pixels PX includes a photodiode. The photodiode may receive light transmitted from an object and generate charges. The image sensor 100 may perform an autofocus function using a phase difference between pixel signals generated from the photodiodes included in the unit pixels PX. Each of the unit pixels PX includes a pixel circuit for generating a pixel signal from charges generated in the photodiode.

[0027] In an exemplary embodiment, the image sensor 100 is also an image sensor capable of performing a global shutter operation. For example, when the image sensor 100 is operated, all unit pixels PX included in the pixel array 10 are simultaneously exposed to an optical signal provided from the outside, and charges may be simultaneously stored in each of the unit pixels PX. In an exemplary embodiment, pixel signals based on the charges stored in each of the unit pixels PX may be output sequentially by row.

[0028] The column driver 20 includes a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler is connected to a unit pixel PX included in a row selected by a row selection signal supplied by the row driver 30 through a column line, and may perform correlated double sampling to detect a reset voltage and a pixel voltage. The analog-to-digital converter may convert the reset voltage and the pixel voltage detected by the correlated double sampler into digital signals and transmit them to the readout circuit 50.

[0029] The readout circuit 50 may include a latch or buffer circuit, an amplifier circuit, etc., capable of temporarily storing a digital signal, and may temporarily store or amplify the digital signal received from the column driver 20 to generate image data. Operation timings of the column driver 20, the row driver 30, and the readout circuit 50 are determined by a timing controller 40, and the timing controller 40 may operate according to a control command transmitted by an image processor 70.

[0030] The image processor 70 may signal-process the image data output by the readout circuit 50 and output the processed image data to a display device or store the processed image data in a storage device such as a memory. When the image sensor 100 is mounted on an autonomous vehicle, the image processor 70 may signal-process the image data and transmit the processed image data to a main controller that controls the autonomous vehicle.

[0031] Fig. 3 is a cross-sectional view for explaining a partial configuration of the image sensor 100 illustrated in Fig. 1. Fig. 4 is an enlarged cross-sectional view showing a partial area indicated by "EX1" in Fig. 3 rotated 180° on the XY plane.

[0032] 1, 3 and 4, the image sensor 100 includes a second semiconductor chip 120 bonded onto a first semiconductor chip 110 using a bonding layer BL. The second semiconductor chip 120 includes an active pixel sensor area APS, an optical black sensor area OBS, and a capacitor area CA arranged in sequence along a first horizontal direction (X direction). The active pixel sensor area APS and the optical black sensor area OBS may constitute a sensor array area SA.

[0033] A plurality of unit pixels PX may be arranged in the active pixel sensor area APS and the optical black sensor area OBS. Active pixels for generating active signals corresponding to wavelengths of external light may be arranged in the active pixel sensor area APS. Optical black pixels for blocking external light and generating optical black signals may be arranged in the optical black sensor area OBS.

[0034] The optical black sensor area OBS may be formed along the periphery of the active pixel sensor area APS. The active pixel sensor area APS and the optical black sensor area OBS may constitute a sensor array area. In an exemplary embodiment, a dummy unit pixel may be disposed within the optical black sensor area OBS. The dummy unit pixel is also a pixel that does not generate an active signal.

[0035] The image sensor 100 includes a substrate 122. The substrate 122 may be a semiconductor layer. In an exemplary embodiment, the substrate 122 may be a semiconductor layer doped with P-type impurities. For example, the substrate 122 may be a semiconductor layer made of Si, Ge, SiGe, a II-VI compound semiconductor, a III-V compound semiconductor, or a combination thereof. In an exemplary embodiment, the substrate 122 may be a P-type epitaxial semiconductor layer epitaxially grown from a P-type bulk silicon substrate. The substrate 122 has a front side surface 122A and a back side surface 122B that are opposite surfaces.

[0036] Each of the unit pixels PX in the active pixel sensor region APS and the optical black sensor region OBS includes a photodiode PD, a floating diffusion region FD, and a transfer transistor TX. The photodiode PD and the floating diffusion region FD may be disposed in the substrate 122. The photodiode PD may generate charges in proportion to the amount of light incident from the outside. The generated charges may be accumulated in the photodiode PD, and the charges accumulated in the photodiode PD may be transferred to the floating diffusion region FD. The charges transferred to the floating diffusion region FD may be applied to a source follower gate included in the unit pixel PX. One end of the transfer transistor TX may be connected to the photodiode PD, and the other end of the transfer transistor TX may be connected to the floating diffusion region FD. The transfer transistor TX may transfer the charges generated in the photodiode PD to the floating diffusion region FD. The transfer transistor TX includes a transfer gate, a gate insulating film, and a gate spacer. The transfer gate includes a portion embedded in the substrate 122. A gate insulating layer may be interposed between the transfer gate and the substrate 122. Gate spacers may cover both sidewalls of the transfer gate.

[0037] The substrate 122 includes a plurality of isolation structures DSA configured to isolate the plurality of unit pixels PX in the active pixel sensor area APS and the optical black sensor area OBS. In an exemplary embodiment, at least some of the isolation structures DSA illustrated in the active pixel sensor area APS and the optical black sensor area OBS in FIG. 3 may have a structure connected to each other. The isolation structures DSA may penetrate the substrate 122 in a vertical direction (Z direction). In this specification, the vertical direction (Z direction) may refer to a direction perpendicular to the backside surface 122B of the substrate 122.

[0038] The capacitor region CA may be adjacent to the sensor array region SA in a horizontal direction parallel to the backside surface 122B of the substrate 122, for example, in a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of capacitors 158 and a plurality of dummy isolation structures DSB may be arranged in the capacitor region CA. The plurality of capacitors 158 may be arranged on the frontside surface 122F on the active region AC of the substrate 122. The plurality of dummy isolation structures DSB may penetrate the substrate 122 in a vertical direction (Z direction) at positions adjacent to each of the plurality of capacitors 158.

[0039] In the capacitor region CA, an insulating film 156 may be interposed between the front side surface 122F of the substrate 122 and the capacitor 158. In an exemplary embodiment, the capacitor 158 is made of a doped polysilicon film. The insulating film 156 may be made of a silicon oxide film. However, the respective constituent materials of the capacitor 158 and the insulating film 156 are not limited to those exemplified. The structure of the plurality of capacitors 158 is not limited to the structure exemplified in FIG. 3. For example, the plurality of capacitors 158 included in the capacitor region CA may each be a capacitor having a MOS (metal-oxide-semiconductor) structure or a capacitor having a MIM (metal-insulator-metal) structure.

[0040] One end surface D1 of each of the plurality of isolation structures DSA in the sensor array region SA and one end surface D2 of each of the plurality of dummy isolation structures DSB in the capacitor region CA may extend from the same plane as the backside surface 122B of the substrate 122. The plurality of isolation structures DSA in the sensor array region SA and the plurality of dummy isolation structures DSB in the capacitor region CA include the same material.

[0041] Each of the isolation structures DSA in the sensor array region SA includes a local isolation film 152A and a main isolation film 154A. The main isolation film 154A may penetrate the substrate 122 in a vertical direction (Z direction) from the front side surface 122F to the back side surface 122B of the substrate 122. The local isolation film 152A may penetrate only a portion of the substrate 122 from the front side surface 122F of the substrate 122 in the vertical direction (Z direction) and cover a sidewall of a portion of the main isolation film 154A adjacent to the front side surface 122F of the substrate 122.

[0042] Each of the dummy isolation structures DSB in the capacitor region CA includes a local isolation film 152B and a main isolation film 154B. The main isolation film 154B may penetrate the substrate 122 in a vertical direction (Z direction) from the front side surface 122F to the back side surface 122B of the substrate 122. The local isolation film 152B may penetrate only a portion of the substrate 122 from the front side surface 122F of the substrate 122 in the vertical direction (Z direction) and cover a sidewall of a portion of the main isolation film 154B adjacent to the front side surface 122F of the substrate 122.

[0043] In the plurality of isolation structures DSA in the sensor array region SA and the plurality of dummy isolation structures DSB in the capacitor region CA, the width of the main element isolation films 154A, 154B in the first horizontal direction (X direction) may become gradually narrower from the front side surface 122F of the substrate 122 toward the back side surface 122B.

[0044] The local isolation films 152A, 152B and the main isolation films 154A, 154B may each include, but are not limited to, silicon oxide, silicon nitride, SiCN, SiON, SiOC, polysilicon, metal, metal nitride, metal oxide, borosilicate glass (BSG), phosphosilicate glass (SG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PE-TEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), organosilicate glass (OSG), air, or a combination thereof. In this specification, the term "air" may refer to the atmosphere or other gases present during the manufacturing process. When at least one of the local isolation films 152A, 152B and the main isolation films 154A, 154B includes a metal, the metal may be tungsten (W), copper (Cu), or a combination thereof. When at least one of the local isolation films 152A, 152B and the main isolation films 154A, 154B includes a metal nitride, the metal nitride is TiN, TaN, or a combination thereof. When at least one of the local isolation films 152A, 152B and the main isolation films 154A, 154B includes a metal oxide, the metal oxide is ITO (indium tin oxide), aluminum oxide (Al 2 O 3 ), or a combination thereof.

[0045] In an example embodiment, at least one of the local isolation layers 152A, 152B and the main isolation layers 154A, 154B may further include a silicon region doped with P+ type impurities. The silicon region doped with P+ type impurities may reduce dark current in the unit pixel PX, thereby improving the quality of the image sensor 100.

[0046] In an exemplary embodiment, the density of the isolation structures DSA in the sensor array area SA and the density of the dummy isolation structures DSB in the capacitor area CA are the same or similar. In another exemplary embodiment, the density of the isolation structures DSA in the sensor array area SA and the density of the dummy isolation structures DSB in the capacitor area CA may be different from each other. In one embodiment, the density of the dummy isolation structures DSB in the capacitor area CA is lower than the density of the isolation structures DSA in the sensor array area SA. In another example, the density of the dummy isolation structures DSB in the capacitor area CA is higher than the density of the isolation structures DSA in the sensor array area SA.

[0047] The image sensor 100 includes a backside insulating film 162 covering the backside surface 122B of the substrate 122, a plurality of grid patterns 164 disposed on the backside insulating film 162 in the active pixel sensor region APS, a plurality of color filters 170 disposed on the backside insulating film 162 in the active pixel sensor region APS, and a plurality of microlenses 180 covering the plurality of color filters 170 in the active pixel sensor region APS.

[0048] In an exemplary embodiment, the backside insulating film 162 may be made of, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, or a combination thereof. The backside insulating film 162 may function as an anti-reflection film. The backside insulating film 162 may improve the light receiving rate of the photodiode PD by preventing reflection of light incident on the substrate 122 from the outside. The backside insulating film 162 may also have a planarized surface. The color filters 170 and the microlenses 180 are disposed on the planarized surface of the backside insulating film 162, so that the heights of the color filters 170 and the microlenses 180 are uniform.

[0049] The color filters 170 may be disposed on the backside insulating film 162 to correspond to the unit pixels PX. The color filters 170 may have various color filters according to the unit pixels PX. In an exemplary embodiment, the color filters 170 may be arranged in a Bayer pattern including a red color filter, a green color filter, and a blue color filter. In another exemplary embodiment, the color filters 170 may include a yellow filter, a magenta filter, and a cyan filter, and may further include a white filter.

[0050] The grid pattern 164 includes a material having a refractive index lower than that of silicon (Si) and may be made of, but is not limited to, a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or a combination thereof, in an exemplary embodiment.

[0051] In the active pixel sensor region APS, a first protective layer 166 may be interposed between the backside insulating layer 162 and the plurality of color filters 170 and between the plurality of grid patterns 164 and the plurality of color filters 170. The first protective layer 166 may conformally cover an upper surface of the backside insulating layer 150 and side and upper surfaces of the grid patterns 164. The first protective layer 166 may play a role in protecting the backside insulating layer 162 and the grid patterns 164 from being damaged. The first protective layer 166 may be made of, but is not limited to, an aluminum oxide layer.

[0052] A second protective film 182 may be formed on the microlens 180. The second protective film 182 may conformally cover the surface of the microlens 180. The second protective film 182 may serve to protect the microlens 180 from external impacts and improve the light collecting ability of the microlens 180. In an exemplary embodiment, the second protective film 182 may be, but is not limited to, a silicon oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a combination thereof.

[0053] A wiring structure may be disposed on the front side surface 122F of the substrate 122. The wiring structure includes a plurality of interlayer insulating films 130, 132, 134, 136, 138 covering the plurality of transfer transistors TX, a plurality of via contacts 141, 143 covered by the plurality of interlayer insulating films 130, 132, 134, 136, 138, and a plurality of wiring layers 142, 144, 145, 146. Some of the via contacts 141, 143 may electrically connect the floating diffusion region FD to the wiring layers 142, 144, 145, 146. Of the plurality of wiring layers 142, 144, 145, 146, some of the wiring layers 142, 144, 145, 146 disposed in the capacitor region CA may be disposed to overlap the capacitor 158 in the vertical direction (Z direction).

[0054] The number and arrangement of the interlayer insulating films 130, 132, 134, 136, 138 and the wiring layers 142, 144, 145, 146 are not limited to those illustrated in FIG. 3, and may be modified and changed in various ways as necessary. The wiring layers 142, 144, 145, 146 include conductive lines connected to a plurality of transistors electrically connected to the photodiodes PD. An electrical signal converted by the photodiodes PD may be processed through the wiring layers 142, 144, 145, 146. In an exemplary embodiment, the interlayer insulating films 130, 132, 134, 136, 138 may be made of, but are not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a dielectric film having a lower dielectric constant than a silicon oxide film, or a combination thereof. In an exemplary embodiment, the via contacts 141, 143 and the wiring layers 142, 144, 145, 146 may each be made of, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or combinations thereof.

[0055] The first semiconductor chip 110 includes a logic substrate 112 and a plurality of transistors TR disposed on the logic substrate 112. The plurality of transistors TR may constitute a logic circuit. In an exemplary embodiment, the plurality of transistors TR may constitute a circuit for controlling transistors included in the second semiconductor chip 120.

[0056] An interlayer insulating film 114 covering the transistors TR, and a plurality of via contacts 115 and a plurality of wiring layers 116 covered by the interlayer insulating film 114 may be disposed on the logic substrate 112. The transistors TR and the wiring layers 116 may be electrically connected to each other through the via contacts 115. Among the wiring layers 116, a portion of the wiring layers 116 that vertically overlaps the capacitor region CA may be disposed to overlap the capacitor 158 in the vertical direction (Z direction). The interlayer insulating film 114 may be made of, but is not limited to, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a dielectric film having a lower dielectric constant than a silicon oxide film, or a combination thereof. The via contacts 115 and the wiring layers 116 may be made of, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or a combination thereof.

[0057] A backside metal layer BML may be disposed on the backside surface 122B of the substrate 122 from the optical black sensor region OBS and the capacitor region CA. The backside metal layer BML may be separated from the backside surface 122B of the substrate 122 by a backside insulating film 162. The backside metal layer BML may block light incident on the optical black sensor region OBS. In an exemplary embodiment, the backside metal layer BML may be made of, but is not limited to, titanium (Ti), titanium nitride (TiN), tungsten (W), or a combination thereof.

[0058] A color filter 170B may be disposed on the backside metal layer BML in the optical black sensor area OBS and the capacitor area CA. In an exemplary embodiment, the color filter 170B may be, but is not limited to, a blue color filter.

[0059] The color filter 170B in the optical black sensor region OBS and the capacitor region CA may be covered with a third protective film 180B. The third protective film 180B may be made of a light-transmitting resin. In an exemplary embodiment, the third protective film 180B includes the same material as the material constituting the microlens 180. The third protective film 180B may be covered with a fourth protective film 182B. The fourth protective film 182B may have substantially the same configuration as that described for the second protective film 182 disposed in the active pixel sensor region APS.

[0060] 1 to 4 includes a capacitor region CA surrounding at least a part of the sensor array region SA at a position adjacent to the sensor array region SA, and a plurality of dummy isolation structures DSB are arranged in the capacitor region CA, penetrating the substrate 122 in the vertical direction (Z direction) at positions adjacent to each of the capacitors 158. One end surface D1 of each of the plurality of isolation structures DSA in the sensor array region SA and one end surface D2 of each of the plurality of dummy isolation structures DSB in the capacitor region CA extend in the same plane as the backside surface 122B of the substrate 122, and the isolation structures DSA arranged in the sensor array region SA and the plurality of dummy isolation structures DSB arranged in the capacitor 158 include the same material. Therefore, when the substrate 122 is planarized to the backside surface 122B in the manufacturing process of the image sensor 100, a polishing rate difference between the sensor array region SA and the surrounding capacitor region CA is minimized, thereby suppressing process defects due to a step between the sensor array region SA and the capacitor region CA, for example, defects caused by dishing from the capacitor region CA. In addition, when a photolithography process is performed after the process of planarizing the substrate 122 to the backside surface 122B in the manufacturing process of the image sensor 100, a decrease in process efficiency due to deterioration of DOF (depth of focus) is prevented, and the productivity of the manufacturing process of the image sensor 100 is improved, and the sensitivity and resolution of the image sensor 100 are improved, thereby improving the product completion rate.

[0061] 5A and 5B are diagrams for explaining an image sensor 200 according to another embodiment of the technical idea of ​​the present invention, in which Fig. 5A is a plan view of a portion of a capacitor region CA, and Fig. 5B is a cross-sectional view of a portion of a portion along the cross section line X2-X2' in Fig. 5A. Fig. 5B illustrates the configuration of a region of the image sensor 200 corresponding to the region indicated by "EX1" in Fig. 3. In Figs. 5A and 5B, the same reference numerals as in Figs. 1 to 4 indicate the same members, and detailed descriptions thereof will be omitted here.

[0062] 5A and 5B, the image sensor 200 has substantially the same configuration as the image sensor 100 described with reference to Figures 1 to 4. However, the image sensor 200 includes a plurality of capacitors 158 disposed in a capacitor region CA, and a plurality of dummy isolation structures DSB2 disposed adjacent to the capacitors 158 from the capacitor region CA. The plurality of dummy isolation structures DSB2 may be disposed to be spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0063] In the image sensor 200, the plurality of capacitors 158 may be arranged in a matrix in a row along a first horizontal direction (X direction) and a second horizontal direction (Y direction) that are parallel to the backside surface 122B of the substrate 122 and perpendicular to each other. The plurality of capacitors 158 may be arranged spaced apart from each other in the first horizontal direction (X direction) and the second horizontal direction (Y direction). In the image sensor 200, some of the plurality of capacitors 158 may be arranged in a row along the first horizontal direction (X direction). In this specification, among the plurality of capacitors 158, the plurality of capacitors 158 arranged in a row along the first horizontal direction (X direction) may each be referred to as a first capacitor. In the image sensor 200, another portion of the plurality of capacitors 158 may be arranged in a row along the second horizontal direction (Y direction). In this specification, among the plurality of capacitors 158, the plurality of capacitors 158 arranged in a row along the second horizontal direction (Y direction) may each be referred to as a second capacitor.

[0064] The plurality of dummy isolation structures DSB2 may have substantially the same configuration as that of the dummy isolation structure DSB described with reference to Figures 3 and 4. However, two dummy isolation structures DSB2 may be disposed between two adjacent capacitors 158 among the plurality of capacitors 158 in the image sensor 200.

[0065] The multiple dummy isolation structures DSB2 may penetrate the portions of the multiple capacitors 158 on the substrate 122 that face the isolation space between two adjacent capacitors 158 in the vertical direction (Z direction) so as not to overlap with the multiple capacitors 158 in the vertical direction (Z direction).

[0066] As illustrated in FIG. 5A, among the multiple dummy isolation structures DSB2, the multiple dummy isolation structures DSB2 arranged in a row along the first horizontal direction (X direction) are also spaced apart from each other along the first horizontal direction (X direction). In this specification, the multiple dummy isolation structures DSB2 arranged in a row along the first horizontal direction (X direction) may each be referred to as a first dummy isolation structure. Among the multiple dummy isolation structures DSB2, the multiple dummy isolation structures DSB2 arranged in a row along the second horizontal direction (Y direction) are also spaced apart from each other along the second horizontal direction (Y direction). In this specification, the multiple dummy isolation structures DSB2 arranged in a row along the second horizontal direction (Y direction) may each be referred to as a second dummy isolation structure.

[0067] Each of the dummy isolation structures DSB2 has a rectangular ring shape surrounding the capacitor 158 at a position horizontally spaced apart from the capacitor 158 in a plan view parallel to the backside surface 122B of the substrate 122 (XY plane in FIGS. 5A and 5B ), and may penetrate the substrate 122 in the vertical direction (Z direction) around the capacitor 158. The dummy isolation structures DSB2 may be arranged in a matrix in a row along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0068] Each of the dummy isolation structures DSB2 includes a portion extending long along the second horizontal direction (Y direction) in a local region of the substrate 122 facing a space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row along the first horizontal direction (X direction). Each of the dummy isolation structures DSB2 includes a portion extending long along the first horizontal direction (X direction) in a local region of the substrate 122 facing a space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row along the second horizontal direction (Y direction).

[0069] Fig. 6 is a plan view for explaining an image sensor 300 according to still another embodiment of the technical concept of the present invention. Fig. 6 illustrates a planar configuration of a part of a capacitor area CA of the image sensor 300. In Fig. 6, the same reference symbols as Figs. 1 to 5 indicate the same members, and detailed descriptions thereof will be omitted here.

[0070] 6, the image sensor 300 has substantially the same configuration as the image sensor 200 described with reference to Figures 5A and 5B, except that the image sensor 300 includes a plurality of dummy isolation structures DSB3 disposed adjacent to the capacitor 158 from the capacitor region CA. The plurality of dummy isolation structures DSB3 may be disposed to be spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0071] The plurality of dummy isolation structures DSB3 may have substantially the same configuration as the dummy isolation structures DSB described with reference to Figures 3 and 4. However, in the image sensor 300, two dummy isolation structures DSB3 may be disposed between two adjacent capacitors 158 among the plurality of capacitors 158.

[0072] Of the multiple dummy isolation structures DSB3, the separation distance between two dummy isolation structures DSB3 arranged between two adjacent capacitors 158 in the first horizontal direction (X direction) is shorter than the separation distance between two dummy isolation structures DSB3 spaced apart in the first horizontal direction (X direction) with one capacitor 158 sandwiched between them. Of the multiple dummy isolation structures DSB3, the separation distance between two dummy isolation structures DSB3 arranged between two adjacent capacitors 158 in the second horizontal direction (Y direction) is shorter than the separation distance between two dummy isolation structures DSB3 spaced apart in the second horizontal direction (Y direction) with one capacitor 158 sandwiched between them.

[0073] Some of the dummy isolation structures DSB3 include a portion extending long along the second horizontal direction (Y direction) in a local region of the substrate 122 facing a space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row along the first horizontal direction (X direction). Other of the dummy isolation structures DSB3 include a portion extending long along the first horizontal direction (X direction) in a local region of the substrate 122 facing a space between two adjacent capacitors 158 among the plurality of capacitors 158 arranged in a row along the second horizontal direction (Y direction).

[0074] Fig. 7 is a plan view for explaining an image sensor 400 according to still another embodiment of the technical concept of the present invention. Fig. 7 illustrates a planar configuration of a part of a capacitor area CA of the image sensor 400. In Fig. 7, the same reference symbols as Figs. 1 to 5 indicate the same members, and detailed descriptions thereof will be omitted here.

[0075] 7, the image sensor 400 has substantially the same configuration as the image sensor 200 described with reference to Figures 5A and 5B, except that the image sensor 400 includes a plurality of dummy isolation structures DSB4 disposed adjacent to the capacitor 158 from the capacitor region CA. The plurality of dummy isolation structures DSB4 may be disposed to be spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0076] The plurality of dummy isolation structures DSB4 may have substantially the same configuration as the dummy isolation structures DSB described with reference to Figures 3 and 4. However, one dummy isolation structure DSB4 may be disposed between two adjacent capacitors 158 among the plurality of capacitors 158 in the image sensor 400.

[0077] Some of the dummy isolation structures DSB4 may be spaced apart from one another along the first horizontal direction (X direction) and arranged in a row along the first horizontal direction (X direction). In this specification, the dummy isolation structures DSB4 that are spaced apart from one another along the first horizontal direction (X direction) and arranged in a row along the first horizontal direction (X direction) among the dummy isolation structures DSB4 may be referred to as first dummy isolation structures. Other of the dummy isolation structures DSB4 may be spaced apart from one another along the second horizontal direction (Y direction) and arranged in a row along the second horizontal direction (Y direction). In this specification, the dummy isolation structures DSB4 that are spaced apart from one another along the second horizontal direction (Y direction) and arranged in a row along the second horizontal direction (Y direction) among the dummy isolation structures DSB4 may be referred to as second dummy isolation structures.

[0078] Among the multiple dummy isolation structures DSB4, the first dummy isolation structures are each selected from the multiple capacitors 158, are arranged one by one between two adjacent capacitors 158 in the second horizontal direction (Y direction), and may each have a linear first line shape extending long along the first horizontal direction (X direction).

[0079] The second dummy isolation structures DSB4 among the plurality of dummy isolation structures may be selected from the plurality of capacitors 158, may be disposed between two adjacent capacitors 158 in the first horizontal direction (X direction), and may have a linear second line shape extending long along the second horizontal direction (Y direction). The second lines may be perpendicular to the first lines.

[0080] In an exemplary embodiment, the separation distance between each of the dummy isolation structures DSB4 arranged in a row along the first horizontal direction (X direction) is constant along the first horizontal direction (X direction). In an exemplary embodiment, the separation distance between each of the dummy isolation structures DSB4 arranged in a row along the second horizontal direction (Y direction) is constant along the second horizontal direction (Y direction).

[0081] The image sensors 200, 300, 400 described with reference to Figures 5A, 5B, 6, and 7 include a capacitor region CA that surrounds at least a part of the sensor array region SA at a position adjacent to the sensor array region SA, and a plurality of dummy isolation structures DSB2, DSB3, and DSB4 that penetrate the substrate 122 in the vertical direction (Z direction) are arranged in the capacitor region CA at positions adjacent to the capacitors 158. One end surface of each of the plurality of dummy isolation structures DSB2, DSB3, and DSB4 and one end surface D1 (see Figure 3) of each of the plurality of isolation structures DSA in the sensor array region SA extend in the same plane as the backside surface 122B of the substrate 122, and the plurality of dummy isolation structures DSB2, DSB3, and DSB4 and the isolation structure DSA arranged in the sensor array region SA include the same material. Therefore, when the substrate 122 is planarized to the backside surface 122B in the manufacturing process of the image sensors 200, 300, 400, a polishing rate difference between the sensor array region SA and the capacitor region CA therearound can be minimized, thereby suppressing process defects due to a step between the sensor array region SA and the capacitor region CA, for example, defects that cause dishing in the capacitor region CA. In addition, when a photolithography process is performed after the process of planarizing the substrate 122 to the backside surface 122B in the manufacturing process of the image sensors 200, 300, 400, a decrease in process efficiency due to DOF deterioration can be prevented, and the productivity of the manufacturing process of the image sensors 200, 300, 400 can be improved, and the sensitivity and resolution of the image sensors 200, 300, 400 can be improved, thereby improving the product completion rate.

[0082] 8A to 8C are cross-sectional views showing a process sequence for explaining a method for manufacturing an image sensor according to an embodiment of the technical concept of the present invention. An exemplary method for manufacturing the image sensor 100 illustrated in FIGS. 3 and 4 will be explained with reference to FIGS. 8A to 8C. In FIGS. 8A to 8C, the same reference numerals as those in FIGS. 1 to 4 indicate the same members, and redundant explanations thereof will be omitted here.

[0083] 8A, after preparing the substrate 122, a plurality of shallow trenches T1 may be formed by partially etching the substrate 122 from a front side surface 122F of the substrate 122 in the sensor array region SA and the capacitor region CA, and a plurality of local device isolation layers 152A, 152B may be formed to fill the plurality of shallow trenches T1. Then, a plurality of dip trenches T2 penetrating the local device isolation layer 152B and a portion of the substrate 122 may be formed, and a plurality of main device isolation layers 154A, 154B may be formed to fill the plurality of dip trenches T2. As a result, a plurality of isolation structures DSA each including the local device isolation layer 152A and the main device isolation layer 154A may be formed in the sensor array region SA, and a plurality of dummy isolation structures DSB each including the local device isolation layer 152B and the main device isolation layer 154B may be formed in the capacitor region CA. A plurality of active regions AC may be defined in the capacitor region CA by the plurality of dummy isolation structures DSB.

[0084] Next, in the sensor array region SA, ions may be implanted into the substrate 122 from the front side surface 122F of the substrate 122 to form a plurality of photodiodes PD in the sensor array region SA.

[0085] Thereafter, in the sensor array region SA, a gate dielectric layer and a plurality of gate structures including a transfer transistor TX having a transfer gate may be formed on the front side surface 122F of the substrate 122, and impurity ions may be implanted into a portion of the substrate 122 from the front side surface 122F of the substrate 122 to form a floating diffusion region FD. The plurality of gate structures may include gate structures constituting transistors required to drive a plurality of unit pixels PX included in the image sensor 100.

[0086] During the formation of a plurality of gate structures including the transfer transistors TX in the sensor array region SA, a plurality of insulating films 156 and a plurality of capacitors 158 may be formed on the front side surface 122F of the substrate 122 in the capacitor region CA.

[0087] Thereafter, in the sensor array region SA and the capacitor region CA, a wiring structure including a plurality of interlayer insulating films 130, 132, 134, 136, and 138 covering a plurality of gate structures including the transfer transistors TX and a plurality of capacitors 158, a plurality of via contacts 141, 143, and a plurality of wiring layers 142, 144, 145, and 146 may be formed. Then, a bonding layer BL may be formed on the interlayer insulating film 138 exposed to the outside of the wiring structure.

[0088] Referring to FIG. 8B, the first semiconductor chip 110 is bonded onto the bonding layer BL, and the resultant is rotated so that the substrate 122 faces upward in the vertical direction (Z direction).

[0089] 8C, in the sensor array region SA and the capacitor region CA, a mechanical grinding process, a chemical mechanical polishing (CMP) process, a wet etching process, or a combination thereof may be used to remove exposed portions of the substrate 122, portions of each of the isolation structures DSA, and portions of each of the dummy isolation structures DSB, so that a backside surface 122B of the substrate 122, one end surface D1 of each of the isolation structures DSA in the sensor array region SA, and one end surface D2 of each of the dummy isolation structures DSB in the capacitor region CA may extend from the same plane. At this time, since the isolation structures DSA and the dummy isolation structures DSB having the same structure are formed in the sensor array region SA and the capacitor region CA, the result of removing a portion of the substrate 122 may cause process defects such as an undesired dishing phenomenon in the capacitor region CA, and the backside surface 122B of the substrate 122 may extend flat in each of the sensor array region SA and the capacitor region CA.

[0090] 3, a backside insulating film 162 may be formed on the backside surface 122B of the substrate 122, one end surface D1 of each of the isolation structures DSA, and one end surface D2 of each of the dummy isolation structures DSB, a plurality of grid patterns 164, a first protective film 166, and a plurality of color filters 170 may be formed on the backside insulating film 162 in the active pixel sensor region APS, and a backside metal layer BML and a color filter 170B may be formed on the backside insulating film 162 in the optical black sensor region OBS and the capacitor region CA. Then, a microlens 180 and a second protective film 182 disposed on the plurality of color filters 170 in the active pixel sensor region APS, and a third protective film 180B and a fourth protective film 182B disposed on the color filter 170B in the optical black sensor region OBS and the capacitor region CA may be formed, thereby manufacturing the image sensor 100 described with reference to FIGS. 1 to 4.

[0091] As described above, an example of an exemplary manufacturing method of the image sensor 100 described with reference to Figures 1 to 4 has been described with reference to Figures 8A to 8C. However, those skilled in the art will readily understand that various modifications and changes can be made to the example described with reference to Figures 8A to 8C within the scope of the technical spirit of the present invention to manufacture the image sensors 200, 300, 400 described with reference to Figures 5A, 5B, 6, and 7, as well as image sensors having various structures that have been modified and altered in various ways therefrom.

[0092] FIG. 9A is a block diagram of an electronic system according to an embodiment of the inventive concept, and FIG. 9B is a detailed block diagram of a camera module included in the electronic system of FIG. 9A.

[0093] Referring to FIG. 9A , the electronic system 1000 includes a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0094] The camera module group 1100 includes a plurality of camera modules 1100a, 1100b, and 1100c. Although the drawings show an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, the technical idea of ​​the present invention is not limited thereto. In some embodiments, the module group 1100 may be modified to include only two camera modules. In some embodiments, the camera module group 1100 may be modified to include n camera modules (n is a natural number equal to or greater than 4).

[0095] Hereinafter, the detailed configuration of the camera module 1100b will be described in more detail with reference to FIG. 9B. However, the following description may also be applied to the other camera modules 1100a and 1100c according to the embodiment.

[0096] Referring to FIG. 9B, a camera module 1100b includes a prism 1105, an optical path folding element (hereinafter, OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0097] The prism 1105 can change the path of incident light L from outside, including the reflecting surface 1107 made of a light reflecting material.

[0098] In some embodiments, the prism 1105 may change the path of the light L incident in a first direction (X direction in FIG. 9B) to a second direction (Y direction in FIG. 9B) perpendicular to the first direction. The prism 1105 may rotate in the A direction around a central axis 1106 of a reflective surface 1107 of a light-reflecting material or rotate the central axis 1106 in the B direction to change the path of the light L incident in the first direction (X direction) to a second direction (Y direction) perpendicular to the first direction (X direction). In this case, the OPFE 1110 may also move in a third direction (Z direction in FIG. 9B) perpendicular to the first direction (X direction) and the second direction (Y direction).

[0099] In some embodiments, as shown in FIG. 9B, the maximum rotation angle of prism 1105 in the A direction is less than 15 degrees in the plus (+) A direction and is greater than 15 degrees in the minus (-) A direction, but the technical concept of the present invention is not limited thereto.

[0100] In some embodiments, prism 1105 moves in the plus (+) or minus (-) B direction by approximately 20°, or between 10° and 20°, or between 15° and 20°, where the angle of movement can be the same angle in the plus (+) or minus (-) B direction, or can move to an approximately similar angle within a range of approximately 1°.

[0101] In some embodiments, the prism 1105 may move the reflective surface 1107 of the light-reflecting material in a third direction (eg, Z direction) parallel to the extension direction of the central axis 1106 .

[0102] The OPFE 1110 includes, for example, m (where m is a natural number) optical lenses in a group. The m lenses may move in a second direction (Y direction) to change the optical zoom ratio of the camera module 1100b. For example, when the basic optical zoom ratio of the camera module 1100b is Z, when the m optical lenses included in the OPFE 1110 are moved, the optical zoom ratio of the camera module 1100b may be changed to an optical zoom ratio of 3Z, 5Z, or more.

[0103] The actuator 1130 may move the OPFE 1110 or an optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 may adjust the position of the optical lens so that the image sensor 1142 is located at the focal length of the optical lens for accurate sensing.

[0104] The image sensing device 1140 includes an image sensor 1142, a control logic 1144, and a memory 1146. The image sensor 1142 may sense an image of a sensing target using light L provided through an optical lens. The control logic 1144 may control the overall operation of the camera module 1100b. For example, the control logic 1144 may control the operation of the camera module 1100b according to a control signal provided through a control signal line CSLb.

[0105] The memory 1146 may store information required for the operation of the camera module 1100b, such as calibration data 1147. The calibration data 1147 includes information required for the camera module 1100b to generate image data using light L provided from the outside. The calibration data 1147 includes, for example, information on the degree of rotation, information on the focal length, information on the optical axis, etc. If the camera module 1100b is embodied in the form of a multi-state camera in which the focal length changes depending on the position of the optical lens, the calibration data 1147 includes focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing.

[0106] The storage unit 1150 may store image data sensed through the image sensor 1142. The storage unit 1150 may be disposed outside the image sensing device 1140 and may be embodied in a stacked form with a sensor chip constituting the image sensing device 1140. In some embodiments, the storage unit 1150 may be embodied as an Electrically Erasable Programmable Read-Only Memory (EEPROM), but the technical spirit of the present invention is not limited thereto.

[0107] The image sensor 1142 may include the image sensors 100, 200, 300, and 400 described with reference to FIGS. 1 to 7, or image sensors variously modified and altered therefrom within the scope of the technical concept of the present invention.

[0108] 9A and 9B, in some embodiments, each of the camera modules 1100a, 1100b, and 1100c includes an actuator 1130. Thus, each of the camera modules 1100a, 1100b, and 1100c includes calibration data 1147 that may be the same or different from one another depending on the operation of the actuator 1130 included therein.

[0109] In some embodiments, one of the multiple camera modules 1100a, 1100b, and 1100c (e.g., 1100b) is a folded lens type camera module including the above-mentioned prism 1105 and OPFE 1110, and the remaining camera modules (e.g., 1100a and 1100b) are vertical type camera modules that do not include the prism 1105 and OPFE 1110, but the technical idea of ​​the present invention is not limited thereto.

[0110] In some embodiments, one of the camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, infrared rays (IR). In that case, the application processor 1200 may merge image data provided by the vertical depth camera with image data provided by the other camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0111] In some embodiments, at least two of the camera modules 1100a, 1100b, and 1100c (e.g., 1100a and 1100b) may have different fields of view (fields of view) from each other, for example, but not limited to, optical lenses of at least two of the camera modules 1100a, 1100b, and 1100c (e.g., 1100a and 1100b) may be different from each other.

[0112] In some embodiments, the viewing angles of the camera modules 1100a, 1100b, and 1100c may be different from each other, and in that case, the optical lenses included in the camera modules 1100a, 1100b, and 1100c may also be different from each other, but are not limited to this.

[0113] In some embodiments, the camera modules 1100a, 1100b, and 1100c may be physically separated from one another, i.e., the sensing area of ​​one image sensor 1142 is not shared among the camera modules 1100a, 1100b, and 1100c, but an independent image sensor 1142 may be disposed within each of the camera modules 1100a, 1100b, and 1100c.

[0114] 9A, the application processor 1200 includes an image processor 1210, a memory controller 1220, and an internal memory 1230. The application processor 1200 may be implemented separately from the camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 and the camera modules 1100a, 1100b, and 1100c may be implemented separately from each other on separate semiconductor chips.

[0115] The image processing device 1210 includes a plurality of sub-processors 1212a, 1212b, 1212c, an image generator 1214, and a camera module controller 1216. The image processing device 1210 includes sub-processors 1212a, 1212b, 1212c in a number corresponding to the number of the camera modules 1100a, 1100b, 1100c.

[0116] Image data generated from each of the camera modules 1100a, 1100b, and 1100c may be provided to the corresponding sub-processors 1212a, 1212b, and 1212c through separate image signal lines ISLa, ISLb, and ISLc. For example, image data generated from the camera module 1100a may be provided to the sub-image processor 1212a through the image signal line ISLa, image data generated from the camera module 1100b may be provided to the sub-image processor 1212b through the image signal line ISLb, and image data generated from the camera module 1100c may be provided to the sub-image processor 1212c through the image signal line ISLc. Such image data transmission may be performed using, for example, a Camera Serial Interface (CSI) based on a Mobile Industry Processor Interface (MIPI), but the technical idea of ​​the present invention is not limited thereto.

[0117] Meanwhile, in some embodiments, one sub-image processor may be arranged to correspond to a plurality of camera modules. For example, sub-image processor 1212a and sub-image processor 1212c may not be implemented separately from each other as shown in the figure, but may be implemented integrated into one sub-image processor, and image data provided from camera module 1100a and camera module 1100c may be selected through a selection element (e.g., a multi-flexor) and then provided to the integrated sub-image processor.

[0118] The image data provided to each of the sub-processors 1212a, 1212b, and 1212c may be provided to an image generator 1214. The image generator 1214 may generate an output image using the image data provided from each of the sub-processors 1212a, 1212b, and 1212c by image generation information or a mode signal.

[0119] Specifically, the image generator 1214 may generate an output image by merging at least a portion of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal. Also, the image generator 1214 may select one of the image data generated from the camera modules 1100a, 1100b, and 1100c having different viewing angles according to the image generation information or the mode signal to generate an output image.

[0120] In some embodiments, the image generation information includes a zoom signal or zoom factor, and in some embodiments the mode signal is based on a mode selected by a user, for example.

[0121] When the image generation information is a zoom signal (zoom factor) and each of the camera modules 1100a, 1100b, and 1100c has a different observation field of view (viewing angle), the image generator 1214 may perform different operations according to the type of zoom signal. For example, when the zoom signal is a first signal, the image generator 1214 may merge the image data output from the camera module 1100a and the image data output from the camera module 1100c, and generate an output image using the merged image signal and the image data output from the camera module 1100b that is not used for merging. If the zoom signal is a second signal different from the first signal, the image generator 1214 does not perform such image data merging, but selects one of the image data output from each of the camera modules 1100a, 1100b, and 1100c to generate an output image. However, the technical idea of ​​the present invention is not limited thereto, and the method of processing the image data may be modified as necessary.

[0122] In some embodiments, the image generator 1214 receives multiple image data with different exposure times from at least one of multiple sub-processors 1212a, 1212b, and 1212c, and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0123] The camera module controller 1216 may provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated from the camera module controller 1216 may be provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

[0124] One of the multiple camera modules 1100a, 1100b, and 1100c, for example, the camera module 1100b, may be designated as a master camera module by image generation information including a zoom signal or a mode signal, and the remaining camera modules, for example, the camera modules 1100a and 1100c, may be designated as slave cameras. Such information may be included in a control signal and provided to the corresponding camera modules 1100a, 1100b, and 1100c through separate control signal lines CSLa, CSLb, and CSLc.

[0125] The camera modules operating as the master and the slave may be changed depending on the zoom factor or the operation mode signal. For example, when the viewing angle of the camera module 1100a is wider than that of the camera module 1100b and the zoom factor indicates a low zoom ratio, the camera module 1100b may operate as the master and the camera module 1100a may operate as the slave. Conversely, when the zoom factor indicates a high zoom ratio, the camera module 1100a may operate as the master and the camera module 1100b may operate as the slave.

[0126] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c include a sync enable signal. For example, if the camera module 1100b is a master camera and the camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 may transmit a sync enable signal to the camera module 1100b. The camera module 1100b that has received such a sync enable signal may generate a sync signal based on the provided sync enable signal and provide the generated sync signal to the camera modules 1100a and 1100c via a sync signal line SSL. The camera module 1100b and the camera modules 1100a and 1100c may transmit image data to the application processor 1200 in synchronization with such a sync signal.

[0127] In some embodiments, the control signals provided from the camera module controller 1216 to the camera modules 1100a, 1100b, 1100c include mode information in the form of a mode signal, such that the camera modules 1100a, 1100b, 1100c may operate in a first or second operating mode based on the sensing speed.

[0128] In a first operation mode, the camera modules 1100a, 1100b, and 1100c may generate image signals at a first rate (e.g., generate image signals at a first frame rate), encode the image signals at a second rate faster than the first rate (e.g., encode image signals at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second rate may be 30 times faster than the first rate or less.

[0129] The application processor 1200 may store the received image signal, i.e., the encoded image signal, in the internal memory 1230 or the external memory 1400 outside the application processor 1200, and thereafter read and decode the encoded image signal from the internal memory 1230 or the external memory 1400, and display image data generated based on the decoded image signal. For example, a corresponding sub-processor among a plurality of sub-processors 1212a, 1212b, and 1212c of the image processing device 1210 may perform decoding and image processing on the decoded image signal.

[0130] In the second operation mode, the camera modules 1100a, 1100b, and 1100c may generate image signals at a third rate slower than the first rate (e.g., generate image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may also be unencoded signals. The application processor 1200 may perform image processing on the received image signals or store the image signals in the internal memory 1230 or the external memory 1400.

[0131] The PMIC 1300 may provide power, e.g., a power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC 1300 may provide a first power to the camera module 1100a via a power signal line PSLa, a second power to the camera module 1100b via a power signal line PSLb, and a third power to the camera module 1100c via a power signal line PSLc.

[0132] The PMIC 1300 generates power corresponding to each of the camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and can adjust the power level. The power control signal PCON includes a power adjustment signal for each operation mode of the camera modules 1100a, 1100b, and 1100c. For example, the operation mode includes a low power mode, and the power control signal PCON includes information related to a camera module operating in the low power mode and a power level to be set. The levels of power provided to each of the camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Also, the power levels may be dynamically changed.

[0133] Although the present invention has been described in detail above with reference to preferred embodiments, the present invention is not limited to the embodiments, and various modifications and alterations can be made by those having ordinary skill in the art within the technical spirit and scope of the present invention. [Explanation of symbols]

[0134] 100 Image Sensor 110 First semiconductor chip 120 Second semiconductor chip 122 Substrate CA Capacitor Area DSA separation structure DSB Dummy Separation Structure SA Sensor array area

Claims

1. a sensor array region including: a plurality of unit pixels, each of the unit pixels including a plurality of photodiodes disposed in a substrate having a front side surface and a back side surface; and at least one isolation structure configured to isolate each of the plurality of unit pixels and penetrating the substrate in a direction perpendicular to the back side surface; a capacitor region adjacent to the sensor array region in a horizontal direction parallel to the backside surface, the capacitor region including at least one capacitor disposed on the frontside surface, and at least one dummy isolation structure penetrating the substrate in the vertical direction adjacent to the at least one capacitor; an end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends flush with the backside surface of the substrate; The at least one isolation structure and the at least one dummy isolation structure each include the same material.

2. Each of the at least one isolation structure and the at least one dummy isolation structure comprises: a main element isolation film that penetrates the substrate in the vertical direction from the front side surface to the back side surface; a local isolation film that penetrates only a portion of the substrate from the front side surface of the substrate in the vertical direction and covers a sidewall of a portion of the main isolation film adjacent to the front side surface.

3. The image sensor of claim 1 , wherein the sensor array region is disposed within an area defined by the capacitor region.

4. the at least one capacitor includes a plurality of first capacitors arranged in a row along a first horizontal direction parallel to the backside surface of the substrate; 2. The image sensor of claim 1, wherein the at least one dummy isolation structure includes a portion extending long along a second horizontal direction perpendicular to the first horizontal direction and parallel to the backside surface of the substrate in a local region of the substrate facing a separation space between two adjacent first capacitors among the plurality of first capacitors.

5. The at least one capacitor is parallel to the backside surface of the substrate and includes a plurality of capacitors arranged in a matrix in a row along a first horizontal direction and a second horizontal direction perpendicular to each other, the first horizontal direction and the second horizontal direction being parallel to each other, 2. The image sensor of claim 1, wherein the at least one dummy isolation structure includes a plurality of dummy isolation structures that penetrate a portion of the substrate facing a separation space between two adjacent capacitors of the plurality of capacitors in the vertical direction so as not to overlap the plurality of capacitors in the vertical direction.

6. the at least one capacitor includes a plurality of capacitors spaced apart from one another in the horizontal direction; the at least one dummy isolation structure includes a plurality of dummy isolation structures spaced apart from one another and penetrating the substrate in the vertical direction around each of the plurality of capacitors; The image sensor of claim 1 , wherein each of the plurality of dummy isolation structures has a rectangular ring shape penetrating the substrate in the vertical direction around the capacitor.

7. a sensor array region including: a plurality of unit pixels, each of the unit pixels including a plurality of photodiodes disposed in a substrate having a front side surface and a back side surface; and at least one isolation structure configured to isolate each of the plurality of unit pixels and penetrating the substrate in a direction perpendicular to the back side surface; a pad area surrounding the sensor array area and including a plurality of conductive pads; a capacitor region disposed between the sensor array region and the pad region, the capacitor region including: a plurality of capacitors disposed on the front side surface; and at least one dummy isolation structure penetrating the substrate in the vertical direction between two adjacent capacitors selected from the plurality of capacitors; an end surface of each of the at least one isolation structure and the at least one dummy isolation structure extends flush with the backside surface of the substrate; The at least one isolation structure and the at least one dummy isolation structure comprise the same material.

8. In a horizontal direction parallel to the backside surface of the substrate, the capacitor region is disposed closer to the sensor array region than the pad region; The image sensor of claim 7 , wherein the capacitor area surrounds at least a portion of the sensor array area.

9. the plurality of capacitors are arranged in a matrix in a row along a first horizontal direction and a second horizontal direction that are parallel to the backside surface of the substrate and perpendicular to each other; the at least one dummy isolation structure includes a plurality of dummy isolation structures penetrating the substrate in the vertical direction around each of the plurality of capacitors; the plurality of dummy isolation structures include a plurality of first dummy isolation structures spaced apart from one another along the first horizontal direction and arranged in a row along the first horizontal direction, and a plurality of second dummy isolation structures spaced apart from one another along the second horizontal direction and arranged in a row along the second horizontal direction, 9. The image sensor of claim 7, wherein the first dummy isolation structures and the second dummy isolation structures each penetrate the substrate in the vertical direction between two selected capacitors of the plurality of capacitors.

10. a first semiconductor chip including a logic region including a logic element and a peripheral circuit region including a peripheral circuit; a second semiconductor chip stacked on the first semiconductor chip so as to overlap the first semiconductor chip in a vertical direction; The second semiconductor chip is a substrate having a front side surface and a back side surface; a sensor array region including a plurality of unit pixels, each including a plurality of photodiodes disposed in the substrate, and a plurality of isolation structures configured to isolate each of the plurality of unit pixels and penetrating the substrate in a direction perpendicular to the backside surface; a capacitor region surrounding the sensor array region and including a plurality of capacitors disposed on the front side surface of the substrate and a plurality of dummy isolation structures penetrating the substrate in the vertical direction adjacent to the plurality of capacitors; one end surface of each of the plurality of isolation structures and the plurality of dummy isolation structures extends flush with the backside surface of the substrate; The image sensor, wherein the plurality of isolation structures and the plurality of dummy isolation structures comprise the same material.

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