Semiconductor device, control method thereof, and control program

Abstract

To provide a semiconductor device capable of implementing a high quality operation, a control method thereof, and a control program.SOLUTION: A semiconductor device includes a comparator circuit for comparing a measurement target signal with a reference voltage signal whose potential changes periodically and linearly, a counter circuit, and a latch circuit for storing a count value of the counter circuit at a timing when the output signal of the comparator circuit changes. The counter circuit includes a multiphase signal generator for shifting the phase of a reference clock signal to generate a plurality of clock signals having different phases, and a plurality of flip-flop circuits. A first-stage flip-flop captures an inverted signal of an output signal of a last-stage flip-flop, and each flip-flop of the second and subsequent stages captures an output signal of a flip-flop of a previous stage in synchronization with each of the plurality of clock signals, and outputs the output signal of each of the plurality of flip-flop circuits as a count signal of the count value.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a control method thereof, and a control program, and, for example, to a semiconductor device suitable for achieving high-quality operation, a control method thereof, and a control program thereof. [Background technology]

[0002] In general, an image sensor includes at least a plurality of pixels, a comparison circuit for comparing a pixel signal (a signal to be measured) indicating a potential corresponding to the amount of light received by the pixel with a ramp signal, and a counter circuit for counting the period from when the comparison circuit starts comparing the pixel signal with the ramp signal to when the pixel signal and the ramp signal match. The count value of the counter circuit is used as a digital signal obtained by AD converting the pixel signal.

[0003] Techniques relating to image sensors are disclosed in, for example, Non-Patent Document 1. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] 57, NO. 10, OCTOBER 2022 Summary of the Invention [Problem to be solved by the invention]

[0005] Image sensors are required to suppress noise and obtain high-quality captured images. Here, noise is suppressed by repeating the counting operation of a counter circuit multiple times at high speed during the period from when a comparator circuit starts comparing a pixel signal with a ramp signal until the pixel signal and the ramp signal match, and averaging the count values ​​obtained thereby.

[0006] However, when the counting operation of the counter circuit is accelerated, the waveform of the multiple bits representing the count value is crushed, which causes a problem that the accuracy of the counting operation of the counter circuit is deteriorated. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A semiconductor device according to the present disclosure has a semiconductor chip, and on a surface of the semiconductor chip, there are formed a comparator circuit having one terminal to which a signal to be measured is input and a reference voltage signal whose potential changes periodically and linearly to the other terminal, a counter circuit whose count value changes in accordance with the time change of the reference voltage signal, and a latch circuit connected to the comparator circuit and storing the count value of the counter circuit at a timing when an output signal from the comparator circuit changes, and the counter circuit includes a multiphase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases from each other, and a plurality of flip-flop circuits that are connected to the multiphase signal generator and are connected in series, and in the plurality of flip-flop circuits, a first stage flip-flop takes in an inverted signal of an output signal of a final stage flip-flop, and each of the second stage and subsequent flip-flops takes in an output signal of a previous stage flip-flop in synchronization with each of the plurality of clock signals, and outputs each output signal of the plurality of flip-flop circuits as a count signal of the count value.

[0008] A control method for a semiconductor device according to the present disclosure includes a semiconductor chip, the semiconductor chip having a surface formed with a comparator circuit having one terminal to which a signal under measurement is input and a reference voltage signal whose potential changes periodically and linearly to the other terminal, a counter circuit whose count value changes in accordance with the time change of the reference voltage signal, and a latch circuit connected to the comparator circuit and storing the count value of the counter circuit at a timing when an output signal from the comparator circuit changes, the counter circuit comprising: a multiphase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases from each other; and a plurality of flip-flop circuits connected to the multiphase signal generator and connected in series, wherein a first stage flip-flop in the plurality of flip-flop circuits outputs an inverted signal of an output signal of a final stage flip-flop, and each of second and subsequent stages flip-flops outputs an output signal of a previous stage flip-flop in synchronization with each of the plurality of clock signals. a first count value that is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal; a second count value that is a count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal matches the reference voltage signal; and a difference between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal.

[0009] A control program according to the present disclosure has a semiconductor chip, and on a surface of the semiconductor chip, there are formed a comparator circuit having one terminal to which a signal under measurement is input and a reference voltage signal whose potential changes periodically and linearly to the other terminal, a counter circuit whose count value changes in accordance with the time change of the reference voltage signal, and a latch circuit connected to the comparator circuit and storing the count value of the counter circuit at a timing when an output signal from the comparator circuit changes, the counter circuit comprising: a multiphase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases from each other, and a plurality of flip-flop circuits that are connected to the multiphase signal generator and are connected in series, and in the plurality of flip-flop circuits, a first stage flip-flop takes in an inverted signal of an output signal of a final stage flip-flop, and each of the second and subsequent stages flip-flops takes in an output signal of a previous stage in synchronization with each of the plurality of clock signals, and a control program for causing a computer to execute control processing in a semiconductor device that outputs an output signal as a count signal of the count value, the control program causing the computer to execute the following processing: causing the comparator circuit to compare a black signal, which is a black pixel signal, with the reference voltage signal; causing the latch circuit to latch a first count value, which is the count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal; causing the comparator circuit to compare a pixel signal, which is the signal under measurement, with the reference voltage signal; causing the latch circuit to latch a second count value, which is the count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal matches the reference voltage signal; and treating a difference between the second count value and the first count value as a digital signal corresponding to the pixel signal. Effect of the Invention

[0010] The present disclosure can provide a semiconductor device capable of achieving high quality operation, a control method thereof, and a control program thereof. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram of an example of a configuration of an image sensor according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram specifically showing a configuration of a portion of the image sensor according to the first embodiment. [Diagram 3] FIG. 3 is a block diagram of a configuration example of a counter circuit provided in the image sensor according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating a first configuration example of the four-phase clock signal generating circuit provided in the counter circuit according to the first embodiment. [Diagram 5] FIG. 5 is a timing chart showing the operation of the four-phase clock signal generating circuit shown in FIG. [Figure 6] FIG. 6 is a diagram illustrating a second configuration example of the four-phase clock signal generating circuit provided in the counter circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of a clock signal output circuit provided in the four-phase clock signal generating circuit shown in FIG. [Figure 8] FIG. 8 is a timing chart showing the operation of the four-phase clock signal generating circuit shown in FIGS. [Figure 9] FIG. 9 is a block diagram of a first configuration example of the phase shift counter provided in the counter circuit according to the first embodiment. [Figure 10] FIG. 10 is a block diagram of a second configuration example of the phase shift counter provided in the counter circuit according to the first embodiment. As shown in FIG. [Figure 11] FIG. 11 is a timing chart illustrating the overall operation of the counter circuit according to the first embodiment. [Figure 12] FIG. 12 is a timing chart illustrating an operation of the image sensor according to the second embodiment. [Figure 13] FIG. 13 is a block diagram showing a configuration example of an image sensor that has been previously examined. [Figure 14] FIG. 14 is a block diagram showing in more detail the configuration of a portion of the image sensor shown in FIG. [Figure 15] FIG. 15 is a diagram illustrating a configuration example of a ramp signal generating circuit provided in the image sensor illustrated in FIG. [Figure 16] FIG. 16 is a block diagram showing a configuration example of a counter circuit provided in the image sensor shown in FIG. [Figure 17] FIG. 17 is a timing chart showing a first example of the AD conversion process by the image sensor shown in FIG. [Figure 18] FIG. 18 is a diagram for explaining a problem with the first example of the AD conversion process by the image sensor shown in FIG. [Figure 19] FIG. 19 is a timing chart showing a second example of the AD conversion process by the image sensor shown in FIG. [Figure 20] FIG. 20 is a diagram for explaining a problem of the second example of the AD conversion process by the image sensor shown in FIG. [Figure 21] FIG. 21 is a timing chart showing a third example of the AD conversion process by the image sensor shown in FIG. [Figure 22] FIG. 22 is a diagram for explaining a problem in the third operation of the image sensor shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0014] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0015] <Preliminary review by inventors, etc.> First, an image sensor previously examined by the present inventor will be described. Fig. 13 is a block diagram showing a configuration example of the previously examined image sensor 50. Fig. 14 is a block diagram showing a more specific configuration of a portion of the image sensor 50.

[0016] As shown in FIG. 13 and FIG. 14, the image sensor 50 includes at least a plurality of pixels 51 arranged in a matrix, a plurality of comparison circuits 52 corresponding to the number of columns of the plurality of pixels 51, a plurality of latch circuits 53 corresponding to the number of columns of the plurality of pixels 51, a counter circuit 54, a ramp signal generating circuit 55, a control circuit 56, and a PLL circuit 57. These circuits are formed on the surface of a semiconductor chip. In the example of FIG. 13, a group of a plurality of comparison circuits 52, a group of a plurality of latch circuits 53, and the counter circuit 54 are arranged in the upper and lower areas of the formation area of ​​the plurality of pixels 51 on the surface of the semiconductor chip. In addition, a plurality of AD conversion circuits each consisting of the comparison circuit 52 and the latch circuit 53 are arranged along one side of the rectangular semiconductor chip. Since the image sensor 50 includes several thousand AD converters each consisting of the comparison circuit 52 and the latch circuit 53, each AD converter has a simple single slope integral type AD converter configuration.

[0017] The ramp signal generating circuit 55 generates a ramp signal (reference voltage signal) RS whose potential changes linearly in a horizontal scanning period (a period for accessing a plurality of pixels in each row). Here, a case will be described in which the ramp signal generating circuit 55 generates a ramp signal RS whose potential decreases linearly in a horizontal scanning period.

[0018] FIG. 15 is a diagram showing a configuration example of the ramp signal generating circuit 55. As shown in FIG. 15, the ramp signal generating circuit 55 includes a DA converter (DAC) 551, an operational amplifier 552, and a resistive element 553. The resistive element 553 is provided between a non-inverting input terminal of the operational amplifier 552 and a ground voltage terminal to which a ground voltage GND is supplied. The DA converter 551 converts a digital code input from the outside into an analog voltage. The output voltage of the DA converter 551 is supplied to a non-inverting input terminal of the operational amplifier 552. The output signal of the operational amplifier 552 is fed back to an inverting input terminal of the operational amplifier 552. The operational amplifier 552 amplifies and outputs a potential difference between voltages supplied to two input terminals. The output voltage of the operational amplifier 522 is not only used as a feedback signal to the inverting input terminal of the operational amplifier 552, but also used as a ramp signal RS. Here, the ramp signal generating circuit 55 generates a ramp signal RS whose potential changes linearly with a slope (slew rate) according to the digital code.

[0019] The PLL circuit 57 generates a reference clock signal CLK. Here, a case will be described in which the PLL circuit 57 generates a reference clock signal CLK having a frequency of 1.34 GHz.

[0020] Each comparison circuit 52 compares a pixel signal (signal to be measured) VPIX, which indicates a potential corresponding to the amount of light received by a pixel, with a ramp signal RS, the potential of which decreases linearly in a horizontal scanning period, and outputs a comparison result COUT. For example, each comparison circuit 52 changes (raises) the comparison result COUT from an L level to an H level when the potential of the ramp signal RS changes from equal to or higher than the potential of the pixel signal VPIX to less than the potential of the pixel signal VPIX.

[0021] The counter circuit 54 performs a count-up operation in synchronization with the reference clock signal CLK.

[0022] Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from L level to H level. That is, each latch circuit 53 latches the count value of the counter circuit 54 counted during the period from when the comparison between the pixel signal VPIX and the ramp signal RS is started by the corresponding comparison circuit 52 to when the pixel signal VPIX and the ramp signal RS match. This latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD converting the pixel signal.

[0023] 16 is a block diagram showing a configuration example of the counter circuit 54. Here, a case will be described where the counter circuit 54 outputs a count signal CNT_code having a count value of substantially 12 binary digits represented by a 13-bit value.

[0024] As shown in FIG. 16, the counter circuit 54 includes an LSB counter 541, a binary counter 542, and a binary gray converter 543. The LSB counter 541 performs a count-up operation of a count value LSB[3:0] of a substantial three-digit binary number represented by the lower four-bit value of a count value represented by a 13-bit value. The binary counter 542 performs a count-up operation of a binary code count value represented by the upper nine-bit value of a count value represented by a 13-bit value. The binary gray converter 543 converts the binary code count value output from the binary counter 542 into a gray code count value GC[12:4]. This reduces the change in bit value accompanying the count-up operation, thereby reducing malfunctions.

[0025] The counter circuit 54 outputs a count signal CNT_code, which is a 13-bit count value consisting of a count value GC[12:4] and a count value LSB[3:0].

[0026] The control circuit 56 performs overall control of the image sensor 50. Furthermore, the control circuit 56 performs control for removing offsets in AD conversion processing, which will be described later, and control for suppressing noise in AD conversion processing, which will be described later.

[0027] 17 is a timing chart showing a first example of AD conversion processing by the image sensor 50. As shown in FIG. 17, in the image sensor 50, when the potential of the ramp signal RS changes from equal to or higher than the potential of the pixel signal VPIX to less than the potential of the pixel signal VPIX, each comparison circuit 52 changes the comparison result COUT from L level to H level (time t11). Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from L level to H level. This latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD converting the pixel signal.

[0028] FIG. 18 is a diagram for explaining the problem of the first example of AD conversion processing by the image sensor 50. As shown in FIG. 18, in the image sensor 50, AD converters each consisting of a comparison circuit 52 and a latch circuit 53 are arranged in a row in units of several thousand. Here, power is supplied to the several thousand AD converters arranged in a row from both ends in most cases. Therefore, the power supply voltage of the AD converter arranged in the center of the several thousand AD converters arranged in a row drops due to IR drop. For example, if 4096 AD converters are arranged in a row, and the power supply voltages VDD supplied to the comparison circuit 52 and the latch circuit 53 constituting the AD converter arranged at the end are 3.0V and 1.2V, respectively, and the current consumption per AD converter is about 10uA, the power supply voltages VDD supplied to the comparison circuit 52 and the latch circuit 53 constituting the AD converter arranged in the center drop to about 2.9V and 1.1V, respectively. In addition, the ground voltage GND of the AD converter arranged in the center rises to about 0.1V.

[0029] Therefore, the inventors have considered an AD conversion process as shown in Fig. 19. Fig. 19 is a timing chart showing a second example of an AD conversion process by the image sensor 50. In the example of Fig. 19, an offset generated in each AD converter is removed by an AD conversion process using digital CDS (Digital Correlated Double Sampling).

[0030] First, the control circuit 56 causes each comparison circuit 52 and each latch circuit 53 to execute the following process as a first AD conversion process. Specifically, each comparison circuit 52 compares a pixel signal VPIX (hereinafter referred to as a black signal VPIX) indicating the potential of black not received by a pixel with a ramp signal RS, and outputs a comparison result COUT. For example, each comparison circuit 52 changes the comparison result COUT from L level to H level (time t21) when the potential of the ramp signal RS changes from the potential of the black signal VPIX or more to the potential of the black signal VPIX or less. Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from L level to H level (time t21). This latched count value is used as a digital value obtained by AD converting the black signal VPIX. The pixel signal indicating the potential of black not received by a pixel refers to a pixel signal in a state where the shutter is closed and no external light is incident.

[0031] After that, the control circuit 56 causes each comparison circuit 52 and each latch circuit 53 to execute the following process as a second AD conversion process. Specifically, each comparison circuit 52 compares a pixel signal VPIX indicating a potential according to the amount of light received by a pixel with a ramp signal RS, and outputs a comparison result COUT. For example, when the potential of the ramp signal RS changes from a potential equal to or higher than the potential of the pixel signal VPIX to a potential lower than the potential of the pixel signal VPIX, each comparison circuit 52 changes the comparison result COUT from an L level to an H level (time t22). Each latch circuit 53 latches the count value of the counter circuit 54 at the timing when the comparison result COUT of the corresponding comparison circuit 52 changes from an L level to an H level (time t22). This latched count value is used as a digital value obtained by AD converting the pixel signal VPIX.

[0032] Then, for each AD converter, the control circuit 56 subtracts the digital value obtained by AD converting the black signal VPIX from the digital value obtained by AD converting the pixel signal VPIX, thereby obtaining the digital value of the pixel signal with the offset removed.

[0033] Fig. 20 is a diagram for explaining a problem of the second example of AD conversion processing by the image sensor 50. As shown in Fig. 20, when two-stage AD conversion processing is performed to remove the offset, the noise received by the element increases. The noise received by the element is mainly classified into three types: noise received by the element of the ramp signal generating circuit 55, noise received by the pixel 51, and noise received by the AD converter (comparison circuit 52 and latch circuit 53).

[0034] Here, if the noise received by the element (mainly thermal noise here) is Vsd, the noise generated in the first AD conversion process is Vs(t1), and the noise generated in the second AD conversion process is Vs(t2), then the effective value of the noise received by the element, Vsd rms is expressed as the following equation (1).

[0035] Vsd rms ={Vs(t2)-Vs(t1)}rms (1)

[0036] The effective values ​​of Vs(t2) and Vs(t1) are the same. rms Therefore, the following equation (2) holds.

[0037] Vsd rms =√(2×Vs 2 ) rms =√2×Vs rms (2)

[0038] In other words, the noise generated when two-stage AD conversion processing is performed is √2 times the noise generated when only one-stage AD conversion processing is performed.

[0039] Therefore, the inventors have considered an AD conversion process as shown in Fig. 21. Fig. 21 is a timing chart showing a third example of an AD conversion process by the image sensor 50. Note that a comparative example is shown in the upper part of Fig. 21.

[0040] In the example of FIG. 21, each AD converter repeats the first AD conversion process using the black signal n times (n is an integer equal to or greater than 2; 4 times in the example of FIG. 21) and repeats the second AD conversion process using the image signal n times. At this time, the ramp signal generating circuit 55 is adjusted so that the speed of the potential change (slope of the potential change) of the ramp signal RS becomes n times that of the comparative example (reference speed). Also, the counter circuit 54 is adjusted so that the counting operation becomes n times that of the comparative example (reference speed). The control circuit 56 subtracts the average value of n digital values ​​obtained by AD converting the black signal VPIX n times from the average value of n digital values ​​obtained by AD converting the pixel signal VPIX n times for each AD converter, thereby obtaining a digital value of the pixel signal with noise suppressed to 1 / (√n) times.

[0041] However, as shown in FIG. 22, in order to realize the third example of the AD conversion process at the same processing speed as the second example, the image sensor 50 needs to increase the operating frequency of the reference clock signal CLK by n times (four times in this example). However, when the operating frequency of the reference clock signal CLK is increased from 1.34 GH to 5.36 GHz, for example, the signal line through which the count signal of the counter circuit 54 used in common with the plurality of AD converters propagates is arranged along one side of the rectangular semiconductor chip together with the plurality of AD converters, so that the waveform of the count signal of the counter circuit 54 may be distorted by long-distance transmission. As a result, there is a problem that the image sensor 50 cannot realize high-quality operation. In order to solve this problem, if a dedicated transmission block using a small-amplitude high-speed I / F or the like is provided in the image sensor 50, or if a repeater circuit is provided at every fixed distance, the current consumption and the circuit size will increase.

[0042] Therefore, an image sensor 1 has been found that is capable of achieving high quality operation.

[0043] <Embodiment 1> Fig. 1 is a block diagram showing an example of the configuration of an image sensor 1 according to the first embodiment. Fig. 2 is a block diagram showing a more specific configuration of a portion of the image sensor 1.

[0044] As shown in Fig. 1 and Fig. 2, the image sensor 1 includes at least a plurality of pixels 11 arranged in a matrix, a plurality of comparison circuits (comparator circuits) 12 corresponding to the number of columns of the plurality of pixels 11, a plurality of latch circuits 13 corresponding to the number of columns of the plurality of pixels 11, a counter circuit 14, a ramp signal generating circuit (reference voltage signal generating circuit) 15, a control circuit 16, and a PLL circuit 17. These circuits are formed on the surface of a semiconductor chip. In the example of Fig. 1, a group of the plurality of comparison circuits 12, a group of the plurality of latch circuits 13, and the counter circuit 14 are arranged in the upper and lower regions of the formation region of the plurality of pixels 11 on the surface of the semiconductor chip. In addition, a plurality of AD conversion circuits each consisting of the comparison circuit 12 and the latch circuit 13 are arranged along one side of the rectangular semiconductor chip.

[0045] The ramp signal generating circuit 15 generates a ramp signal RS whose potential changes linearly in a horizontal scanning period (a period for accessing a plurality of pixels in each row). In this embodiment, a case will be described in which the ramp signal generating circuit 15 generates a ramp signal RS whose potential decreases linearly in a horizontal scanning period. A specific configuration example of the ramp signal generating circuit 15 is similar to that of the ramp signal generating circuit 55, and therefore description thereof will be omitted.

[0046] The PLL circuit 17 generates a reference clock signal CLK. In this embodiment, a case will be described in which the PLL circuit 17 generates a reference clock signal CLK having a frequency of 1.34 GHz.

[0047] Each comparison circuit 12 compares a pixel signal (signal to be measured) VPIX, which indicates a potential corresponding to the amount of light received by a pixel, with a ramp signal RS, the potential of which decreases linearly in a horizontal scanning period, and outputs a comparison result COUT. For example, each comparison circuit 12 changes (raises) the comparison result COUT from an L level to an H level when the potential of the ramp signal RS changes from equal to or higher than the potential of the pixel signal VPIX to less than the potential of the pixel signal VPIX.

[0048] The counter circuit 14 performs a count-up operation in synchronization with the reference clock signal CLK.

[0049] Each latch circuit 13 latches the count value of the counter circuit 14 at the timing when the comparison result COUT of the corresponding comparison circuit 12 changes from L level to H level. That is, each latch circuit 13 latches the count value of the counter circuit 14 counted during the period from when the comparison between the pixel signal VPIX and the ramp signal RS is started by the corresponding comparison circuit 12 until the pixel signal VPIX and the ramp signal RS match. This latched count value is input to a processing circuit (not shown) as a digital signal obtained by AD converting the pixel signal.

[0050] The control circuit 16 performs overall control of the image sensor 1. Furthermore, the control circuit 16 performs control for removing offsets in the AD conversion process and control for suppressing noise in the AD conversion process.

[0051] (Example of the configuration of the counter circuit 14) 3 is a block diagram showing a configuration example of the counter circuit 14. In this embodiment, a case will be described in which the counter circuit 14 outputs a count signal CNT_code having a count value of substantially 12 binary digits represented by a 13-bit value.

[0052] As shown in FIG. 3, the counter circuit 14 includes a multi-phase clock signal generating circuit (multi-phase signal generator) 141, a phase shift counter (lower bit counter) 142, a CML / CMOS converter (level conversion circuit) 143, a binary counter (higher bit counter) 144, and a binary gray converter (code conversion circuit) 145.

[0053] Both the multi-phase clock signal generating circuit 141 and the phase shift counter 142 are configured using a CML (Current Mode Logic) circuit. This suppresses signal waveform distortion (dulling) in the multi-phase clock signal generating circuit 141 and the phase shift counter 142. Other circuits in the image sensor 1 are not particularly limited, but are basically configured using CMOS (Complementary Metal-Oxide-Semiconductor) circuits.

[0054] The multi-phase clock signal generating circuit 141 generates four clock signals CLK1 to CLK4 with different phases from a reference clock signal CLK. The frequency of each of the clock signals CLK1 to CLK4 is 1.34 GHz, which is the same as the frequency of the reference clock signal CLK.

[0055] (First Configuration Example of Multiphase Clock Signal Generation Circuit 141) 4 is a diagram showing a multi-phase clock signal generation circuit 141a as a first configuration example of the multi-phase clock signal generation circuit 141. As shown in FIG. 4, the multi-phase clock signal generation circuit 141a includes a buffer BF11, delay circuits DL1 to DL4, a phase comparator (PFD; Phase Frequency Detector) 1411, a charge pump (CP; Charge Pump) 1412, and a low-pass filter (LPF; Low-Pass Filter) 1413.

[0056] The buffer BF11 outputs a reference clock signal CLK supplied from the outside. The delay circuits DL1 to DL4 are connected in cascade and output clock signals CLK1 to CLK4 obtained by delaying the reference clock signal CLK by different delay amounts. The phase comparator 1411 compares the phase of the reference clock signal CLK with that of the output signal of the delay circuit DL4 in the final stage, and outputs the comparison results UP and DN. The charge pump 1412 outputs a current Icp according to the comparison results UP and DN of the phase comparator 1411. The low-pass filter 1413 filters the voltage generated based on the output current Icp of the charge pump 1412, and outputs the result as a drive voltage Vcnt for the delay circuits DL1 to DL4.

[0057] Fig. 5 is a timing chart showing the operation of the multi-phase clock signal generation circuit 141a. As shown in Fig. 4 and Fig. 5, the delay amount of each of the delay circuits DL1 to DL4 is, for example, 186.6 ps. Therefore, the multi-phase clock signal generation circuit 141a generates clock signals CLK1 to CLK4 that are shifted from each other by a quarter period of the reference clock signal CLK.

[0058] (Second Configuration Example of Multiphase Clock Signal Generation Circuit 141) 6 is a diagram showing a multi-phase clock signal generation circuit 141b as a second configuration example of the multi-phase clock signal generation circuit 141. As shown in FIG. 6, the multi-phase clock signal generation circuit 141b includes an inverter INV21, a buffer BF21, frequency division circuits DIV21 and DIV22, integrators INT21 to INT24, and a clock signal output circuit 1415.

[0059] The inverter INV21 outputs an inverted signal of the reference clock signal CLK. The buffer BF21 outputs a non-inverted signal of the reference clock signal CLK. The frequency divider circuit DIV21 divides the frequency of the output signal of the inverter INV21 (the inverted signal of the reference clock signal CLK) by two and outputs a frequency-divided signal Q1 and its inverted signal QB1. The frequency divider circuit DIV22 divides the frequency of the output signal of the buffer BF21 (the non-inverted signal of the reference clock signal CLK) by two and outputs a frequency-divided signal Q2 and its inverted signal QB2. The integrator INT21 performs integration processing on the frequency-divided signal Q1 and outputs an integration result M1 (=φ180). The integrator INT22 performs integration processing on the frequency-divided signal Q2 and outputs an integration result M2 (=φ540). The integrator INT23 performs integration processing on the frequency-divided signal Q3 and outputs an integration result M3 (=φ0). The integrator INT24 performs integration processing on the frequency-divided signal Q4 and outputs an integration result M4 (=φ360). The clock signal output circuit 1415 generates and outputs clock signals CLK1 to CLK4 based on the integration results M1 to M4 of the integrators INT21 to INT24.

[0060] Fig. 7 is a diagram showing an example of the configuration of the clock signal output circuit 1415 provided in the multi-phase clock signal generation circuit 141b, and Fig. 8 is a timing chart showing the operation of the multi-phase clock signal generation circuit 141b.

[0061] As shown in FIG. 7, the clock signal output circuit 1415 has inverters INV31 to INV33, INV41 to INV43, INV51 to INV53, and INV61 to INV63, and capacitance elements C31, C41, C51, and C61.

[0062] The inverter INV31 outputs an inverted signal of the integration result M3. The inverter INV32 outputs an inverted signal of the integration result M3. The capacitive element C31 is provided between the input terminal of the inverter INV33 and a ground voltage terminal to which the ground voltage GND is supplied. The charges of the output signals of the inverters INV31 and INV32 are accumulated in the capacitive element C31. The inverter (logic circuit) INV33 outputs a clock signal CLK1 at an L level when a voltage according to the charge accumulated in the capacitive element C31 is equal to or greater than a threshold voltage Vt, and at an H level when the voltage is less than the threshold voltage Vt.

[0063] The inverter INV41 outputs an inverted signal of the integration result M3. The inverter INV42 outputs an inverted signal of the integration result M1. The capacitive element C41 is provided between the input terminal of the inverter INV43 and a ground voltage terminal to which the ground voltage GND is supplied. The charges of the output signals of the inverters INV41 and INV42 are accumulated in the capacitive element C41. The inverter (logic circuit) INV43 outputs a clock signal CLK2 at an L level when a voltage according to the charge accumulated in the capacitive element C41 is equal to or greater than a threshold voltage Vt, and at an H level when the voltage is less than the threshold voltage Vt.

[0064] The inverter INV51 outputs an inverted signal of the integration result M1. The inverter INV52 outputs an inverted signal of the integration result M1. The capacitive element C51 is provided between the input terminal of the inverter INV53 and a ground voltage terminal to which the ground voltage GND is supplied. The charges of the output signals of the inverters INV51 and INV52 are accumulated in the capacitive element C51. The inverter (logic circuit) INV53 outputs a clock signal CLK3 at an L level when a voltage according to the charge accumulated in the capacitive element C51 is equal to or greater than a threshold voltage Vt, and at an H level when the voltage is less than the threshold voltage Vt.

[0065] The inverter INV61 outputs an inverted signal of the integration result M1. The inverter INV62 outputs an inverted signal of the integration result M4. The capacitive element C61 is provided between the input terminal of the inverter INV63 and a ground voltage terminal to which the ground voltage GND is supplied. The charges of the output signals of the inverters INV61 and INV62 are accumulated in the capacitive element C61. The inverter (logic circuit) INV63 outputs a clock signal CLK4 at an L level when a voltage according to the charge accumulated in the capacitive element C61 is equal to or greater than a threshold voltage Vt, and at an H level when the voltage is less than the threshold voltage Vt.

[0066] The phase shift counter 142 performs a count-up operation of the count value JC[3:0], which is essentially a three-digit binary number represented by the value of the lowest four bits of the count value represented by a 13-bit value. Here, the phase shift counter 142 performs a count-up operation of the count value JC[3:0] represented by the value of the lowest four bits by selectively changing the value of any one of the lowest four bits whose value changes in synchronization with each of the clock signals CLK1 to CLK3. As a result, when the operating frequency of the reference clock signal CLK is 1.34 GHz, the operating frequency of the count signal of the lowest four bits representing the count value JC[3:0] is suppressed to 670 MHz (=5.36 GHz / 8). Therefore, the waveform distortion of the count signal of the lowest four bits representing the count value JC[3:0] due to long-distance transmission is suppressed.

[0067] (First Configuration Example of Phase Shift Counter 142) FIG. 9 is a diagram showing a first configuration example of the phase shift counter 142 as a phase shift counter 142a.

[0068] As shown in FIG. 9, the phase shift counter 142a includes four D flip-flops FF11 to FF14. The D flip-flops FF12 to FF14 receive and output the output signals of the preceding D flip-flops FF11 to FF13 in synchronization with the clock signals CLK2 to CLK4, respectively. The D flip-flop FF11 receives and outputs an inverted signal of the output signal of the final D flip-flop FF14 in synchronization with the clock signal CLK1. Note that the inverted output terminals QB of the D flip-flops FF11 to FF13 other than the final D flip-flop FF14 among the D flip-flops FF11 to FF14 are not connected to any of the other D flip-flops. The phase shift counter 142a outputs the output signals of the D flip-flops FF11 to FF14 as count signals of the count values ​​JC[0], JC[1], JC[2], and JC[3].

[0069] (Second Configuration Example of Phase Shift Counter 142) FIG. 10 is a diagram showing a second configuration example of the phase shift counter 142 as a phase shift counter 142b.

[0070] 10, the phase shift counter 142b includes four JK flip-flops FF21 to FF24. The JK flip-flops FF22 to FF24 receive and output the output signals and inverted signals of the preceding JK flip-flops FF21 to FF23 at input terminals J and K in synchronization with the clock signals CLK2 to CLK4, respectively. The JK flip-flop FF21 receives and outputs the output signal and inverted signal of the final JK flip-flop FF24 at input terminals K and J in synchronization with the clock signal CLK1. The phase shift counter 142b outputs the output signals (Q) of the JK flip-flops FF21 to FF24 as count signals of count values ​​JC[0], JC[1], JC[2], and JC[3].

[0071] In this embodiment, the phase shift counter 142 counts up the count value JC[3:0] represented by the lowest 4 bits of the 13-bit count value, but the present invention is not limited to this. The phase shift counter 142 may be configured to count up the count value represented by the lowest 2 or more bits of the 13-bit count value, or the count value represented by all 13 bits. In this case, the number of flip-flops provided in the phase shift counter 142 corresponds to the number of bits used to represent the count value.

[0072] The CML / CMOS converter 143 converts the output signal of the phase shift counter 142 (the count signal of the count value JC[3:0]) from the CML circuit level to the CMO circuit level. That is, the counter circuit 14 converts the count signal of the count value JC[3:0] output from the phase shift counter 142 to the CMOS level by the CML / CMOS converter 143 and outputs it. This further suppresses the distortion of the waveform of the lower 4 bits of the count signal.

[0073] The binary counter 144 counts up the count value of the binary code represented by the upper 9 bits of the count value represented by a 13-bit value. In other words, the binary counter 144 counts up the count value of the binary code represented by the upper 9 bits of the count value represented by a 13-bit value based on the count value of the lower bits (carry-over of the count value of the lower bits).

[0074] The binary gray converter 145 converts the binary code count value output from the binary counter 144 into a gray code count value GR[12:4]. When the operating frequency of the reference clock signal CLK is 1.34 GHz, the operating frequency of the upper 9-bit count signal representing the count value GR[12:4] is 167 MHz (=5.36 GHz / 32). Here, in the gray code, only one bit of the 9-bit count value GR[12:4] changes for one code change, which reduces malfunctions.

[0075] The counter circuit 14 outputs a count signal CNT_code, which is a 13-bit count value consisting of a count value GR[12:4] and a count value JC[3:0].

[0076] FIG. 11 is a timing chart showing the overall operation of the counter circuit 14. As shown in FIG. 11, the operating frequency of the clock signals CLK1 to CLK4 generated inside the counter circuit 14 is 1.34 GHz, which is the same as the operating frequency of the reference clock signal CLK. Moreover, the operating frequency of the 13-bit count signal representing the count value of the counter circuit 14 is lower than the operating frequency of the reference clock signal CLK. Nevertheless, the counter circuit 14 can realize a count operation at an operating frequency of 5.36 GHz, which is four times the operating frequency of the reference clock signal CLK. That is, the counter circuit 14 can realize a high-speed count operation without increasing the speed of the reference clock signal CLK and without increasing the speed of internal operations. In addition, the counter circuit 14 can thereby realize a count operation without crushing the waveform of the count signal. That is, the counter circuit 14 can realize a high-speed and high-quality count operation. Furthermore, in the counter circuit 14, the shapes of the signal waveforms of the 13 bits are not significantly different from each other, so that DNL (Differential Non-Linearity) degradation is suppressed.

[0077] For example, the image sensor 1 performs AD conversion processing as shown in FIG. 21. Specifically, in the image sensor 1, each AD converter repeats the first AD conversion processing using the black signal n times (n is an integer of 2 or more; 4 in the example of FIG. 21) and repeats the second AD conversion processing using the image signal n times. The control circuit 16 subtracts the average value of n digital values ​​obtained by AD converting the black signal VPIX n times from the average value of n digital values ​​obtained by AD converting the pixel signal VPIX n times for each AD converter, thereby obtaining a digital value of the pixel signal in which noise is suppressed to 1 / (√n) times. Here, the image sensor 1 can realize a counter operation equivalent to 5.36 GHz without increasing the operating frequency of the reference clock signal CLK to 5.36 GHz, which is four times 1.34 GHz, and can therefore realize a high-quality operation in which noise is suppressed without crushing the waveform of the count signal. Furthermore, the image sensor 1 can significantly reduce power consumption compared to the case in which the operating frequency of the reference clock signal CLK is increased four times.

[0078] <Embodiment 2> FIG. 12 is a timing chart showing the AD conversion process by the image sensor 1 according to the second embodiment. A comparative example is shown at the top of FIG. 12. As shown in FIG. 12, in the image sensor 1 according to the second embodiment, each AD converter executes the first AD conversion process using the black signal once, and executes the second AD conversion process using the image signal once. The control circuit 16 can obtain the digital value of the pixel signal from which the offset has been removed by subtracting the digital value obtained by AD converting the black signal VPIX from the digital value obtained by AD converting the pixel signal VPIX for each AD converter. Here, the image sensor 1 according to the second embodiment can realize a counter operation equivalent to 5.36 GHz without increasing the operating frequency of the reference clock signal CLK to 5.36 GHz, which is four times 1.34 GHz, and can therefore realize high-speed operation without crushing the waveform of the count signal. In the example of FIG. 12, the AD conversion process consisting of the first AD conversion and the second AD conversion is shortened from 13.6 us to 9.8 us.

[0079] As described above, the image sensor 1 according to the above embodiment and the counter circuit 14 provided therein can achieve high-quality operation without distorting the waveform of the count signal even during high-speed operation.

[0080] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the gist of the invention.

[0081] In this embodiment, the case where the multi-phase clock signal generation circuit 141 generates four clock signals CLK1 to CLK4 with different phases from the reference clock signal CLK is described as an example, but is not limited to this. The multi-phase clock signal generation circuit 141 may be configured to generate p (p is an integer of 2 or more) clock signals CLK1 to CLKp with different phases from the reference clock signal CLK according to the bit width representing the count value.

[0082] In the present embodiment, the counter circuit 14 is applied to the image sensor 1, but the present invention is not limited to this. The counter circuit 14 is applicable to various semiconductor devices having an internal circuit that operates based on the count value.

[0083] Furthermore, in the present disclosure, a part or all of the processing of the image sensor 1 or a semiconductor device to which the counter circuit 14 is applied can be realized by causing a CPU to execute a computer program.

[0084] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal. [Explanation of symbols]

[0085] 1 Image sensor 11 pixels 12 Comparison circuit 13 Latch Circuit 14 Counter Circuit 15 Ramp signal generating circuit 16 Control circuit 17 PLL circuit 141 Multi-phase clock signal generation circuit 141a Multiphase clock signal generation circuit 141b Multiphase clock signal generation circuit 142 Phase Shift Counter 142a Phase Shift Counter 142b Phase Shift Counter 143 CML / CMOS Converter 144 Binary Counter 145 Binary Gray Converter 1411 Phase Detector (PFD) 1412 Charge Pump (CP) 1413 Low-pass filter (LPF) 1415 Clock signal output circuit BF11 Buffer BF21 Buffer C31, C41, C51, C61 Capacitor elements DIV21,DIV22 frequency divider circuit DL1~DL4 Delay circuit FF11~FF14 D Flip-Flop FF21~FF24 JK Flip-Flop INT21~INT24 Integrator INV21 Inverter INV31~INV33 inverter INV41~INV43 Inverter INV51~INV53 inverter INV61~INV63 Inverter

Claims

1. A semiconductor chip is included. The surface of the semiconductor chip is provided with a comparator circuit having one terminal to which a signal to be measured is input and another terminal to which a reference voltage signal whose potential changes periodically and linearly is input; a counter circuit whose count value changes in accordance with a time change of the reference voltage signal; a latch circuit connected to the comparator circuit and configured to store the count value of the counter circuit at a timing when an output signal from the comparator circuit changes; The counter circuit includes: a multi-phase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases; a plurality of flip-flop circuits connected to the multi-phase signal generator and connected in series; In the plurality of flip-flop circuits, a first stage flip-flop takes in an inverted signal of an output signal of a final stage flip-flop, and each of the second stage and subsequent flip-flops takes in an output signal of a previous stage flip-flop, in synchronization with each of the plurality of clock signals, and outputs each output signal of the plurality of flip-flop circuits as a count signal of the count value. Semiconductor device.

2. In the plurality of flip-flop circuits, an inverted output terminal of each flip-flop other than the final stage flip-flop is not connected to other flip-flops. The semiconductor device according to claim 1 .

3. The surface of the semiconductor chip is provided with A plurality of the comparator circuits; a plurality of the latch circuits corresponding to the plurality of the comparator circuits are formed; a count signal representing a count value of the common counter circuit is input to the plurality of latch circuits; The semiconductor device according to claim 1 .

4. the counter circuit outputs the count signal having a longer cycle than the plurality of clock signals; The semiconductor device according to claim 3 .

5. The semiconductor chip has a rectangular shape, a plurality of signal lines through which the count signals are transmitted are wired along one side of the rectangular semiconductor chip; The semiconductor device according to claim 4.

6. a reference voltage signal generating circuit for generating the reference voltage signal; the reference voltage signal generation circuit is configured to start a voltage change of the reference voltage signal in synchronization with a start timing of a counting operation by the counter circuit. The semiconductor device according to claim 1 .

7. the reference voltage signal generation circuit generates the reference voltage signal, the speed of voltage change of which is n (n is an integer of 2 or more) times the reference speed; The counter circuit performs a counting operation at a speed n times a reference speed, the comparator circuit and the latch circuit repeat the AD conversion process of the signal under measurement n times; The semiconductor device according to claim 6.

8. The multi-phase signal generator and the counter circuit are both configured using a CML (Current Mode Logic) circuit, The counter circuit further includes a level conversion circuit for converting an output signal of the counter circuit from a CML circuit level to a CMOS (Complementary Metal-Oxide-Semiconductor) circuit level. The semiconductor device according to claim 1 .

9. The multi-phase signal generator includes: a plurality of delay circuits connected in cascade to each other, each delaying the reference clock signal by a different delay amount and outputting the delay amount as the plurality of clock signals; a phase comparator for comparing the phases of output signals from the final stages of the plurality of delay circuits with the reference clock signal; a charge pump that outputs a current corresponding to a comparison result by the phase comparator; a filter that filters a voltage generated based on an output current of the charge pump and outputs the filtered voltage as a drive voltage for the plurality of delay circuits; having The semiconductor device according to claim 1 .

10. The multi-phase signal generator includes: a frequency divider circuit that divides the reference clock signal to generate a plurality of frequency-divided signals having different phases; A plurality of integrators that perform integration processing on each of the plurality of frequency-divided signals; a plurality of logic circuits that output the plurality of clock signals having logic values ​​corresponding to a plurality of potentials that are combinations of any of the integration results of the plurality of integrators; having The semiconductor device according to claim 1 .

11. The counter circuit includes: a high-order bit counter that counts up based on a count value of the low-order bit counter constituted by the plurality of flip-flop circuits; a count value of the lower-bit counter and a count value of the upper-bit counter are set as count values ​​of the counter circuit, and the count signal is output. The semiconductor device according to claim 1 .

12. the upper-bit counter is a binary counter that performs a count-up operation based on the count value of the lower-bit counter; The semiconductor device according to claim 11.

13. The upper bit counter is a binary counter that performs a count-up operation based on the count value of the lower-bit counter; a code conversion circuit for converting the count value of the binary counter into a Gray code; Equipped with The semiconductor device according to claim 12.

14. A control circuit is further provided. The control circuit includes: causing the comparator circuit to compare a black signal, which is a black pixel signal, with the reference voltage signal; causing the latch circuit to latch a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal; causing the comparator circuit to compare the pixel signal, which is the signal under measurement, with the reference voltage signal; causing the latch circuit to latch a second count value which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal and the reference voltage signal match; processing a difference between the second count value and the first count value as a digital signal corresponding to the pixel signal; The semiconductor device according to claim 1 .

15. The control circuit includes: causing the comparator circuit to compare the black signal with the reference voltage signal n times (n is an integer equal to or greater than 2); causing the latch circuit to latch a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal, n times; causing the comparator circuit to compare the pixel signal, which is the signal under measurement, with the reference voltage signal n times; causing the latch circuit to latch a second count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal and the reference voltage signal match, n times; an average of n differences between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal; The semiconductor device according to claim 14.

16. A semiconductor chip is included. The surface of the semiconductor chip is provided with a comparator circuit having one terminal to which a signal to be measured is input and another terminal to which a reference voltage signal whose potential changes periodically and linearly is input; a counter circuit whose count value changes in accordance with a time change of the reference voltage signal; a latch circuit connected to the comparator circuit and configured to store the count value of the counter circuit at a timing when an output signal from the comparator circuit changes; The counter circuit includes: a multi-phase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases; a plurality of flip-flop circuits connected to the multi-phase signal generator and connected in series; In the plurality of flip-flop circuits, a first stage flip-flop takes in an inverted signal of an output signal of a final stage flip-flop, and each of the second stage and subsequent flip-flops takes in an output signal of a previous stage flip-flop, in synchronization with each of the plurality of clock signals, and outputs each output signal of the plurality of flip-flop circuits as a count signal of the count value. A method for controlling a semiconductor device, comprising the steps of: causing the comparator circuit to compare a black signal, which is a black pixel signal, with the reference voltage signal; causing the latch circuit to latch a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal; causing the comparator circuit to compare the pixel signal, which is the signal under measurement, with the reference voltage signal; causing the latch circuit to latch a second count value which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal and the reference voltage signal match; processing a difference between the second count value and the first count value as a digital signal corresponding to the pixel signal; A method for controlling a semiconductor device.

17. causing the comparator circuit to compare the black signal with the reference voltage signal n times (n is an integer equal to or greater than 2); causing the latch circuit to latch a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal, n times; causing the comparator circuit to compare the pixel signal, which is the signal under measurement, with the reference voltage signal n times; causing the latch circuit to latch a second count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the pixel signal with the reference voltage signal to when the pixel signal and the reference voltage signal match, n times; an average of n differences between the second count value and the first count value is processed as a digital signal corresponding to the pixel signal; The method for controlling a semiconductor device according to claim 16.

18. A semiconductor chip is included. The surface of the semiconductor chip is provided with a comparator circuit having one terminal to which a signal to be measured is input and another terminal to which a reference voltage signal whose potential changes periodically and linearly is input; a counter circuit whose count value changes in accordance with a time change of the reference voltage signal; a latch circuit connected to the comparator circuit and configured to store the count value of the counter circuit at a timing when an output signal from the comparator circuit changes; The counter circuit includes: a multi-phase signal generator that shifts the phase of a reference clock signal to generate a plurality of clock signals having different phases; a plurality of flip-flop circuits connected to the multi-phase signal generator and connected in series; In the plurality of flip-flop circuits, a first stage flip-flop takes in an inverted signal of an output signal of a final stage flip-flop, and each of the second stage and subsequent flip-flops takes in an output signal of a previous stage flip-flop, in synchronization with each of the plurality of clock signals, and outputs each output signal of the plurality of flip-flop circuits as a count signal of the count value. A control program for causing a computer to execute a control process in a semiconductor device, A process of causing the comparator circuit to compare a black signal, which is a black pixel signal, with the reference voltage signal; a process of latching a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal and the reference voltage signal match; A process of causing the comparator circuit to compare a pixel signal, which is the signal under measurement, with the reference voltage signal; a process of latching, in the latch circuit, a second count value which is a count value of the counter circuit during a period from when the comparator circuit starts to compare the pixel signal with the reference voltage signal until the pixel signal and the reference voltage signal match; a process of treating a difference between the second count value and the first count value as a digital signal corresponding to the pixel signal; A control program that causes a computer to execute the above.

19. A process of causing the comparator circuit to compare the black signal with the reference voltage signal n times (n is an integer equal to or greater than 2); A process of latching a first count value, which is a count value of the counter circuit during a period from when the comparator circuit starts comparing the black signal with the reference voltage signal to when the black signal matches the reference voltage signal, n times in the latch circuit; A process of causing the comparator circuit to compare the pixel signal, which is the signal under measurement, with the reference voltage signal n times; a process of latching, in the latch circuit, a second count value, which is a count value of the counter circuit during a period from when the comparator circuit starts to compare the pixel signal with the reference voltage signal until the pixel signal and the reference voltage signal match; a process of treating an average of n differences between the second count value and the first count value as a digital signal corresponding to the pixel signal; The control program according to claim 18, which causes a computer to execute the control program.

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