Display panel

Abstract

To provide a display panel with improved contact reliability.SOLUTION: A display panel includes a driving element layer including a pixel driving unit, a light-emitting element disposed on the driving element layer and including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, a pixel definition film disposed on the driving element layer and having an opening defined therein to expose at least a portion of the first electrode, and a connecting electrode disposed on the pixel definition film and electrically connected to the pixel driving unit and the second electrode, and the intermediate layer may include a functional layer having a first area and a light-emitting layer having a second area smaller than the first area.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a display panel having improved contact reliability. [Background technology]

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, game consoles, etc. include display panels for displaying images. The display panels include light emitting elements and circuits for driving the light emitting elements. The light emitting elements included in the display panel emit light in response to a voltage applied from the circuit to generate an image. Research into the connection between the light emitting elements and the circuits has been ongoing in order to improve the reliability of the display panels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 11,315,986 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display panel having improved contact reliability. [Means for solving the problem]

[0005] A display panel according to one embodiment of the present invention includes a driving element layer including a pixel driving unit, a light-emitting element arranged on the driving element layer and including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer, a pixel definition film arranged on the driving element layer and having an opening defined therein to expose at least a portion of the first electrode, and a connecting electrode arranged on the pixel definition film and electrically connected to the pixel driving unit and the second electrode, wherein the intermediate layer may include a functional layer having a first area and a light-emitting layer having a second area smaller than the first area.

[0006] The connecting electrode may have a ring shape surrounding the opening, and a lower surface of the second electrode may be in contact with an upper surface of the connecting electrode.

[0007] A connection region where the second electrode and the connecting electrode are connected may surround at least a portion of the opening.

[0008] The functional layer may include a first intermediate functional layer disposed on the first electrode and a second intermediate functional layer disposed on the light-emitting layer, and the light-emitting layer may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0009] The semiconductor device may further include a separator disposed on the connecting electrode, wherein the second electrode and the connecting electrode are connected in a region adjacent to the separator.

[0010] The display panel may further include a first dummy layer disposed on the separator and including the same material as the functional layer, and a second dummy layer disposed on the first dummy layer and including the same material as the second electrode.

[0011] The connecting electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap (overlap) the separator.

[0012] The light emitting device, the pixel driving part, and the connecting electrode may each be provided in a plurality of parts, and the plurality of connecting electrodes may electrically connect the plurality of light emitting devices and the plurality of pixel driving parts, respectively. Gaps between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with the separator.

[0013] A through hole may be defined in the pixel defining layer, and the connection electrode may be connected to the pixel driving part through the through hole.

[0014] The light emitting layer may not overlap the through hole, and the functional layer may overlap the through hole.

[0015] The light emitting layer and the functional layer may overlap the through hole.

[0016] The connecting electrode may include a protruding portion protruding in a direction away from the opening, the protruding portion not overlapping the light emitting layer.

[0017] The protruding portion of the connecting electrode and the light emitting layer may be spaced apart, and the functional layer may overlap a region between the protruding portion and the light emitting layer and at least a portion of the protruding portion.

[0018] According to an embodiment of the present invention, a display panel includes a driving element layer including a pixel driving unit, a light emitting element including a first electrode disposed on the driving element layer and having a light emitting unit defined corresponding to a portion thereof, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, and a connecting electrode electrically connected to the pixel driving unit and the second electrode, the connecting electrode including a first edge surrounding the light emitting unit and a second edge surrounding the first edge, a portion of the first edge not overlapping with the light emitting layer, and the portion of the first edge being separated from an edge of the light emitting layer.

[0019] The display panel may further include a pixel definition film disposed on the driving element layer, the pixel definition film having an opening exposing a portion of the first electrode to define the light emitting portion and a through hole spaced apart from the opening, and the connecting electrode may be disposed on the pixel definition film and connected to the pixel driving part through the through hole.

[0020] The pixel electrode may further include a separator disposed on the pixel defining layer and overlapping the second edge, the second electrode and the connecting electrode being connected in a region adjacent to the separator.

[0021] The light emitting layer may overlap the opening and not overlap the through hole.

[0022] The light emitting layer may overlap the opening and the through hole.

[0023] The portion of the first edge may protrude in a direction away from the opening.

[0024] The light-emitting device may further include a first intermediate functional layer disposed between the first electrode and the light-emitting layer, and a second intermediate functional layer disposed between the light-emitting layer and the second electrode.

[0025] The area of ​​each of the first intermediate functional layer and the second intermediate functional layer may be greater than the area of ​​the light emitting layer.

[0026] The first intermediate functional layer and the second intermediate functional layer may overlap the portion of the first edge.

[0027] According to one embodiment of the present invention, a display panel includes a driving element layer including a plurality of pixel driving units, a plurality of light-emitting elements arranged on the driving element layer and electrically connected to each of the plurality of pixel driving units, a plurality of connecting electrodes connected to the plurality of pixel driving units and the plurality of light-emitting elements, and a separator arranged between the plurality of light-emitting elements, each of the plurality of light-emitting elements including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer, gaps between adjacent connecting electrodes among the plurality of connecting electrodes overlap with the separator, the intermediate layer includes a plurality of layers, some of the layers are arranged in a first region of the intermediate layer, and all of the layers are arranged in a second region adjacent to the first region of the intermediate layer.

[0028] The display panel may further include a pixel definition film disposed on the driving element layer and having an opening defined therein exposing at least a portion of a first electrode of each of the light-emitting elements, a portion of each of the plurality of connecting electrodes being disposed on the pixel definition film, and the separator being disposed on the pixel definition film.

[0029] The plurality of light-emitting elements include a first light-emitting element, a second light-emitting element spaced apart from the first light-emitting element in the first direction, and a third light-emitting element spaced apart from the first and second light-emitting elements in a second direction intersecting the first direction, and the pixel defining film is defined with a first opening exposing at least a portion of the first electrode of the first light-emitting element, a second opening exposing at least a portion of the first electrode of the second light-emitting element, and a third opening exposing at least a portion of the first electrode of the third light-emitting element, and the plurality of connecting electrodes may include a first connecting electrode surrounding the first opening, a second connecting electrode surrounding the second opening, and a third connecting electrode surrounding the third opening.

[0030] The first region of the first light-emitting element and the first region of the second light-emitting element may be arranged between the first opening and the second opening, and the first region of the first light-emitting element and the first region of the second light-emitting element may be spaced apart in the second direction.

[0031] The plurality of pixel driving parts may include a first pixel driving part electrically connected to the first light emitting element, a second pixel driving part electrically connected to the second light emitting element, and a third pixel driving part electrically connected to the third light emitting element, and a first through hole, a second through hole, and a third through hole may be defined in the pixel defining layer, the first connecting electrode may be connected to the first pixel driving part through the first through hole, the second connecting electrode may be connected to the second pixel driving part through the second through hole, and the third connecting electrode may be connected to the third pixel driving part through the third through hole.

[0032] The first region of the first light-emitting element may overlap the first through hole, the first region of the second light-emitting element may overlap the second through hole, and the first region of the third light-emitting element may overlap the third through hole.

[0033] The first region of the first light-emitting element may not overlap with the first through hole, the first region of the second light-emitting element may not overlap with the second through hole, and the first region of the third light-emitting element may overlap with the third through hole.

[0034] The first region of the first light emitting device or the first region of the second light emitting device may be adjacent to the first region of the third light emitting device in the second direction.

[0035] The multiple layers of the intermediate layer include a first intermediate functional layer disposed on the first electrode, an emitting layer disposed on the first intermediate functional layer, and a second intermediate functional layer disposed on the emitting layer, the first region of the intermediate layer includes the first intermediate functional layer and the second intermediate functional layer, and the second region of the intermediate layer includes the first intermediate functional layer, the emitting layer, and the second intermediate functional layer. Effect of the Invention

[0036] As described above, the light emitting element and the pixel driving circuit may be in stable contact with each other, thereby improving contact reliability. For example, the connecting electrode electrically connected to the cathode of the light emitting element and the pixel driving circuit may be connected in a relatively wide area rather than at a specific point, thereby improving contact reliability. Also, at least a portion of the connecting electrode may not overlap with the light emitting layer. Therefore, the area of ​​the exposed area of ​​the connecting electrode may be stably secured. Therefore, appearance defects caused by contact defects, for example, dirt defects found during lighting, may be reduced or eliminated. As a result, the image quality and manufacturing yield of the display panel may be improved.

[0037] In addition, since the lower surface of the connecting electrode and the upper surface of the intermediate connecting electrode are in contact with each other, contact reliability may be improved. Therefore, the size of a through hole for connecting the connecting electrode and the intermediate connecting electrode may be reduced or minimized. Therefore, the area and resolution of a light emitting portion of a display panel may be easily increased. [Brief description of the drawings]

[0038] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2A] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention; [Figure 2B] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention; [Figure 2C] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention; [Figure 3A] 1 is a plan view showing a simplified view of a display panel according to an embodiment of the present invention; [Figure 3B] 1 is a plan view showing a simplified view of a display panel according to an embodiment of the present invention; [Figure 4A] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 4B] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 4C] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 4D] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 4E] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Diagram 5] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 6A] 2 is an enlarged cross-sectional view showing a portion of a display panel according to an embodiment of the present invention; [Figure 6B] 1 is an image obtained by photographing a portion of a display panel according to an embodiment of the present invention. [Figure 6C] 2 is an enlarged cross-sectional view showing a portion of a display panel according to an embodiment of the present invention; [Figure 7] 2 is an enlarged cross-sectional view showing a portion of a display panel according to an embodiment of the present invention; [Figure 8] 2 is an enlarged cross-sectional view showing a portion of a display panel according to an embodiment of the present invention; [Figure 9] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 10A] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 10B]2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 11A] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 11B] 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention; FIG. [Figure 12] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] In this specification, when a given component (or region, layer, portion, etc.) is described as being "on," "connected," or "bonded" to another component, it means that it can be directly disposed / connected / bonded onto the other component, or that a third component can be disposed therebetween.

[0040] The same reference numerals refer to the same elements. Also, in the drawings, the thickness of the elements is exaggerated for efficient explanation of the technical contents. "And / or" includes all one or more combinations that the associated elements can define.

[0041] Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present invention. A singular expression includes a plural expression unless otherwise clearly indicated by the context.

[0042] In addition, terms such as "under", "below", "on", and "above" are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0043] It should be understood that the use of terms such as "comprise" or "have" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof set forth in the specification, but does not preclude the presence or additional possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0044] The terms "part" and "unit" refer to a software component or hardware component that performs a specific function. A hardware component may include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A software component may refer to executable code and / or data used by executable code in an addressable storage medium. Thus, software components are, for example, object-oriented software components, class components, and operation components, and may include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or overly formal sense unless expressly defined herein.

[0046] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0047] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0048] Referring to FIG. 1, the display device DD may include a display panel DP, a panel driver SDC, EDC, DDC, a power supply unit PWS, and a timing controller TC. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. In the following embodiment, an organic light emitting display panel will be taken as an example for detailed description. The panel driver SDC, EDC, DDC may include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0049] The display panel DP may include scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm (where m and n are integers greater than 1).

[0050] For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or the ith pixel row) and the jth vertical line (or the jth pixel column) may be connected to the ith first scan line (or the write scan line GWLi), the ith second scan line (or the compensation scan line GCLi), the ith third scan line (or the first initialization scan line GILi), the ith fourth scan line (or the second initialization scan line GBLi), the ith fifth scan line (or the reset scan line GRLi), the jth data line DLj, and the ith emission line ESLi.

[0051] The pixel PXij may include a plurality of light emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel PXij may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or a reference voltage VREF), a fourth power supply voltage (or a first initialization voltage VINT1), a fifth power supply voltage (or a second initialization voltage VINT2), and a sixth power supply voltage (or a compensation voltage VCOMP) through a power supply unit PWS.

[0052] The first and second power supply voltages VDD and VSS are set to a voltage value such that a current flows through the light emitting element to emit light. For example, the first power supply voltage VDD may be set to a voltage higher than the second power supply voltage VSS.

[0053] The third power supply voltage VREF may be a voltage for initializing a gate of a driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement a predetermined gray scale by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0054] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present invention is not limited thereto.

[0055] The fifth power supply voltage VINT2 may be a voltage for initializing a cathode of a light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto, and the fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0056] The sixth power supply voltage VCOMP can supply a predetermined current to the driving transistor during the threshold voltage compensation of the driving transistor.

[0057] 1, the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied by the power supply unit PWS, but the present invention is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS are all supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied depending on the structure of the pixel PXij.

[0058] In the embodiment of the present invention, the signal lines connected to the pixels PXij can be variously set in accordance with the circuit structure of the pixels PXij.

[0059] The scan driver SDC receives a first control signal SCS from the timing controller TC, and can supply scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0060] The scan signal may be set to a voltage that turns on a transistor that receives the scan signal. For example, the scan signal supplied to a P-type transistor may be set to a logic low level, and the scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, the meaning of "a scan signal is supplied" may be understood to mean that the scan signal is supplied at a logic level that turns on a transistor controlled thereby.

[0061] 1, for the sake of simplicity, the scan driver SDC is illustrated as being a single component, but the present invention is not limited thereto. According to an embodiment, a plurality of scan drivers may be included to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively.

[0062] The light-emitting driver EDC may supply light-emitting signals to the light-emitting lines ESL1 to ESLn based on the second control signal ECS. For example, the light-emitting signals may be sequentially supplied to the light-emitting lines ESL1 to ESLn.

[0063] The transistors connected to the light emitting lines ESL1 to ESLn of the present invention may be N-type transistors. In this case, the light emitting signals provided to the light emitting lines ESL1 to ESLn may be set to a gate-off voltage. The transistors receiving the light emitting signals may be turned off when the light emitting signals are provided, and may be turned on otherwise.

[0064] The second control signal ECS includes a light emission start signal and a clock signal, and the light emission driver EDC may be implemented as a shift register that sequentially shifts the light emission start signal in a pulse form using the clock signal to sequentially generate and output light emission signals in a pulse form.

[0065] The data driver DDC can receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC can convert the digital image data RGB into an analog data signal (i.e., a data signal). The data driver DDC can provide a data signal to the data lines DL1 to DLm in response to the third control signal DCS.

[0066] The third control signal DCS may include a data enable signal for instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register for shifting the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch for latching image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) for converting the latched image data (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​for outputting the data signal to the data lines DL1 to DLm.

[0067] The power supply unit PWS can supply a first power supply voltage VDD, a second power supply voltage VSS, and a third power supply voltage VREF to the display panel DP for driving the pixels PXij, and can also supply at least one of a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP.

[0068] As an example, the power supply unit PWS can supply the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 2A), a second power supply line VSL (see FIG. 2A), a third power supply line (or a reference voltage line VRL, see FIG. 2A), a fourth power supply line (or a first initialization voltage line VIL1, see FIG. 2A), a fifth power supply line (or a second initialization voltage line VIL2, see FIG. 2A), and a sixth power supply line (or a compensation voltage line VCL, see FIG. 2A), which are not shown.

[0069] The power supply unit PWS can be realized by a power management integrated circuit, but is not limited thereto.

[0070] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power supply PWS. The timing controller TC may rearrange the input image data IRGB in response to an arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0071] Meanwhile, the scan driver SDC, the light emission driver EDC, the data driver DDC, the power supply PWS, and / or the timing controller TC may be directly formed on the display panel DP or may be provided in the form of separate driver chips and connected to the display panel DP. At least two of the scan driver SDC, the light emission driver EDC, the data driver DDC, the power supply PWS, and the timing controller TC may be provided on one driver chip. For example, the data driver DDC and the timing controller TC may be provided on one driver chip.

[0072] Although the display device DD according to an embodiment has been described with reference to FIG. 1, the display device DD of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Also, the connection relationship between one pixel and the signal lines may be changed. When one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0073] 2A, 2B, and 2C are equivalent circuit diagrams of pixels according to an embodiment of the present invention, which exemplarily illustrate equivalent circuit diagrams of pixels PXij, PXij-1, and PXij-2 connected to an i-th first scan line GWLi (hereinafter, first scan line) and a j-th data line DLj (hereinafter, data line), respectively.

[0074] 2A, the pixel PXij includes a light emitting element LD and a pixel driving circuit PDC. The light emitting element LD is connected to a first power line VDL and the pixel driving circuit PDC.

[0075] The pixel driving unit PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, VCL. The pixel driving unit PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8, a first capacitor C1, and a second capacitor C2. Hereinafter, a case in which each of the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 is an N-type transistor will be described as an example. However, the present invention is not limited thereto, and some of the first to eighth transistors T1 to T8 are N-type transistors and the rest are P-type transistors, and each of the first to eighth transistors T1 to T8 is a P-type transistor, and is not limited to any one of the embodiments.

[0076] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL through the light emitting element LD to the second power line VSL in response to the voltage of the first node N1. At this time, the first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0077] In this specification, "electrically connected between a transistor and a signal line or between transistors" means "the source, drain, and gate of the transistor are integral with the signal line or are connected through a connecting electrode."

[0078] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is provided to the write scan line GWLi, thereby electrically connecting the data line DLj to the first node N1.

[0079] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0080] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 providing the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI through an i-th third scan line GILi (hereinafter, a first initialization scan line). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0081] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. A first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 may be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, a compensation scan line). When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 may be turned on to provide the compensation voltage VCOMP to the second node N2, and the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0082] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. In particular, a gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, emission line). A first electrode of the sixth transistor T6 may be connected to a cathode of the light emitting element LD through a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to a first electrode of the first transistor T1 through a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0083] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS through the second power line VSL. A gate of the seventh transistor T7 may be electrically connected to the light emitting line ESLi. The seventh transistor T7 may be referred to as a second light emitting control transistor. When an emission signal EM is supplied to the emission line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0084] Meanwhile, in the present embodiment, the sixth transistor T6 and the seventh transistor T7 are illustrated as being connected to the same emission line ESLi and turned on by the same emission signal EM, but this is merely an example, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driving unit PDC according to an embodiment of the present invention, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0085] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to an i-th fourth scan line GBLi (hereinafter, a second initialization scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0086] Meanwhile, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on / off by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be substantially provided as a single scan line. Therefore, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0087] In addition, according to the present invention, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 may be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor may be performed with one power supply voltage, so that the design of the driving unit may be simplified. However, this is merely an example, and the present invention is not limited to any one embodiment.

[0088] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0089] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL to which the second power voltage VSS is supplied, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacity than the first capacitor C1. Therefore, the second capacitor C2 may minimize a voltage change of the third node N3 in response to a voltage change of the first node N1.

[0090] In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode facing the anode. In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through the cathode. That is, in the pixel PXij according to the present invention, the connection node where the light emitting element LD and the pixel driving part PDC are connected is the fourth node N4, and the fourth node N4 may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0091] Specifically, the anode of the light emitting element LD may be connected to the first power line VDL and may be applied with the first power supply voltage VDD, which is a constant voltage, and the cathode may be connected to the first transistor T1 through the sixth transistor T6. That is, in this embodiment in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if the light emitting element LD is deteriorated, the influence on the transistors constituting the pixel driving unit PDC, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, since the amount of change in the driving current due to deterioration of the light emitting element LD is reduced, the afterimage defect of the display panel that occurs as the usage time increases may be reduced and the lifespan may be improved.

[0092] Alternatively, as shown in Fig. 2B, the pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1, T2 and a first capacitor C1. The pixel driver PDC-1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in Fig. 2B may correspond to the pixel driver PDC shown in Fig. 2A with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0093] Each of the first and second transistors T1 and T2 may be an N-type or P-type transistor. In this embodiment, the first and second transistors T1 and T2 are exemplarily described as being an N-type transistor.

[0094] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0095] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0096] The first capacitor C1 may include an electrode coupled to the first node N1 and an electrode coupled to the third node N3, and may store a data signal DATA transmitted to the first node N1.

[0097] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving part PDC-1 through a second node N2. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving part PDC-1.

[0098] In this embodiment, where the first and second transistors T1 and T2 are N-type transistors, the second node N2 to which the cathode of the light emitting element LD and the pixel driving part PDC-1 are connected may correspond to the drain of the first transistor T1. That is, it is possible to prevent the gate-source voltage Vgs of the first transistor T1 from changing due to the light emitting element LD. Therefore, since the amount of change in the driving current due to the deterioration of the light emitting element LD is reduced, the image retention defect of the display panel that occurs as the usage time increases may be reduced and the life span may be improved.

[0099] Or, as shown in FIG. 2C, pixel PXij-2 may include a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a, T6a and two capacitors C1, C2.

[0100] The pixel driving unit PDC-2 may be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first light emitting line ESL1i (hereinafter, the first light emitting line), the i-th second light emitting line ESL2i (hereinafter, the second light emitting line), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL, and the initialization voltage line VIL.

[0101] The pixel driver PDC-2 shown in Fig. 2C may have a structure similar to that of the pixel driver PDC shown in Fig. 2A, except that the fourth transistor T4 and the fifth transistor T5 are omitted. Since the area of ​​the pixel driver PDC-2 shown in Fig. 2C is smaller than the area of ​​the pixel driver PDC-1 shown in Fig. 2A, it may be easier to implement a high resolution.

[0102] Each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a may be an N-type or P-type transistor. In this embodiment, a case where each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a is an N-type transistor will be described as an example.

[0103] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0104] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0105] The third transistor T3 may be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0106] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. In particular, the gate of the fourth transistor T4a may receive a first light emitting signal EM1 through the first light emitting line ESL1i. A first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD through a fourth node N4, and a second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 through a second node N2. The fourth transistor T4a may be referred to as a first light emitting control transistor. When the first light emitting signal EM1 is supplied to the first light emitting line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0107] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the fifth transistor T5a may receive the second power voltage VSS through the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a may be referred to as a second light-emitting control transistor. When a second light-emitting signal EM2 is supplied to the second light-emitting line ESL2i, the fifth transistor T5a is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0108] Meanwhile, in the present embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the first and second light-emitting lines ESL1i and ESL2i that are distinct from each other and may be turned on by the first and second light-emitting signals EM1 and EM2 that are distinct from each other. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently of each other. However, this is merely an example and is not limited thereto. For example, in an embodiment of the present invention, the fourth transistor T4a and the fifth transistor T5a may be connected to the same light-emitting line and controlled by the same light-emitting signal. Also, in the pixel driving unit PDC-2 according to an embodiment of the present invention, one of the fourth transistor T4a and the fifth transistor T5a may be omitted.

[0109] The sixth transistor T6a may be connected between the initialization voltage line VIL and a fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0110] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0111] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL that receives the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor.

[0112] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving part PDC-2 through a fourth node N4. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 through a fourth transistor T4a. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving part PDC-2.

[0113] In this embodiment, where the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting device LD. Therefore, even if the light emitting device LD deteriorates, the influence on the transistors constituting the pixel driving unit PDC-2, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, since the amount of change in the driving current due to deterioration of the light emitting device LD is reduced, the image retention defect of the display panel that occurs as the usage time increases may be reduced and the lifespan may be improved.

[0114] Meanwhile, Figures 2A, 2B, and 2C show circuits for pixel driving units PDC, PDC-1, and PDC-2 according to an embodiment of the present invention, and the display panel according to an embodiment of the present invention is a circuit connected to the cathode of the light emitting element LD, so the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways and are not limited to any one of the embodiments.

[0115] 3A and 3B are schematic plan views of a display panel according to an embodiment of the present invention. Some components are omitted in each of the drawings. Hereinafter, the present invention will be described with reference to FIGS. 3A and 3B.

[0116] 3A, a display panel DP according to an embodiment may be divided into a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a plurality of light emitting parts EP.

[0117] The light emitting portion EP may be an area that is emitted by each pixel PXij (see FIG. 1). Specifically, each light emitting portion EP may correspond to a light emitting opening OP-PDL (see FIG. 5) described later. The light emitting opening OP-PDL may be referred to as an opening or an aperture.

[0118] The peripheral area NDA may be disposed adjacent to the display area DA. In the present embodiment, the peripheral area NDA is illustrated to surround the edge of the display area DA. However, this is merely an example, and the peripheral area NDA may be disposed on one side of the display area DA or may be omitted, and is not limited to any one embodiment.

[0119] In this embodiment, the scan driver SDC and the data driver DDC may be mounted on a display panel DP. In one embodiment, the scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the plurality of light emitting units EP disposed in the display area DA in a plan view. As the scan driver SDC is disposed in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to a conventional display panel in which a scan driver is disposed in the peripheral area, and a display device with a thin bezel may be easily implemented.

[0120] Meanwhile, unlike the embodiment shown in Fig. 3A, the scan driver SDC may be provided in two parts separated from each other. The two scan drivers SDC may be disposed to the left and right of the center of the display area DA, spaced apart from each other. Alternatively, the scan driver SDC may be provided in a number of two or more, and is not limited to any one embodiment.

[0121] 3A shows an example of a display panel, and the data driver DDC may be disposed in the display area DA. In this case, a part of the light emitting unit EP disposed in the display area DA may be overlapped with the data driver DDC on a plane.

[0122] In one embodiment, the data driver DDC may be provided in the form of a separate driver chip independent of the display panel DP and connected to the display panel DP, but this is merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to configure the display panel DP, and is not limited to any one embodiment.

[0123] As shown in Fig. 3B, the display panel DP may have a length in a first direction DR1 that is longer than a length in a second direction DR2. A plurality of pixels PX11 to PXnm arranged in n rows and m columns are exemplarily illustrated in the display area DA. In this embodiment, the display panel DP may include a plurality of scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 are exemplarily illustrated to include a first scan driver SDC1 and a second scan driver SDC2 that are spaced apart from each other in the first direction DR1.

[0124] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other parts of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0125] For ease of explanation, pads PD of the data lines DL1 to DLm are illustrated in Fig. 3B. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to a data driver DDC (see Fig. 3A) through the pads PD.

[0126] According to the present invention, the pads PD may be divided and arranged at positions separated by the display area DA in the peripheral area NDA. For example, some of the pads PD may be arranged on the upper side, i.e., adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other part of the pads PD may be arranged on the lower side, i.e., adjacent to the last scan line GLn among the scan lines GL1 to GLn. In this embodiment, the pads PD connected to odd-numbered data lines among the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to even-numbered data lines among the data lines DL1 to DLm may be arranged on the lower side.

[0127] Although not shown, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged on the upper side and / or a plurality of lower data drivers connected to the pads PD arranged on the lower side. However, this is merely an example, and the display panel DP may include one upper data driver connected to the pads PD arranged on the upper side and / or one lower data driver connected to the pads PD arranged on the lower side. The pads PD according to an embodiment of the present invention may be arranged on only one side of the display panel DP and connected to a single data driver, and is not limited to any one embodiment.

[0128] Also, as described above in FIG. 3A, the display panel DP in FIG. 3B may also have a scan driver and / or a data driver arranged in the display area DA, and therefore some of the light-emitting units arranged in the display area DA may overlap with the scan driver and / or the data driver in a plane.

[0129] 4A to 4E are enlarged plan views of a portion of a display panel according to an embodiment of the present invention.

[0130] 4A exemplarily illustrates light emitting units UT11, UT12, UT21, and UT22 in two rows and two columns. Referring to FIG. 4A, the light emitting unit in the first row Rk includes light emitting units constituting the light emitting unit UT11 in the first row and first column and the light emitting unit UT12 in the first row and second column, and the light emitting unit in the second row Rk+1 includes light emitting units constituting the light emitting unit UT21 in the second row and first column and the light emitting unit UT22 in the second row and second column.

[0131] Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL (see FIG. 5) described later. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area where light is emitted by the light-emitting element described above. The light-emitting portions EP1, EP2, and EP3 may correspond to a unit that configures an image displayed on the display panel DP (see FIG. 1). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by the light-emitting opening OP-PDL described later, in particular, an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0132] The light emitting units EP1, EP2, and EP3 may include a first light emitting unit EP1, a second light emitting unit EP2, and a third light emitting unit EP3. The first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3 may emit light of different colors. For example, the first light emitting unit EP1 may emit red light, the second light emitting unit EP2 may emit green light, and the third light emitting unit EP3 may emit blue light, but the color combination is not limited thereto. Also, at least two of the first to third light emitting units EP1, EP2, and EP3 may emit light of the same color. For example, all of the first to third light emitting units EP1, EP2, and EP3 may emit blue light, or all of them may emit white light.

[0133] Among the first to third light emitting parts EP1, EP2, and EP3, the third light emitting part EP3 displaying light emitted by the third light emitting element may include two sub-light emitting parts EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light emitting part EP3 may be provided in a single pattern having an integral shape like the first and second light emitting parts EP1 and EP2, or at least one of the first and second light emitting parts EP1 and EP2 may include a sub-light emitting part spaced apart from each other, and is not limited to any one embodiment.

[0134] The light-emitting section in the first row Rk may include first to third light-emitting sections EP1, EP2, EP3 that constitute the light-emitting unit UT11 in the first row, first column, and first to third light-emitting sections EP1, EP2, EP3a that constitute the light-emitting unit UT12 in the first row, second column, and the light-emitting section in the second row Rk+1 may include first to third light-emitting sections EP1, EP2, EP3a that constitute the light-emitting unit UT21 in the second row, first column, and first to third light-emitting sections EP1, EP2, EP3 that constitute the light-emitting unit UT22 in the second row, second column.

[0135] In one embodiment of the present invention, the shape of the light emitting portion constituting the light emitting unit UT11 in the first row and first column may be substantially the same as that of the light emitting portion constituting the light emitting unit UT22 in the second row and second column. Also, the shape of the light emitting portion constituting the light emitting unit UT12 in the first row and second column may be substantially the same as that of the light emitting portion constituting the light emitting unit UT21 in the second row and first column. The shape of the light emitting portion constituting the light emitting unit UT11 in the first row and first column may be different from the shape of the light emitting portion constituting the light emitting unit UT12 in the first row and second column. For example, a part of the light emitting portion in the first row Rk and a part of the light emitting portion in the second row Rk+1 may have a symmetrical shape.

[0136] In one embodiment of the present invention, the third light emitting part EP3a of the light emitting unit UT21 in the second row and first column and the third light emitting part EP3 of the light emitting unit UT11 in the first row and first column may have a shape and arrangement shape that is line symmetrical with respect to an axis aligned with the first direction DR1, and the third light emitting part EP3 of the light emitting unit UT22 in the second row and second column and the third light emitting part EP3a of the light emitting unit UT12 in the first row and second column may have a shape and arrangement shape that is line symmetrical with respect to an axis along the first direction DR1, but this is merely an example and is not limited thereto.

[0137] Fig. 4B illustrates light emitting units arranged in one row. For ease of explanation, Fig. 4B illustrates a plurality of second electrodes EL2_1, EL2_2, EL2_3, a plurality of pixel driving units PDC1, PDC2, PDC3, first to third connecting electrodes CNE1, CNE2, CNE3, and a separator SPR. Fig. 4C illustrates a separator SPR, a plurality of light emitting units EP1, EP2, EP3, and a plurality of connecting electrodes CNE1, CNE2, CNE3 arranged in an area partitioned by the separator SPR in the configuration of the display panel.

[0138] 4B and 4C, the second electrodes EL2_1, EL2_2, and EL2_3 may be electrically disconnected by being separated from each other by a separator SPR. In this embodiment, one light emitting unit UT11 may include three light emitting parts EP1, EP2, and EP3. Therefore, the light emitting unit UT11 may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter, first to third cathodes), three pixel driving parts PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light emitting parts included in the light emitting unit UT11 may be variously designed, and is not limited to any one embodiment.

[0139] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the first to third light emitting elements LD1, LD2, and LD3 including the first to third light emitting units EP1, EP2, and EP3, respectively. In this specification, "connected" includes not only a case where they are connected by direct physical contact, but also a case where they are electrically connected.

[0140] Also, as shown in FIG. 4B, each area in which the first to third pixel driving units PDC1, PDC2, and PDC3 are defined on a plane may correspond to a unit in which transistors and capacitor elements constituting a circuit PDC (see FIG. 2A) for driving a light emitting element of a pixel are repeatedly arranged.

[0141] The first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along a first direction DR1. Meanwhile, the positions of the first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be designed independently regardless of the positions and shapes of the first, second, and third light emitting units EP1, EP2, and EP3.

[0142] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged at positions different from the positions where the regions defined by the separator SPR, i.e., the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged, or may be designed to have shapes and areas different from the shapes of the first to third cathodes EL2_1, EL2_2, and EL2_3. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged to overlap the positions where the first to third light emitting units EP1, EP2, and EP3 are present, respectively, and may be designed to have a shape having an area similar to the regions defined by the separator SPR, for example, the first to third cathodes EL2_1, EL2_2, and EL2_3.

[0143] In this embodiment, each of the first to third pixel driving units PDC1, PDC2, and PDC3 is illustrated as a rectangle, each of the first to third light emitting units EP1, EP2, and EP3 is arranged in a different shape with a smaller area, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3 and are illustrated as having an irregular shape.

[0144] 4B, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitting units. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third cathode EL2_3. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions of the first to third pixel driver PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independent of the first to third light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0145] The light emitting unit UT11 may include first to third connecting electrodes CNE1, CNE2, and CNE3. The first connecting electrode CNE1 may electrically connect the first light emitting element LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 is defined) to the first pixel driving part PDC1, the second connecting electrode CNE2 may electrically connect the second light emitting element LD2 forming the second light emitting part EP2 to the second pixel driving part PDC2, and the third connecting electrode CNE3 may electrically connect the third light emitting element LD3 forming the third light emitting part EP3 to the third pixel driving part PDC3.

[0146] Specifically, the first, second and third connecting electrodes CNE1, CNE2 and CNE3 may electrically connect the first, second and third cathodes EL2_1, EL2_2 and EL2_3 to the first, second and third pixel driving parts PDC1, PDC2 and PDC3 in one-to-one correspondence, respectively.

[0147] Each of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel definition layer PDL (see FIG. 5) described below. The first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting portions EP1, EP2, and EP3. In an embodiment of the present invention, each of the first to third connecting electrodes CNE1, CNE2, and CNE3 is illustrated as having a ring shape of a closed line, but is not limited thereto. For example, at least some of the first to third connecting electrodes CNE1, CNE2, and CNE3 may have an open ring shape with a part cut.

[0148] Since the first to third connecting electrodes CNE1, CNE2, and CNE3 have a ring shape, the degree of freedom of positions at which the first to third connecting electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving parts PDC1, PDC2, and PDC3 may be improved. For example, the first connecting electrode CNE1 may be connected to the first pixel driving part PDC1 through the first connecting part CE1, the second connecting electrode CNE2 may be connected to the second pixel driving part PDC2 through the second connecting part CE2, and the third connecting electrode CNE3 may be connected to the third pixel driving part PDC3 through a connecting wire CN3. That is, a connecting wire additionally connected to the first and second connecting electrodes CNE1 and CNE2 may be omitted.

[0149] One connection wire CN3 may electrically connect the third pixel driving part PDC3 and the third light emitting element LD3 constituting the third light emitting part EP3. Specifically, the connection wire CN3 may correspond to a node (see the fourth node N4 in FIG. 2A, the second node N2 in FIG. 2B, or the fourth node N4 in FIG. 2C) at which the light emitting element LD (see FIG. 2A) is connected to the pixel driving part (PDC in FIG. 2A, PDC-1 in FIG. 2B, or PDC-2 in FIG. 2C).

[0150] The connecting wire CN3 may include a third connecting part CE3 and a driving connecting part CD3. The third connecting part CE3 may be provided on one side of the connecting wire CN3, and the driving connecting part CD3 may be provided on the other side of the connecting wire CN3.

[0151] The driving connection part CD3 may be a part of the connecting wire CN3 that is connected to the third pixel driving part PDC3. In this embodiment, the driving connection part CD3 may be connected to one electrode of a transistor constituting the third pixel driving part PDC3. Specifically, the driving connection part CD3 may be connected to the drain of the sixth transistor T6 shown in FIG. 2A, the drain of the first transistor T1 shown in FIG. 2B, or the drain of the fourth transistor T4a shown in FIG. 2C. Therefore, the position of the driving connection part CD3 may correspond to the position of a transistor physically connected to the connecting wire CN3 in the pixel driving part. The third connection part CE3 may be a part of the connecting wire CN3 that is connected to the third light emitting element LD3. In this embodiment, the third connection part CE3 may be connected to the third connecting electrode CNE3.

[0152] The first connecting electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connecting electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connecting electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0153] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be arranged to be spaced apart from each other. For example, gaps GP1, GP2, and GP3 between adjacent connecting electrodes among the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. For example, first edges EG11, EG21, and EG31 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not be covered by the separator SPR, and second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. Or, the second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be covered by the separator SPR.

[0154] In an embodiment of the present invention, the first to third connection parts CE1, CE2, and CE3 may be disposed at positions not overlapping the first to third light emitting parts EP1, EP2, and EP3 on a plane. For example, a light emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) separated from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL.

[0155] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection parts CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light emitting opening OP-PDL may include a first light emitting opening OP-PDL1, a second light emitting opening OP-PDL2, and a third light emitting opening OP-PDL3. The first to third light emitting parts EP1, EP2, and EP3 may be defined corresponding to the first to third light emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. Therefore, the first to third connection parts CE1, CE2, and CE3 may be disposed at positions spaced apart from the first to third light emitting parts EP1, EP2, and EP3.

[0156] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel definition film PDL (see FIG. 5). When viewed in a plan view, the first connecting electrode CNE1 may surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 may surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 may surround the third light-emitting opening OP-PDL3.

[0157] According to an embodiment of the present invention, the driving connection part CD3, which is a position where the connecting wire CN3 is connected to the transistor TR (see FIG. 5) of the third pixel driver PDC3, may be defined at a position not overlapping the third connection part CE3 on a plane and may be disposed at a position overlapping the third light emitter EP3. For example, the connecting wire CN3 may correspond to the connecting wire CN-ad shown in FIG. 9, the driving connection part CD3 may correspond to a portion contacting the middle connecting electrode CN shown in FIG. 9, and the third connection part CE3 may correspond to a portion contacting the connecting electrode CNEa shown in FIG. 9. By connecting the third cathode EL2_3 and the pixel driver PDC3 through the connecting wire CN3, restrictions according to the position and shape of the third light emitter EP3 are reduced in designing the pixel driver PDC3, and the degree of freedom in designing the pixel driver PDC3 may be improved.

[0158] The first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to the first to third connecting electrodes CNE1, CNE2, and CNE3. For example, the lower surfaces of the first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected (or in contact) with the upper surfaces of the first to third connecting electrodes CNE1, CNE2, and CNE3, respectively. Therefore, the contact reliability (or connection stability) between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CNE1, CNE2, and CNE3 may be further improved.

[0159] In addition, a connection region in which the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connecting electrodes CNE1, CNE2, CNE3 are connected may surround at least a portion of each of the first to third light emitting openings OP-PDL1, OP-PDL2, OP-PDL3. The first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connecting electrodes CNE1, CNE2, CNE3 may be connected in a region adjacent to the separator SPR, and each of the connection regions may be defined adjacent to the separator SPR. That is, the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connecting electrodes CNE1, CNE2, CNE3 may be connected over a relatively wide area, for example, an area similar to the shape of each of the first to third connecting electrodes CNE1, CNE2, CNE3, rather than at a specific point, so that the area of ​​the connection area is increased and the connection may proceed stably.

[0160] FIG. 4D illustrates light emitting portions EP1, EP2, EP3, connecting electrodes CNE1, CNE2, CNE3, and a plurality of intermediate layers IML1, IML2, IML3 in the configuration of the display panel.

[0161] 4C and 4D, the intermediate layers IML1, IML2, and IML3 may be separated from each other by a separator SPR. The intermediate layers IML1, IML2, and IML3 may include a first intermediate layer IML1 disposed between the first cathode EL2_1 and the first electrode EL1 (see FIG. 4E), a second intermediate layer IML2 disposed between the second cathode EL2_2 and the first electrode EL1, and a third intermediate layer IML3 disposed between the third cathode EL2_3 and the first electrode EL1.

[0162] The first intermediate layer IML1 can include a first functional layer FNL1 having a first area and a first emissive layer EML1 having a second area smaller than the first area. The second intermediate layer IML2 can include a second functional layer FNL2 having a third area and a second emissive layer EML2 having a fourth area smaller than the third area. The third intermediate layer IML3 can include a third functional layer FNL3 having a fifth area and a third emissive layer EML3 having a sixth area smaller than the fifth area.

[0163] The first to third functional layers FNL1, FNL2, and FNL3 may be formed by being commonly deposited on a plurality of pixels through an open mask. In this case, the first to third functional layers FNL1, FNL2, and FNL3 may be divided by a separator SPR. The separator SPR may have a closed line shape for each light emitting portion, and therefore the first to third functional layers FNL1, FNL2, and FNL3 may have a shape divided for each light emitting portion. Each of the first to third light emitting layers EML1, EML2, and EML3 may be formed by being deposited on a corresponding plurality of pixels through a fine metal mask. Therefore, at least a portion of each of the first to third light emitting layers EML1, EML2, and EML3 may not overlap or be separated from the separator SPR.

[0164] According to an embodiment of the present invention, at least a portion of a first edge EG11 of the first connecting electrode CNE1 does not overlap with the first emission layer EML1 and may be separated from the edge EG1 of the first emission layer EML1. At least a portion of a first edge EG21 of the second connecting electrode CNE2 does not overlap with the second emission layer EML2 and may be separated from the edge EG2 of the second emission layer EML2. At least a portion of a first edge EG31 of the third connecting electrode CNE3 does not overlap with the third emission layer EML3 and may be separated from the edge EG3 of the third emission layer EML3.

[0165] Unlike the embodiment of the present invention, if a portion of each of the first to third connecting electrodes CNE1, CNE2, and CNE3 that is not covered by the separator SPR and is exposed is covered by the first to third light emitting layers EML1, EML2, and EML3, the contact stability between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CNE1, CNE2, and CNE3 may be reduced. According to an embodiment of the present invention, at least a portion of each of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not overlap with the first to third light emitting layers EML1, EML2, and EML3. In this case, the area of ​​the exposed region of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be stably secured. Therefore, the first to third cathodes EL2_1, EL2_2, and EL2_3 can be stably connected to the first to third connecting electrodes CNE1, CNE2, and CNE3, respectively, and contact reliability can be improved. As a result, appearance defects caused by contact failure, such as stain defects found when turned on, can be reduced or eliminated. Image quality or manufacturing yield of the display panel DP and the display device DD including the same (see FIG. 1) can be improved.

[0166] According to an embodiment of the present invention, the first to third light emitting layers EML1, EML2, EML3 may overlap the first to third light emitting openings OP-PDL1, OP-PDL2, OP-PDL3, respectively. Also, the first to third light emitting layers EML1, EML2, EML3 may not overlap the first to third through holes OP-P1, OP-P2, OP-P3, respectively. The first to third functional layers FNL1, FNL2, FNL3 may overlap the first to third light emitting openings OP-PDL1, OP-PDL2, OP-PDL3, respectively, and the first to third through holes OP-P1, OP-P2, OP-P3, respectively. Therefore, the first functional layer FNL1 can overlap at least a portion of the first edge EG11 of the first connecting electrode CNE1, the second functional layer FNL2 can overlap at least a portion of the first edge EG21 of the second connecting electrode CNE2, and the third functional layer FNL3 can overlap at least a portion of the first edge EG31 of the third connecting electrode CNE3.

[0167] The first intermediate layer IML1 may include a first region AR11 and a second region AR12 adjacent to the first region AR11. The second intermediate layer IML2 may include a first region AR21 and a second region AR22 adjacent to the first region AR21. The third intermediate layer IML3 may include a first region AR31 and a second region AR32 adjacent to the first region AR31. For example, each of the first regions AR11, AR21, and AR31 may be a region in which some layers among the multiple layers constituting each of the first to third intermediate layers IML1, IML2, and IML3 are arranged, and each of the second regions AR21, AR22, and AR23 may be a region in which all of the multiple layers constituting each of the first to third intermediate layers IML1, IML2, and IML3 are arranged.

[0168] In an embodiment of the present invention, the first light emitting element LD1 including the first light emitting portion EP1 and the second light emitting element LD2 including the second light emitting portion EP2 may be spaced apart in the second direction DR2. The third light emitting element LD3 including the third light emitting portion EP3 may be spaced apart from the first and second light emitting elements LD1 and LD2 in the first direction DR1.

[0169] In an embodiment of the present invention, the first region AR11 of the first light emitting element LD1 and the first region AR21 of the second light emitting element LD2 may be arranged between the first light emitting opening OP-PDL1 and the second light emitting opening OP-PDL2. The first region AR11 of the first light emitting element LD1 and the first region AR21 of the second light emitting element LD2 may be spaced apart in a first direction DR1. The first region AR11 of the first light emitting element LD1 may overlap the first through hole OP-P1, the first region AR21 of the second light emitting element LD2 may overlap the second through hole OP-P2, and the first region AR31 of the third light emitting element LD3 may overlap the third through hole OP-P3.

[0170] FIG. 4E illustrates the separator SPR, the light emitting portions EP1, EP2, EP3, and the first electrode EL1.

[0171] 4E, a first electrode EL1 (hereinafter, anode) of the light emitting element LD (see FIG. 5) according to an embodiment of the present invention may be provided in common to the first to third light emitting parts EP1, EP2, and EP3. That is, the anode EL1 may be formed as one layer integral with the entire display area DA, and therefore the anode EL1 layer may be disposed overlapping the separator SPR. Alternatively, each anode EL1 of the light emitting element LD may be formed as an independent conductive pattern spaced apart from each other and electrically connected to each other through another conductive layer, and therefore the anode EL1 pattern may be disposed not overlapping the separator SPR.

[0172] As described above, the first power supply voltage VDD (see FIG. 2A) is applied to the anode EL1, and a common voltage may be provided to all the light emitting units. The anode EL1 may be connected to the first power supply line VDL (see FIG. 2A) that provides the first power supply voltage VDD in the peripheral area NDA, or may be connected to the first power supply line VDL (see FIG. 2A) in the display area DA, and is not limited to any one of the embodiments.

[0173] Meanwhile, a plurality of openings may be defined in the anode EL1 according to the present embodiment, and the openings may penetrate the anode EL1 layer. The openings in the anode EL1 layer may be disposed at a position not overlapping with the light emitting portion EP (see FIG. 3A), and may be disposed at a position overlapping with the separator SPR. The openings may facilitate the discharge of gas generated from an organic layer disposed below the anode EL1, for example, a sixth insulating layer 60 (see FIG. 5) described below. Therefore, gas from an organic layer disposed below the light emitting element may be sufficiently discharged during the manufacturing process of the display panel, and the rate at which the light emitting element is deteriorated may be reduced by reducing the amount of gas discharged from the organic layer after manufacturing.

[0174] Fig. 5 is a cross-sectional view of a display panel DP according to an embodiment of the present invention. Fig. 6A is a cross-sectional view showing an enlarged portion of a display panel DP according to an embodiment of the present invention. Fig. 6B is an image of a portion of a display panel according to an embodiment of the present invention. Fig. 6C is a cross-sectional view showing an enlarged portion of a display panel DP according to an embodiment of the present invention.

[0175] Figure 5 shows a cross-sectional view of a portion corresponding to line I-I' in Figure 4A. Figure 6A shows an enlarged cross-sectional view of region AA' in Figure 5, and Figure 6B is an image of a portion of Figure 6A. Figure 6C shows an enlarged cross-sectional view of region BB' in Figure 5. The present invention will now be described with reference to Figures 5 to 6C.

[0176] 5 and 6A, the display panel DP according to an embodiment may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, a sealing layer ECL, and a sensing layer ISL. However, this is merely an example, and in an embodiment of the present invention, the display panel DP may not include the sensing layer ISL.

[0177] The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, 60 to configure a pixel driving unit PDC. For ease of explanation, FIG. 5 illustrates a cross section of one region in which one light emitting unit is disposed.

[0178] The base layer BS may be a member that provides a base surface on which the pixel driving unit PDC is disposed. The base layer BS may be a rigid substrate or a flexible substrate that is capable of bending, folding, rolling, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiment of the present invention is not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0179] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0180] The polymer resin layer may include a polyimide-based resin. Also, the polymer resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in the present specification, a "based" resin means that it includes a functional group of "based".

[0181] Each of the insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may be formed by a method such as coating, deposition, etc. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or a semiconductor pattern, a conductive pattern, a signal line, etc.

[0182] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, 60 and a pixel driving unit PDC, which are sequentially stacked on a base layer BS. In FIG. 5, one transistor TR and two capacitors C1 and C2 are illustrated in the pixel driving unit PDC.

[0183] The transistor TR corresponds to a transistor connected to the light emitting element LD through the intermediate connecting electrode CN and the connecting electrode CNE, i.e., a connection transistor connected to a node corresponding to the cathode of the light emitting element LD (the fourth node N4 in FIG. 2A, the second node N2 in FIG. 2B, or the fourth node N4 in FIG. 2C), and specifically may correspond to the sixth transistor T6 in FIG. 2A, the first transistor T1 in FIG. 2B, or the fourth transistor T4a in FIG. 2C. Meanwhile, although not shown, other transistors constituting the pixel driving unit PDC may have the same structure as the transistor TR (hereinafter, a connection transistor) shown in FIG. 5. However, this is merely an example, and the other transistors constituting the pixel driving unit PDC may have a different structure from the connection transistor TR, and are not limited to any one of the embodiments.

[0184] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 is illustrated as a single silicon oxide layer. Meanwhile, an insulating layer to be described later may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0185] Meanwhile, the first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL arranged to overlap the connection transistor TR. The lower conductive layer BCL may block the electric potential caused by the polarization development of the base layer BS from affecting the connection transistor TR. Also, the lower conductive layer BCL may block light incident on the connection transistor TR from below. At least one of an inorganic barrier layer and a buffer layer may be further arranged between the lower conductive layer BCL and the base layer BS.

[0186] The lower conductive layer BCL may include a reflective metal, such as titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0187] In this embodiment, the lower conductive layer BCL may be connected to the source of the connection transistor TR (or transistor) through the source electrode pattern W1. In this case, the lower conductive layer BCL may be synchronized with the source of the transistor TR. However, this is shown by way of example, and the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BCL may be connected to another electrode and a constant voltage or a pulse signal may be applied independently. Alternatively, the lower conductive layer BCL may be provided in a form isolated from other conductive patterns. The lower conductive layer BCL according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0188] A connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 However, without being limited thereto, the semiconductor pattern SP may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0189] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR, which are divided according to the degree of conductivity. The channel region CR may be a portion overlapping the gate electrode GE on a plane. The source region SR and the drain region DR may be portions separated by the channel region CR. When the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduced region. Therefore, the source region SR and the drain region DR have a relatively high reduced metal content compared to the channel region CR. Alternatively, when the semiconductor pattern SP is polycrystalline silicon, each of the source region SR and the drain region DR may be a region doped at a high concentration.

[0190] The source region SR and the drain region DR may have a relatively high conductivity compared to the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. As shown in FIG. 5, a separate source electrode pattern W1 and a drain electrode pattern W2 connected to the source region SR and the drain region DR, respectively, may be further provided. Specifically, the separate source electrode pattern W1 and the drain electrode pattern W2 may be integrally formed with one of the lines constituting the pixel driving unit (see PDC in FIG. 2A, PDC-1 in FIG. 2B, or PDC-2 in FIG. 2C), and are not limited to any one embodiment.

[0191] The second insulating layer 20 may overlap a plurality of pixels in common and cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0192] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. The gate electrode GE may be disposed above the semiconductor pattern SP. However, this is merely an example, and the gate electrode GE may be disposed below the semiconductor pattern SP, and is not limited to any one embodiment.

[0193] The gate electrode GE may include, but is not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or an alloy thereof.

[0194] A third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0195] Among the conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart by a first insulating layer 10 and a second insulating layer 20.

[0196] In an embodiment of the present invention, the first capacitor electrode CPE1 and the lower conductive layer BCL may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0197] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be separated from the second capacitor electrode CPE2 via the third insulating layer 30 and may overlap on a plane. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0198] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0199] A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the connection transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the connection transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may function as the drain of the connection transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0200] An intermediate connecting electrode CN may be disposed on the fifth insulating layer 50. The intermediate connecting electrode CN may electrically connect the pixel driving part PDC and the light emitting element LD. That is, the intermediate connecting electrode CN may electrically connect the connection transistor TR and the light emitting element LD. The intermediate connecting electrode CN may be a connection node connecting the pixel driving part PDC and the light emitting element LD. That is, the intermediate connecting electrode CN may correspond to the fourth node N4 (see FIG. 2A) shown in FIG. 2A, the second node N2 (see FIG. 2B) shown in FIG. 2B, or the fourth node N4 (see FIG. 2C) shown in FIG. 2C.

[0201] A sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connecting electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0202] The sixth insulating layer 60 may have a through hole OP-60 exposing at least a portion of the intermediate connecting electrode CN. The intermediate connecting electrode CN may be connected to the connecting electrode CNE through a portion exposed from the sixth insulating layer 60, and may be electrically connected to the light emitting element LD. That is, the intermediate connecting electrode CN may electrically connect the connection transistor TR and the light emitting element LD together with the connecting electrode CNE. Meanwhile, in the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted, or a plurality of sixth insulating layers 60 may be provided, and is not limited to any one embodiment. When the sixth insulating layer 60 is omitted, the intermediate connecting electrode CN may also be omitted.

[0203] The intermediate connecting electrode CN may include a first layer L1, a second layer L2, and a third layer L3 that are sequentially stacked along a third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a material having high conductivity. In one embodiment, the second layer L2 may include aluminum (Al).

[0204] A light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining film PDL, a light emitting element LD, and a separator SPR.

[0205] The pixel definition layer PDL may be an organic layer. For example, the pixel definition layer PDL may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), and PS (Polystyrene), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0206] In one embodiment, the pixel defining layer PDL may have a light absorbing property, for example, a color of black. The pixel defining layer PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking property.

[0207] An opening OP-PDL (hereinafter, a light-emitting opening) exposing at least a portion of a first electrode EL1 described later may be defined in the pixel definition film PDL. A plurality of light-emitting openings OP-PDL may be provided and arranged corresponding to each light-emitting element. All components of the light-emitting element LD may be arranged overlapping each other in the light-emitting opening OP-PDL, and the light-emitting opening OP-PDL may be an area in which light emitted by the light-emitting element LD is substantially displayed. Therefore, the shape of the first light-emitting portion EP1 (see FIG. 4A) may substantially correspond to the shape of the light-emitting opening OP-PDL on a plane.

[0208] A connecting electrode CNE may be disposed on the pixel defining layer PDL. The connecting electrode CNE may electrically connect the pixel driving part PDC and the light emitting element LD. That is, the pixel driving part PDC may be electrically connected to the light emitting element LD via the intermediate connecting electrode CN and the connecting electrode CNE. The connecting electrode CNE may correspond to the first connecting electrode CNE1 shown in FIG. 4A. The second connecting electrode CNE2 (see FIG. 4A) and the third connecting electrode CNE3 (see FIG. 4A) may also have a similar structure to the connecting electrode CNE.

[0209] The connecting electrode CNE may include a first edge EG1c adjacent to the light emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light emitting element LD may be in contact with the connecting electrode CNE in a region adjacent to the second edge EG2c.

[0210] The connecting electrode CNE may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 However, the material constituting the connecting electrode CNE is not limited to the above example.

[0211] A through hole OP-P separated from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL. A plurality of through holes OP-P may be provided and disposed corresponding to each light emitting element. The size of the through hole OP-P defined in the pixel defining layer PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connecting electrode CNE may be disposed in the through hole OP-P and the through hole OP-60 and connected to the intermediate connecting electrode CN.

[0212] The light emitting element LD may include a first electrode EL1, an intermediate layer IML, and a second electrode EL2.

[0213] The first electrode EL1 may be a semi-transparent, transparent, or reflective electrode. According to an embodiment of the present invention, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 For example, the first electrode EL1 may include a stacked structure of ITO / Ag / ITO.

[0214] In this embodiment, the first electrode EL1 may be an anode of the light emitting element LD. That is, the first electrode EL1 may be connected to the first power line VDL (see FIG. 2A) and may be applied with a first power voltage VDD (see FIG. 2A). The first electrode EL1 may be connected to the first power line VDL in the display area DA (see FIG. 3A or 3B) or may be connected to the first power line VDL in the peripheral area NDA. In the latter case, the first power line VDL may be disposed in the peripheral area NDA (see FIG. 3A or 3B) and the first electrode EL1 may have a shape extended to the peripheral area NDA.

[0215] 5, the first electrode EL1 is overlapped with the light emitting opening OP-PDL and not overlapped with the separator SPR, but as described above in FIG 4E, the first electrode EL1 of the light emitting element may have an integral shape and a mesh or lattice shape with an opening defined in a part of the area. That is, as long as the same first power supply voltage VDD can be applied to the first electrode EL1 of each of the plurality of light emitting elements, the shape of the first electrode EL1 may be variously provided and is not limited to any one embodiment.

[0216] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light emitting element LD may include the intermediate layer IML of various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided in a plurality of layers, or may be provided as two or more layers separated by the emitting layer EML.

[0217] The emission layer EML may include an organic light-emitting material. The emission layer EML may also include an inorganic light-emitting material, or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In this embodiment, the emission layers EML included in each of the adjacent emission units EP (see FIG. 3A) may include light-emitting materials that display different colors. For example, the emission layer EML included in each emission unit EP may provide any one of blue, red, and green light. However, the present invention is not limited thereto, and the emission layers EML disposed in all the emission units EP may include light-emitting materials that display the same color. In this case, the emission layer EML may provide blue light or white light.

[0218] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. Specifically, the functional layer FNL may include a first intermediate functional layer FNLa disposed between the first electrode EL1 and the light emitting layer EML, and a second intermediate functional layer FNLb disposed between the second electrode EL2 and the light emitting layer EML. In one embodiment of the present invention, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb may be omitted. In this embodiment, the light emitting layer EML is illustrated as being inserted in the functional layer FNL. That is, it may be understood that the light emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0219] The functional layer FNL can control the transfer of charges between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0220] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connecting electrode CNE and electrically connected to the pixel driving part PDC. That is, the second electrode EL2 may be electrically connected to the connecting transistor TR through the connecting electrode CNE.

[0221] The separator SPR may be disposed on the pixel definition film PDL. Also, the separator SPR may be disposed on the connecting electrode CNE disposed on the pixel definition film PDL and on the gap GP between the connecting electrode CNE and the adjacent adjacent connecting electrode CNEn.

[0222] In one embodiment, the second electrode EL2 and the functional layer FNL may be formed by common deposition on a plurality of pixels through an open mask. At this time, the second electrode EL2 and the functional layer FNL may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape (a shape surrounding each light emitting portion) for each light emitting portion, and therefore the second electrode EL2 and the functional layer FNL may have a shape divided for each light emitting portion. That is, the second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel.

[0223] 5, 6A, and 6B, the separator SPR may have a double inverse taper shape. That is, the taper angle formed between the upper surface of the pixel defining film PDL and a first side surface TP1 of the separator SPR and the taper angle formed between the upper surface of the pixel defining film PDL and a second side surface TP2 of the separator SPR may be different from each other. The taper angle may be an obtuse angle. For example, referring to FIG. 6B, the taper angle formed by the first side surface TP1 with respect to the upper surface of the pixel defining film PDL may be smaller than the taper angle formed by the second side surface TP2 with respect to the upper surface of the pixel defining film PDL.

[0224] In one embodiment of the present invention, the connection region BDA between the first side TP1 and the second side TP2 may have a curved line in cross section, i.e., the connection region BDA between the first side TP1 and the second side TP2 having different taper angles may have a rounded shape with a gradually changing slope.

[0225] In an embodiment of the present invention, the second side surface TP2 has a larger taper angle than the first side surface TP1, so that a predetermined space may be defined between the second side surface TP2 of the separator SPR and the connecting electrode CNEn. The second electrode EL2n may have a shape extending toward the predetermined space.

[0226] However, the shape of the separator SPR shown in Fig. 6A is merely an example, and the taper angle can be set in various ways as long as the separator SPR can electrically disconnect the second electrode EL2 so as to separate each pixel. Also, the separator SPR can have a structure such as a tip portion (a shelf-like protruding portion to the outside), and is not limited to any one embodiment.

[0227] In one embodiment, the separator SPR may include a material having insulating properties, and may particularly include an organic insulating material. The separator SPR may include an inorganic insulating material, may be configured with a multi-layer structure of an organic insulating material and an inorganic insulating material, or may include a conductive material depending on the embodiment. That is, as long as the second electrode EL2 can be electrically disconnected so as to be separated for each pixel, the separator SPR is not particularly limited in terms of the type of material.

[0228] A dummy layer UP may be disposed on the upper portion of the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR, and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML, and may include the same material as the intermediate layer IML. The first dummy layer UP1 may include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a may be formed in the same process as the first intermediate functional layer FNLa, and may include the same material as the intermediate layer FNLb. The 1-2 dummy layer UP1b may be formed in the same process as the second intermediate functional layer FNLb, and may include the same material as the intermediate layer FNLb. The second dummy layer UP2 may be formed in the same process as the second electrode EL2, and may include the same material as the intermediate layer EL2. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the functional layer FNL and the second electrode EL2. In another embodiment, the display panel DP may not include the dummy layer UP.

[0229] 5, 6A, and 6C, the intermediate layer IML may include a first region AR1 and a second region AR2. For example, the first region AR1 may be a region including only layers formed by an open mask among layers constituting the intermediate layer IML, and the second region AR2 may be a region including all layers formed by an open mask and layers formed by a fine metal mask among layers constituting the intermediate layer IML.

[0230] For example, the first region AR1 may include a first intermediate functional layer FNLa and a second intermediate functional layer FNLb. The second region AR2 may include a first intermediate functional layer FNLa, a second intermediate functional layer FNLb, and an emitting layer EML. Thus, a first thickness TK1 of the first region AR1 in the intermediate layer IML may be smaller than a second thickness TK2 of the second region AR2 in the intermediate layer IML. A portion of the boundary between the first region AR1 and the second region AR2 may not overlap with the connecting electrode CNE and may be separated from a first edge EG1c of the connecting electrode CNE. Thus, an edge EG of the emitting layer EML included only in the second region AR2 may be separated from the first edge EG1c.

[0231] 6A, a first region AR1 of the intermediate layer IML is illustrated on the right side of the separator SPR, and a second region AR2n of the adjacent intermediate layer IML is illustrated on the left side. Comparing the left and right sides of the separator SPR, it can be seen that the area of ​​the region where the connecting electrode CNE is exposed in the portion adjacent to the first region AR1 is larger than the area of ​​the region where the connecting electrode CNEn is exposed in the portion adjacent to the second region AR2n.

[0232] The second electrode EL2 may be in contact with the connecting electrode CNE through the connection region CA. The second electrode EL2n may be in contact with the connecting electrode CNEn through the connection region CAn. That is, by forming a layer formed by a fine metal mask, for example, the light emitting layer EML, so as not to overlap with a portion of the connecting electrode CNE, an exposed area may be stably secured in the portion of the connecting electrode CNE, and the contact reliability between the connecting electrode CNE and the second electrode EL2 may be improved. Therefore, contamination defects caused by contact defects may be reduced or eliminated. As a result, the image quality or manufacturing yield of the display panel DP and the display device DD including the same (see FIG. 1) may be improved.

[0233] According to an embodiment of the present invention, the connecting electrode CNE has a shape surrounding at least a part of the light emitting portion EP1 (see FIG. 4A) defined in the light emitting element LD. Therefore, the degree of freedom of the position at which the connecting electrode CNE and the light emitting element LD are connected and the degree of freedom of the position at which the connecting electrode CNE and the pixel driving part PDC are connected can be improved. In addition, the upper surface CNE-us of the connecting electrode CNE can be in contact with the lower surface EL2-bs of the second electrode EL2 of the light emitting element LD. In this case, the contact reliability between the connecting electrode CNE and the second electrode EL2 can be improved. In addition, since the lower surface of the connecting electrode CNE is in contact with the upper surface of the intermediate connecting electrode CN, the contact reliability can be improved. Therefore, the size of the through holes OP-P, OP-60 for connecting the connecting electrode CNE and the intermediate connecting electrode CN can be reduced or minimized. Therefore, the area or resolution of the light emitting portion in the display panel DP can be easily increased.

[0234] 5, an encapsulation layer ECL may be disposed on the light emitting device layer LDL. The encapsulation layer ECL may cover the light emitting device LD and may cover the separator SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which are sequentially stacked. However, without being limited thereto, the encapsulation layer ECL may further include a plurality of inorganic layers and an organic layer. The encapsulation layer ECL may also be a glass substrate.

[0235] The first and second inorganic layers IL1 and IL2 protect the light emitting element LD from moisture and oxygen outside the display panel DP, and the organic layer OL protects the light emitting element LD from particles and foreign substances remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one of them.

[0236] The sensing layer ISL can sense an external input. In the present embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a continuous process. In this case, the sensing layer ISL can be expressed as being directly disposed on the encapsulation layer ECL. Being directly disposed can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. That is, a separate adhesive member may not be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is shown by way of example, and in the display panel DP according to an embodiment of the present invention, the sensing layer ISL can be formed separately and then coupled to the display panel DP through an adhesive member, and is not limited to any one embodiment.

[0237] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is shown by way of example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0238] Each of the first to third sensing insulating layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0239] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0240] The single-layered sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO), etc. Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0241] The multi-layered sensing conductive layer can include a metal layer, for example, a titanium (Ti) / aluminum (Al) / titanium (Ti) three-layer structure, or the multi-layered sensing conductive layer can include at least one metal layer and at least one transparent conductive layer.

[0242] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor for sensing an external input in the sensing layer ISL. The sensor may be driven in a capacitive manner, and may be driven by any one of a mutual capacitance manner or a self-capacitance manner. However, this is merely an example, and the sensor may be driven by a resistive film manner, an ultrasonic wave manner, or an infrared ray manner in addition to the capacitive manner, and is not limited to any one of the embodiments.

[0243] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0244] 7 is an enlarged cross-sectional view of a portion of a display panel according to an embodiment of the present invention, for example, an enlarged cross-sectional view of a region corresponding to region AA′ of FIG.

[0245] 5 and 7, the display panel DP may further include a lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be disposed between the pixel defining layer PDL and the separator SPR. In an embodiment in which the lower encapsulation layer IL-ad is applied, a portion of the connecting electrode CNE may be disposed on the lower encapsulation layer IL-ad. The lower encapsulation layer IL-ad may be an inorganic layer.

[0246] Even if a gap is formed in the first inorganic layer IL1 in a portion adjacent to a side surface of the separator SPR, the gap can be sealed by the lower sealing layer IL-ad. Therefore, even if the gap acts as an outgassing route or a moisture permeating route of the organic layer IL, gas and moisture can be sealed by the lower sealing layer IL-ad. Therefore, the protective function of protecting the light emitting element LD can be improved, and as a result, the reliability of the display panel DP can be improved.

[0247] 8 is an enlarged cross-sectional view of a portion of a display panel according to an embodiment of the present invention, for example, an enlarged cross-sectional view of a region corresponding to region AA′ of FIG.

[0248] 5 and 8, a first encapsulating layer IL1a may be applied instead of the first inorganic layer IL1 shown in FIG. 5. The first encapsulating layer IL1a may include a plurality of sub-encapsulating layers ILs1, Ils2, and Ils3. Therefore, the first encapsulating layer IL1a may cover the separator SPR relatively loosely. Therefore, a gap formed in a portion of the upper surface of the first encapsulating layer IL1a adjacent to the side surface of the separator SPR may be eliminated. Therefore, the protective function of the encapsulating layer that protects the light emitting element LD may be improved.

[0249] In one embodiment of the present invention, the first sealing layer IL1a may include a first sub sealing layer Ils1, a second sub sealing layer Ils2, and a third sub sealing layer Ils3. The first sub sealing layer Ils1 may cover the separator SPR. The second sub sealing layer Ils2 may be disposed on the first sub sealing layer Ils1. The third sub sealing layer Ils3 may be disposed on the second sub sealing layer Ils2. However, this is merely an example, and some of the sub sealing layers constituting the first sealing layer IL1a may be omitted, or more sub sealing layers may be included.

[0250] In an embodiment of the present invention, at least a portion of the first to third sub-encapsulation layers Ils1, Ils2, and Ils3 may include an organic material. For example, the first sub-encapsulation layer Ils1 and the third sub-encapsulation layer Ils3 may include an inorganic material, and the second sub-encapsulation layer Ils2 may include an organic material. Even if a gap is formed in the first sub-inorganic layer IL1s1 at a portion adjacent to the side of the separator SPR, the gap can be filled by the second sub-encapsulation layer Ils2. For example, the first sub-encapsulation layer Ils1 and the third sub-encapsulation layer Ils3 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second sub-encapsulation layer Ils2 may include silicon carbonate (SiOCx). However, the present invention is not particularly limited thereto.

[0251] Fig. 9 is a cross-sectional view of a display panel DP-1 according to an embodiment of the present invention. Fig. 9 shows a cross-sectional view of a portion corresponding to line I-I' in Fig. 4A. In describing Fig. 9, the same reference numerals are used to refer to the same components as those described in Fig. 5, and description thereof will be omitted.

[0252] 9, the display panel DP-1 may further include a connecting wire CN-ad disposed between the sixth insulating layer 60 and the pixel defining layer PDL. The connecting wire CN-ad may be connected to the intermediate connecting electrode CN through a through hole OP-60 that exposes at least a portion of the intermediate connecting electrode CN.

[0253] In an embodiment of the present invention, the connecting wire CN-ad may be disposed on the same layer as the first electrode EL1. For example, the connecting wire CN-ad may be made of the same material and have the same layer structure as the first electrode EL1. Also, the connecting wire CN-ad may be formed by the same process as the first electrode EL1. However, this is merely an example and is not limiting. For example, the connecting wire CN-ad may include a different material and be formed by a different process than the first electrode EL1.

[0254] A through hole OP-Pa may be defined in the pixel definition film PDL. The through hole OP-Pa and the through hole OP-60 may not overlap each other, but are not particularly limited thereto. For example, the through hole OP-Pa and the through hole OP-60 may overlap each other. A connecting electrode CNE may be disposed in the through hole OP-Pa. The connecting electrode CNEa may be connected to a portion of the connecting wiring CN-ad exposed by the through hole OP-Pa.

[0255] FIG. 10A is an enlarged plan view of a partial region of a display panel according to an embodiment of the present invention.

[0256] 10A shows an area in which a total of four light emitting units UT11a, UT12, UT21, and UT22a are arranged in two rows and two columns. The light emitting section in the first row Rk includes light emitting sections constituting the light emitting unit UT11a in the first row and first column and the light emitting unit UT12 in the first row and second column, and the light emitting section in the second row Rk+1 includes light emitting sections constituting the light emitting unit UT21 in the second row and first column and the light emitting unit UT22a in the second row and second column.

[0257] In an embodiment of the present invention, the shapes of the light emitting portions included in each of the four light emitting units UT11a, UT12, UT21, and UT22a may all be substantially the same, and thus, light emitting units having the same shape may be repeatedly arranged in the first direction DR1 and the second direction DR2.

[0258] Fig. 10B is an enlarged plan view of a part of a display panel according to an embodiment of the present invention, illustrating a part of the display panel shown in Fig. 10A, such as light emitting portions EP1, EP2, EP31, and EP32, connecting electrodes CNE1, CNE2, and CNE3, and a plurality of intermediate layers IML1, IML2, and IML3.

[0259] 10B, the intermediate layers IML1, IML2, and IML3 may be separated from each other by a separator SPR. The intermediate layers IML1, IML2, and IML3 may include a first intermediate layer IML1 disposed between a first cathode EL2_1 (see FIG. 4B) and a first electrode EL1 (see FIG. 4E), a second intermediate layer IML2 disposed between a second cathode EL2_2 (see FIG. 4B) and the first electrode EL1, and a third intermediate layer IML3 disposed between a third cathode EL2_3 (see FIG. 4B) and the first electrode EL1.

[0260] The first intermediate layer IML1 can include a first functional layer FNL1 having a first area and a first emissive layer EML1 having a second area smaller than the first area. The second intermediate layer IML2 can include a second functional layer FNL2 having a third area and a second emissive layer EML2 having a fourth area smaller than the third area. The third intermediate layer IML3 can include a third functional layer FNL3 having a fifth area and a third emissive layer EML3 having a sixth area smaller than the fifth area.

[0261] According to an embodiment of the present invention, at least a portion of a first edge EG11 of the first connecting electrode CNE1 does not overlap with the first emission layer EML1 and may be separated from the edge EG1 of the first emission layer EML1. At least a portion of a first edge EG21 of the second connecting electrode CNE2 does not overlap with the second emission layer EML2 and may be separated from the edge EG2 of the second emission layer EML2. At least a portion of a first edge EG31 of the third connecting electrode CNE3 does not overlap with the third emission layer EML3 and may be separated from the edge EG3 of the first emission layer EML1.

[0262] According to an embodiment of the present invention, at least a portion of each of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not overlap with the first to third light emitting layers EML1, EML2, and EML3. In this case, the area of ​​the exposed region of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be stably secured. Therefore, the first to third cathodes EL2_1, EL2_2, and EL2_3 may be stably connected to the first to third connecting electrodes CNE1, CNE2, and CNE3, respectively, and contact reliability may be improved. As a result, appearance defects caused by contact failure, for example, dirt defects found during lighting, may be reduced or eliminated. The image quality or manufacturing yield of the display panel DP and the display device DD including the same (see FIG. 1) may be improved.

[0263] FIG. 11A is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention.

[0264] Referring to FIG. 11A, a region in which a total of four light emitting units UT11b, UT12b, UT21b, and UT22b are arranged in two rows and two columns is shown.

[0265] In one embodiment of the present invention, the light emitting portion constituting the light emitting unit UT11b in the first row and first column may have substantially the same shape as the light emitting portion constituting the light emitting unit UT22b in the second row and second column. Also, the light emitting portion constituting the light emitting unit UT12b in the first row and second column may have substantially the same shape as the light emitting portion constituting the light emitting unit UT21b in the second row and first column. The shape of the light emitting portion constituting the light emitting unit UT11b in the first row and first column may be different from the shape of the light emitting portion constituting the light emitting unit UT12b in the first row and second column. For example, a part of the light emitting portion in the first row Rk and a part of the light emitting portion in the second row Rk+1 may have a symmetrical shape.

[0266] In an embodiment of the present invention, the third light emitting part EP3a of the light emitting unit UT21b in the second row and first column and the third light emitting part EP3 of the light emitting unit UT11b in the first row and first column may have a shape and arrangement shape that are line symmetrical with respect to an axis along the first direction DR1, and the third light emitting part EP3 of the light emitting unit UT22b in the second row and second column and the third light emitting part EP3a of the light emitting unit UT12b in the first row and second column may have a shape and arrangement shape that are line symmetrical with respect to an axis along the first direction DR1, but this is merely an example and is not limited thereto.

[0267] In an embodiment of the present invention, in order to stably connect the first to third cathodes EL2_1, EL2_2, and EL2_3 to the first to third connecting electrodes CNE1, CNE2, and CNE3, the shape of a portion of the separator SPRa may be modified.

[0268] For example, a portion of the separator SPRa surrounding the first light-emitting portion EP1 in each of the light-emitting unit UT11b in the first row and first column and the light-emitting unit UT22b in the second row and second column may have a shape protruding toward the third connection portion CE3 in each of the light-emitting unit UT11b in the first row and first column and the light-emitting unit UT22b in the second row and second column. A portion of the separator SPRa surrounding the first light-emitting portion EP1 of the light-emitting unit UT12b in the first row and second column may have a shape protruding toward the third connection portion CE3 of the light-emitting unit UT11b in the first row and first column. A portion PR2 of the separator SPRa surrounding the second light-emitting portion EP2 of the light-emitting unit UT12b in the first row and second column may have a shape protruding toward the third connection portion CE3 of the light-emitting unit UT12b in the first row and second column. A portion of the separator SPRa surrounding the second light emitting portion EP2 of the light emitting unit UT2b in the second row and second column may have a shape that protrudes toward the third connection portion CE3 of the light emitting unit UT21b in the second row and first column.

[0269] The third light emitting unit EP3 may include two sub light emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. The separator SPRa surrounding the third light emitting unit EP3 may have a closed line shape. A region defined by the separator SPRa surrounding the third light emitting unit EP3 of the light emitting unit UT11b in the first row and first column may be defined as a main region having a first width WT1 and a protruding region having a second width WT2. The second width WT2 may be smaller than the first width WT1. The main region may be arranged between a protruding portion PR1 of the separator SPRa surrounding the first light emitting unit EP1 of the light emitting unit UT11b in the first row and first column and a protruding portion PR1a of the separator SPRa surrounding the second light emitting unit EP2 of the light emitting unit UT12b in the first row and second column.

[0270] Fig. 11B is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention, illustrating a portion of the display panel shown in Fig. 11A, such as light emitting portions EP1, EP2, EP31, and EP32, connecting electrodes CNE1a, CNE2a, and CNE3a, and a plurality of intermediate layers IML1a, IML2a, and IML3a.

[0271] 11A and 11B, the first to third intermediate layers IML1a, IML2a, and IML3a may be separated from each other by a separator SPRa. The first to third intermediate layers IML1a, IML2a, and IML3a may be disposed between a first electrode EL1 (see FIG. 12) and a corresponding second electrode EL2 (see FIG. 12).

[0272] The first intermediate layer IML1a can include a first functional layer FNL1a having a first area and a first emissive layer EML1a having a second area smaller than the first area. The second intermediate layer IML2a can include a second functional layer FNL2a having a third area and a second emissive layer EML2a having a fourth area smaller than the third area. The third intermediate layer IML3a can include a third functional layer FNL3a having a fifth area and a third emissive layer EML3a having a sixth area smaller than the fifth area.

[0273] The first connecting electrode CNE1a may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connecting electrode CNE2a may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connecting electrode CNE3a may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0274] In an embodiment of the present invention, the first connecting electrode CNE1a may further include a first protruding portion CPR1 protruding in a direction away from the first light emitting opening OP-PDL1. The second connecting electrode CNE2a may further include a second protruding portion CPR2 protruding in a direction away from the second light emitting opening OP-PDL2. The third connecting electrode CNE3a may further include a third protruding portion CPR3 protruding in a direction away from the third light emitting opening OP-PDL3.

[0275] According to an embodiment of the present invention, the first edge EG11 and the second edge EG12 of the first connecting electrode CNE1a may be protruded in a direction away from the first light emitting opening OP-PDL1 in accordance with the shape of the first protruding portion CPR1. The first edge EG21 and the second edge EG22 of the second connecting electrode CNE2a may be protruded in a direction away from the second light emitting opening OP-PDL2 in accordance with the shape of the second protruding portion CPR2. The first protruding portion CPR1 may be separated from the first light emitting layer EML1a without overlapping therewith. The second protruding portion CPR2 may be separated from the second light emitting layer EML2a without overlapping therewith. The third protruding portion CPR3 may be separated from the third light emitting layer EML3a without overlapping therewith.

[0276] The first functional layer FNL1a can overlap the region between the first protruding portion CPR1 and the first light-emitting layer EML1a, and a part of the first protruding portion CPR1. The second functional layer FNL2a can overlap the region between the second protruding portion CPR2 and the second light-emitting layer EML2a, and a part of the second protruding portion CPR2. The third functional layer FNL3a can overlap the region between the third protruding portion CPR3 and the third light-emitting layer EML3a, and a part of the third protruding portion CPR3.

[0277] In one embodiment of the present invention, the first light emitting layer EML1a may overlap the first light emitting opening OP-PDL1 and the first through hole OP-P1, and the second light emitting layer EML2a may overlap the second light emitting opening OP-PDL2 and the second through hole OP-P2. The third through hole OP-P3 may be disposed between the third protruding portion CPR3 and the third light emitting portion EP3. Thus, the third light emitting layer EML3a may overlap the third light emitting opening OP-PDL3 but not overlap the third through hole OP-P3.

[0278] The first intermediate layer IML1a may include a first region AR11a and a second region AR12a adjacent to the first region AR11a. The second intermediate layer IML2a may include a first region AR21a and a second region AR22a adjacent to the first region AR21a. The third intermediate layer IML3a may include a first region AR31a and a second region AR32a adjacent to the first region AR31a. For example, each of the first regions AR11a, AR21a, and AR31a may be a region in which some of the layers constituting each of the first to third intermediate layers IML1a, IML2a, and IML3a are arranged, and each of the second regions AR12a, AR22a, and AR32a may be a region in which all of the layers constituting each of the first to third intermediate layers IML1a, IML2a, and IML3a are arranged.

[0279] In an embodiment of the present invention, the first region AR11a of the first intermediate layer IML1a may not overlap the first through hole OP-P1, and the second region AR12a may overlap the first through hole OP-P1. The first region AR21a of the second intermediate layer IML2a may not overlap the second through hole OP-P2, and the second region AR22a may overlap the second through hole OP-P2. The first region AR31a of the third intermediate layer IML3a may overlap the third through hole OP-P3, and the second region AR32a may not overlap the third through hole OP-P3. For example, the first region AR11a of the first intermediate layer IML1a or the first region AR21a of the second intermediate layer IML2a may be adjacent to the first region AR31a of the third intermediate layer IML3a in the first direction DR1. FIG. 11B illustrates an example in which the first region AR11a of the first intermediate layer IML1a is adjacent to the first region AR31a of the third intermediate layer IML3a in the first direction DR1.

[0280] Fig. 12 is a cross-sectional view of a display panel DP-2 according to an embodiment of the present invention, taken along line II-II' in Fig. 11A.

[0281] 12, a protruding region PRA may be further defined in the display panel DP-2. The protruding region PRA may be a region defined by a portion PR2 of the separator SPRa surrounding the second light emitting portion EP2 described in FIG. 11A.

[0282] Corresponding to the protruding region PRA, the connecting electrode CNEb may include a protruding portion CRP. A part of the functional layer FNL may be disposed in the protruding region PRA, and the light emitting layer EML may not be disposed therein. In this case, the area of ​​the exposed region of the connecting electrode CNEb may be stably secured. Therefore, the second electrode EL2 may be stably connected to the connecting electrode CNEb, and thus the contact reliability may be improved. As a result, appearance defects caused by contact failure, for example, dirt defects found during lighting, may be reduced or eliminated. The image quality or manufacturing yield of the display panel DP-2 and the display device DD including the same (see FIG. 1) may be improved.

[0283] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those having ordinary knowledge in the art that the present invention can be modified and changed in various ways without departing from the spirit and scope of the present invention as described in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0284] According to a preferred specific embodiment, it is as follows.

[0285] The background and issues of this case are as follows (i) to (vi). (i) In organic light-emitting display panels in which organic light-emitting elements (OLEDs) are arranged for each sub-pixel, the adoption of an Inverted OLED structure is being considered in order to address issues such as deterioration of the OLEDs over time that can occur when oxide semiconductors are used in drive transistors in pixel circuits.

[0286] (ii) Inverted OLED, for each subpixel, the lower electrode (on the pixel circuit side) of the organic light-emitting element (OLED) is a common electrode, and the upper electrode (on the side farther from the pixel circuit) is a pixel electrode, which is connected to the drive transistor of the pixel circuit.

[0287] (iii) When an inverted OLED structure is adopted, the upper electrode (pixel electrode) for each subpixel must be connected to the drive transistor of the pixel circuit in a small area and with high reliability.

[0288] (iv) In addition, the separator structure, which prevents leakage current from the light-emitting layer or intermediate layer between adjacent subpixels, needs to have a small area and a high reliability.

[0289] (v) Furthermore, it is desirable to form the light-emitting layer and the functional layer of the organic light-emitting device (OLED) in a predetermined region through a deposition mask in order to reduce the process burden.

[0290] (vi) On the other hand, Patent Document 1 (US Pat. No. 1,315,986B) discloses providing separators (spacers 123a, 123b) having a reverse tapered cross section on a pixel defining layer (PDL).

[0291] Therefore, according to a particularly preferred embodiment, any combination of the following A1 to A3 or the following A1 to A6 is used.

[0292] A1 A planarization film (fifth insulating layer 50) and a pixel definition film PDL thereon are formed from a resin material, and an insulating film (sixth insulating layer 60) made of an inorganic material and / or a resin material is disposed between them as necessary. Then, an "intermediate connecting electrode CN" is formed on the planarization film (fifth insulating layer 50), and a contact opening (through hole OP-P) that exposes the "intermediate connecting electrode CN" is formed in the pixel definition film PDL, together with a pixel opening (light-emitting opening OP-PDL).

[0293] A2 The "connecting electrode CNE" is formed for each subpixel so as to cover the contact opening (through hole OP-P), is disposed so as to surround the pixel opening (light-emitting opening OP-PDL), and is directly overlapped with and connected to the peripheral portion of the upper electrode (pixel electrode; second electrode EL2) for each subpixel (FIG. 6C). Furthermore, between adjacent sub-pixels, a "gap GP" is provided in the "connecting electrode CNE" (FIG. 6A).

[0294] A3 The light emitting layer EML is omitted at least in the contact opening (through hole OP-P) and its vicinity. As a result, the upper electrode (pixel electrode; second electrode EL2) and the "connecting electrode CNE" make better contact in the vicinity of the contact opening (through hole OP-P) and along the "gap GP." That is, a contact area (connection area CA) between the periphery of the upper electrode (pixel electrode; second electrode EL2) and the periphery of the "connecting electrode CNE" can be sufficiently secured.

[0295] A4 Place a separator (SPR) with a reverse tapered cross section along the "gap GP". The separator (SPR) is preferably as shown in A4-1 to A4-5. A4-1 The lower end of the separator (SPR) covers the outermost periphery of the "gap GP" and the "connecting electrodes CNE" on both sides thereof. The lower side of the A4-2 separator (SPR) forms an overhanging portion that tapers outward. In the illustrated example, the inclination increases toward the top. This inclination can be, for example, 60 to 30 degrees with respect to the vertical direction. The upper side surface of the A4-3 separator (SPR) may be approximately vertical (e.g., the inclination with respect to the vertical may be 10° or less, or 5° or less.

[0296] A4-4 After the separator (SPR) is formed, the upper and lower functional layers (FNL) are deposited. As a result, even if deposition using an “open mask” (deposition over the entire surface of at least the area of ​​multiple subpixels) is performed, the functional layer (FNL) is omitted below the lower side of the separator (SPR), and the “connecting electrode CNE” is exposed. A4-5 The subsequent deposition of the upper electrode (pixel electrode; second electrode EL2) can be performed using an "open mask" but with a method and deposition material with low anisotropy, so that the deposition can be performed up to the bottom of the separator (SPR) lower side. As a result, the upper electrode (pixel electrode; second electrode EL2) and the "connecting electrode CNE" can be connected at this point.

[0297] A5 In areas where the light-emitting layer (EML) is omitted, such as the contact opening (through hole OP-P) and its vicinity, the functional layers (FNL) (at least one of the electron blocking layer, hole transport layer, hole injection layer, hole blocking layer, electron transport layer, electron injection layer, and charge generation layer) arranged above and below the light-emitting layer (EML) are not omitted ( FIG. 6A ). This allows the functional layer (FNL) to be deposited in a predetermined area using a deposition mask with only relatively large openings, and allows only the light-emitting layer (EML) to be deposited using a fine metal mask or the like that requires relatively high precision.

[0298] A6: Regarding the planar shape of the ring-shaped "gap GP" and separator (SPR) that form the boundary between sub-pixels, a protruding portion (CPR) that protrudes from one sub-pixel toward another sub-pixel is formed in part, preferably as described in A6-1 to A6-2 below.

[0299] A6-1 In the protruding portion (CPR), not only the light-emitting layer (EML) but also the functional layer (FNL) is omitted. This allows contact between the upper electrode (pixel electrode; second electrode EL2) and the "connecting electrode CNE" to be made over almost the entire protruding portion (CPR). A6-2 The protruding portion (CPR) can be disposed at a corner portion of the sub-pixel separate from the contact opening (through hole OP-P). [Explanation of symbols]

[0300] DP display panel DDL Drive element layer LD light emitting element PDL Pixel Defining Membrane CNE connection electrode PDC pixel driver EL1 First electrode IML middle tier EL2 2nd electrode FNL functional layer EML Light Emitting Layer

Claims

1. A driving element layer including a pixel driving unit; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a pixel defining film disposed on the driving element layer and having an opening defined therein exposing at least a portion of the first electrode; a connecting electrode disposed on the pixel defining film and electrically connected to the pixel driving part and the second electrode, The intermediate layer includes a functional layer having a first area, and a light-emitting layer having a second area smaller than the first area.

2. The display panel according to claim 1 , wherein the connecting electrode has a ring shape surrounding the opening.

3. The display panel of claim 1 , wherein a lower surface of the second electrode is in contact with an upper surface of the connecting electrode.

4. The display panel according to claim 1 , wherein a connection region in which the second electrode and the connecting electrode are connected surrounds at least a portion of the opening.

5. The display panel described in claim 1, wherein the functional layer includes a first intermediate functional layer arranged on the first electrode and a second intermediate functional layer arranged on the light-emitting layer, and the light-emitting layer is arranged between the first intermediate functional layer and the second intermediate functional layer.

6. The display panel of claim 1 , further comprising a separator disposed on the connecting electrode, the second electrode and the connecting electrode being connected to each other in a region adjacent to the separator.

7. a first dummy layer disposed on the separator and containing the same material as the functional layer; The display panel of claim 6 , further comprising: a second dummy layer disposed on the first dummy layer and containing the same material as the second electrode.

8. The display panel of claim 6 , wherein the connecting electrodes each include a first edge and a second edge surrounding the first edge, the second edge overlapping the separator.

9. The light emitting device, the pixel driving part, and the connecting electrode are each provided in a plurality of parts, The plurality of connection electrodes electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively. The display panel of claim 6 , wherein gaps between adjacent ones of the plurality of connecting electrodes overlap the separator.

10. The display panel of claim 1 , wherein a through hole is defined in the pixel defining film, and the connecting electrode is connected to the pixel driving part through the through hole.

11. The display panel according to claim 10 , wherein the light-emitting layer does not overlap the through-hole, and the functional layer overlaps the through-hole.

12. The display panel according to claim 10 , wherein the light-emitting layer and the functional layer overlap the through-hole.

13. The display panel of claim 1 , wherein the connecting electrode includes a protruding portion protruding in a direction away from the opening, the protruding portion not overlapping the light-emitting layer.

14. The protruding portion of the connecting electrode and the light emitting layer are spaced apart from each other, The display panel according to claim 13 , wherein the functional layer overlaps a region between the protruding portion and the light-emitting layer, and at least a part of the protruding portion.

15. A driving element layer including a pixel driving unit; a light emitting element including a first electrode disposed on the driving element layer and having a light emitting portion defined corresponding to a part of the first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer; a connecting electrode electrically connected to the pixel driving part and the second electrode, the connecting electrode includes a first edge surrounding the light emitting portion and a second edge surrounding the first edge, A display panel, wherein a portion of the first edge does not overlap the light emitting layer, and the portion of the first edge is spaced apart from an edge of the light emitting layer.

16. A driving element layer including a plurality of pixel driving units; a plurality of light emitting elements disposed on the driving element layer and electrically connected to each of the plurality of pixel driving units; a plurality of connecting electrodes connected to the pixel driving units and the light emitting devices; a separator disposed between the plurality of light emitting elements; Each of the plurality of light-emitting elements includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; Gaps between adjacent connecting electrodes among the plurality of connecting electrodes are overlapped with the separator, A display panel in which the intermediate layer includes a plurality of layers, a portion of the plurality of layers is arranged in a first region of the intermediate layer, and all of the plurality of layers are arranged in a second region of the intermediate layer adjacent to the first region.

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