Power transistor with soft recovery body diode

Abstract

To provide a semiconductor device.SOLUTION: A semiconductor device comprises: a substrate; a drift layer on the substrate; one or more injection regions in the drift layer, configured to provide a vertical transistor device configured to direct current in a first direction and a body diode configured to direct current in a second direction opposite the first direction; and a recombination region that comes into contact with one or more injection regions of the drift layer and have a higher density of minority carrier recombination centers than the drift layer.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 110,027, filed December 2, 2020, and U.S. Patent Application No. 17 / 208,271, filed March 22, 2021, the entire disclosures of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices, and more particularly to power transistors including body diodes with soft recovery characteristics and methods of fabricating power transistors. [Background technology]

[0003] Transistors have many applications in modern electronic devices. Power transistors, which are transistors capable of handling high voltages and currents, are often used in switching circuits that deliver power to a load. Transistors used in power switching circuits generally need to be able to conduct current in both directions. Therefore, anti-parallel diodes are provided in conjunction with transistors in power switching circuits. In the case of metal-oxide-semiconductor field-effect transistors (MOSFETs), the anode of the anti-parallel diode is tied to the drain of the MOSFET, and the cathode of the anti-parallel diode is tied to the source of the MOSFET. This allows current to flow in the MOSFET from the drain to the source in the forward conduction mode of operation, and from the source through the anti-parallel diode to the drain in the reverse conduction mode of operation. When the anti-parallel diode switches between conducting and blocking, the performance characteristics of the anti-parallel diode determine the speed at which such a transition can be made and the switching losses incurred. It is generally desirable to minimize both the transition time between operating modes and the switching losses. Therefore, there is a current need for anti-parallel diodes for use in conjunction with transistors to improve switching speed and reduce switching losses. Summary of the Invention [Means for solving the problem]

[0004] In one embodiment, a transistor includes a substrate, a drift layer over the substrate, and a junction implant in the drift layer opposite the substrate. The junction implant includes a body well and a source well within the body well. A source contact is in electrical contact with the source well and the body well. A drain contact is in electrical contact with the substrate. An insulator layer is over the drift layer and over a portion of the body well and the source well. A gate contact is on the insulator layer. A body diode between the source contact and the drain contact has a softness factor of greater than 0.5. By providing a transistor such that the body diode has a softness factor of greater than 0.5, the switching performance of the body diode, and therefore the switching losses of the transistor, are significantly reduced when used in bidirectional conduction applications.

[0005] In one embodiment, a transistor includes a substrate, a drift layer on the substrate, and a junction implant in the drift layer opposite the substrate. The junction implant includes a body well and a source well in the body well. A source contact is in electrical contact with the source well and the body well. A drain contact is in electrical contact with the substrate. An insulator layer is on the drift layer and over a portion of the body well and the source well. A gate contact is on the insulator layer. A body diode is formed by the body well, the drift layer, and the substrate between the source contact and the drain contact. During a forward bias mode of operation of the body diode, a concentration of minority carriers at the interface between the body well and the drift layer is lower than a concentration of minority carriers at the interface between the drift layer and the substrate. By designing the transistor to provide the aforementioned minority carrier profile in the drift layer of the body diode, the snappiness of the body diode is significantly reduced, thereby improving the switching performance of the transistor when used in bidirectional conduction applications.

[0006] In one embodiment, a semiconductor device includes a substrate, a drift layer, and one or more implanted regions in the drift layer. The drift layer has a carrier lifetime between 1 μs and 20 μs. The one or more implanted regions are configured to provide a vertical transistor device and a body diode. The vertical transistor device is configured to conduct current in a first direction, while the body diode is configured to conduct current in a second direction opposite the first direction. By providing a drift layer with a carrier lifetime between 1 μs and 20 μs, the softness of the body diode can be increased, which in turn can reduce switching losses associated with the semiconductor device.

[0007] In one embodiment, the body diode has a softness factor between 0.5 and 10. As discussed above, this may reduce switching losses associated with the semiconductor device. The semiconductor device may include a recombination zone in the drift layer, the recombination zone being greater than or equal to 1×10 13 cm -3 ~1×10 18 cm -3 The body diode may be provided as a non-punch-through diode.

[0008] In one embodiment, a semiconductor device includes a substrate, a drift layer, one or more implanted regions in the drift layer, and a recombination region in the drift layer. The one or more implanted regions are configured to provide a vertical transistor device and a body diode. The vertical transistor device is configured to conduct current in a first direction, while the body diode is configured to conduct current in a second direction opposite the first direction. The recombination region abuts the one or more implanted regions in the drift layer and has a recombination region of about 1×10 13 cm -3 ~1×10 18 cm -3The recombination region may increase the softness of the body diode, which in turn reduces switching losses associated with the semiconductor device.

[0009] In one embodiment, the softness factor of the body diode is between 0.5 and 10. The drift layer may have a carrier lifetime between 1 μs and 20 μs. The body diode may be configured to be a non-punch-through diode.

[0010] In certain embodiments, aspects of any of the above embodiments may be combined to further advantage.

[0011] Those skilled in the art will appreciate the scope of the present disclosure and further aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings.

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a cross-sectional view of a transistor according to one embodiment of the present disclosure. [Diagram 2] 1 is a graph showing reverse recovery of a body diode in a transistor according to one embodiment of the present disclosure. [Figure 3A] FIG. 2 illustrates the electric field in the drift layer for a punch through diode according to one embodiment of the present disclosure. [Figure 3B] FIG. 2 illustrates the electric field in the drift layer for a non-punch-through diode according to one embodiment of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a body diode of a transistor according to one embodiment of the present disclosure. [Figure 5A] 1 is a cross-sectional view of a transistor according to various embodiments of the present disclosure. [Figure 5B] 1 is a cross-sectional view of a transistor according to various embodiments of the present disclosure. [Figure 5C] 1 is a cross-sectional view of a transistor according to various embodiments of the present disclosure. [Figure 5D] 1 is a cross-sectional view of a transistor according to various embodiments of the present disclosure. [Figure 5E] 1 is a cross-sectional view of a transistor according to various embodiments of the present disclosure. [Figure 6] 1 is a graph illustrating a doping profile for multiple implants in a transistor according to one embodiment of the present disclosure. [Figure 7] FIG. 1 is a flow diagram illustrating a method for fabricating a transistor according to one embodiment of the present disclosure. [Figure 8] 1 is a graph illustrating the performance of a body diode of a transistor according to one embodiment of the present disclosure. [Figure 9] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 10] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 12] FIG. 2 illustrates a transistor according to one embodiment of the present disclosure. [Figure 13A] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 13B] 13B is a graph showing the electric field in a vertical semiconductor device for the embodiment of FIG. 13A. [Figure 13C] 13B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 13A. [Figure 14A] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 14B] 14B is a graph showing the electric field in a semiconductor device for the example of FIG. 14A. [Figure 14C]14B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the embodiment of FIG. 14A. [Figure 15A] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 15B] 15B is a graph showing the electric field in a semiconductor device for the example of FIG. 15A. [Figure 15C] 15B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the example of FIG. 15A. [Figure 16A] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 16B] 16B is a graph showing the electric field in a semiconductor device for the example of FIG. 16A. [Figure 16C] 16B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the example of FIG. 16A. [Figure 17A] FIG. 1 illustrates a semiconductor device according to one embodiment of the present disclosure. [Figure 17B] 17B is a graph illustrating the relative graded doping concentration levels throughout various layers of a vertical semiconductor device for the embodiment of FIG. 17A. [Figure 17C] 17B is a graph showing the electric field at the bottom of the drift layer and the drain-source current as the drain-source voltage increases in the blocking state for the example of FIG. 17A. [Figure 18A] FIG. 1 illustrates a power device according to an embodiment of the present disclosure. [Figure 18B] 18B is a graph illustrating the relative graded doping concentration levels throughout various layers of a vertical semiconductor device for the embodiment in FIG. 18A. [Figure 19] 11 is a graph illustrating the response of a body diode according to various embodiments of the present disclosure. [Figure 20] 11 is a graph illustrating the response of a body diode according to various embodiments of the present disclosure. [Figure 21] 11 is a graph illustrating the response of a body diode according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The examples described below represent the necessary information to enable those skilled in the art to implement the examples and show the best mode of implementing the examples. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0015] Terms such as first, second, etc. may be used herein to describe various elements, but it will be understood that these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] When an element such as a layer, region, or substrate is said to be "on" or extend "onto" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is said to be "directly on" or extend "directly onto" another element, no intervening elements are present. Similarly, when an element such as a layer, region, or substrate is said to be "over" or extend "over" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is said to be "directly over" or extend "directly over" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0017] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms, and those described above, are intended to encompass various orientations of the device in addition to the orientation shown in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and the related art, and will be further understood not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] FIG. 1 is a cross-sectional view of a transistor 10 according to one embodiment of the present disclosure. The transistor 10 includes a substrate 12 and a drift layer 14 on the substrate 12. A body well 16 is provided on the surface of the drift layer 14 opposite the substrate 12. A source well 18 is provided in the body well 16 so as to be within the body well 16. A contact well 19 is also provided in the body well 16 so as to be adjacent to the source well 18 of the body well 16. A junction field-effect transistor (JFET) region 20 is also provided on the surface of the drift layer 14 opposite the substrate 12 adjacent to the body well 16. A source contact 22 is provided on the drift layer 14 opposite the substrate 12 so as to be in electrical contact with the source well 18 and the body well 16 through the contact well 19. A drain contact 24 is provided in the substrate 12 so as to be in electrical contact with the substrate 12. A gate insulator 26 is provided on the surface of the drift layer 14 opposite the substrate 12 so as to overlie the JFET region 20, a portion of the body well 16, and a portion of the source well 18. A gate contact 28 is on the gate insulator 26.

[0021] In one embodiment, transistor 10 is an n-type device in that substrate 12, drift layer 14, source well 18, and JFET region 20 are n-type, while body well 16 and contact well 19 are p-type. The doping concentration of substrate 12 is 1×10 18 cm -3 ~1×10 21 cm -3 The thickness of the substrate 12 may be between 10 μm and 360 μm. The doping concentration of the drift layer 14 may be between 1×10 17 cm -3 ~5×10 13 cm -3The doping concentration of the drift layer 14 may be continuous along its thickness (from top to bottom as shown in FIG. 1) or may vary according to a doping profile that varies along its thickness. The thickness of the drift layer 14 may be between 2 μm and 200 μm. The doping concentration of the drift layer 14 may depend on the thickness of the drift layer 14. In particular, the doping concentration may be inversely proportional to the thickness of the drift layer 14. The body well 16 may have a doping concentration of 1×10 16 cm -3 ~3×10 19 cm -3 The body well 16 may have a thickness between 0.2 μm and 4 μm. The source well 18 may have a doping concentration between 1×10 18 cm -3 ~1×10 21 cm -3 The source well 18 may have a thickness between 0.1 μm and 2 μm. The JFET region 20 may have a doping concentration between 1×10 16 cm -3 ~2×10 17 cm -3 The JFET region 20 may have a doping concentration between 0.2 μm and 4 μm. Although the transistor 10 is described above as an n-type device, the principles of the present disclosure apply equally to p-type devices. In one embodiment, the transistor 10 is a silicon carbide (SiC) device. However, the principles of the present disclosure apply equally to any material system, particularly wide bandgap material systems. With respect to any of the doping concentration ranges or thickness ranges above, the present disclosure contemplates the use of any discrete point within that range or any subrange within a broader range. For example, the present disclosure contemplates the use of any discrete point within that range or any subrange within a broader range, with the doping concentration of the drift layer 14 being between 1×10 17 cm -3 ~5×10 13 cm -3 Between 1×10 17 cm -3 Or close to 5×10 13 cm -3 Or close to 1×10 16 cm -3 ~5×10 13 cm-3 Between 1×10 17 cm -3 ~1×10 15 cm -3 , or any other discrete point or subrange within the broader exemplary range. The same applies to all ranges of doping concentrations and thickness ranges set forth herein. The contact well 19 may have a thickness between 0.1 μm and 2 μm. The doping concentration of the contact well 19 may be between 1×10 16 cm -3 ~1×10 21 cm -3 The range may be between 0.01 and 0.1.

[0022] In one embodiment, the transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). In such an embodiment, the gate insulator 26 may be an oxide layer. In another embodiment, the transistor is a metal-insulator-semiconductor field-effect transistor (MISFET).

[0023] Transistor 10 may be a power device capable of blocking high voltages and conducting high currents. In particular, transistor 10 may have a breakdown voltage between 350 V and 20 kV, depending on the application. In accordance with this range of breakdown voltages, the on-state resistance of transistor 10 may be less than 0.3 mΩ cm. 2 ~100mΩ cm 2 That is, for a breakdown voltage of 350 V, the on-state resistance of transistor 10 may be between 0.3 mΩ cm 2 while for a breakdown voltage of 20 kV the on-state resistance of transistor 10 may be less than 100 mΩ cm 2 As another example, it can be less than 90 mΩ cm for a breakdown voltage of 15 kV. 2 On-state resistance of less than 70 mΩ cm for a breakdown voltage of 10 kV 2 On-state resistance of less than 10 mΩ cm and breakdown voltage of 3.3 kV 2The on-state resistance can vary between these minimum and maximum values ​​depending on the breakdown voltage.

[0024] As mentioned above, a transistor used for power switching applications should conduct current in both directions. While this can be accomplished with an external diode coupled anti-parallel between the source contact 22 and the drain contact 24 (anode to source, cathode to drain), the same result can also be achieved with an in-built body diode formed within the structure of the transistor 10. As shown in FIG. 1, a body diode 30 is formed between the source contact 22 and the drain contact 24 on the right side of the device. The body diode 30 is a PiN diode that includes the source contact 22 as the anode, the body well 16, the contact well 19, the drift layer 14, the substrate 12, and the drain contact 24 as the cathode. Using the body diode 30 to enable bidirectional current conduction saves space by eliminating the need for an external diode. However, the body diode 30 may not be optimized for switching. In particular, the body diode 30 may suffer from a high degree of snappiness, which can increase switching times and switching losses, as discussed in more detail below.

[0025] The snappiness of a diode characterizes its reverse recovery. To illustrate, FIG. 2 is a graph showing the forward current and voltage across a diode when switching from forward conduction to reverse bias or blocking. Before time t0, the diode is forward biased, thus conducting current from the anode to the cathode. Hence, the voltage across the diode is about zero. When forward biased, excess minority carriers are injected into the drift region of the diode so that the drift region contains excess minority carriers. At time t0, the diode is switched from forward bias to reverse bias by changing the voltages supplied at its anode and cathode. Thus, the current through the diode begins to decrease as the excess minority carriers decrease. Due to the current flow due to the excess minority carriers, the voltage across the diode remains the same. At time t1, the current through the diode switches from a positive current to a negative current. The voltage across the diode continues to remain the same. As the accumulated excess minority carriers in the drift region begin to decrease, the resistance of the region begins to increase. Thus, at time t2, the voltage across the diode begins to drop while the current continues to decrease. At this point a depletion region begins to form. At time t3, the reverse current through the diode reaches its maximum value as there are few excess minority carriers left in the drift region. At time t4, the negative voltage across the diode reaches its peak value. The current through the diode and the voltage across the diode continue to increase until time t5 when they stabilize at zero and reverse voltage, respectively.

[0026] During the reverse recovery process, the capacitance across the diode is determined by the diffusion capacitance and depletion capacitance due to the diffusion and depletion regions in the diode, respectively. As the depletion region grows, the value of the diffusion capacitance and the value of the depletion capacitance change. If the depletion region punches through the diode such that the diffusion region is no longer present, the diffusion capacitance suddenly becomes zero, causing a large change in the overall capacitance of the diode, which can cause ringing and distortion.

[0027] The time between when the current through the diode passes zero (t1) and reaches its negative peak value (t3) is t s The current through the diode decreases from 0.2 I RRM (t 5 ) is the time it takes for the f It is shown as t f and s Ratio to (t f / t s ) is defined herein as the diode softness factor S1. The softness factor is inversely related to the diode snappiness; therefore, a higher softness factor is desirable. A secondary softness factor S2 is defined herein as the diode softness factor S1.

number

[0028] Traditionally, those skilled in the art design transistors based on some desired characteristics of the transistor itself, such as breakdown voltage and on-state resistance. In other words, those skilled in the art do not generally design transistors with the performance of the body diode in mind. The inventors of the present disclosure have discovered that one or more characteristics of the body diode of a transistor can be significantly improved with little or minimal impact on the performance of the transistor. In particular, the snappiness of the body diode in a transistor can be significantly reduced while maintaining the performance of the transistor.

[0029] To improve the snappiness of the body diode 30 in the transistor 10, several adjustments are made. First, the transistor 10 is designed such that the body diode 30 is a non-punch-through diode. As discussed herein, a non-punch-through diode is defined as a diode in which the depletion region formed in the drift layer of the diode does not penetrate into the substrate or adjacent n+ layer at the breakdown voltage of the diode. In the case of the body diode 30, this means that at its breakdown voltage, the depletion region remains within the drift layer 14 and does not penetrate into the substrate 12. The body diode 30 can be designed to be non-punch-through by varying the doping concentration and / or thickness of the drift layer 14 compared to conventional designs where these parameters are optimized for the desired breakdown voltage and on-state resistance of the transistor 10. In particular, the thickness and doping concentration of the drift layer 14 can be increased compared to conventional designs to ensure that the depletion region of the body diode 30 remains within the drift layer 14 when reverse biased. Thus, for a given breakdown voltage of transistor 10, drift layer 14 is thicker and more heavily doped than its conventional counterpart.

[0030] To provide a non-punch-through diode, the thickness and doping concentration of the drift layer 14 may be determined using the following equation: diode and doping concentration N D Equation (2) shows the relationship between the maximum width of the depletion region, W d,max and doping concentration N D This shows the relationship between:

number

[0031] 3A and 3B show the electric field in the drift layer 14 for a punch-through diode and a non-punch-through diode, respectively. In particular, FIG. 3A shows lines showing the electric field in the drift layer 14 of a punch-through diode as described herein, and FIG. 3B shows lines showing the electric field in the drift layer 14 of a non-punch-through diode. As shown, for a non-punch-through diode, the electric field drops to zero before reaching the interface between the drift layer 14 and the substrate 12. For a punch-through diode, the electric field remains at a significant level at the interface between the drift layer 14 and the substrate 12, and thus "punches through" the drift layer 14. As discussed herein, the transistor 10 can be designed to provide the body diode 30 as a non-punch-through diode, which may improve the snappiness of the body diode 30. As discussed herein, one way to achieve a non-punch-through body diode 30 is to increase the thickness of the drift layer 14, which is why the drift layer 14 is thicker in Figure 3B than in Figure 3A, however, other design considerations also apply.

[0032] Applying conventional design rules to the transistor 10 would dictate the selection of the thickness and doping concentration of the drift layer 14 to minimize the on-state resistance for a given breakdown voltage. This could result in optimizing these features, but could result in the body diode 30 being a punch-through diode. The inventors of the present disclosure have discovered that the thickness and doping concentration of the drift layer 14 can be selected such that the body diode 30 is a non-punch-through diode while still maintaining a desirable, but perhaps slightly higher, on-state resistance of the transistor 10 at a given breakdown voltage. Providing the body diode 30 as a non-punch-through diode allows carriers to remain in the drift layer 14 longer because they are not swept away as quickly at the interface with the substrate 12 due to the reduced electric field in this area. Additionally, providing the body diode 30 as a non-punch-through diode reduces ringing and distortion that would otherwise result from large changes in the diffusion capacitance of the body diode 30 during reverse recovery, by preventing the diffusion capacitance from going abruptly to zero.

[0033] In addition to or independent of providing the body diode 30 as a non-punch-through diode, the minority carrier distribution profile within the body diode 30 during forward bias is also modified. Thus, FIG. 4 shows a cross-section of the body diode 30 isolated from the transistor 10. The dashed line shows the minority carrier distribution during forward bias when the body diode 30 is provided in a conventional manner without the improvements discussed herein. The solid line shows the minority carrier distribution during forward bias for the body diode 30 when the improvements discussed herein are made. As shown, without the improvements discussed herein, the concentration of minority carriers is higher at the interface between the body well 16 and the drift layer 14 than at the interface between the drift layer 14 and the substrate 12. This can cause a degradation in the reverse recovery performance of the diode. In particular, as the body diode 30 enters reverse bias, if there is a high concentration of minority carriers at the interface between the body well 16 and the drift layer 14, as shown by the dashed line, it takes longer to sweep these minority carriers away and a depletion region begins to form, as shown in FIG. s is extended, which increases the snappiness (softness factor t f / t s 1) and performance degradation. Furthermore, as the depletion region grows, if there is a relatively low concentration of minority carriers at the interface between the drift layer 14 and the substrate 12, as also shown by the dashed line, these carriers may be swept out of the drift layer 14, thus causing the depletion region to tunnel through the substrate 12. As mentioned above, this also degrades performance due to the abrupt disappearance of the diffusion capacitance in the body diode 30. Furthermore, as shown in FIG. 2, an increase in the concentration of minority carriers near the interface between the drift layer 14 and the substrate 12 may result in a decrease in t f This reduces the snappiness (softness factor t f / t s(increases). Thus, as shown by the solid lines, it is desirable to have a lower concentration of minority carriers at the interface between the body well 16 and the drift layer 14, and a higher concentration of minority carriers at the interface between the drift layer 14 and the substrate 12. In general, it is desirable to have a positive gradient (on average) of minority carrier concentration in the drift layer 14 between the body well 16 and the substrate 12.

[0034] There are several ways to achieve the desired minority carrier profile described above. In one embodiment, the carrier lifetime of the drift layer 14 is enhanced to increase the concentration of minority carriers at and near the interface between the drift layer 14 and the substrate 12. In SiC, carbon vacancies can reduce carrier lifetime by forming recombination centers for minority carriers. To reduce carbon vacancies, high temperature oxidation of the drift layer 14 is performed, as discussed in detail below, thereby increasing carrier lifetime throughout the drift layer 14. In various embodiments, the minority carrier lifetime in the drift layer 14 can be intentionally enhanced to be between 0.5 μs and 20 μs. In particular, the present disclosure contemplates the use of any discrete value within the exemplary range of minority carrier lifetimes given above, or within any subrange within the broader range. For example, in various embodiments, the minority carrier lifetime of drift layer 14 can be between 1 μs and 20 μs, between 10 μs and 20 μs, between 1 μs and 5 μs, between 5 μs and 10 μs, between 15 μs and 20 μs, between 3 μs and 10 μs, or any other subrange or discrete point within the broader exemplary range. 1 / 2 It will be appreciated that trap density is inversely related to carrier lifetime in SiC. Thus, increasing the carrier lifetime in the drift layer 14 increases the Z 1 / 2 In various embodiments, this may involve reducing the trap density of the drift layer 14. 1 / 2 The trap density is 5×10 13 cm -3 Less than 1×10 13 cm -3 Less than 5×10 12 cm -3 Less than 1×1012 cm -3 Less than or equal to 1 x 10 10 cm -3 can be reduced to be as low as

[0035] In addition to improving the carrier lifetime in the drift layer 14, it is also desirable to reduce minority carriers at the interface between the body well 16 and the drift layer 14. This can be accomplished by reducing the doping concentration of the body well 16 so that fewer minority carriers are injected from the body well 16 into the drift layer 14 under forward bias. In various embodiments, the doping concentration of the body well 16 near the interface between the body well 16 and the drift layer 14 is less than 1×10 16 cm -3 ~3×10 19 cm -3 , which can be anywhere from about 5 to 15 times lower than conventional doping concentrations. More specifically, the doping concentration of the body well 16 within 0.2 μm of the interface between the body well 16 and the drift layer 14 is between 1×10 16 cm -3 ~3×10 19 cm -3 Among other things, the present disclosure contemplates that the doping concentration of the body well 16 may be any discrete value within the given exemplary range of doping concentrations, or any subrange within the exemplary range.

[0036] In addition to or in lieu of reducing the doping concentration of the body well 16, a recombination region 32 may be provided in the drift region 14 at or near the interface between the body well 16 and the drift layer 14, as shown in FIG. 5A. The recombination region 32 is a region that has a higher density of minority carrier recombination centers than the surrounding drift layer 14. This may be accomplished by intentionally damaging the recombination region 32 via an implantation process or by doping the recombination region 32. In one embodiment, the recombination region is implanted with argon to increase the density of minority carrier recombination centers in the recombination region. However, other implants such as hydrogen and helium may also be used in some embodiments. The density of minority carriers in the recombination region 32 may be between 5-10 times higher than in the drift layer 14. In various embodiments, the density of minority carrier recombination centers in the recombination region 32 is between 1×10 13 cm -3 ~1×10 18 cm -3 In particular, the density of minority carrier recombination centers in the recombination region 32 can be any discrete point within this range, or any subrange within this range. For example, the density of minority carrier recombination centers in the recombination region 32 can be between 1×10 14 cm -3 ~1×10 18 cm -3 Between 1×10 15 cm -3 ~1×10 18 cm -3 Between 1×10 16 cm -3 ~1×10 18 cm -3 Between 1×10 17 cm -3 ~1×10 18 cm -3 Between 1×10 14 cm -3 ~1×10 17 cm -3 Between 1×10 14 cm -3 ~1×10 16 cm -3 Between 1×1014 cm -3 ~1×10 15 cm -3 Between 1×10 15 cm -3 ~1×10 17 cm -3 Between and 1×10 17 cm -3 ~1×10 18 cm -3 or any discrete point within any of these ranges. Although recombination region 32 is shown as a localized region of body diode 30 at or near the interface between body well 16 and drift layer 14, recombination region 32 may be a blanket region throughout transistor 10 or may include multiple regions that are separated from one another. The density of minority carrier recombination centers in recombination region 32 may be between 6-7 times greater than drift layer 14, between 7-8 times greater than drift layer 14, between 8-9 times greater than drift layer 14, between 5-9 times greater than drift layer 14, between 6-9 times greater than drift layer 14, or any other subrange or discrete point within the broader exemplary range.

[0037] The thickness of the body well 16 is T bw In various embodiments, T bw can be between 0.1 μm and 2.0 μm. bw may be any subrange within the larger range of 0.1 μm to 2.0 μm. For example, T bwbetween 0.25μm and .5μm, between 0.25μm and .75μm, between 0.25μm and 1.0μm, between 0.25μm and 1.25μm, between 0.25μm and 1.5μm, between 0.25μm and 1.75μm, between 0.5μm and .75μm, between 0.5μm and 1.0μm, between 0.5μm and 1.25μm, between 0.5μm and 1.5μm, between 0.5μm and 1.75μm, between 0.5μm and 2.0μm, between .75μm and 1.0μm, between 0.75μm and 1.25μm The width of the body well 16 may be between W, between 0.75 μm and 1.5 μm, between 0.75 μm and 1.75 μm, between 0.75 μm and 2.0 μm, between 1.0 μm and 1.25 μm, between 1.0 μm and 1.5 μm, between 1.0 μm and 1.75 μm, between 1.0 μm and 2.0 μm, between 1.25 μm and 1.5 μm, between 1.25 μm and 1.75 μm, between 1.25 μm and 2.0 μm, between 1.5 μm and 1.75 μm, between 1.5 μm and 2.0 μm, and between 1.75 μm and 2.0 μm. bw In various embodiments, the width of the body well 16 can be between 1 μm and 10 μm. bw may be any subrange within the larger range of 1 μm to 10 μm. For example, W bw is between 1μm~2μm, 1μm~3μm, 1μm~4μm, 1μm~5μm, 1μm~6μm, 1μm~7μm, 1μm~8μm, 1μm~9μm, 1μm~10μm, 2μm~3μm, 2μm ~4μm, 2μm~5μm, 2μm~6μm, 2μm~7μm, 2μm~8μm, 2μm~9μm, 2μm~10μm, 3μm~4μm, 3μm~5μm, 3μm~6μm, 3μm~7μm, 3μm The doping concentration of the body well 16 may be 1×10 to 8 μm, 3 μm to 9 μm, 3 μm to 10 μm, 4 μm to 5 μm, 4 μm to 6 μm, 4 μm to 7 μm, 4 μm to 8 μm, 4 μm to 9 μm, 4 μm to 10 μm, 5 μm to 6 μm, 5 μm to 7 μm, 5 μm to 8 μm, 5 μm to 9 μm, 5 μm to 10 μm, 6 μm to 7 μm, 6 μm to 8 μm, 7 μm to 9 μm, 7 μm to 10 μm, 8 μm to 9 μm, 8 μm to 10 μm, and 9 μm to 10 μm. 16 cm -3 ~3×10 19 cm -3or any subrange of this larger range. In various embodiments, the doping concentration of the body well 16 is between 5×10 16 cm -3 ~3×10 19 cm -3 Between 1×10 17 cm -3 ~3×10 19 cm -3 Between 5×10 17 cm -3 ~3×10 19 cm -3 Between 1×10 18 cm -3 ~3×10 19 cm -3 Between 5×10 18 cm -3 ~3×10 19 cm -3 Between 1×10 16 cm -3 ~1×10 19 cm -3 Between 1×10 16 cm -3 ~5×10 18 cm -3 Between 1×10 16 cm -3 ~1×10 18 cm -3 Between 1×10 16 cm -3 ~5×10 17 cm -3 Between 1×10 16 cm -3 ~1×10 17 cm -3 Between 1×10 16 cm -3 ~5×10 16 cm -3 Between 5×10 16 cm -3 ~1×10 19 cm -3 Between 1×10 17 cm -3 ~5×10 18 cm -3 Between and 5×10 17 ~1×10 18 cm -3In some embodiments, the doping profile of the body well 16 may be between its thickness T bw In another embodiment, the doping concentration of the body well 16 remains relatively constant along its thickness T bw For example, the doping profile of the body well 16 can be linear (increasing from top to bottom or bottom to top), triangular (increasing and then decreasing from top to bottom), stepped (increasing or decreasing along a curve from top to bottom), or any other doping profile. In one embodiment, the doping profile of the body well 16 decreases in proportion to the distance from the surface of the drift layer 14 such that injection of minority carriers from the body well 16 is reduced at the junction between the body well 16 and the drift layer 14.

[0038] The thickness of the recombination region 32 is T rr In various embodiments, T rr can be between 1 nm up to the maximum thickness of the drift layer 14, which can be as thick as 200 μm. rr can be between any subrange within the larger range of 1 nm to 200 μm. For example, T rr The width W of the recombination region 32 may be between 1 nm and 100 nm, between 1 nm and 1 μm, between 1 nm and 5 μm, between 1 nm and 10 μm, between 10 nm and 1 μm, between 10 nm and 5 μm, between 10 nm and 10 μm, between 100 nm and 1 μm, between 100 nm and 5 μm, between 100 nm and 10 μm, between 1 μm and 5 μm, between 1 μm and 10 μm, between 5 μm and 10 μm, between 5 μm and 50 μm, between 10 μm and 50 μm, between 10 μm and 100 μm, or any other subrange within the larger range of 1 nm to 200 μm. rr can be between 0.25 μm and as large as the width of the active area of ​​transistor 10, which can be up to 15 mm. rr can be any subrange within the larger range of 0.25 μm to 15 mm. For example, W rrmay be between 0.25 μm and 0.5 μm, between 0.25 μm and 0.75 μm, between 0.25 μm and 1.0 μm, between 0.25 μm and 1.25 μm, between 0.25 μm and 1.5 μm, between 0.25 μm and 1.75 μm, between 0.25 μm and 2.0 μm, between 0.25 μm and 2.5 μm, between 0.25 μm and 2.5 μm, between 0.5 μm and 1.0 μm, between 0.5 μm and 2.0 μm, between 1.0 μm and 2.0 μm, between 1.0 μm and 5.0 μm, between 2.0 μm and 5.0 μm, between 2.0 μm and 10 μm, between 5.0 μm and 10 μm, or any other subrange of a larger range. rr The recombination region 32 may be at least as wide as the contact region 19. As mentioned above, the recombination region 32 may be provided in a localized area beneath the body well 16, or beneath a portion of the body well 16, e.g., in the area shown as the body diode 30, or may extend across a larger portion of the drift layer 14, such as beneath all or a portion of the JFET region 20 and / or any other regions not shown, such as the entire active area. In some embodiments, the density of minority carrier recombination centers in the recombination region 32 is approximately equal to its thickness T rr In other embodiments, the density of minority carrier recombination centers in recombination region 32 can remain relatively constant along its thickness T rr The desired profile may vary along the length, be it linear, triangular, stepped, etc.

[0039] The recombination region 32 can be located in the drift layer 14 directly below the body well 16, as shown in FIG. 5B, or can overlap all or part of the thickness of the body well 16. Additionally, the recombination region 32 can extend along only a portion of the width of the body well 16, as shown in FIG. 5C. In some embodiments, the recombination region 32 may encapsulate the bottom corner or the entire body well 16, as shown in FIG. 5D. Finally, the recombination region 32 may be provided along the entire thickness of the drift layer 14 in any portion of the drift layer below the body well 16, as shown in FIG. 5E. In short, the recombination region 32 can be provided in all or part of the area near the body well 16 to form a desired minority carrier profile and thus to enhance the softness of the body diode 30. The recombination region 32 can reduce minority carrier injection into the drift layer 14 by providing a recombination center for minority carriers below the body well 16. This increases the carrier lifetime in the drift layer 14 and therefore may further enhance the softness of the body diode 30.

[0040] FIG. 6 is a graph showing possible injection profiles for the body well 16 and the recombination region 32 according to various embodiments of the present disclosure. On the left side of the graph, four different doping profiles for the body well 16 are shown. The first solid line represents a conventional doping profile for the body well 16. As mentioned above, this can result in undesirably high levels of minority carrier injection into the drift layer 14. Therefore, below this first solid line, three lines shown as dashed, dotted, and dashed dots represent doping profiles for the body well 16 according to various embodiments of the present disclosure. As shown, each of the doping profiles peaks at approximately the same level, but with reduced doping concentrations near the bottom of the body well 16, where the interface between the body well 16 and the drift layer 14 is located. In the center of the graph, three lines are shown showing various doping profiles for the recombination region 32. In particular, the solid lines represent a doping profile with a doping concentration of 1×10 13 cm -3 The dashed line indicates the recombination region 32 resulting from an argon injection dose of 5×10 13 cm -3 The dotted line shows the recombination region 32 resulting from an argon injection dose of 2.5×10 14 cm -3 6 shows a recombination region 32 resulting from an implantation dose of argon of 1000 nm. As shown, the recombination region 32 overlaps the body well 16 and may peak at the interface between the body well 16 and the drift layer 14. Notably, the doping profile for the body well 16 and recombination region 32 shown in FIG. 6 is merely exemplary. Those skilled in the art will readily appreciate that there are a variety of ways to provide the body well 16 and recombination region 32 to achieve the above-mentioned objectives, all of which are contemplated herein.

[0041] Providing the body diode 30 as a non-punch-through diode and / or redistributing the minority carriers in the drift layer 14 as described above may enable the body diode 30 to provide a softness factor S1 of greater than 0.5. In various embodiments, the improvements to the body diode 30 described above, alone or in combination, may enable the body diode 30 to provide a softness factor S1 of greater than 0.6, greater than 0.7, greater than 0.8, greater than 0.9, greater than 1.0, greater than 1.1, greater than 1.2, greater than 1.3, greater than 1.4, greater than 1.5, greater than 2.0, greater than 2.5, greater than 3.0, greater than 3.5, greater than 4.0, greater than 4.5, greater than 5.0, greater than 5.5, greater than 6.0, greater than 6.5, greater than 7.0, greater than 7.5, greater than 8.0, greater than 8.5, greater than 9.0, greater than 9.5, or up to 10. More generally, this disclosure contemplates the softness factor S1 of the body diode 30 at any discrete point between 0.5 and 10, or any subrange therebetween.

[0042] Similarly, improvements to the body diode 30 may result in a secondary softness factor S2 of greater than 0.5. In various embodiments, the improvements to the body diode 30 described above, alone or in combination, may enable the body diode 30 to provide a secondary softness factor S2 of greater than 0.6, greater than 0.7, greater than 0.8, greater than 0.9, greater than 1.0, greater than 1.1, greater than 1.2, greater than 1.3, greater than 1.4, greater than 1.5, greater than 2.0, greater than 2.5, greater than 3.0, greater than 3.5, greater than 4.0, greater than 4.5, greater than 5.0, greater than 5.5, greater than 6.0, greater than 6.5, greater than 7.0, greater than 7.5, greater than 8.0, greater than 8.5, greater than 9.0, greater than 9.5, up to 10. More generally, this disclosure contemplates the quadratic softness factor S2 of the body diode 30 at any discrete point between 0.5 and 10, or any subrange therebetween.

[0043] FIG. 7 is a flow diagram illustrating a method of fabricating a transistor according to one embodiment of the present disclosure. First, a substrate is provided (step 100). A drift layer is provided on the substrate (step 102). As discussed above, the thickness and doping concentration of the drift layer are selected to provide a body diode in the completed transistor as a non-punch through diode. In particular, the thickness of the drift layer and / or the doping concentration of the drift layer are increased relative to conventional designs for a given breakdown voltage to provide the body diode as a non-punch through diode. A carrier lifetime enhancement process is performed in the drift layer (step 104). In one embodiment, the carrier lifetime enhancement process is a high temperature oxidation of the drift layer. In particular, the drift layer may be oxidized at a temperature between 1300° C. and 1500° C. for a time period between 30 minutes and 5 hours to reduce carbon vacancies that may otherwise shorten minority carrier lifetime in the drift layer. Notably, the present disclosure is not limited to a particular carrier lifetime enhancement process, but contemplates any currently existing method of enhancing carrier lifetime.

[0044] A recombination region is provided in the drift layer (step 106). In one embodiment, providing the recombination region includes damaging a region of the drift layer by ion implantation. In another embodiment, providing the recombination region includes implanting argon into the region of the drift layer. The recombination region may be provided as a blanket region or may be localized to a specific region in the drift layer. Generally, the recombination region is provided to be localized to a specific depth in the drift layer to provide increased recombination centers near the interface between the body well and the drift layer. A junction implant is provided in the drift layer on a surface opposite the substrate (step 108), the junction implant including a body well and a source well. Notably, the body well is provided with a doping concentration less than that determined by a conventional design process near the interface between the body well and the drift layer. A source well is provided in the body well at the surface of the drift layer. A contact well is also provided in the body well adjacent to the source well. Both the source well and the body well may be provided by an ion implantation process. A JFET region may also be provided in some embodiments. The JFET region is an area of ​​increased carrier concentration adjacent to the body well, and may also be provided by an ion implantation process.

[0045] Finally, a source contact, a drain contact, a gate insulator, and a gate contact are provided (step 110). The source contact is provided on the surface of the drift layer opposite the substrate and is in electrical contact with the source well and the body well through the contact well. The drain contact is provided on the surface of the substrate opposite the drift layer and is in electrical contact with the substrate. A gate oxide is provided on the surface of the drift layer opposite the substrate over the JFET region, a portion of the body well, and a portion of the source well. A gate contact is provided to the gate oxide.

[0046] FIG. 8 is a graph comparing the reverse recovery of a conventional body diode in a transistor with a body diode including the improvements discussed herein to reduce snappiness. In particular, the solid lines show the current through and voltage across a body diode including the improvements discussed herein (each of which is noted on the graph), while the dashed lines show the current through and voltage across a body diode in a conventional transistor. As shown, the improved body diode takes less time to reach its maximum reverse recovery current, and the maximum reverse recovery current is significantly less than for the conventional body diode. The improved body diode also exhibits an extended time between the maximum reverse recovery current and 0.2 times the maximum reverse recovery time compared to the conventional body diode, and the slope of the current is shallower than for the conventional diode as the current increases between these values. The current through the improved body diode also exhibits significantly less ringing than the conventional body diode. All of the above is taken into account in the softness factor S1 (t as discussed above) of the improved body diode. s / t f ) is significantly improved in the improved body diode. Additionally, the quadratic softness factor S2 is also improved in relation to the slope of the reverse recovery current, and the total area between the x-axis and the reverse recovery current curve is reduced. In essence, the improved body diode is significantly less snappy than the conventional body diode. As mentioned above, the reduced snappiness means that the improved body diode can switch faster and with less switching losses than the conventional body diode.

[0047] As discussed above, the doping concentration of the drift layer 14 may be continuous along its thickness (from top to bottom as shown in FIG. 1 ) or may vary according to a doping profile that varies along its thickness. Additionally, in some embodiments, the drift layer 14 may include multiple different layers, each having a different doping concentration and / or doping profile. In other embodiments, the transistor 10 may include a buffer layer, which is a layer having a specific doping profile in the drift layer 14. The buffer layer may be located between the drift layer 14 and the substrate 12 in some embodiments. Providing multiple drift layers and / or buffer layers may increase the ruggedness of the transistor, particularly by lowering its second breakdown voltage, and may further be used to design the body diode 30 to be a non-punch-through diode or to change the distribution of minority carriers in the body diode 30 to reduce snappiness as discussed above.

[0048] FIG. 9 illustrates a simplified version of a transistor 10 according to one embodiment of the present disclosure. The transistor 10 includes a substrate 12, a buffer layer 34 on the substrate 12, and a drift layer 14 on the buffer layer 34. The graph illustrates the relative doping concentrations of the substrate 12, the buffer layer 34, and the drift layer 14. As shown, the substrate 12 is more highly doped than the buffer layer 34, which is also more highly doped than the drift layer 14. Notably, the substrate 12, the buffer layer 34, and the drift layer 14 are all doped in a relatively uniform manner, thus forming a step doping profile as shown. Providing the buffer layer 34 with a doping concentration higher than the drift layer 14 but lower than the substrate 12 provides a buffer for charged particles that may be accelerated by collision with radiation particles, allowing these accelerated charged particles to recombine rather than passing through the transistor 10. This may increase the ruggedness of the transistor 10, and further, such a tailored doping profile may be used to configure a desired profile of minority carriers in the device to reduce the snappiness of the body diode 30 and thus enhance its performance.

[0049] In particular, the thicknesses and doping concentrations of the substrate 12, buffer layer 34, and drift layer 14 are merely exemplary. In particular, these thicknesses and doping concentrations are shown for a device rated at 1200V. Those skilled in the art will readily appreciate that higher blocking voltages may dictate thicker thicknesses for the drift layer 14, and in some embodiments, the buffer layer 34, and / or reduced doping concentrations for these layers. However, the relationship between the thicknesses and doping concentrations of these layers remains relatively unchanged. In one embodiment, the thickness of the buffer layer 34 may be between 5% and 35% of the thickness of the drift layer 14. In certain embodiments, the thickness of the buffer layer 34 may be between 5% and 10% of the thickness of the drift layer 14, between 10% and 15% of the thickness of the drift layer 14, between 15% and 20% of the thickness of the drift layer 14, between 20% and 25% of the thickness of the drift layer 14, between 25% and 30% of the thickness of the drift layer 14, between 30% and 35% of the thickness of the drift layer 14, between 15% and 25% of the thickness of the drift layer 14, between 25% and 35% of the thickness of the drift layer 14. Furthermore, the doping concentration of the buffer layer 34 may vary between 20% and 90% of the doping concentration of the substrate 12 while remaining at least 20% greater than the doping concentration of the drift layer 14. In certain embodiments, the doping concentration of buffer layer 34 may be between 20% and 30% of the doping concentration of substrate 12, between 30% and 40% of the doping concentration of substrate 12, between 40% and 50% of the doping concentration of substrate 12, between 50% and 60% of the doping concentration of substrate 12, between 60% and 70% of the doping concentration of substrate 12, between 70% and 80% of the doping concentration of substrate 12, or between 80% and 90% of the doping concentration of substrate 12.

[0050] In one embodiment, the substrate 12, the buffer layer 34, and the drift layer 14 are silicon carbide (SiC). Thus, the buffer layer 34 may be an epitaxial layer grown on the substrate 12 before the drift layer 14. The drift layer 14 may then be grown on the buffer layer 34. The buffer layer 34 may be grown in an environment using dopants to provide the desired doping concentration, or may be grown and then implanted (e.g., via ion implantation) to the desired doping concentration. In another embodiment, the buffer layer 34 may be an implanted region at the surface of the substrate 12. Since the substrate 12 is doped more highly than the desired doping level for the buffer layer 34, it may be doped with the opposite doping type to reduce its net doping concentration (e.g., if the substrate 12 is an n-type substrate, it may be doped with a p-dopant). Notably, the principles of the present disclosure apply equally to n-type or p-type substrates, buffer layers, and drift layers. That is, the principles of the present disclosure may be applied to n-type and p-type devices alike.

[0051] FIG. 10 shows a simplified version of a transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in FIG. 10 is substantially similar to that shown in FIG. 9, except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 34 exhibits a linearly graded doping concentration that decreases in proportion to the distance from the drift layer 14 such that the overall doping profile of the device includes a step between the drift layer 14 and the buffer layer 34 and another step between the buffer layer 34 and the substrate 12. In this embodiment, the buffer layer 34 may be thicker to allow for a linear transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 34 and then ion implanting the buffer layer, or by growing the buffer layer 34 in an environment where the concentration of the dopant is controlled throughout the growth process. Notably, this doping profile is merely exemplary and any linearly graded doping concentration may be substituted for that shown in FIG. 10 without departing from the principles of the present disclosure.

[0052] FIG. 11 shows a simplified version of a transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in FIG. 11 is substantially similar to that shown in FIG. 9, except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 34 provides a substantially smooth transition between the doping concentration of the drift layer 14 and the doping concentration of the substrate 12. In this embodiment, the buffer layer 34 may be substantially thicker to allow for a transition in its doping profile. Such a doping profile may be formed by first growing the buffer layer 34 and then ion implanting the buffer layer, or by growing the buffer layer 34 in an environment in which the concentration of the dopant is controlled throughout the growth process. Notably, this doping profile is merely exemplary and any graded doping concentration, linear or otherwise, may be substituted for that shown in FIG. 11 without departing from the principles of the present disclosure.

[0053] FIG. 12 shows a simplified version of a transistor 10 according to a further embodiment of the present disclosure. The transistor 10 shown in FIG. 12 is substantially similar to that shown in FIG. 9, except for the doping profile of the device and the relative thicknesses of the layers. In particular, the buffer layer 34 is provided as a doping "spike" and is not directly on the substrate 12. In this embodiment, the buffer layer 34 may be reduced in thickness. Such a doping profile may be formed via separate growth on a small portion of the drift layer 14, or by growing a small portion of the drift layer 14, performing ion implantation to create the buffer layer 34, and then growing the remainder of the drift layer 14. Notably, this doping profile is merely exemplary, and any "spike" doping profile may be substituted for that shown in FIG. 12 without departing from the principles of the present disclosure.

[0054] As shown in FIG. 13A, in certain cases, a relatively thin but more highly doped diffusion layer 36 is provided above the drift layer 14 to aid in current spreading before reaching the more lightly doped drift layer 14. Thus, a typical SiC or other wide bandgap transistor 10 may have a thin more highly doped top region as the diffusion layer 36, a thicker more lightly doped drift layer 14, and a relatively thin substrate 12, which is shown thin in FIG. 13A to save space. FIG. 13B is a graph of the electric field in a vertical semiconductor versus distance from the top of the transistor 10. In avalanching, the electric field is highest at the top surface of the diffusion layer 36 and drops off in strength throughout the diffusion layer 36 and the drift layer 14, but at different rates. Notably, the electric field remains at a significant level at the interface between the drift layer 14 and the substrate 12 (i.e., the top surface of the substrate 12). Thus, as shown in FIG. 13B, the electric field effectively punches through (PT) the entire drift layer 14. Figure 13C shows that this type of punch-through can occur well before avalanche breakdown, and that second breakdown can occur at voltages lower than avalanche for such a structure. In particular, Figure 13C is a graph of the electric field at the bottom of drift layer 14 and the drain-source current (lds) as the drain-source voltage (Vds) increases in blocking mode for a FET or diode configuration of transistor 10. The punch-through voltage V(PT) is observed, as well as the voltages of second breakdown and avalanche breakdown.

[0055] To avoid or reduce the punch-through of the electric field to the substrate, a buffer layer 34 may be used in conjunction with the diffusion layer 36 as shown in FIG. 14A. The doping concentration of the buffer layer 34 may be between the doping concentration of the drift layer 20 and the doping concentration of the substrate 12. The inclusion of the buffer layer 34 moves the electric field away from the top surface of the substrate 12, increasing the second breakdown voltage. For the exemplary embodiment, as shown in FIG. 14B, the electric field at the avalanche voltage punches through the drift layer 14 but is stopped at the buffer layer 34 and therefore does not punch through to the substrate 12. The inclusion of the buffer layer 34 increases the second breakdown voltage, which increases the durability in high electric field bipolar conditions and moves the electric field away from the substrate 12. By moving the electric field away from the substrate, the effect of the movement of basal plane dislocations from the substrate 12 to the drift layer 14 is minimized. 14C shows the electric field at the bottom of the drift layer 14 and the drain-source current (lds) as the drain-source voltage (Vds) increases in blocking mode for the diode-configured FET of transistor 10. With the buffer layer 34, the avalanche (Vaval) and punch-through voltage V(PT) remain unchanged, but the voltage of the second breakdown is significantly increased. Furthermore, for the reasons discussed above, the buffer layer 34 may increase the softness of the body diode 30, since it may prevent the electric field from punching through.

[0056] For a particular embodiment, the diffusion layer 36 generally has a doping level of 1×10 16 cm -3 ~1×10 17 cm -3 and thickness between 1 μm and 4 μm. The doping for the drift layer 14 depends on the voltage rating of the device, and ranges from 1×10 13 ~1×10 17 cm -3 The doping range of the buffer layer 34 may vary from 1×10 to 2×100, and the thickness may range from 2 μm to 300 μm. The buffer layer 34 is generally less doped than the substrate 12, often less than 1×10 18 cm -3The buffer layer 34 is doped at or above 1×10, depending on the doping, and high enough not to be significantly depleted in blocking. 17 cm -3 ~5×10 18 cm -3 and may range from 0.5 μm to 5 μm thick. The thickness of the substrate 12 may range from 50 to 500 μm. The concept associated with the embodiment of FIG. 14A adds little resistance to the structure, but potentially aids in ruggedness performance and snappiness of the body diode 30.

[0057] Alternative doping concentration ranges for the embodiment of FIG. 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; 1×10 for drift layer 14 13 ~1×10 17 cm -3 ; 5×10 for the buffer layer 34 16 ~5×10 18 cm -3 and 5x10 for board 12 17 ~1×10 20 cm -3 Includes.

[0058] 15A, multiple drift layers are provided in the transistor 10, referred to as an upper first drift layer 14A and a lower second drift layer 14B. The buffer layer 34 is not included. The first drift layer 14A is between the diffusion layer 36 and the second drift layer 14B. The second drift layer 14B is between the first drift layer 14A and the substrate 12.

[0059] The lower second drift layer 14B may have a slightly higher doping level than the upper first drift layer 14A to thicken the drift according to the previous embodiment. Additionally, the first drift layer 14A may be thinner than the drift layer 14 of the embodiment in FIG. 14A while having a slightly higher doping level to keep the overall drift resistance low. These changes increase both the punch through voltage (V(PT)) and the second breakdown voltage compared to the previous embodiment.

[0060] In certain embodiments, the second drift layer 14B may have a doping level that is 1-3 times the doping level of the first drift layer 14A while being any thickness close to or less than the thickness of the first drift layer 14A. This embodiment provides increased durability by not providing a high electric field that penetrates the substrate 12. In selected embodiments, the first drift layer 14A and the second drift layer 14B of the transistor 10 may be designed to prevent any electric field from penetrating through the second drift layer 14B to the substrate 12, as shown in FIG. 15B. FIG. 15B shows the electric field in the transistor 10 at the avalanche voltage. Notably, the electric field is stopped just before the substrate 12 in the second drift layer 14B.

[0061] 15C shows the electric field at the bottom of the second drift layer 14B and the drain-source current (lds) as the drain-source voltage (Vds) is increased in blocking mode for the FET or diode configuration of transistor 10. By adding the bottom second drift layer 14B, the avalanche voltage (Vaval) can remain constant while both the punch-through voltage V(PT) and the second breakdown voltage are increased above the avalanche voltage (Vaval).

[0062] The use of multiple drift layers, such as the first drift layer 14A and the second drift layer 14B, can aid in overall device durability under high electric field, high current, and fast switching conditions. Snappiness in switching is reduced and the electric field is kept away from the substrate 12 so that basal plane dislocations do not migrate into the first drift layer 14A or the second drift layer 14B. More than two drift layers may be used to achieve similar results.

[0063] Exemplary doping concentration ranges for the embodiment of FIG. 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1×10 13 ~4×10 16 cm -3 ; For the second drift layer 14B, 2×10 13 ~8×10 16 cm -3 and 5x10 for board 12 17 ~1×10 20 cm -3 Includes. An alternative set of ranges is 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1×10 15 ~2×10 16 cm -3 ; For the second drift layer 14B, 2×10 15 ~3×10 16 cm -3 and 1x10 for board 12 18 ~1×10 20 cm -3 Includes. Exemplary thickness ranges are: 1-4 μm for the diffusion layer 36; 2 to 50 μm for the first drift layer 14A; 1 to 30 μm for the second drift layer 14B; and The thickness of the substrate 12 is in the range of 50 to 500 μm.

[0064] The embodiment shown in FIG. 16A builds on the embodiment of FIG. 15A by adding a buffer layer 34 between the second drift layer 14B and the substrate 12. As in the previous embodiment, the electric field at the avalanche voltage does not punch through the second drift layer 14B, as shown in FIG. 16B, and is therefore stopped just before the buffer layer 34. A further advantage of this embodiment is more readily apparent in FIG. 16C, which shows the electric field at the bottom of the drift layer 14B and the lds current as the drain-source voltage (Vds) increases in blocking mode when the transistor 10 is configured as a FET or diode. By adding the buffer layer 34, the avalanche voltage (Vaval) and punch-through voltage (V(PT)) remain relatively constant, while the second breakdown voltage is further increased, resulting in further field reduction at high field, high current discharge conditions.

[0065] Exemplary doping concentration ranges for the embodiment of FIG. 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; For the first drift layer 14A, 1×10 13 ~5×10 16 cm -3 ; For the second drift layer 14B, 2×10 13 ~1×10 17 cm -3 ; 5×10 for the buffer layer 34 16 ~5×10 18 cm -3 and 1x10 for board 12 18 ~1×10 20 cm -3 Includes. An alternative set of ranges is 1×10 for diffusion layer 3616 ~5×10 16 cm -3 ; For the first drift layer 14A, 1×10 15 ~2×10 16 cm -3 ; For the second drift layer 14B, 2×10 15 ~3×10 16 cm -3 ; Buffer layer 34: 1×10 17 ~1×10 18 cm -3 and 1x10 for board 12 18 ~1×10 20 cm -3 Includes. Exemplary thickness ranges are: 1-5 μm for the diffusion layer 36; 2 to 50 μm for the first drift layer 14A; 1 to 30 μm for the second drift layer 14B; Buffer layer 34: 1 to 20 μm; and The thickness of the substrate 12 is in the range of 50 to 500 μm. The first drift layer 14A and the second drift layer 14B may have the same or different doping concentrations and the same or different doping profiles. For example, both the first drift layer 14A and the second drift layer 14B may have the same or different graded or constant doping concentrations. Furthermore, either the first drift layer 14A or the second drift layer 14B may have a graded doping profile, while the other drift layer is constant. In certain embodiments, the diffusion layer 36 has a higher doping concentration than at least one of the first drift layer and the second drift layer, if not both.

[0066] The embodiment of FIG. 17A provides a transistor 10 with a drift layer 14 having graded doping. In the illustrated embodiment, there is only one drift layer 14 and no buffer layer 34. The doping concentration increases in the drift layer 14 from the bottom (i.e., the substrate interface) to the top (i.e., the diffusion layer 36 interface) of the drift layer 14. Thus, the doping concentration is slightly higher at the bottom of the drift layer 14 and lower near the top of the drift layer 14. As shown in FIG. 17B, the doping concentration is a relative level through the diffusion layer 36 that drops to a first level at the top of the drift layer 14, increases continuously in the drift layer 14 to a level below the diffusion layer 36, and then jumps to a much higher, relatively constant level at the substrate 12. The doping concentrations in FIG. 17B are shown on a log scale.

[0067] With the proper doping concentration, profile, and thickness, an increase in both the punch-through voltage (V(PT)) and the second breakdown voltage is achieved, as shown in Figure 17C. With the graded drift layer 14, the avalanche voltage (Vaval) can remain constant, whereas the second breakdown voltage and punch-through voltage V(PT) are increased beyond the avalanche voltage (Vaval) limit. This results in further field reduction at high field, high current discharge conditions.

[0068] By not providing any electric field that penetrates or is high enough to penetrate the substrate 12, durability is increased under high field, high current, and high speed switching conditions. The snappiness of the bipolar device in switching is also reduced. As in other embodiments, by keeping the electric field away from the substrate 12, basal plane dislocations are prevented from migrating into the drift layer 14.

[0069] Exemplary doping concentration ranges for the embodiment of FIGS. 17A and 17B are: 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; 1×10 for drift layer 14 13~5×10 18 cm -3 Between 1×10 15 ~5×10 17 cm -3 Between; and 1x10 for board 12 18 ~1×10 20 cm -3 Includes. An alternative set of ranges is 1×10 for diffusion layer 36 16 ~5×10 16 cm -3 ; 5×10 for drift layer 14 15 ~5×10 17 cm -3 Between 1×10 16 ~1×10 17 cm -3 Between; and 1x10 for board 12 18 ~5×10 19 cm -3 Includes. Exemplary thickness ranges are: 1-5 μm for the diffusion layer 36; 3 to 200 μm for the drift layer 14; and The thickness of the substrate 12 is in the range of 50 to 500 μm.

[0070] Referring now to FIG. 18, a buffer layer 34 and a graded drift layer 14 are provided between the diffusion layer 36 and the substrate 12. In this embodiment, the diffusion layer 36 and the buffer layer 34 are uniformly doped, and the drift layer 14 is graded as described above. In other embodiments, the doping for the diffusion layer 36 and / or the buffer layer 34 is graded. The graph of FIG. 18B presents an exemplary doping profile in log scale. As shown in FIG. 18B, the doping concentration decreases continuously from a first level at the top of the diffusion layer 36 to a second level at the bottom of the diffusion layer 36, increases continuously from the second level at the top of the drift layer 14 to a third level at the bottom of the drift layer 14 that is lower than the first level, and increases continuously from the second level to a fourth level in the buffer layer 34. The doping in the substrate 12 is shown to be constant at the fourth level. In the illustrated embodiment, the doping levels in the illustrated layers are continuous in that there are no abrupt changes in doping concentration within a given layer or at layer junctions.

[0071] Exemplary doping concentration ranges for all graded embodiments are: 5×10 for diffusion layer 36 16 ~1×10 14 cm -3 Between 3×10 16 ~5×10 15 cm -3 Between; 1×10 for drift layer 14 13 ~1×10 17 cm -3 Between 5×10 15 ~5×10 16 cm -3 Between; 5×10 for the buffer layer 34 16 ~1×10 20 cm -3 Between 1×10 17 ~1×10 20 cm -3 Between; and 1x10 for board 12 18 ~1×10 20 cm -3 Includes. Exemplary thickness ranges are: 1-5 μm for the diffusion layer 36; 3 to 200 μm for the drift layer 14; Buffer layer 34: 1 to 20 μm; and The thickness of the substrate 12 is in the range of 50 to 500 μm. For the embodiments in Figures 9 to 12, the characteristics, thicknesses, doping concentrations, thickness relationships and / or doping concentration relationships of the substrate 12, buffer layer 34, and drift layer 14 may, but need not, be applied to any of the embodiments in Figures 13 to 18, and vice versa.

[0072] The use of multiple drift layers, buffer layers 34, and diffusion layers 36 as described above with respect to Figures 9-18 may not only increase the ruggedness of the transistor 10, but may also reduce the snappiness of the body diode 30. First, various configurations of the drift layers 14, buffer layers 34, and diffusion layers 36 may prevent punch-through, as described above, and therefore improve the performance of the body diode 30. Additionally, various configurations of the drift layers 14, buffer layers 34, and diffusion layers 36 may be designed to provide a desired distribution of minority carriers to reduce snappiness, as described above with respect to Figure 4.

[0073] FIG. 19 is a graph illustrating the effect of providing the body diode 30 as a non-punch-through diode according to one embodiment of the present disclosure. In particular, the graph illustrates several portions of the voltage and current transient response for the body diode 30 when provided as a punch-through diode and a non-punch-through diode. The dashed line illustrates the response of the body diode 30 at 25° C. when provided as a punch-through diode. The dotted line illustrates the response of the body diode 30 at 175° C. when provided as a punch-through diode. The solid line illustrates the response of the body diode 30 at 25° C. when provided as a non-punch-through diode. As discussed above, this can be achieved, by way of example, by varying the thickness and doping concentration of the drift layer 14. The dash-dotted line illustrates the response of the body diode 30 at 175° C. when provided as a non-punch-through diode. As shown, the response of the body diode 30 is slower at both 25° C. and 175° C. when provided as a non-punch-through diode.

[0074] FIG. 20 is a graph showing the effect of the drift layer 14 carrier lifetime on the body diode 30. In particular, the graph shows several portions of the voltage and current transient response for the body diode 30 given various carrier lifetimes in the drift layer 14. The dashed line, which is mostly obscured by the solid line discussed below, shows the response of the body diode 30 without carrier lifetime enhancement. The dotted line shows the effect of Z in the drift layer 14. 1 / 2 Trap density is 1×10 15 cm -3 The solid line shows the response of the body diode 30 with carrier lifetime enhancement as follows: 1 / 2 Trap density is 5×10 13 cm -3 The dashed line shows the response of the body diode 30 with carrier lifetime enhancement as follows: Z 1 / 2 Trap density is 1×10 12 cm -3The response of the body diode 30 with carrier lifetime enhancement is shown below. The carrier lifetime is Z 1 / 2 This is related to the trap density because these traps act as recombination centers for carriers. For example, as mentioned above, thermal oxidation can increase the 1 / 2 By reducing the trap density, the carrier lifetime can be increased, which may reduce the snappiness and therefore the softness of the body diode 30. In particular, the graph in Figure 20 shows the response of the body diode 30 as a punch-through diode.

[0075] FIG. 21 is a graph illustrating the effect of the recombination region 32 on the body diode 30. In particular, the graph illustrates several portions of voltage and current transient responses for the body diode 30 with and without the recombination region 32. The dashed line illustrates the response of the body diode 30 without the recombination region 32, whereas the solid line illustrates the response of the body diode 30 with the recombination region 32. In particular, the graph illustrates the response of the body diode 30 as a non-punch-through diode, where the drift layer 14 has an improved carrier lifetime. As shown, the inclusion of the recombination region 32 increases the softness of the body diode 30.

[0076] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are deemed to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

1. A substrate; a drift layer on the substrate; one or more implanted regions in the drift layer, providing a vertical transistor device configured to conduct current in a first direction; the one or more implanted regions configured to provide a body diode configured to conduct current in a second direction opposite the first direction; a recombination region in contact with the one or more injection regions of the drift layer and having a higher density of minority carrier recombination centers than the drift layer; A semiconductor device comprising:

2. The density of minority carrier recombination centers in the recombination region is 1×10 １３ cm －３ ~1×10 １８ cm －３ 2. The semiconductor device of claim 1 , wherein:

3. 2. The semiconductor device of claim 1, wherein the density of minority carrier recombination centers in the recombination region is 5 to 10 times higher than the density of minority carrier recombination centers in the drift layer.

4. 2. The semiconductor device of claim 1, wherein a minority carrier lifetime in the drift layer is between 1 μs and 20 μs.

5. Z in the drift layer １／２ The trap density is 5×10 １３ cm －３ The semiconductor device of claim 1 .

6. the drift layer has a first doping type; the one or more implanted regions include a body well having a second doping type; The semiconductor device of claim 1 , wherein at least a portion of the recombination region is between a bottom of the body well and the substrate.

7. The semiconductor device of claim 6 , wherein the recombination region overlaps at least a portion of a thickness of the body well.

8. The semiconductor device of claim 6 , wherein the width of the recombination region is narrower than the width of the body well in a direction parallel to a top surface of the substrate.

9. The semiconductor device of claim 6 , wherein the width of the recombination region is equal to or greater than the width of the body well in a direction parallel to a top surface of the substrate.

10. 7. The semiconductor device of claim 6, wherein a density of minority carrier recombination centers in the recombination region reaches a peak value at an interface between the drift layer and the body well.

11. The doping concentration of the body well is 1×10 １６ cm －３ ~3×10 １９ cm －３ Between The semiconductor device of claim 6 , wherein a doping concentration of the body well decreases in proportion to the distance from the drift layer.

12. The semiconductor device of claim 1 , wherein the recombination region extends along an entire thickness of at least a portion of the drift layer in a direction perpendicular to a top surface of the substrate.

13. 10. The semiconductor device of claim 1, wherein the body diode is a non-punch through diode.

14. A substrate; a drift layer on the substrate having a minority carrier lifetime between 1 μs and 20 μs; One or more implanted regions of the drift layer, providing a vertical transistor device configured to conduct current in a first direction; the one or more implanted regions configured to provide a body diode configured to conduct current in a second direction opposite to the first direction; A semiconductor device comprising:

15. The Z of the drift layer １／２ Trap density is 5 x 10 １３ cm －３ The semiconductor device of claim 14 .

16. The drift layer further includes a recombination region, and a density of minority carrier recombination centers in the recombination region is 1×10 １３ cm －３ and 1 x 10 １８ cm －３ The semiconductor device of claim 14 , wherein

17. The drift layer is a first drift layer having a first doping type and a first doping profile; a second drift layer having the first doping type and a second doping profile different from the first doping profile; The semiconductor device of claim 14 .

18. The semiconductor device of claim 14 , wherein the body diode has a softness factor between 0.5 and 10.

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