Power amplifier circuit

Abstract

To provide a power amplifier circuit that can suppress a gain variation caused by switching an operation mode.SOLUTION: A two-stage power amplifier circuit in which a drive stage amplifier and a power stage amplifier are connected in series, includes: a first switch circuit for switching between conduction and non-conduction between an output terminal and a node between the drive stage amplifier and the power stage amplifier; and a second switch circuit for switching between conductive and non-conductive between the output terminal and the power stage amplifier. The power amplifier circuit has: a first mode in which the first switch circuit is conducted and the second switch circuit is made non-conductive; and a second mode in which the first switch circuit is made non-conductive and the second switch circuit is conducted. When shifting from the first mode to the second mode, the first switch circuit is made non-conductive after the second switch circuit is conducted. When shifting from the second mode to the first mode, the second switch circuit is made non-conductive after the first switch circuit is conducted.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a power amplifier circuit. [Background technology]

[0002] Conventionally, in a power amplifier circuit used in wireless communication and the like, a technique for switching an operation mode according to the magnitude of the output power has been disclosed (for example, Patent Document 1). Patent Document 1 exemplifies, as an example of a method for switching an operation mode, a configuration in which a bypass switching circuit is provided to bypass a power stage amplifier when low output power is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2006-512847 Summary of the Invention [Problem to be solved by the invention]

[0004] In a configuration in which a bypass switching circuit is used to switch a high-frequency signal path, the high-frequency signal path may be cut off depending on the switching timing, causing a drop in gain. In addition, when switching from a low-power mode to a high-power mode, an overshoot may occur, and it may take time for the gain to stabilize after the mode switching. Such gain fluctuations accompanying switching of operation modes may cause communication errors.

[0005] The present invention has been made in view of the above, and has an object to provide a power amplifier circuit capable of suppressing gain fluctuations that occur when the operation mode is switched. [Means for solving the problem]

[0006] A power amplifier circuit according to one aspect of the present invention is a two-stage power amplifier circuit in which a drive stage amplifier and a power stage amplifier are connected in series, and includes a first switch circuit that switches between conduction and non-conduction between an output terminal and a node between the drive stage amplifier and the power stage amplifier, and a second switch circuit that switches between conduction and non-conduction between the power stage amplifier and the output terminal. The power amplifier circuit has a first mode in which the first switch circuit is made conductive and the second switch circuit is made non-conductive, and a second mode in which the first switch circuit is made non-conductive and the second switch circuit is made conductive. When transitioning from the first mode to the second mode, the second switch circuit is made conductive and then the first switch circuit is made non-conductive, and when transitioning from the second mode to the first mode, the first switch circuit is made conductive and then the second switch circuit is made non-conductive.

[0007] In this configuration, it is possible to suppress gain fluctuations that occur when the operation mode is switched. Effect of the Invention

[0008] According to the present invention, it is possible to realize a power amplifier circuit capable of suppressing gain fluctuations that occur when the operation mode is switched. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a configuration of a power amplifier circuit according to an embodiment. [Diagram 2] FIG. 2 is a timing chart showing an example of control timing in a conventional example. [Figure 3A] FIG. 3A is a diagram showing the control state of switching elements in an LPM. [Figure 3B] FIG. 3B is a diagram showing the control state of the switching elements in the HPM. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of a switching element. [Figure 5A] FIG. 5A is a diagram showing an example of the operation of switching elements when transitioning from LPM to HPM in a conventional example. [Figure 5B] FIG. 5B is a diagram showing an example of the operation of switching elements when transitioning from HPM to LPM in a conventional example. [Figure 6] FIG. 6 is a conceptual diagram showing an example of gain fluctuation when switching from LPM to HPM in a conventional example. [Figure 7] FIG. 7 is a timing chart showing an example of control timing of the power amplifier circuit according to the embodiment. [Figure 8] FIG. 8 is a block diagram showing an example of the internal configuration of the control circuit. [Figure 9A] FIG. 9A is a first diagram showing an example of the operation of a switching element at the time of mode transition in the power amplifier circuit according to the embodiment. [Figure 9B] FIG. 9B is a second diagram showing an example of the operation of the switching elements at the time of mode transition in the power amplifier circuit according to the embodiment. [Figure 10] FIG. 10 is a timing chart showing an example of control timing of the power amplifier circuit according to the comparative example. [Figure 11A] FIG. 11A is a diagram showing an example of the operation of switching elements when transitioning from LPM to HPM in a comparative example. [Figure 11B] FIG. 11B is a diagram showing a loop path at the time of mode transition in the power amplifier circuit according to the embodiment. [Figure 12] FIG. 12 is a timing chart showing an example of control timing of the power amplifier circuit according to the modified example of the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The power amplifier circuit according to the embodiment will be described in detail below with reference to the drawings. Note that the present invention is not limited to these embodiments. Each embodiment is merely an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. From embodiment 2 onwards, a description of matters common to embodiment 1 will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] Fig. 1 is a diagram showing the configuration of a power amplifier circuit according to an embodiment. The power amplifier circuit 1 shown in Fig. 1 is a two-stage RF power amplifier in which a drive stage amplifier DRV and a power stage amplifier PA are connected in series. The power amplifier circuit 1 amplifies a high-frequency signal input from an input terminal RFin and outputs it from an output terminal RFout. Although not shown, matching circuits are provided at the input and output of the power amplifier circuit and between the drive stage amplifier DRV and the power stage amplifier PA.

[0012] The power amplifier circuit 1 according to the embodiment has, as its operating modes, a low power mode (hereinafter also referred to as "LPM") in which the circuit operates at a relatively low output power, and a high power mode (hereinafter also referred to as "HPM") in which the circuit operates at a relatively high output power. In the present disclosure, the low power mode (LPM) corresponds to the first mode. Also, in the present disclosure, the high power mode (HPM) corresponds to the second mode.

[0013] The power amplifier circuit 1 includes a first switch circuit 21, a second switch circuit 22, and a control circuit 23 as components for switching the operation mode.

[0014] The first switch circuit 21 switches between conduction and non-conduction between a node between the drive stage amplifier DRV and the power stage amplifier PA and the output terminal RFout.

[0015] The first switch circuit 21 includes first switching elements SW1_1, SW1_2, and a third switching element SW3. The first switching elements SW1_1, SW1_2 are connected in series between a node between the drive stage amplifier DRV and the power stage amplifier PA and the output terminal RFout. The third switching element SW3 is shunt-connected between a node between the first switching elements SW1_1, SW1_2 and the ground potential.

[0016] The second switch circuit 22 switches between conduction and non-conduction between the power stage amplifier PA and the output terminal RFout.

[0017] The second switch circuit 22 includes a second switching element SW2. The second switching element SW2 is connected in series between the power stage amplifier PA and the output terminal RFout.

[0018] In the present disclosure, the control circuit 23 performs on / off control of the first switching elements SW1_1 and SW1_2, the second switching element SW2, and the third switching element SW3. Also, in the present disclosure, the control circuit 23 performs bias control of the power stage amplifier PA.

[0019] 1, the drive stage amplifier DRV, the first switch circuit 21, the second switch circuit 22, and the control circuit 23 are configured, for example, by silicon devices (integrated circuits, ICs) including field effect transistors (FETs) formed on a Si (silicon) substrate 2. The power stage amplifier PA is configured, for example, by HBT devices (integrated circuits, ICs) including heterojunction bipolar transistors (HBTs) formed on a GaAs (gallium arsenide) substrate 3.

[0020] Fig. 2 is a timing chart showing an example of control timing in a conventional example, Fig. 3A is a diagram showing the control state of switching elements in an LPM, and Fig. 3B is a diagram showing the control state of switching elements in an HPM.

[0021] In the present disclosure, an operation mode control signal MODE_CTRL is input from a higher-level control system (not shown) to the control circuit 23. The control circuit 23 performs switching control between LPM and HPM based on the operation mode control signal MODE_CTRL.

[0022] Specifically, in the LPM, the control circuit 23 turns on the first switching elements SW1_1 and SW1_2, turns off the second switching element SW2 and the third switching element SW3, and turns off the bias of the power stage amplifier PA, as shown in Fig. 3A. This forms a high-frequency signal path indicated by the dashed arrow, and the high-frequency signal amplified by the drive stage amplifier DRV is output from the output terminal RFout.

[0023] 3B, the control circuit 23 turns off the first switching elements SW1_1 and SW1_2, turns on the second switching element SW2 and the third switching element SW3, and turns on the bias of the power stage amplifier PA. As a result, a high frequency signal path indicated by the dashed line arrow is formed, and the high frequency signal amplified by the drive stage amplifier DRV is further amplified by the power stage amplifier PA and output from the output terminal RFout.

[0024] Fig. 4 is a diagram showing an example of the configuration of a switching element. Fig. 5A is a diagram showing an example of the operation of a switching element when transitioning from LPM to HPM in a conventional example. Fig. 5B is a diagram showing an example of the operation of a switching element when transitioning from HPM to LPM in a conventional example. Fig. 6 is a conceptual diagram showing an example of gain fluctuation when switching from LPM to HPM in a conventional example.

[0025] As shown in FIG. 4, each of the first switching elements SW1_1 and SW1_2, the second switching element SW2, and the third switching element SW3 is configured with a plurality of FETs connected in series.

[0026] The timing when the switching element in the embodiment shown in Fig. 4 is controlled to turn on and actually turns on is delayed with respect to the on control timing. This delay amount is determined by the gate capacitance and gate resistance according to the size of the FET. In contrast, the delay amount when the switching element in the embodiment shown in Fig. 4 is controlled to turn off and actually turns off is smaller than the delay amount with respect to the on control timing.

[0027] For this reason, in the conventional timing chart shown in Fig. 2, for example, as shown in Fig. 5A, when transitioning from LPM to HPM, the on-timing of the second switching element SW2 may be delayed with respect to the off-timing of the first switching elements SW1_1 and SW1_2, which may result in disconnection of the high-frequency signal path. Also, for example, as shown in Fig. 5B, when transitioning from HPM to LPM, the on-timing of the first switching elements SW1_1 and SW1_2 may be delayed with respect to the off-timing of the second switching element SW2, which may result in disconnection of the high-frequency signal path.

[0028] The gain change period Gain_Change associated with switching of the operation mode is specified as, for example, 500 ns to 2 μs. FIG. 6 shows an example in which the high-frequency signal path is cut off and a drop in gain occurs when the on-timing of the second switching element SW2 is delayed with respect to the off-timing of the first switching elements SW1_1 and SW1_2 during a transition from LPM to HPM. FIG. 6 also shows an example in which an overshoot occurs when the second switching element SW2 is actually turned on, and the gain is not stable within the gain change period Gain_Change associated with switching of the operation mode. Such gain fluctuations associated with switching of the operation mode may be a cause of communication errors.

[0029] Hereinafter, a description will be given of switching timing of each switching element that can suppress gain fluctuations accompanying switching of the operation mode, and a configuration that can realize the switching timing.

[0030] Fig. 7 is a timing chart showing an example of control timing of the power amplifier circuit according to the embodiment. Fig. 8 is a block diagram showing an example of the internal configuration of a control circuit. Fig. 9A is a first diagram showing an example of the operation of a switching element at the time of mode transition in the power amplifier circuit according to the embodiment. Fig. 9B is a second diagram showing an example of the operation of a switching element at the time of mode transition in the power amplifier circuit according to the embodiment.

[0031] As shown in FIG. 3A, in LPM, the first switching elements SW1_1 and SW1_2 are on, and the second switching element SW2 and the third switching element SW3 are off. When shifting from LPM to HPM, as shown in FIG. 7, the control circuit 23 turns on the second switching element SW2 before turning off the first switching elements SW1_1 and SW1_2, and turns on the bias of the power stage amplifier PA. In other words, when shifting from LPM to HPM, the control circuit 23 delays the off control timing of the first switching elements SW1_1 and SW1_2 with respect to the on control timing of the second switching element SW2. In the configuration shown in FIG. 8, the delay amount of the off control timing of the first switching elements SW1_1 and SW1_2 can be set by the R1C1 circuit in FIG. 8 with respect to the switching timing of the operation mode control signal MODE_CTRL from LPM to HPM.

[0032] When the second switching element SW2 is controlled to be on, both the high-frequency signal path (dashed line) by the LPM and the high-frequency signal path (dashed line) by the HPM are formed as shown in Fig. 9A. After that, the first switching elements SW1_1 and SW1_2 are controlled to be off, and the high-frequency signal path (dashed line) by the LPM is cut off as shown in Fig. 9B.

[0033] In the state shown in FIG. 9B, a loop path (two-dot chain line) of the high frequency signal of the HPM is formed due to the capacitive components of the first switching elements SW1_1 and SW1_2, and good reverse isolation may not be obtained.

[0034] Therefore, the control circuit 23 turns on the third switching element SW3 after turning off the first switching elements SW1_1 and SW1_2. That is, the control circuit 23 delays the timing of turning on the third switching element SW3 with respect to the timing of turning off the first switching elements SW1_1 and SW1_2. This makes it possible to maintain good reverse isolation in HPM. In the configuration shown in FIG. 8, the delay amount of the timing of turning on the third switching element SW3 can be set by the R3C3 circuit in FIG. 8 with respect to the switching timing of the operation mode control signal MODE_CTRL from LPM to HPM.

[0035] By controlling the third switching element SW3 to be on, the capacitive components of the first switching elements SW1_1 and SW1_2 are grounded, resulting in the control state of the switching elements in the HPM shown in Figure 3B, and the high-frequency signal amplified by the drive stage amplifier DRV is further amplified by the power stage amplifier PA and output from the output terminal RFout.

[0036] As shown in FIG. 3B, in HPM, the first switching elements SW1_1 and SW1_2 are off, and the second switching element SW2 and the third switching element SW3 are on. When shifting from HPM to LPM, as shown in FIG. 7, the control circuit 23 turns on the first switching elements SW1_1 and SW1_2 and turns off the third switching element SW3 before turning off the second switching element SW2. In other words, when shifting from HPM to LPM, the control circuit 23 delays the timing of turning off the second switching element SW2 with respect to the timing of turning on the first switching elements SW1_1 and SW1_2. In the configuration shown in FIG. 8, the delay amount of the timing of turning off the second switching element SW2 can be set by the R2C2 circuit in FIG. 8 with respect to the switching timing of the operation mode control signal MODE_CTRL from HPM to LPM.

[0037] When the first switching elements SW1_1 and SW1_2 are controlled to be on and the third switching element SW3 is controlled to be off, both the high frequency signal path (dashed line) by LPM and the high frequency signal path (dash line) by HPM are formed as shown in FIG. 9A. After that, the second switching element SW2 is controlled to be off, resulting in the control state of the switching elements in LPM shown in FIG. 3A. After that, the control circuit 23 controls the bias of the power stage amplifier PA to be off. As a result, the high frequency signal amplified by the drive stage amplifier DRV is output from the output terminal RFout. In the configuration shown in FIG. 8, the amount of delay in the timing of controlling the bias of the power stage amplifier PA off can be set by the RPCP circuit of FIG. 8 with respect to the switching timing of the operation mode control signal MODE_CTRL from HPM to LPM.

[0038] Fig. 10 is a timing chart showing an example of control timing of a power amplifier circuit according to a comparative example, Fig. 11A is a diagram showing an example of operation of a switching element when transitioning from LPM to HPM in the comparative example.

[0039] 10 shows an example in which the third switching element SW3 is turned on before the first switching elements SW1_1 and SW1_2 are turned off when shifting from LPM to HPM. In this case, as shown in FIG 11A, short-circuit paths to the ground potential are formed in both the high frequency signal path by LPM (dashed line) and the high frequency signal path by HPM (dotted line).

[0040] Fig. 11B is a diagram showing a loop path at the time of mode transition in the power amplifier circuit according to the embodiment. As shown in Fig. 9A, when both a high-frequency signal path (dashed line) by LPM and a high-frequency signal path (dash line) by HPM are formed, a loop path indicated by a two-dot chain line arrow in Fig. 11B is formed. The phase of this loop path changes depending on the impedance of the circuit, and it may become a positive feedback loop, causing the power stage amplifier PA to oscillate.

[0041] FIG. 12 is a timing chart showing an example of control timing of the power amplifier circuit according to the modified example of the embodiment.

[0042] 12, the bias of the power stage amplifier PA is set to a low bias (LOW) lower than the normal bias (HIGH) in HPM during the period from the timing of controlling the bias of the power stage amplifier PA on to the timing of controlling the first switching elements SW1_1 and SW1_2 off when shifting from LPM to HPM, and during the period from the timing of controlling the first switching elements SW1_1 and SW1_2 on to the timing of controlling the bias of the power stage amplifier PA off when shifting from HPM to LPM. This makes it possible to prevent the power stage amplifier PA from oscillating when a loop path is formed.

[0043] The above-described embodiments are provided to facilitate understanding of the present invention, and are not intended to limit the present invention. The present invention may be modified or improved without departing from the spirit of the present invention, and equivalents thereof are also included in the present invention.

[0044] Furthermore, the present disclosure can have the following configuration as described above or instead of the above.

[0045] (1) A power amplifier circuit according to one aspect of the present invention is a two-stage power amplifier circuit in which a drive stage amplifier and a power stage amplifier are connected in series, the power amplifier circuit comprising: a first switch circuit that switches between conduction and non-conduction between an output terminal and a node between the drive stage amplifier and the power stage amplifier; and a second switch circuit that switches between conduction and non-conduction between the power stage amplifier and the output terminal. The power amplifier circuit has a first mode in which the first switch circuit is made conductive and the second switch circuit is made non-conductive, and a second mode in which the first switch circuit is made non-conductive and the second switch circuit is made conductive. When transitioning from the first mode to the second mode, the second switch circuit is made conductive and then the first switch circuit is made non-conductive, and when transitioning from the second mode to the first mode, the first switch circuit is made conductive and then the second switch circuit is made non-conductive.

[0046] In this configuration, when transitioning from the first mode to the second mode, it is possible to prevent both the first switch circuit and the second switch circuit from becoming non-conductive. Also, when transitioning from the second mode to the first mode, it is possible to prevent both the first switch circuit and the second switch circuit from becoming non-conductive. This makes it possible to suppress gain fluctuations that accompany switching of the operation mode.

[0047] (2) In the power amplifier circuit of (1) above, it is preferable that the first switch circuit includes at least a first switching element connected in series between an output terminal and a node between the drive stage amplifier and the power stage amplifier, the second switch circuit includes a second switching element connected in series between the power stage amplifier and the output terminal, and at least a control circuit which controls on and off the first switching element and the second switching element, and that when transitioning from the first mode to the second mode, the control circuit turns on the second switching element and then turns off the first switching element, and when transitioning from the second mode to the first mode, the control circuit turns on the first switching element and then turns off the second switching element.

[0048] In this configuration, when transitioning from the first mode to the second mode, it is possible to prevent both the first switching element and the second switching element from being turned off. Also, when transitioning from the second mode to the first mode, it is possible to prevent both the first switching element and the second switching element from being turned off. This makes it possible to suppress gain fluctuations that accompany switching of the operation mode.

[0049] (3) In the power amplifier circuit of (2) above, the first switch circuit includes a plurality of first switching elements connected in series between a node between the drive stage amplifier and the power stage amplifier and an output terminal, and further includes a third switching element shunt-connected between a node between the plurality of first switching elements and a ground potential, and when transitioning from the first mode to the second mode, the control circuit turns off the first switching element and then turns on the third switching element, and when transitioning from the second mode to the first mode, turns on the first switching element and turns off the third switching element.

[0050] In this configuration, it is possible to prevent the third switching element from being turned on while the multiple first switching elements are on, thereby preventing the formation of a short-circuit path to the ground potential in the high-frequency signal path.

[0051] (4) In the power amplifier circuit of (3) above, it is preferable that, when transitioning from the first mode to the second mode, the control circuit turns on the second switching element and turns on the bias of the power stage amplifier, and, when transitioning from the second mode to the first mode, turns off the second switching element and then turns off the bias of the power stage amplifier.

[0052] (5) In the power amplifier circuit of (4) above, when transitioning from the first mode to the second mode, the control circuit turns on the second switching element, and sets the bias of the power stage amplifier to a low bias lower than the bias of the power stage amplifier in the second mode during the period from the on control timing of the bias of the power stage amplifier to the off control timing of the first switching element, and when transitioning from the second mode to the first mode, sets the bias of the power stage amplifier to the low bias during the period from the on control timing of the first switching element to the off control timing of the bias of the power stage amplifier.

[0053] In this configuration, when both the first switching element and the second switching element are on, the phase changes due to the impedance, and in the case where a positive feedback loop is formed, oscillation of the power stage amplifier can be suppressed.

[0054] (6) In any one of the power amplifier circuits (1) to (5) above, the drive stage amplifier is a silicon device formed on a Si substrate, and the power stage amplifier is an HBT device formed on a GaAs substrate.

[0055] In this configuration, the drive stage amplifier, the first bias circuit, and the second bias circuit can be integrally formed on a Si substrate, and the effect of heat generated by the power stage amplifier on the drive stage amplifier can be suppressed.

[0056] According to the present disclosure, it is possible to realize a power amplifier circuit capable of suppressing gain fluctuations that occur when the operation mode is switched. [Explanation of symbols]

[0057] 1 Power amplifier circuit 2. Si (silicon) substrate 3 GaAs (gallium arsenide) substrate 21 First switch circuit 22 Second switch circuit 23 Control circuit DRV Drive stage amplifier PA Power Stage Amplifier RFin input terminal RFout output terminal SW1_1, SW1_2 First switching element SW2 Second switching element SW3 Third switching element

Claims

1. A two-stage power amplifier circuit in which a drive stage amplifier and a power stage amplifier are connected in series, a first switch circuit that switches between conduction and non-conduction between a node between the drive stage amplifier and the power stage amplifier and an output terminal; a second switch circuit that switches between conductive and non-conductive states between the power stage amplifier and the output terminal; Equipped with a first mode in which the first switch circuit is conductive and the second switch circuit is non-conductive; a second mode in which the first switch circuit is non-conductive and the second switch circuit is conductive; having When transitioning from the first mode to the second mode, the second switch circuit is made conductive and then the first switch circuit is made non-conductive; When transitioning from the second mode to the first mode, the first switch circuit is made conductive and then the second switch circuit is made non-conductive. Power amplifier circuit.

2. 2. The power amplifier circuit according to claim 1, the first switch circuit includes at least a first switching element connected in series between a node between the drive stage amplifier and the power stage amplifier and an output terminal; the second switch circuit includes a second switching element connected in series between the power stage amplifier and the output terminal; A control circuit that controls on / off of at least the first switching element and the second switching element, The control circuit includes: When transitioning from the first mode to the second mode, the second switching element is turned on and then the first switching element is turned off; When transitioning from the second mode to the first mode, the first switching element is turned on and then the second switching element is turned off. Power amplifier circuit.

3. 3. The power amplifier circuit according to claim 2, the first switch circuit includes a plurality of first switching elements connected in series between a node between the drive stage amplifier and the power stage amplifier and an output terminal, and further includes a third switching element shunt-connected between a node between the plurality of first switching elements and a ground potential; The control circuit includes: When transitioning from the first mode to the second mode, the first switching element is turned off and then the third switching element is turned on; When transitioning from the second mode to the first mode, the first switching element is controlled to be on and the third switching element is controlled to be off. Power amplifier circuit.

4. 4. The power amplifier circuit according to claim 3, The control circuit includes: When transitioning from the first mode to the second mode, the second switching element is turned on and a bias of the power stage amplifier is turned on; When transitioning from the second mode to the first mode, the second switching element is turned off and then a bias of the power stage amplifier is turned off. Power amplifier circuit.

5. 5. A power amplifier circuit according to claim 4, The control circuit includes: When transitioning from the first mode to the second mode, the second switching element is turned on, and the bias of the power stage amplifier is set to a low bias lower than the bias of the power stage amplifier in the second mode during a period from a timing of turning on the bias of the power stage amplifier to a timing of turning off the first switching element; When transitioning from the second mode to the first mode, the bias of the power stage amplifier is set to the low bias during a period from an on-control timing of the first switching element to an off-control timing of the bias of the power stage amplifier. Power amplifier circuit.

6. 6. A power amplifier circuit according to claim 1, the drive stage amplifier is a silicon device formed on a Si substrate; the power stage amplifier is an HBT device formed on a GaAs substrate; Power amplifier circuit.

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