Equalizer circuit, laser driver circuit, cpo module, and optical communication system

Abstract

To provide an equalizer circuit capable of adjusting band extension performance with a simple configuration.SOLUTION: An equalizer circuit 430 shapes the waveform of a reference signal. The equalizer circuit 430 includes a delay signal generation circuit 432 that generates one or more delay signals delayed from the reference signal, and a signal combination circuit 434 that adds delayed current signals synchronized with the delay signals in opposite phase to a reference current signal synchronized with the reference signal. The delay signal generation circuit 432 is composed of multiple stages of delay circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an equalizer circuit, a laser driver circuit, a CPO module, and an optical communication system. [Background technology]

[0002] With the spread of IoT, a lot of data is being sent and received via optical and wireless communications. In recent years, there are high expectations for the realization of cyber-physical systems (CPS) that use AI to process big data on the cloud (cyberspace) collected by IoT devices (physical space) and provide feedback to the physical space.

[0003] The data transmission capacity required for the switch equipment in data centers, which are the realization of the cloud, is steadily increasing, and power consumption in data centers is also increasing. In order to achieve even higher speeds and lower power consumption, it is desirable to shorten the electrical wiring on switch equipment boards and between boards and replace it with optical wiring. One method that has attracted attention is CPO (Co-Packaged Optics), which combines a large number of optical elements, integrated circuits, and switch ASICs into a single package to minimize the length of electrical wiring, reduce power consumption, improve thermal efficiency, and reduce size.

[0004] The VCSEL (Vertical-Cavity Surface-Emitting Laser) driver chip mounted on the CPO module has many channels densely integrated, making it susceptible to electromagnetic interference (crosstalk noise) from other channels. In addition, it is expected that the optimal operating conditions for each channel will differ depending on the optical element characteristics and the CPO module mounting state.

[0005] Therefore, it is desirable to be able to change the operating conditions for each channel independently via a control line using an external control device.When applying a feedforward equalizer (FFE) to extend the bandwidth of a VCSEL driver, it is desirable to provide effective bandwidth extension performance for multiple channels with a small number of wirings so that it is compatible with the CPO module.The FFE here is a circuit that emphasizes the edges of the signal waveform by adding a signal that has been given a certain amount of delay by a delay circuit to the reference differential signal output from the input buffer.

[0006] As a technique for improving the band extension performance of a signal, Patent Document 1 discloses an equalizer circuit including a first amplifier circuit, a second amplifier circuit to which an output signal of a filter circuit is input, and an adder circuit that adds the output signal of the first amplifier circuit and the output signal of the second amplifier circuit in reverse phase. Patent Document 2 discloses an FFE in which a cell is formed by combining an emitter follower circuit and a differential circuit, a sub-tap in which a plurality of cells are connected in multiple stages according to the delay amount is connected in parallel to a main tap, the final stage cell functions as a weighting circuit whose gain can be adjusted by coefficient setting, and the 50Ω termination resistors on the output side of the differential circuit and the input side of the emitter follower circuit in the transmission line between the plurality of cells are combined into a 25Ω termination resistor. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-129619 A [Patent Document 2] JP 2019-161393 A Summary of the Invention [Problem to be solved by the invention]

[0008] The equalizer circuit described in Patent Document 1 uses a filter circuit as a delay element, resulting in a large circuit scale and a complex circuit configuration. In order to change the frequency characteristics of the equalizer circuit, a current adjustment means for the current source circuit is provided, but the current value is adjusted by adjusting the current flowing through the current mirror circuit with a D / A converter, which further increases the circuit scale. A CPO module that is based on a multi-channel concept with many transmission channels requires a D / A converter for each channel, making it difficult to adopt due to mounting constraints. The FFE described in Patent Document 2 aims to improve gain in the high frequency range, and does not improve the band extension performance in accordance with the characteristics of the output side circuit, and is not suitable for the purpose of providing band extension performance to multiple channels of a CPO module. As the number of taps for providing band extension performance in the FFE increases, it becomes disadvantageous in terms of high density of the VCSEL driver chip, such as an increase in the delay circuit scale and a complicated signal line layout. There is a demand for an equalizer circuit that can provide band extension performance while suppressing an increase in circuit scale.

[0009] An object of the present invention is to provide an equalizer circuit, a laser driver circuit, a CPO module, and an optical communication system that are capable of providing a bandwidth extension performance with a simple configuration. [Means for solving the problem]

[0010] The equalizer circuit of the present invention is an equalizer circuit that shapes the waveform of a reference signal, and is characterized in that it comprises a delay signal generation circuit that generates one or more delay signals delayed from the reference signal, and a signal synthesis circuit that adds a delayed current signal synchronized with the delay signal in opposite phase to a reference current signal synchronized with the reference signal, and the delay signal generation circuit is composed of multiple stages of delay circuits.

[0011] According to the above configuration, by generating a delay time using multiple delay circuits, the delay signal generating circuit can be configured using a semiconductor circuit, so that the equalizer circuit can be made compact.

[0012] Here, it is preferable that the signal synthesis circuit of the equalizer circuit has a reference differential amplifier circuit and a delay differential amplifier circuit that share an output terminal, and the equalizer circuit has a current varying means for discretely varying the current value of at least one of the current sources of the reference differential amplifier circuit and the delay differential amplifier circuit. According to the above configuration, it is possible to realize a band extension effect with a plurality of characteristics by discretely varying the current value of the current source.

[0013] In addition, it is preferable that the current varying means of the equalizer circuit is configured to vary the current value by turning on and off the current source of the reference differential amplifier circuit or the delayed differential amplifier circuit with a binary control signal. With the above configuration, the control signal can be configured as a binary digital signal, so that it can be realized with a small-scale semiconductor circuit, and the entire circuit can be made compact.

[0014] Here, it is preferable that the delay differential amplifier circuit has a plurality of differential amplifier circuits each operated by a plurality of delay signals having different delay times. According to the above configuration, different band extension effects can be realized in accordance with the different delay times.

[0015] The laser driver circuit according to the present invention comprises an input buffer circuit which amplifies an external signal, the above-mentioned equalizer circuit which shapes the waveform of the output signal of the input buffer circuit and outputs it to the driver circuit, and a driver circuit which outputs a drive signal synchronized with the output of the equalizer circuit, and is characterized in that a laser diode is driven by the drive signal of the driver circuit.

[0016] According to the above configuration, the laser diode is driven by a band-stretched signal, making it possible to send a stable optical signal to a subsequent circuit.

[0017] A CPO module according to the present invention is characterized in that a plurality of the above-mentioned laser driver circuits and a plurality of laser diodes to which the output currents of the laser driver circuits are input are mounted on a substrate.Also, another CPO module according to the present invention is characterized in that it comprises a photodiode that receives an external optical signal and outputs a current signal, a transimpedance amplifier that converts the current signal output by the photodiode into an electric signal, a switch ASIC that processes the electric signal output by the transimpedance amplifier, the above-mentioned laser driver circuit that inputs the signal output by the switch ASIC, and a laser diode that is driven by the signal output by the laser driver circuit.

[0018] According to the above configuration, the input signal of the laser driver circuit can drive the laser diode with an output current whose band has been expanded, and a CPO module capable of high-speed and stable optical communication can be realized.

[0019] Here, the CPO module may have a control circuit for controlling the variable current means mounted on the board. According to the above configuration, the entire CPO module can be made compact.

[0020] An optical communication system according to the present invention is characterized by comprising the above-mentioned CPO module.

[0021] According to the above configuration, an optical communication system capable of high-speed and stable optical communication can be realized. Effect of the Invention

[0022] The equalizer circuit, the laser driver circuit, the CPO module, and the optical communication system according to the present invention can provide a band extension performance with a simple configuration. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a configuration diagram of a multi-channel VCSEL driver according to the present invention. [Diagram 2]1A and 1B are diagrams illustrating the configuration of a delay circuit that constitutes a delayed signal generating circuit of the present invention, where (a) is a block diagram of the delay circuit, and (b) is a circuit diagram of (a). [Diagram 3] FIG. 2 is a circuit diagram of a signal synthesis circuit according to the present invention. [Figure 4] 4 is an operation waveform diagram of the equalizer circuit of the present invention. [Diagram 5] FIG. 4 is a diagram showing an output voltage gain characteristic of the equalizer circuit of the present invention. [Figure 6] 4 is an output voltage waveform of an experimental result of the equalizer circuit of the present invention. [Figure 7] FIG. 2 is a configuration diagram of a CPO module of the present invention. [Figure 8] FIG. 13 is a configuration diagram of a CPO module according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, specific shapes, directions, values, etc. are examples for facilitating understanding of the present invention, and can be appropriately changed according to the application, purpose, specifications, etc. In addition, it is assumed from the beginning that the components of the embodiment and modified examples described below can be selectively combined.

[0025] First Embodiment A multi-channel VCSEL driver 400 according to a first embodiment of the present invention will be described with reference to Figs. 1 to 3. Fig. 1 is a configuration diagram of the multi-channel VCSEL driver 400. The multi-channel VCSEL driver 400 has a plurality of channels (TX1 to TX4). Each channel of the multi-channel VCSEL driver 400 includes VCSEL drivers 401 to 404. The VCSEL drivers 401 to 404 have the same configuration. The VCSEL drivers 401 to 404 of the present invention include an equalizer circuit having a band extension performance. The multi-channel VCSEL driver 400 and the VCSEL array 420 are mounted on one substrate to form a CPO module.

[0026] In this embodiment, a VCSEL array in which many VCSELs are integrated on the same semiconductor substrate is used as an optical signal transmitting element. VCSELs can operate at a low threshold current and can be directly modulated at high speed, making them effective as light sources in CPO modules. Laser oscillation occurs when a current above the threshold is supplied to the VCSEL from the VCSEL driver. Since the optical output power of the VCSEL increases approximately linearly with respect to the current above the threshold, it is possible to convert the modulated current signal into a modulated optical signal by inputting the modulated current signal to the VCSEL by the VCSEL driver.

[0027] Next, the VCSEL driver 401 will be described. The VCSEL driver 401 receives an external signal V p , V n and an input buffer circuit 410 that amplifies the output signal V INp , V INn The waveform-shaped signal V OUTp , V OUTn to the driver circuit 440, and an output signal V OUTp , V OUTn and a driver circuit 440 that outputs a drive signal synchronized with the VCSEL array 420.

[0028] The input buffer circuit 410 has a positive-phase input terminal and a negative-phase input terminal. The positive-phase input terminal of the input buffer circuit 410 receives an external signal V p The inverted input terminal receives the signal V P and the opposite phase signal V n The input buffer circuit 410 receives the signal V p and signal V n The amplified voltage is the differential signal V INp , V INn The differential signal V INp , V INn becomes a reference signal for the subsequent equalizer circuit 430.

[0029] The equalizer circuit 430 is a circuit that processes and adjusts the frequency characteristics of the signal output by the input buffer circuit 410 and extends the band of the signal. In this embodiment, the equalizer circuit 430 is a feed-forward equalizer (FFE). The FFE emphasizes the high-frequency components of the reference signal by synthesizing the reference signal and a delayed signal. The detailed operation of the equalizer circuit 430 will be described later.

[0030] The driver circuit 440 converts the signal V OUTp , V OUTn Input the signal V OUTp , V OUTn The driver circuit 440 outputs a drive signal synchronized with the VCSEL array 420. The VCSEL array 420 emits light (blinks) in response to the drive signal and outputs an optical signal.

[0031] The equalizer circuit 430 receives a reference signal, signal V INp , V INn and a signal synthesis circuit 434 that adds a delayed current signal synchronized with the delay signal in reverse phase to a reference current signal synchronized with the reference signal. The delay signal generation circuit 432 is composed of multiple delay circuits. Since the delay signal generation circuit 432 is configured to generate a delay signal using multiple delay circuits, it can be configured using a semiconductor circuit that can be mounted on a CPO module, and therefore the equalizer circuit 430 can be made smaller.

[0032] The delay signal generating circuit 432 includes delay blocks 432A and 432B connected in series. The delay block 432A delays the signal V INp , V INn (Reference signal) to delay time Δτ D1 The delayed signal V INp1 , V INn1 The delay block 432B outputs the signal (delayed signal) V INp1 , V INn1 from delay time Δτ D2 The delayed signal VINp2 , V INn2 The delay block 432B outputs the delayed signal V INp2 , V INn2 is the delay time Δτ of the delay block 432A. D1 The delay time Δτ of the delay block 432B D2 is added, and the signal V INp , V INn (Reference signal) Delay time Δτ D1 +Δτ D2 The delayed signal is delayed by the

[0033] 2A and 2B are diagrams showing the configuration of a delay circuit constituting the delayed signal generating circuit 432. Fig. 2A is a block diagram of the delay circuit, and Fig. 2B is a circuit diagram of the delay circuit. The delayed signal generating circuit 432 is configured by cascading the delay circuits shown in Fig. 2 in multiple stages.

[0034] The delay circuit shown in Figure 2(a) outputs a differential signal V inp , V inn Input the differential signal V outn , V outp As shown in Figure 2(b), the differential amplifier circuit is composed of a differential pair consisting of n-type MOSFETs T1 and T2, resistors R1 and R2 connected to the output terminals of the differential pair, and a current source I x A differential amplifier circuit generates a delay between the input signal and the output signal that is determined by the characteristics of the MOSFETs that make up the differential pair. Therefore, by cascading delay circuits in multiple stages, it is possible to configure a delay block that outputs a delayed signal with the desired delay time. If the delay time of a delay circuit is δt, then the delay time of a delay block consisting of n stages of cascaded delay circuits is Δτ=δt*n.

[0035] 3 shows a circuit diagram of the signal synthesis circuit 434. The signal synthesis circuit 434 is composed of a reference differential amplifier circuit 435 and a delay differential amplifier circuit 436. The reference differential amplifier circuit 435 and the delay differential amplifier circuit 436 share resistors R3 and R4. The reference differential amplifier circuit 435 and the delay differential amplifier circuit 436 each have current sources I0 to I4. Furthermore, the signal synthesis circuit 434 has a current varying means 437 that varies the current values ​​of the current sources I0 to I4 discretely. Here, "varying discretely" means that the current values ​​of the current sources are changed discontinuously, and in this embodiment, this means that the connection and non-connection states of the current sources I1 to I4 of the reference differential amplifier circuit 435 and the delay differential amplifier circuit 436 are changed by an on / off signal.

[0036] The equalizer circuit 430 of the present invention has a current varying means 437 that varies the current value of the current source of the reference differential amplifier circuit 435 or the delay differential amplifier circuit 436 in a discrete manner, so that it is possible to vary the frequency characteristic (band extension effect) of the output signal in a stepwise manner. Moreover, the equalizer circuit 430 of the present invention varies the band extension effect by a digital signal of an on / off signal. The current varying means 437 of the signal synthesis circuit 434 is configured to vary the current value by turning on and off the current sources I1 to I4 of the reference differential amplifier circuit 435 or the delay differential amplifier circuit 436 by a binary control signal. Therefore, the equalizer circuit 430 of the present invention does not increase in circuit scale and is suitable for a CPO module with strict mounting conditions. However, the configuration of the current varying means is not limited to this embodiment.

[0037] The reference differential amplifier circuit 435 includes a differential pair of n-type MOSFETs T3 and T4 and a control power supply V DDL The reference differential amplifier circuit 435 is composed of resistors R3 and R4 connected between the output terminals of the differential pair and the control ground GND, and current sources I0, I1, and I2 connected between the differential pair and the control ground GND. INp , V INn The reference current signal I Mn The reference current signal I is output to the n-type MOSFET T3, which is one of the differential pairs. Similarly, the reference current signal I MpThe reference current signal I Mn is the reference signal V INp , V INn The current is proportional to the sum of the currents of the current sources I0, I1, and I2.

[0038] The current source I0 of the reference differential amplifier circuit 435 is always connected to the differential pair, and the current sources I1 and I2 are connected to the control ground GND via the switches S1 and S2. The switches S1 and S2 are, for example, made of n-type MOSFETs, and are turned on and off by applying a voltage to their gate terminals. Control signals D[0] and D[1] are input to the gate terminals of the switches S1 and S2. The control signals D[0] and D[1] are digital signals of "0" and "1", and by turning the switches S1 and S2 on and off using the digital signals, the connection state and non-connection state of the current sources I1 and I2 to the differential pair can be switched. The reference current signal I Mn is a current proportional to the total current value of the current sources I0, I1, and I2. Therefore, the reference differential amplifier circuit 435 controls the reference current signal I Mn can be varied discretely.

[0039] The delayed differential amplifier circuit 436 has two differential amplifier circuits 436A and 436B. The differential amplifier circuit 436A is composed of n-type MOSFETs T5 and T6 that form a differential pair, and a current source I3 that is connected between the differential pair and the control ground GND. The output terminals of the differential pair are connected to resistors R3 and R4, and are shared with the reference differential amplifier circuit 435. The configuration of the differential amplifier circuit 436A is the same as that of the reference differential amplifier circuit 435. The differential amplifier circuit 436A receives a signal V INp1 , V INn1 The delayed current signal I F1p The delayed current signal I is output to the n-type MOSFET T6, which is one of the differential pairs. Similarly, the delayed current signal I F1n The signal V INp1 , V INn1is a delayed signal output by the delay block 432A (see FIG. 1) of the delayed signal generating circuit 432. Therefore, the differential amplifier circuit 436A receives the reference signal V INp , V INn Therefore, the delay time Δτ D1 Delayed current signal I F1p Output.

[0040] The current source I3 of the differential amplifier circuit 436A is connected in series with the switch S3 consisting of an n-type MOSFET. When the control signal D[2] is "1", the switch S3 is turned on and the current source I3 is connected to the differential pair, and when the control signal D[2] is "0", the switch S3 is turned off and the current source I3 is disconnected from the differential pair. The differential amplifier circuit 436A outputs the delayed current signal I F1p can be varied discretely.

[0041] The differential amplifier circuit 436B has a basic configuration similar to that of the differential amplifier circuit 436A. The differential amplifier circuit 436B receives the signal V output from the delay block 432B at the input terminals of the differential pair. INp2 , V INn2 is input, and the delay time Δτ D1 +Δτ D2 Delayed current signal I F2p is output to one n-type MOSFET T8 of the differential pair.

[0042] A switch S4 consisting of an n-type MOSFET is connected in series to the current source I4 of the differential amplifier circuit 436B. When the control signal D[3] is "1", the switch S4 is turned on and the current source I4 is connected to the differential pair, and when the control signal D[3] is "0", the switch S4 is turned off and the current source I4 is disconnected from the differential pair. The differential amplifier circuit 436B outputs the delayed current signal I F2p can be varied discretely.

[0043] The resistors R3 and R4 of the reference differential amplifier circuit 435 are shared with the delay differential amplifier circuit 436 (differential amplifier circuits 436A and 436B). Therefore, the voltage drop occurring in the resistor R3 is Mn and the delayed current signal I F1p , I F2p The composite current signal I TOTn Due to the symmetry of the configuration, a similar mechanism is used to determine the reference current signal I Mp and the delayed current signal I F1n , I F2n The composite current signal I is determined by TOTp occurs.

[0044] When the control signal D[2] is “1”, the current source I3 is connected to the differential pair, and the reference current signal I Mn and the delayed current signal I F1p As a result, the combined current signal I TOTn =I Mn +I F1p As a result, the reference signal V INp , V INn Signal V with rising / falling edges emphasized OUTp , V OUTn will be output.

[0045] When the control signal D[3] is “1”, the current source I4 is connected to the differential pair, and the composite current signal I TOTn =I Mn +I F2p A delayed current signal I F2p This makes it possible to obtain signals with different degrees of emphasis on the rising and falling edges.

[0046] The delay differential amplifier circuit 436 shown in FIG. INp , V INn For the delayed current signal (I F1p , I F2p ) can be output. MnThe delayed current signal (I F1p , I F2p ) to obtain a composite current signal I TOTn 3 is configured by two differential amplifier circuits 436A and 436B, but is not limited to this. The number of differential amplifier circuits may be one or three or more. In addition, the current sources I3 and I4 of the delay differential amplifier circuit 436 are described as being connected only one at a time, but the current sources I3 and I4 may be configured to be connected simultaneously. Appropriate changes are possible according to the desired band extension performance.

[0047] Here, the control signals D[0] to D[3] of the variable current means 437 can be configured as bit data for turning on and off the current source, and the control circuit can be configured with a clock signal and a shift register that holds the control signal, and can be realized with a small-scale semiconductor circuit. Therefore, it can be implemented on a chip, and is suitable for a CPO module with strict implementation constraints.

[0048] The equalizer circuit 430 of the present invention uses a delayed current signal (I F1p , I F2p ) can be made variable, it is possible to change the band extension effect stepwise. Mn By making the reference current signal I variable, it is possible to change the strength of the band extension effect by the delay differential amplifier circuit 436. Mn If the amplitude of the reference current signal I is increased, the delayed current signal becomes relatively small, and the band extension effect can be weakened. Mn If the amplitude of is reduced, the delayed current signal becomes relatively large, and the band extension effect can be enhanced.

[0049] The band extension effect of the equalizer circuit 430 will be further described. FIG. 4 shows the operation waveforms of the equalizer circuit 430, from the top to the bottom: (1) the reference signal V INp The reference current signal I Mn , (2) Delay time ΔτD1 The delayed signal V INn1 The delayed current signal I F1p , (3) Delay time Δτ D1 +Δτ D2 The delayed signal V INn2 The delayed current signal I F2p , (4) Composite current signal I TOTn (=I Mn +I F1p +I F2p ) waveform.

[0050] 4(a) to (c) show waveforms of different band extension effects. FIG. 4(a) shows the case where the control signals D[2]=0 and D[3]=0, and the current sources I3 and I4 of the delay differential amplifier circuit 436 are both disconnected. Therefore, the delay current signal I F1p , I F2p does not occur, so the composite current signal I TOTn is the reference current signal I Mn This state is called the FFE disabled state.

[0051] 4B shows the case where the control signals are D[2]=1 and D[3]=0, and the current source I3 of the differential amplifier circuit 436A is connected and the current source I4 of the differential amplifier circuit 436B is disconnected. Therefore, the delay time Δτ D1 The delayed current signal I F1p is the reference current signal I Mn is added to produce a composite current signal I TOTn The waveform in Fig. 4(b) has accentuated rising and falling edges. When the control signals D[2] = 1 and D[3] = 0, this is called FFE mode 1.

[0052] 4(c) shows the case where the control signals are D[2]=0 and D[3]=1, and the current source I4 of the differential amplifier circuit 436B is connected and the current source I3 of the differential amplifier circuit 436A is disconnected. Therefore, the delay time Δτ D1 +Δτ D2 The delayed current signal I F2p is the reference current signal I Mn Since the delay time is different from that of FFE mode 1, the composite current signal I TOTnWhen the control signals in Fig. 4(c) are D[2] = 0 and D[3] = 1, this is called FFE mode 2.

[0053] Reference current signal I Mn can be changed by the control signals D[0] and D[1]. The reference current signal I Mn The dashed line in indicates the amplitude when the control signals are D[0]=1 and D[1]=1. At this time, the reference differential amplifier circuit 435 is in a state in which all of the current sources I0, I1, and I2 are connected to the reference differential amplifier circuit 435, and the reference current signal I Mn The amplitude of the reference current signal I Mn The dashed lines in the figure indicate the amplitudes when the control signals are D[0]=0 and D[1]=0. At this time, only the current source I0 is connected to the reference differential amplifier circuit 435, and the reference current signal I Mn When only one of the control signals D[0] and D[1] is “1”, either the current source I1 or the current source I2 is connected, and the amplitude of the reference current signal I Mn takes an intermediate value between the maximum and minimum values. Therefore, by changing the values ​​of the control signals D[0] and D[1], the reference current signal I Mn It is possible to vary discretely between a maximum and a minimum value.

[0054] Reference current signal I Mn By changing the amplitude of the delayed current signal I F1p , I F2p The contribution of the reference current signal I Mn When the amplitude of is reduced, the band extension effect becomes relatively stronger, and the reference current signal I Mn Increasing the amplitude of the signal weakens the band-stretching effect.

[0055] Next, FIG. 5 shows the output voltage gain characteristic in the equalizer circuit 430 of this embodiment.

[0056] FIG. 5(a) shows the reference current signal I MnThis is the output voltage gain characteristic in FFE mode 1 (control signal D[2] = 1, D[3] = 0) when the amplitude of the reference current signal I Mn The amplitude of takes on four different values ​​depending on the values ​​of the control signals D[0] and D[1], and so the output voltage gain characteristic also has four different characteristics. For comparison, the characteristics when the FFE is disabled (control signals D[2] = 0, D[3] = 0) are shown with a dashed line, but in this case, the characteristics show a similar shape regardless of the values ​​of D[0] and D[1]. Compared to the characteristics when the FFE is disabled, the output voltage gain characteristic of FFE mode 1 shows an increase in gain on the high frequency side, confirming the band extension effect. The reference current signal I Mn By changing the frequency gain characteristic, a change in the frequency gain characteristic can be observed, and it is found that it is possible to obtain output voltage gain characteristics with different band extension effects.

[0057] FIG. 5(b) shows the reference current signal I Mn This shows the output voltage gain characteristics in FFE mode 2 (control signals D[2] = 0, D[3] = 1) when the amplitude of the FFE is changed. The dashed line indicates the FFE disabled state. As with FFE mode 1, an increase in gain on the high frequency side can be confirmed. It can also be seen that an output voltage gain characteristic with a different band extension effect can be obtained from FFE mode 1.

[0058] From the above, in addition to the different FFE modes, the reference current signal I Mn It can be seen that by changing the amplitude of , a number of output voltage gain characteristics can be obtained.

[0059] The equalizer circuit of the present invention selects either FFE mode 1 or FFE mode 2 and outputs a reference current signal I MnBy changing the amplitude of the control signal D[0] to D[3], various output voltage gain characteristics can be realized. Therefore, even if the output characteristics differ for each channel, band extension performance according to the channel characteristics can be obtained. Furthermore, even if the circuit characteristics of the rear stage of each channel change, the output characteristics can be adjusted to match the circuit characteristics of the rear stage. Therefore, the equalizer circuit of the present invention can obtain output voltage gain characteristics with different band extension effects simply by changing the on / off signals of the control signals D[0] to D[3]. As described above, the equalizer circuit of the present invention can flexibly adjust the frequency characteristics with a simple circuit configuration using control signals.

[0060] In the above description of the embodiment, the reference current signal I Mn We have explained two examples of FFE mode with variable reference current signal I Mn It is not essential to change the reference current signal I. Also, the number of FFE modes is not limited to two, and the number of FFE modes may be one, or three or more. Mn Being able to vary the FFE mode will increase the adjustment range of the bandwidth extension effect, and having multiple FFE modes will enable more fine adjustment; however, the specific settings can be determined based on the design conditions of the CPO module and the characteristics of the downstream circuit.

[0061] <Experimental Results> Next, the output voltage waveform (eye pattern) of the experimental results of the VCSEL driver manufactured by the 65 nm CMOS process at 32 Gb / s operation is shown in Figure 6. Figure 6(a) shows the output voltage waveform (eye pattern) of the VCSEL driver manufactured by the 65 nm CMOS process at 32 Gb / s operation. Mn (b) is the output voltage waveform when the amplitude of is maximum, (c) is the output voltage waveform when the control signals are D[0]=0, D[1]=1, and the reference current signal I Mn (c) is the output voltage waveform when the control signal is D[0]=0, D[1]=0, and the reference current signal I Mn The amplitude of the reference current signal I is at its minimum. Mn It can be observed that the band-extending effect changes when the amplitude of the signal is changed.

[0062] The height of the baseline of the output voltage waveform is hBL , the eye pattern opening height is h eye The band extension effect is h eye / h BL When evaluated based on the eye pattern opening height relative to the baseline height, the order of h is (a) ⇒ (b) ⇒ (c). eye / h BL In other words, it is possible to control the strength of the band extension effect by the control signals D[0] to D[3], which are digital signals.

[0063] <Second embodiment> Next, a CPO module using the multi-channel VCSEL driver 400 described in the first embodiment will be described.

[0064] Figure 7 shows a configuration diagram of a CPO module 10 of the present invention. The CPO module 10 has the function of receiving an optical signal from the outside, processing the optical / electrically converted electrical signal, converting the electrical signal into an optical signal, and transmitting the optical signal to the outside via an optical fiber. The CPO module 10 in Figure 7 shows a basic unit for optical input / output, and when applied to an optical communication system, multiple input / output channels are implemented on the CPO module.

[0065] The CPO module 10 includes a photodiode 20 that receives an optical signal from the outside and outputs a current signal, a transimpedance amplifier (TIA) 22 that converts and amplifies the current signal output by the photodiode 20 into a voltage signal, a switch ASIC 30 that processes the voltage signal output by the TIA 22, a laser driver circuit 40 that inputs the signal output by the switch ASIC 30, and a laser diode 42 that is driven by the signal output by the laser driver circuit 40. The photodiode 20 and the TIA 22 correspond to an optical receiver that receives an optical signal from the outside and converts it into an electrical signal. The laser driver circuit 40 and the laser diode 42 correspond to an optical transmitter that outputs an optical signal corresponding to the electrical signal to the outside. The switch ASIC 30 processes the electrical signal from the optical receiver and transmits it to the optical transmitter. In the CPO module 10, the laser driver circuit 40 corresponds to one of the VCSEL drivers 401 to 404 in the multi-channel VCSEL driver 400, and the laser diode 42 corresponds to one of the laser diodes that configure the VCSEL array 420. A control circuit (such as a shift register that holds a clock signal and a control signal) for changing the bandwidth extension performance of the equalizer circuit 430 is built into the VCSEL driver chip or another chip, or is mounted as a dedicated chip and implemented on the CPO module 10.

[0066] Each element of the CPO module 10 is disposed on a motherboard 50, and is connected by an interposer 44, wiring 45, vias 46, sockets 54, etc. Hereinafter, these connection elements are also referred to as the interposer 44, etc.

[0067] 8 is a configuration diagram of a CPO module 10A according to another embodiment of the present invention. In the CPO module 10A, a laser driver circuit 40 and a laser diode 42 are mounted vertically on a substrate with an interposer 44 between them. The CPO module 10A further includes a signal input unit 47 of an external switch ASIC and an optical fiber 48 for extracting the optical output of the laser diode 42 to the outside. The laser driver circuit 40, the laser diode 42, and the signal input unit 47 from the switch ASIC are electrically connected by the interposer 44, etc. The CPO module 10A corresponds to an optical transmitter.

[0068] The laser driver circuit 40 (VCSEL driver) receives an electrical signal from an external switch ASIC and drives a laser diode 42 (VCSEL array). The laser driver circuit 40 (VCSEL driver) includes the above-mentioned equalizer circuit, and drives the laser diode 42 (VCSEL array) with a signal that has an expanded band of the input signal. This improves the high-frequency characteristics of the signal, enabling high-speed optical communication. The control circuit for changing the band expansion performance of the equalizer circuit is mounted on the CPO module 10A, but is not particularly limited thereto.

[0069] 7 and 8 show the configurations of the CPO modules 10 and 10A, but the CPO module of the present invention is not limited to these forms. Also, the CPO module 10A uses a VCSEL array as the electrical / optical signal conversion element, but is not limited to this. The laser diode of the CPO module may be an edge-emitting laser.

[0070] A CPO module is implemented with multiple channels. Therefore, as the number of channels increases, the number of input lines, such as high-frequency signal lines and control lines, also increases, requiring high-density mounting of channels. For this reason, each channel is susceptible to electromagnetic interference from other channels. In addition, it is possible that each channel may not achieve the desired characteristics due to variations in optical element characteristics and mounting conditions.

[0071] Therefore, it is desirable to be able to change the operating conditions for each channel independently via a control line using an external control device so that the operating conditions for each channel are optimized. However, as described above, a large number of wirings occupy the interposer, making it difficult to increase the number of control line systems. Since the control signal can be configured as a binary digital signal, the present invention can be realized with a small-scale semiconductor circuit, and the entire circuit can be made smaller while securing the necessary control lines.

[0072] In this invention, in order to optimize the operating conditions for each channel of the CPO module, it is possible to give each channel a band extension performance. More specifically, the FFE is adopted as an equalizer circuit, and the output frequency characteristics by the FFE can be changed.

[0073] The equalizer circuit, laser driver circuit, and CPO module described above are used in optical communication systems, and enable an increase in the transmission capacity of a switch device used in communication within a data center in a cyber-physical system. It goes without saying that the equalizer circuit, laser driver circuit, and CPO module of the present invention can be applied to various optical communication systems.

[0074] It should be noted that the present invention is not limited to the above-described embodiment and its modified examples, and various modifications and improvements are possible within the scope of the matters described in the claims of this application. [Explanation of symbols]

[0075] 10, 10A CPO module, 20 photodiode, 22 transimpedance amplifier (TIA), 30 switch ASIC, 40 laser driver circuit (VCSEL driver), 42 laser diode (VCSEL array), 44 interposer, 45 wiring, 46 via, 48 optical fiber, 50 motherboard, 54 socket, 400 multi-channel VCSEL driver, 401 to 404 VCSEL driver, 410 input buffer circuit, 420 VCSEL array, 430 equalizer circuit, 432 delay signal generation circuit, 434 signal synthesis circuit, 435 reference differential amplifier circuit, 436 delay differential amplifier circuit, 440 driver circuit

Claims

1. An equalizer circuit for shaping a waveform of a reference signal, a delay signal generating circuit for generating one or more delay signals delayed from the reference signal; a signal synthesis circuit that adds a delayed current signal synchronized with the delayed signal in reverse phase to a reference current signal synchronized with the reference signal; Equipped with The delay signal generating circuit is composed of multiple delay circuits. Equalizer circuit.

2. the signal synthesis circuit has a reference differential amplifier circuit and a delay differential amplifier circuit which share an output terminal; a current varying means for discretely varying a current value of at least one of the current sources of the reference differential amplifier circuit and the delay differential amplifier circuit; 2. The equalizer circuit of claim 1.

3. the current varying means is configured to vary the current value by turning on and off the current source of the reference differential amplifier circuit or the delay differential amplifier circuit in response to a binary control signal; 3. The equalizer circuit according to claim 2.

4. the delay differential amplifier circuit has a plurality of differential amplifier circuits each operated by a plurality of the delay signals having different delay times; 4. The equalizer circuit according to claim 3.

5. an input buffer circuit for amplifying an external signal; The equalizer circuit according to any one of claims 1 to 4, which shapes the waveform of a signal output by the input buffer circuit and outputs the signal; a driver circuit that outputs a drive signal synchronized with an output of the equalizer circuit; Equipped with driving a laser diode with the drive signal of the driver circuit; Laser driver circuit.

6. A plurality of laser driver circuits according to claim 5; a plurality of laser diodes to which the output currents of the laser driver circuits are respectively input; A CPO (Co-Packaged Optics) module mounted on a substrate.

7. A control circuit for controlling the current varying means is further mounted on the substrate. The CPO module of claim 6.

8. An optical communication system comprising the CPO module according to claim 6.

9. a photodiode that receives an external optical signal and outputs a current signal; a transimpedance amplifier that converts the current signal output by the photodiode into an electrical signal; a switch ASIC for processing the electrical signal output by the transimpedance amplifier; 6. A laser driver circuit according to claim 5, which receives a signal output from the switch ASIC; a laser diode driven by a signal output from the laser driver circuit; A CPO module comprising:

10. A control circuit for controlling the current varying means is further mounted on the substrate. The CPO module of claim 9.

11. An optical communication system comprising the CPO module according to claim 9.

Images