Semiconductor device

Abstract

To provide a semiconductor device where a storage capacity is large; miniaturization or high integration can be achieved; reliability is high; power consumption is low; or operation speed is fast.SOLUTION: In a semiconductor device, an open part reaching a first conductive layer is provided to a first insulation layer, a second conductive layer, a second insulation layer, and a third conductive layer provided onto the first conductive layer sequentially. In the open part of the second conductive layer, a third insulation layer, a first electric charging accumulation layer, a fourth insulation layer, an oxide semiconductor layer, a fifth insulation layer, a second electric charging accumulation layer, a sixth insulation layer, and a fourth conductive layer are provided in this order close to a side wall of the open part. The first and third conductive layers function as one and the other of a source electrode and a drain electrode of a transistor; the fourth conductive layer functions as a first control gate; and the second conductive layer functions as a second control gate.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of the semiconductor device or the memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a display device, a light-emitting device, a power storage device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs (Central Processing Units), memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and have electrodes that serve as connection terminals. Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0005] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are also attracting attention as other materials.

[0006] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0007] In addition, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further increasing the density of integrated circuits. There is also a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0008] Furthermore, Non-Patent Document 2 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO.

[0009] Moreover, Patent Document 5 discloses a nonvolatile memory using a floating gate. Moreover, Patent Document 6 discloses a nonvolatile memory having an oxide semiconductor layer. Moreover, as shown in Patent Document 7, in a nonvolatile semiconductor memory device, memory transistors can be arranged three-dimensionally. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] JP 2013-211537 A [Patent Document 5] JP 2009-295971 A [Patent Document 6] JP 2011-124563 A [Patent Document 7] JP 2007-266143 A [Non-patent literature]

[0011] [Non-Patent Document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 [Non-Patent Document 2] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO:FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp.50-150 Summary of the Invention [Problem to be solved by the invention]

[0012] An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device with large storage capacity. Another object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device. Another object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device with low power consumption. Another object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device with high operation speed. Another object of one embodiment of the present invention is to provide a novel transistor, semiconductor device, or memory device. Another object of one embodiment of the present invention is to provide a manufacturing method of the above transistor, semiconductor device, or memory device.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0014] One embodiment of the present invention includes a first conductive layer, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, an oxide semiconductor layer, a fourth conductive layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a first charge storage layer, and a second charge storage layer, wherein the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer each have an opening that reaches the first conductive layer, and the third insulating layer has a region in contact with a sidewall of the opening in the first insulating layer, a region in contact with a sidewall of the opening in the second conductive layer, and a region in contact with a top surface of the first conductive layer, and the first charge storage layer has a region that covers the sidewall of the opening in the second conductive layer with the third insulating layer sandwiched therebetween, and the fourth insulating layer the fourth insulating layer has a region sandwiched between the oxide semiconductor layer and the first charge storage layer, the oxide semiconductor layer has a region in contact with a top surface of the first conductive layer, a region covering the sidewall of the opening of the second conductive layer with the third insulating layer, the first charge storage layer, and the fourth insulating layer sandwiched therebetween, and a region in contact with the third conductive layer, the fourth conductive layer has a region located within the opening of the second conductive layer, the second charge storage layer has a region sandwiched between the oxide semiconductor layer and the fourth conductive layer, the fifth insulating layer has a region sandwiched between the oxide semiconductor layer and the second charge storage layer, and the sixth insulating layer has a region sandwiched between the second charge storage layer and the fourth conductive layer.

[0015] In the above aspect, the fourth insulating layer and the fifth insulating layer preferably have one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0016] In the above aspect, at least one of the first charge storage layer and the second charge storage layer preferably contains one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing these metal elements, or an alloy combining these metal elements.

[0017] In the above aspect, at least one of the first charge storage layer and the second charge storage layer preferably contains a metal nitride or a metal oxide.

[0018] In the above embodiment, at least one of the first charge storage layer and the second charge storage layer preferably contains one or more elements selected from silicon and germanium.

[0019] In the above aspect, at least one of the first charge storage layer and the second charge storage layer preferably has one or more selected from silicon nitride and silicon oxynitride.

[0020] In the above aspect, it is preferable that the first conductive layer and the third conductive layer function as one and the other of a source electrode and a drain electrode of the transistor, the fourth conductive layer function as a first control gate of the transistor, and the second conductive layer function as a second control gate of the transistor. Effect of the Invention

[0021] According to one embodiment of the present invention, a transistor, semiconductor device, or storage device with large storage capacity can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or storage device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or storage device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or storage device with low power consumption can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or storage device with high operation speed can be provided. According to one embodiment of the present invention, a novel transistor, semiconductor device, or storage device can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or storage device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0023] [Figure 1] Fig. 1(A) is a perspective view illustrating an example of a semiconductor device, Fig. 1(B) is a plan view illustrating an example of a semiconductor device, Fig. 1(C) is a cross-sectional view illustrating an example of a semiconductor device, and Fig. 1(D) is a circuit diagram of one embodiment of the present invention. [Diagram 2] 2A to 2E are cross-sectional views showing an example of a semiconductor device. [Diagram 3] 3A and 3B are cross-sectional views showing an example of a semiconductor device, and Fig. 3C is a perspective view showing an example of a semiconductor device. [Figure 4] Fig. 4(A) is a plan view showing an example of a semiconductor device, and Fig. 4(B) and Fig. 4(C) are cross-sectional views showing an example of the semiconductor device. [Diagram 5] Fig. 5(A) is a cross-sectional view showing an example of a semiconductor device, Fig. 5(B) is a plan view showing an example of a semiconductor device, Fig. 5(C) and Fig. 5(D) are cross-sectional views showing an example of a semiconductor device. [Figure 6] 6(A) and 6(B) are cross-sectional views showing an example of a semiconductor device. [Figure 7] 7A and 7B are circuit diagrams showing an example of a semiconductor device. [Figure 8] Fig. 8A is a circuit diagram showing an example of the operation of the semiconductor device, and Fig. 8B shows an example of an Id-Vgs curve of the semiconductor device. [Figure 9] 9A to 9C are timing charts illustrating an operation example of a semiconductor device. [Figure 10] Fig. 10A is a circuit diagram showing an example of the operation of the semiconductor device, and Fig. 10B is a timing chart showing an example of the operation of the semiconductor device. [Figure 11] Fig. 11A is a circuit diagram showing an example of the operation of the semiconductor device, and Fig. 11B is a timing chart showing an example of the operation of the semiconductor device. [Figure 12] FIG. 12 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 13] 13A to 13C are timing charts illustrating an operation example of a semiconductor device. [Figure 14] 14A and 14B are timing charts showing an operation example of a semiconductor device. [Figure 15] FIG. 15 is a circuit diagram showing an example of the operation of the semiconductor device. [Figure 16] 16A to 16C are timing charts illustrating an operation example of a semiconductor device. [Figure 17] 17A and 17C are timing charts showing an example of the operation of a semiconductor device, and FIG 17D is a diagram showing an example of an Id-Vgs curve. [Figure 18] 18A to 18D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19] 19A to 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20]20A to 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] FIG. 21 is a cross-sectional view showing an example of a semiconductor device. [Figure 22] 22A to 22D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. [Figure 23] 23A to 23D are cross-sectional views illustrating examples of oxide semiconductors. [Figure 24] FIG. 24 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 25] 25A and 25B are perspective views illustrating a configuration example of a semiconductor device. [Figure 26] FIG. 26 is a block diagram illustrating the CPU. [Figure 27] 27(A) and 27(B) are perspective views of a semiconductor device. [Figure 28] 28(A) and 28(B) are perspective views of the semiconductor device. [Figure 29] 29(A) and 29(B) are diagrams showing various storage devices by hierarchical level. [Diagram 30] 30(A) and 30(B) are diagrams showing an example of an electronic component. [Diagram 31] Fig. 31(A) to Fig. 31(C) are diagrams showing an example of a mainframe computer. Fig. 31(D) is a diagram showing an example of space equipment. Fig. 31(E) is a diagram showing an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0026] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0028] A transistor is a type of semiconductor element and can realize a function of amplifying a current or voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor, and a transistor having silicon in a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region.

[0031] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0032] Note that impurities in a semiconductor refer to anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O In some cases, a junction (also referred to as a junction) may be formed.

[0033] In this specification and the like, an oxynitride refers to a material having a composition containing more oxygen than nitrogen, and a nitride oxide refers to a material having a composition containing more nitrogen than oxygen.

[0034] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used to analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in the film. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0035] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0036] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0037] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it allows transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements having various functions.

[0038] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source in an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0039] In this specification, the normally-on characteristic refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the normally-off characteristic refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0040] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0041] In this specification, the phrase "top surface shapes are substantially the same" refers to at least a portion of the contours of the stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case, it may also be said that the top surface shapes are substantially the same. In addition, when the top surface shapes are the same or substantially the same, it can also be said that the ends are aligned or substantially aligned, or that the side ends are aligned or substantially aligned.

[0042] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0044] In this specification and the like, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0045] In this specification and the like, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as, A has a region that covers B.

[0046] In this specification and the like, when it is stated that A overlaps with B, at least a portion of A overlaps with B. Therefore, for example, this can be rephrased as saying that A has a region that overlaps with B.

[0047] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, a film, or an electrode is divided due to the shape of the surface on which it is formed (for example, a step or the like).

[0048] In addition, in the drawings and the like related to this specification, arrows indicating the X direction, Y direction, and Z direction may be attached. In addition, in this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." In addition, the X direction, the Y direction, and the Z direction are directions that intersect with each other. For example, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other.

[0049] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0050] A semiconductor device of one embodiment of the present invention includes a first conductive layer, a second conductive layer, and an oxide semiconductor layer.

[0051] The first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer. The first insulating layer has a first opening that reaches the first conductive layer. The oxide semiconductor layer covers a top surface of the first conductive layer and a side surface of the first insulating layer in the first opening. Note that the opening is also referred to as an opening.

[0052] The second conductive layer has a second opening overlapping the first opening, and the oxide semiconductor layer covers a side surface of the second conductive layer within the second opening.

[0053] A semiconductor device according to one embodiment of the present invention includes a third conductive layer, a fourth conductive layer, a first charge accumulation layer, and a second charge accumulation layer.

[0054] The third conductive layer overlaps the oxide semiconductor layer in the first opening, with the first charge storage layer sandwiched therebetween.

[0055] A fourth conductive layer is located on the first insulating layer and below the second conductive layer. The fourth conductive layer has a third opening overlapping the first opening. The oxide semiconductor layer overlaps the fourth conductive layer in the third opening with the second charge storage layer therebetween.

[0056] The first conductive layer serves as one of a source electrode and a drain electrode of the transistor, the second conductive layer serves as the other of the source electrode and the drain electrode of the transistor, the third conductive layer serves as a first gate electrode of the transistor, and the fourth conductive layer serves as a second gate electrode of the transistor.

[0057] The charge storage layer can store charges, can release the stored charges, and can hold the stored charges.

[0058] The transistor included in the semiconductor device of one embodiment of the present invention can store data by accumulating charge in the charge accumulation layer. The transistor included in the semiconductor device of one embodiment of the present invention can function as a memory device. In addition, the transistor included in the semiconductor device of one embodiment of the present invention can be used as a multi-value memory because it has a plurality of charge accumulation layers. Thus, a semiconductor device with a large storage capacity can be realized by using the transistor of one embodiment of the present invention. The transistor of one embodiment of the present invention includes a first charge accumulation layer in which writing of data is controlled by a first gate electrode and a second charge accumulation layer in which writing of data is controlled by a second gate electrode, so that the amount of data that can be stored per transistor can be increased.

[0059] A semiconductor device of one embodiment of the present invention includes a transistor that functions as a memory element. The semiconductor device of one embodiment of the present invention can store data written in the semiconductor device for a long period of time even after power supplied to the memory element is cut off. The semiconductor device of one embodiment of the present invention can be expressed as a nonvolatile semiconductor device. Furthermore, the transistor included in the semiconductor device of one embodiment of the present invention can rewrite written data. The transistor included in the semiconductor device of one embodiment of the present invention may be called an electrically erasable programmable read only memory (EEPROM).

[0060] In this specification, the term "in a cross-sectional view" is used, but may be specifically rephrased as "in a cross-sectional view from the same direction." For example, when explaining the relationship between multiple configurations, the relationship in a cross-sectional view from the same direction is explained. In this case, the relationship between the multiple configurations can be explained using one cross-sectional view.

[0061] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights (for example, heights in a direction perpendicular to a substrate surface or an insulating plane on which the transistor is provided), and a current flows in the height direction through a semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0062] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and thus the occupation area can be significantly reduced as compared with a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0063] In this specification, the term "ends coincide" refers to at least a portion of the contours of stacked layers overlapping in a plan view. For example, this term includes cases where the upper and lower layers are processed using the same mask pattern or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "ends coincide" is also used.

[0064] In general, it may be difficult to clearly distinguish between a "complete match" and a "substantially match." For this reason, in this specification and elsewhere, "match" may include both a complete match and a substantially match.

[0065] <Configuration Example 1 of Semiconductor Device> Fig. 1(A) is a perspective view of a semiconductor device including a transistor 500. Fig. 1(B) is a plan view of the transistor 500 shown in Fig. 1(A), and Fig. 1(C) is a cross-sectional view corresponding to a dashed line C1-C2 shown in Fig. 1(B). Note that some elements are omitted from the perspective view shown in Fig. 1(A) to make the view easier to see.

[0066] The transistor 500 has a function as a memory element. In particular, it can function as a nonvolatile memory element. By arranging memory cells including the transistor 500 in a matrix, a memory device capable of storing a large amount of data can be configured. The memory cell including the transistor 500 can function as, for example, a NOR memory cell, a NAND memory cell, or the like. Note that the transistor 500 may be called a memory transistor. The transistor 500 may be expressed as a nonvolatile memory. A semiconductor device including the transistor 500 may be called a nonvolatile semiconductor device, a nonvolatile memory device, or the like.

[0067] The transistor 500 includes an oxide semiconductor layer 530, a charge storage layer 552, a conductive layer 560, a charge storage layer 555, and a conductive layer 114. The conductive layer 560 has a columnar shape. The charge storage layer 552 is provided to surround the conductive layer 560, the oxide semiconductor layer 530 is provided to surround the conductive layer 560 with the charge storage layer 552 interposed therebetween, the charge storage layer 555 is provided to surround the conductive layer 560 with the charge storage layer 552 and the oxide semiconductor layer 530 interposed therebetween, and the conductive layer 114 is provided to surround the conductive layer 560 with the charge storage layer 552, the oxide semiconductor layer 530, and the charge storage layer 555 interposed therebetween. The charge storage layer 552, the oxide semiconductor layer 530, the charge storage layer 555, and the conductive layer 114 each have a cylindrical shape.

[0068] 1A to 1C, the conductive layer 560 can be expressed as having a cylindrical shape, and the charge storage layer 552, the oxide semiconductor layer 530, the charge storage layer 555, and the conductive layer 114 can be expressed as having a hollow cylindrical shape. Here, the hollow cylinder refers to a structure in which a first cylinder is hollowed out by a second cylinder, the first cylinder and the second cylinder have the same center, and the second cylinder has a smaller diameter than the first cylinder. It can also be expressed that the conductive layer 560 is disposed in a hollow portion of the hollow cylindrical shapes of the charge storage layer 552, the oxide semiconductor layer 530, the charge storage layer 555, and the conductive layer 114.

[0069] The conductive layer 560 and the conductive layer 114 have an overlapping region with the oxide semiconductor layer 530 sandwiched therebetween.

[0070] The charge storage layer 552 has a region sandwiched between the oxide semiconductor layer 530 and the conductive layer 560. The insulating layer 551 has a region sandwiched between the oxide semiconductor layer 530 and the charge storage layer 552. The insulating layer 553 has a region sandwiched between the charge storage layer 552 and the conductive layer 560.

[0071] In the transistor 500, the oxide semiconductor layer 530 functions as a semiconductor layer, the conductive layer 560 functions as a first gate electrode, and the conductive layer 114 functions as a second gate electrode.

[0072] The conductive layer 560 and the conductive layer 114 may each be called a control gate or a control gate electrode. Here, the conductive layer 560 is called a first control gate, and the conductive layer 114 is called a second control gate. When the charge storage layer 552 has high conductivity, the charge storage layer 552 may be called a floating gate or a floating gate electrode. Similarly, when the charge storage layer 555 has high conductivity, the charge storage layer 555 may be called a floating gate or a floating gate electrode.

[0073] Insulating layers are provided between the charge storage layer and the semiconductor layer, and between the charge storage layer and the control gate. Insulating layers 551 and 554 are shown as insulating layers between the charge storage layer and the semiconductor layer, and insulating layers 553 and 556 are shown as insulating layers between the charge storage layer and the control gate in Fig. 1(B) and Fig. 1(C). Note that boundaries between these insulating layers and boundaries between these insulating layers and insulating layers in other regions (such as interlayer insulating layers) are not clearly shown in Fig. 1(B) and Fig. 1(C).

[0074] Each of the insulating layer 551, the charge storage layer 552, and the insulating layer 553 has a region located between the oxide semiconductor layer 530 and the conductive layer 560. The insulating layer 551, the charge storage layer 552, and the insulating layer 553 are arranged in order from closest to the oxide semiconductor layer 530.

[0075] The insulating layer 554, the charge storage layer 555, and the insulating layer 556 each have a region located between the oxide semiconductor layer 530 and the conductive layer 114. The insulating layer 554, the charge storage layer 555, and the insulating layer 556 are arranged in order from closest to the oxide semiconductor layer 530.

[0076] An example of a transistor to which the structure of the transistor 500 can be applied is illustrated in FIG.

[0077] The transistor M1 shown in FIG. 1D has a first control gate (represented as CG1 in the drawing) and a second control gate (represented as CG2 in the drawing). The transistor M1 also has a first charge storage layer (represented as Ch1 in the drawing) whose charge storage and release are controlled by the first control gate, and a second charge storage layer (represented as Ch2 in the drawing) whose charge storage and release are controlled by the second control gate. The first control gate, the second control gate, the first charge storage layer, and the second charge storage layer may correspond to the conductive layer 560, the conductive layer 114, the charge storage layer 552, and the charge storage layer 555 of the transistor 500, respectively. Alternatively, the first control gate, the second control gate, the first charge storage layer, and the second charge storage layer may correspond to the conductive layer 114, the conductive layer 560, the charge storage layer 555, and the charge storage layer 552, respectively, in some cases.

[0078] Writing information to the transistor 500 can be performed by injecting carriers into at least one of the charge storage layer 552 and the charge storage layer 555, or discharging carriers from at least one of the charge storage layer 552 and the charge storage layer 555. By injecting carriers into the charge storage layer or discharging carriers from the charge storage layer, the threshold value of the transistor 500 can be changed, and the value of a current flowing between the source and drain during reading can be changed. Injection or discharge of carriers into or from the charge storage layer 552 can be performed by using a tunnel current flowing through an insulating layer 551 located between the oxide semiconductor layer 530 and the charge storage layer 552. In addition, injection or discharge of carriers into or from the charge storage layer 555 can be performed by using a tunnel current flowing through an insulating layer 554 located between the oxide semiconductor layer 530 and the charge storage layer 555. Each of the insulating layer 551 and the insulating layer 554 may be called a tunnel insulating layer.

[0079] 1C shows an example in which the charge storage layer 555 and the conductive layer 114 are located at the same height, but the charge storage layer 555 may have one or both of a region higher (region with a larger Z coordinate) and a region lower (region with a smaller Z coordinate) than the conductive layer 114. FIG 2A shows an example in which the charge storage layer 555 has a region lower than the conductive layer 114, and FIG 2B shows an example in which the charge storage layer 555 has both a higher region and a lower region.

[0080] As shown in FIG. 2C, the charge accumulation layer 555 may have a region located over the conductive layer 114 in addition to a region between the conductive layer 114 and the oxide semiconductor layer 530 .

[0081] 3A and 3B, the transistor 500 preferably includes a conductive layer 520 and a conductive layer 540. The conductive layer 520 functions as one of a source electrode and a drain electrode, and the conductive layer 540 functions as the other of the source electrode and the drain electrode.

[0082] The oxide semiconductor layer 530 is preferably in contact with the conductive layer 520 and the conductive layer 540. In the structure shown in Figure 3(A), the oxide semiconductor layer 530 is in contact with a side surface of the conductive layer 520 and a side surface of the conductive layer 540. In addition, in Figure 3(B), the oxide semiconductor layer 530 has a region in contact with a top surface of the conductive layer 520. Figure 3(C) is a perspective view corresponding to the cross section shown in Figure 3(B).

[0083] 2D, the oxide semiconductor layer 530 can be in contact with the top surface and the side surface of the conductive layer 540. With such a structure, the contact area can be increased and the contact resistance can be reduced.

[0084] 2E, the insulating layer 554 covers the side surfaces of the conductive layer 560. Although the oxide semiconductor layer 530 covers the side surfaces and the top surface of the conductive layer 540, the oxide semiconductor layer 530 is not in contact with the side surfaces because the insulating layer 554 is provided therebetween, but is in contact with the top surface.

[0085] The structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 4A to 4C. FIG. 4A is a plan view of a semiconductor device including a transistor 500. FIG. 4B is a cross-sectional view corresponding to the dashed dotted line A1-A2 shown in FIG. 4A. FIG. 4C is a cross-sectional view corresponding to the dashed dotted line A3-A4 shown in FIG. 4A. FIG. 5A is an enlarged view of FIG. 4B. Note that some elements are omitted in the plan view of FIG. 4A for clarity. Some elements may also be omitted in the subsequent plan views.

[0086] 4A to 4C includes an insulating layer 210 over a substrate (not shown), a transistor 500 over the insulating layer 210, an insulating layer 481 over the insulating layer 210, an insulating layer 482 over the insulating layer 481, an insulating layer 483 over the insulating layer 482, and an insulating layer 283 and an insulating layer 285 over the transistor 500. The insulating layer 210, the insulating layer 481, the insulating layer 482, the insulating layer 483, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0087] 4A to 4C, the transistor 500 includes a conductive layer 520, a conductive layer 540, an oxide semiconductor layer 530, an insulating layer 551, a charge storage layer 552, an insulating layer 553, a conductive layer 560, an insulating layer 554, a charge storage layer 555, an insulating layer 556, and a conductive layer 114. The conductive layer 520 and the conductive layer 540 are located at different heights. An insulating layer 481, an insulating layer 482, and an insulating layer 483 are located between the conductive layer 520 and the conductive layer 540.

[0088] Moreover, the insulating layer 556 has a region overlapping with the upper surface of the conductive layer 520. In this region, the insulating layer 556 is sandwiched between the conductive layer 520 and the charge storage layer 555. This makes it possible to prevent the conductive layer 520 and the charge storage layer 555 from being in direct contact with each other. If the conductive layer 520 and the charge storage layer 555 were to be in direct contact with each other, the charge held in the charge storage layer 555 would flow to the conductive layer 520.

[0089] The conductive layer 114 and the insulating layer 482 are provided over the insulating layer 481. The insulating layer 483 is provided over the conductive layer 114 and the insulating layer 482.

[0090] 4A to 4C and 5A, the insulating layer 481 is located over the conductive layer 520, the conductive layer 114 is located over the insulating layer 481, the insulating layer 483 is located over the conductive layer 114, and the conductive layer 540 is located over the insulating layer 483. Openings (opening 590c, opening 590d, opening 590e, and opening 590f) reaching the conductive layer 520 are provided in the insulating layer 481, the conductive layer 114, the insulating layer 483, and the conductive layer 540.

[0091] The insulating layer 481 has an opening 590c that reaches the upper surface of the conductive layer 520. Furthermore, the conductive layer 114 has an opening 590d. In a plan view, the openings 590c and 590d overlap. Furthermore, it is preferable that the side surface of the opening 590c and the side surface of the opening 590d are smoothly connected. This can improve coverage when an insulating layer, a conductive layer, a semiconductor layer, or the like is covered from the side surface of the opening 590c to the side surface of the opening 590d.

[0092] The conductive layer 560 has at least a region located in the opening 590e. In the opening 590e, the conductive layer 560 overlaps with the conductive layer 114 with the oxide semiconductor layer 530 therebetween.

[0093] The insulating layer 556 covers the side surface of the opening 590c of the insulating layer 481 and the side surface of the opening 590d of the conductive layer 114. The insulating layer 556 is preferably in contact with the side surface of the opening 590c of the insulating layer 481 and the side surface of the opening 590d of the conductive layer 114. The charge storage layer 555 covers the side surface of the opening 590c of the insulating layer 481 and the side surface of the opening 590d of the conductive layer 114 with the insulating layer 556 sandwiched therebetween.

[0094] As shown in Figures 4(B), 4(C), and 5(A), the conductive layer 114, the insulating layer 482, the insulating layer 556, and the charge storage layer 555 are preferably provided so that their upper surfaces are at approximately the same height.

[0095] The insulating layer 483 has an opening 590e. The opening 590e overlaps with the opening 590c in a plan view. In addition, the opening 590e is preferably included in the opening 590c in a plan view.

[0096] The conductive layer 540 has an opening 590f. The opening 590f overlaps with the opening 590c in a plan view. In addition, the opening 590f is preferably included in the opening 590c in a plan view.

[0097] In addition, it is preferable that the side surface of opening 590e and the side surface of opening 590f are smoothly connected, which can improve coverage when an insulating layer, a conductive layer, a semiconductor layer, or the like is applied from the side surface of opening 590e to the side surface of opening 590f.

[0098] The insulating layer 554 covers a side surface of the opening 590e of the insulating layer 483 and a side surface of the opening 590f of the conductive layer 540. The insulating layer 554 is preferably in contact with the side surface of the opening 590e of the insulating layer 483 and the side surface of the opening 590f of the conductive layer 540. The insulating layer 554 also covers a side surface of the opening 590c of the insulating layer 481 and a side surface of the opening 590d of the conductive layer 114, with the charge storage layer 555 and the insulating layer 556 sandwiched therebetween.

[0099] The oxide semiconductor layer 530 has a region in contact with the top surface of the conductive layer 520 in the opening 590c. The oxide semiconductor layer 530 has a region in contact with the top surface of the conductive layer 540. The oxide semiconductor layer 530 covers the insulating layer 554 in the openings 590c, 590d, 590e, and 590f.

[0100] An insulating layer 551, a charge storage layer 552, and an insulating layer 553 are provided in this order over the oxide semiconductor layer 530. A conductive layer 560 is provided over the insulating layer 553.

[0101] The conductive layer 560 has a region in the opening 590e that faces the conductive layer 114 with the oxide semiconductor layer 530 therebetween.

[0102] 4A to 4C, the insulating layer 554 has a region overlapping with a top surface of the conductive layer 520 and has an opening 290c overlapping with the conductive layer 520. By providing the opening 290c in the insulating layer 554, the oxide semiconductor layer 530 can be in contact with the conductive layer 520 through the opening 290c.

[0103] In the semiconductor device of one embodiment of the present invention, the oxide semiconductor layer 530 can be formed using a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor.

[0104] Regions of the oxide semiconductor layer 530 which are in contact with the conductive layer 520 and the conductive layer 540 preferably function as low-resistance regions.

[0105] The oxide semiconductor layer 530 is provided inside an opening 590c in the insulating layer 481, inside an opening 590d in the conductive layer 114, and inside an opening 590e in the insulating layer 483. The transistor 500 has a structure in which current flows in a vertical direction because one of the source electrode and the drain electrode (the conductive layer 520 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 540 here) is located above.

[0106] Writing information to the transistor 500 is performed by changing the amount of charge accumulated in the charge accumulation layer. Carriers such as electrons and holes can be accumulated in the charge accumulation layer. For example, a conductor can be used as the charge accumulation layer. When a conductor is used as the charge accumulation layer, the conductor is preferably wrapped in an insulator. Alternatively, for example, an insulator having a function of trapping carriers can be used as the charge accumulation layer. For example, by applying a positive high potential to the gate with respect to the source or drain, electrons are injected from the oxide semiconductor layer 530 through the insulating layer between the oxide semiconductor layer and the charge accumulation layer, and are accumulated in the charge accumulation layer. Furthermore, for example, by applying a negative high potential to the gate with respect to the source or drain, electrons are released from the charge accumulation layer to the oxide semiconductor layer 530 through the insulating layer. In addition, the charge accumulation layer can hold the accumulated charges.

[0107] When the oxide semiconductor layer 530 is in contact with not only the side surface but also the top surface of the conductive layer 540, the area of ​​contact between the oxide semiconductor layer 530 and the conductive layer 540 can be made larger than when, for example, the oxide semiconductor layer 530 is in contact with the side surface but not the top surface of the conductive layer 540. Thus, the contact resistance between the oxide semiconductor layer 530 and the conductive layer 540 can be made smaller.

[0108] In addition, in the transistor 500, the charge storage layer 552 covers both the side surface and the top surface of the conductive layer 540, and thus the area covered by the charge storage layer 552 can be made larger than when only one of the side surface or the top surface is covered. When carriers are injected from the oxide semiconductor layer 530 to the charge storage layer 552 due to an electric field between the gate and the drain when data is written to the transistor 500, the efficiency of writing can be improved by increasing the area covered by the conductive layer 540 by the charge storage layer 552. With the structure of the transistor of one embodiment of the present invention, the efficiency of writing can be improved compared to that of a planar transistor.

[0109] In addition, in a planar transistor in which a semiconductor layer is formed in an island shape, the island-shaped semiconductor layer has an end at the boundary between the channel formation region and the drain formation region. When heat is generated due to a current flowing through the transistor, the end of the island-shaped semiconductor layer in the channel width direction may be significantly affected by the heat. Such heat may cause a decrease in the breakdown voltage, and the influence may be more significant in a transistor with a large channel width because the amount of current is large. On the other hand, in the transistor 500, since the semiconductor layer can be provided along the sidewall of the opening of the insulating layer, the semiconductor layer can be configured not to have an end at the boundary between the channel formation region and the drain formation region. Therefore, the source-drain resistance of the transistor can be improved. This also makes it possible to increase the breakdown voltage between the gate-drain or between the gate-source. Therefore, even when a high electric field is applied between the drain-source, between the gate-source, between the gate-drain, or between the gate-drain during writing and erasing, the deterioration of the transistor can be suppressed and the reliability of the memory element can be improved.

[0110] 4(A) to 4(C), an end of the charge storage layer 552 is located outside an end of the conductive layer 560 in the cross section shown in FIG. 4(C). That is, the end of the charge storage layer 552 is located outside an end of the conductive layer 560 in the direction along the Y axis, and the upper surface of the charge storage layer 552 has a region that is not covered by the conductive layer 560. With the configuration shown in FIG. 4(C), the insulating layer 551, the charge storage layer 552, and the insulating layer 553 are sandwiched between the conductive layer 560 and the conductive layer 540, so that a leakage current between the conductive layer 560 and the conductive layer 540 can be suppressed.

[0111] 4B, the end of the charge storage layer 552 is located inside the end of the conductive layer 560. This is because the conductive layer 560 extends in the direction along the X-axis.

[0112] Note that, even in the direction along the Y-axis, the end of the charge storage layer 552 may be located inside the end of the conductive layer 560. With this configuration, it is possible to increase the area where the charge storage layer 552 and the conductive layer 560 overlap, and to increase the capacitance value between the charge storage layer 552 and the conductive layer 560. Increasing the capacitance value may reduce the voltage required for writing, and may improve the efficiency of writing to the memory element.

[0113] The area occupied by the transistor 500, specifically, for example, the area of ​​the transistor as viewed from the top, is roughly determined depending on the width of the opening 590c in the insulating layer 481, the width of the opening 590e in the insulating layer 483, and the like. In the transistor 500, the channel formation region, the source region, and the drain region can be arranged at different heights, and therefore the area occupied by the transistor can be reduced compared to a transistor in which the semiconductor layer is arranged on a plane and the channel formation region, the source region, and the drain region are arranged on the plane. Therefore, the semiconductor device can be highly integrated. By using the semiconductor device of one embodiment of the present invention for a memory device, the memory capacity per unit area can be increased.

[0114] In the transistor 500, the conductive layer 520 functioning as one of a source electrode and a drain electrode and the conductive layer 540 functioning as the other electrode are disposed at different heights. The conductive layer 520 can be shared by a plurality of transistors 500, and the conductive layer 540 can also be shared by a plurality of transistors 500. The conductive layer shared by a plurality of transistors can also be extended and used as a wiring.

[0115] In the semiconductor device of one embodiment of the present invention, the conductive layers 520 and 540 are disposed at different heights, and therefore even when the conductive layers 520 and 540 are each extended and used as wirings, the wiring using the conductive layer 520 and the wiring using the conductive layer 540 can be disposed so as to cross each other without being short-circuited, thereby enabling the area of ​​the memory cell to be reduced.

[0116] 5B shows a cross section in the XY plane including the insulating layer 481. The oxide semiconductor layer 530 surrounds the entire periphery of the conductive layer 560 via the insulating layer 551, the charge storage layer 552, and the insulating layer 553. When a gate electric field is applied from the conductive layer 560, a channel formation region of the transistor 500 can be formed in the entire oxide semiconductor layer 530 surrounding the periphery of the conductive layer 560. Note that FIG. 5B can also be said to be a cross section in the XY plane including the channel formation region of the oxide semiconductor layer 530.

[0117] The periphery of the oxide semiconductor layer 530 is surrounded by the conductive layer 114 with the insulating layer 554, the charge storage layer 555, and the insulating layer 556 interposed therebetween. When a gate electric field is applied from the conductive layer 114, a channel formation region of the transistor 500 can be formed in the entire oxide semiconductor layer 530 whose periphery is surrounded by the conductive layer 114.

[0118] FIG. 5A shows an enlarged view of FIG. 4B. The channel length of the transistor 500 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 500 is determined by the sum of the thicknesses of the insulating layer 481, the insulating layer 483, and the conductive layer 114 on the conductive layer 520. In FIG. 5A, the channel length L of the transistor 500 is indicated by a dashed double-headed arrow. The channel length L is the distance between the end of the region where the oxide semiconductor layer 530 and the conductive layer 520 contact each other and the end of the region where the oxide semiconductor layer 530 and the conductive layer 540 contact each other in a cross-sectional view. In other words, the channel length L roughly corresponds to the sum of the side length of the opening 590c of the insulating layer 481, the side length of the opening 590d of the conductive layer 114, the side length of the opening 590e of the insulating layer 483, and the side length of the opening 590f of the conductive layer 540 in a cross-sectional view.

[0119] The width of the opening 590c is width D. The width of the opening 590e is width D2. The widths D and D2 may vary in the depth direction. For example, they may be the widths at the top and bottom ends of the openings in the insulating layer. Alternatively, they may be the widths at half the depth of the openings in the insulating layer.

[0120] The sidewalls of the openings 590c, 590e, etc. are preferably perpendicular or nearly perpendicular to the top surface of the formation surface of the layer in which the openings are provided (if the top surface of the formation surface is uneven, to the top surface of the layer below that has less unevenness on the top surface, or to the top surface of the substrate surface). By forming the openings in such a shape, the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized.

[0121] The angle between the upper surface of conductive layer 520 (or the upper surface of insulating layer 210, or the upper surface of the substrate) and the sidewall of opening 590c of insulating layer 481 is defined as angle θ481. The angle between the upper surface of conductive layer 520 (or the upper surface of insulating layer 210, or the upper surface of the substrate, or the upper surface of conductive layer 114) and the sidewall of opening 590e of insulating layer 483 is defined as angle θ483. Each of θ481 and θ483 is preferably an angle of 90 degrees or close to 90 degrees. For example, it is preferably an angle between 75 degrees or more and 90 degrees or less.

[0122] In addition, θ481 and θ483 may be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees, respectively. By tapering the sidewall of the opening, the coverage of the film formed on the sidewall of the opening can be improved.

[0123] In a planar transistor, the minimum value of the channel length is limited by the exposure accuracy of photolithography, making further miniaturization difficult, but in a transistor included in a semiconductor device of one embodiment of the present invention, the channel length can be set to a value smaller than the minimum value limited by the exposure accuracy of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more) to correspond to the film thicknesses of the insulating layers 481 and 483, etc. As a result, the on-state current of the transistor 500 can be increased, and the response speed of the memory element can be improved.

[0124] Furthermore, since the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by the thicknesses of the insulating layers 481, 483, and the like over the conductive layer 520, even when the channel length is set to be 60 nm or more, the area occupied by the transistor, specifically, the area of ​​the transistor as viewed from above, is roughly determined by the width of an opening provided in the insulating layers 481, 483, and the like. As described later, the width D2 of the opening 590e is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. For example, even when the channel length is set to 150 nm, the width of the opening 590e can be set to be narrower than 150 nm. That is, the width of the opening can be narrower than the channel length of the transistor, which reduces the area occupied by the transistor and enables high integration of the semiconductor device. By increasing the channel length, the withstand voltage between the source and drain during writing to the memory element can be improved, thereby improving reliability.

[0125] Note that by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the insulating layers 481 and 483, the formation of openings in the insulating layers 481 and 483, and the like.

[0126] Therefore, the channel length of a transistor included in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0127] In addition, when writing and erasing data, a high voltage may be applied between the drain and source of the transistor 500. Therefore, it is preferable that the channel length of the transistor 500 is long enough to withstand the high voltage between the drain and source. Therefore, the channel length of the transistor 500 may be, for example, 10 nm or more, 20 nm or more, or 30 nm or more. As described above, the occupation area of ​​the transistor 500 is roughly determined according to the width of the opening 590c, etc., and even if the channel length is increased, there is almost no effect on the occupation area of ​​the transistor. Therefore, it can be said that the transistor 500 has a configuration that can achieve both high withstand voltage and integration.

[0128] As shown in FIG. 5B, the oxide semiconductor layer 530 and the conductive layer 560 are provided concentrically. Thus, a side surface of the conductive layer 560 provided at the center faces a side surface of the oxide semiconductor layer 530. That is, the entire circumference of the oxide semiconductor layer 530 becomes a channel formation region in a plan view. In this case, for example, the channel width of the transistor 500 is determined by the length of the outer periphery of the oxide semiconductor layer 530. That is, it can be said that the channel width of the transistor 500 is determined by the widths of the openings 590e, 590f, and the like (diameters when the openings are circular in a plan view). In FIG. 5B, the channel width W of the transistor 500 is indicated by a double-headed arrow of a dashed line. By increasing the width D2 of the opening 590e, the channel width per unit area can be increased, and the on-current can be increased.

[0129] When the opening is formed by photolithography, the minimum limit of the width D2 of the opening 590e depends on the exposure accuracy of the photolithography. The width D2 of the opening 590e is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening is circular in plan view, the width D2 of the opening corresponds to the diameter of the opening, and the channel width W can be calculated as "D2 x π". In FIG. 5B and the like, the width D of the opening 590c is the width D2 plus twice the film thickness of the charge storage layer 555 and twice the film thickness of the insulating layer 556.

[0130] Furthermore, the current driving capability of the transistor 500 can be increased by making the channel length L of the transistor 500 smaller than the channel width W of the transistor 500. As a result, for example, the write speed of the memory element can be increased.

[0131] Furthermore, by making the channel length L of the transistor 500 larger than the channel width W of the transistor 500, the source-drain breakdown voltage of the transistor can be increased. This can therefore increase the rewrite endurance of the memory element, for example.

[0132] Moreover, by forming the openings 590c, 590f, and 590e to have a circular shape in a plan view, the oxide semiconductor layer 530 and the conductive layer 560 are provided concentrically. This allows an electric field from the conductive layer 560 to be applied approximately uniformly to the oxide semiconductor layer 530. By forming the opening 590f to have a circular shape, the oxide semiconductor layer 530 and the opening of the conductive layer 114 are provided concentrically. This allows an electric field from the conductive layer 114 to be applied approximately uniformly to the oxide semiconductor layer 530.

[0133] Note that in this embodiment, the openings 590c, 590f, 590e, and the like are circular in plan view, but the present invention is not limited thereto. For example, the openings may be substantially circular such as ellipse, polygonal such as rectangle, or polygonal such as rectangle with rounded corners in plan view. By using a circular or substantially circular shape without corners or a polygonal shape with rounded corners, electric fields from the conductive layer 560 and the conductive layer 114 to the oxide semiconductor layer 530 can be prevented from concentrating at the corners.

[0134] Note that the conductive layer 520 may have a recess as shown in FIG. 5C. In FIG. 5C, the conductive layer 520 has a recess overlapping with an opening 590c. The opening 590c and the recess of the conductive layer 520 form a continuous opening. The oxide semiconductor layer 530 is provided along the bottom and side surfaces of the recess of the conductive layer 520. Thus, the electric field of the drain can be received from the bottom and side surfaces. Thus, writing efficiency can be improved.

[0135] 5D shows an example in which the recess of the conductive layer 520 is deeper. In FIG. 5D, the oxide semiconductor layer 530, the insulating layer 551, the charge storage layer 552, the insulating layer 553, and at least a part of the conductive layer 560 are formed in the recess. With this structure, the gate electric field of the conductive layer 560 can be easily applied up to the vicinity of the conductive layer 520 of the oxide semiconductor layer 530.

[0136] 5D, the conductive layer 520 and the conductive layer 560 have regions that overlap with each other with the oxide semiconductor layer 530, the insulating layer 551, the charge storage layer 552, and the insulating layer 553 sandwiched therebetween. This makes it easier for a gate electric field to be applied to a channel formation region of the oxide semiconductor layer 530, and in some cases, the write voltage of the memory element can be reduced. Thus, the power consumption of the semiconductor device can be reduced in some cases.

[0137] By reducing the thickness of the insulating layer 551, the voltage of the first control gate when writing to the transistor 500 can be reduced. Similarly, by reducing the thickness of the insulating layer 554, the voltage of the second control gate when writing to the transistor 500 can be reduced. By reducing the voltage, the power consumption of the memory device can be reduced. In addition, the time required for writing can be shortened. Thus, the operating speed of the memory device can be increased.

[0138] On the other hand, if the insulating layer 551 is too thin, there is a concern that the carriers stored in the charge storage layer 552 may be reduced by leakage current. Similarly, if the insulating layer 554 is too thin, there is a concern that the carriers stored in the charge storage layer 555 may be reduced by leakage current. The reduction in carriers due to leakage current deteriorates the retention characteristics of the memory device.

[0139] Therefore, the thickness of the insulating layer 551 and the insulating layer 554 can be, for example, greater than or equal to 1 nm and less than or equal to 20 nm. For the insulating layer 551 and the insulating layer 554, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, or the like is preferably used.

[0140] Furthermore, the insulating layer 553 is preferably thicker than the insulating layer 551, for example. This reduces the tunnel current flowing through the insulating layer 553, and suppresses the charge of the charge storage layer 552 from escaping to the first control gate side. Similarly, the insulating layer 556 is preferably thicker than the insulating layer 554, for example. The insulating layers 553 and 556 can each have a thickness of, for example, 8 nm to 30 nm. For the insulating layers 553 and 556, it is preferable to use, for example, silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or the like.

[0141] Materials that can be used for the charge storage layers 552 and 555 will be described later.

[0142] <Modification 1 of the semiconductor device> FIG 6(A) shows a modified example of FIG 4(C). In the configuration example shown in FIG 6(A), an insulating layer 554 is provided mainly along the sidewalls of openings 590c, 590d, 590e, and 590f. The insulating layer 554 shown in FIG 6(A) can be formed by, for example, anisotropic etching. The insulating layer 554 shown in FIG 6(A) can be called a sidewall or sidewall insulating layer.

[0143] 6A, the height of the upper end of the insulating layer 554 can be lower than the top surface of the conductive layer 540. With such a structure, the oxide semiconductor layer 530 can be in contact with not only the top surface of the conductive layer 540 but also the side surface thereof.

[0144] 4B, 4C, 6A, and the like, the height of the upper end of the charge storage layer 555 is approximately equal to the height of the upper end of the conductive layer 114. As a result, the charge storage layer 555 can be provided only in a region sandwiched between the conductive layer 114 and the oxide semiconductor layer 530.

[0145] <Modification 2 of Semiconductor Device> 6B, the height of the top end of the charge accumulation layer 555 may not be substantially equal to the height of the top end of the conductive layer 114, and the charge accumulation layer 555 may be provided also over the conductive layer 114. In the example shown in FIG. 6B, the insulating layer 482 is not provided.

[0146] 4C, the conductive layer 114, the charge storage layer 555, the insulating layer 556, and the insulating layer 482 are provided so that their top surfaces are substantially flush with each other, whereas in FIG. 6B, the charge storage layer 555 and the insulating layer 556 have a region that covers the top surface of the conductive layer 114. Also, in FIG. 6B, a step is formed between the sidewall of the charge storage layer 555 and the sidewall of the insulating layer 483.

[0147] 6B, the manufacturing process can be simplified and the manufacturing cost can be reduced because the step of forming the insulating layer 482 is unnecessary, the step of processing the conductive layer 114, the charge storage layer 555, the insulating layer 556, and the insulating layer 482 so that the top surfaces of the conductive layer 114, the charge storage layer 555, the insulating layer 556, and the insulating layer 482 are approximately aligned, and a step of minimizing a step between a sidewall of the charge storage layer 555 and a sidewall of the insulating layer 483 is not performed. On the other hand, in the structure illustrated in FIG. 4C and the like, the charge storage layer 555 is not provided in a region other than a region sandwiched between the conductive layer 114 and the oxide semiconductor layer 530, and an electric field from the conductive layer 114 can be easily applied uniformly to the charge storage layer 555, which can improve the reliability of the memory element.

[0148] <Example of memory cell array configuration> An application example of a memory cell including a transistor 500 will be described with reference to FIG.

[0149] 7A shows an example of a circuit diagram of a memory cell array 601 including a plurality of NOR-type memory cells 602. The memory cell 602 includes a transistor M1. The above-described transistor 500 can be used as the transistor M1.

[0150] In the memory cell 602, one of the source and drain of the transistor M1 is connected to a wiring BL, and the other is connected to a wiring SL. A first control gate of the transistor M1 is connected to a wiring WL1, and a second control gate of the transistor M1 is connected to a wiring WL2. The wirings WL1 and WL2 function as word lines, and the wiring BL functions as a bit line.

[0151] The memory cell array 601 has a plurality of wirings BL, a plurality of wirings SL, a plurality of wirings WL1, and a plurality of wirings WL2. The transistors M1 of the memory cells 602 arranged in the same column are connected to one wiring BL. The transistors M1 of the memory cells 602 arranged in the same row are connected to one wiring SL. The transistors M1 of the memory cells 602 arranged in the same row are connected to one wiring WL1. The transistors M1 of the memory cells 602 arranged in the same row are connected to one wiring WL2.

[0152] In addition, the same signal can be applied simultaneously to the control gate and one of the source and drain of the transistors M1 of the memory cells 602 arranged in the same row. When the transistors M1 are n-channel transistors, for example, data can be erased simultaneously from the memory cells 602 arranged in the same row by applying a negative potential to one of the source and drain with respect to the control gate.

[0153] 7B shows an example of a circuit diagram of a memory cell array 611 including a plurality of NAND memory cells 612. The memory cell 612 includes transistors M[0] to M

[31] , a transistor S1, and a transistor S2 connected in series. The transistors M[0] to M

[31] can be the transistors 500 described above.

[0154] In each of the transistors M[0] to M

[31] , the transistor S1, and the transistor S2, one of the source and the drain is hereinafter referred to as a first terminal, and the other of the source and the drain is hereinafter referred to as a second terminal. The first terminal of the transistor M[k] is connected to the second terminal of the transistor M[k-1], and the second terminal of the transistor M[k] is connected to the first terminal of the transistor M[k+1]. Here, k is an integer between 2 and 30.

[0155] A first terminal of the transistor S1 is connected to the line SL, a second terminal of the transistor S2 is connected to the first terminal of the transistor M[0], and a first terminal of the transistor S2 is connected to the second terminal of the transistor M

[31] , and a second terminal of the transistor S2 is connected to the line BL.

[0156] The memory cell array 611 has a plurality of wirings BL. One wiring BL is connected to one memory cell 612. The memory cell array 611 also has wirings SG1, SG2, wirings WL1[0] to WL1

[31] , and wirings WL2[0] to WL2

[31] .

[0157] The wiring SG1 is connected to the gate of the transistor S1 of each of the memory cells 612. The wiring SG2 is connected to the gate of the transistor S2 of each of the memory cells 612. The wirings WL1[0] to WL1

[31] are connected to first gates of the transistors M[0] to M

[31] of each of the memory cells 612. The wirings WL2[0] to WL2

[31] are connected to second gates of the transistors M[0] to M

[31] of each of the memory cells 612.

[0158] The wiring SG1 and the wiring SG2 function as wirings for selecting the memory cell 612 when performing operations such as writing, reading, and erasing.

[0159] Note that although FIG. 6 illustrates a configuration in which one memory cell 612 is connected to one wiring, one embodiment of the present invention is not limited to this.

[0160] <Operation example 1-1 of semiconductor device> An operation example of the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0161] FIG. 8A shows four states of the memory cell 602. Specifically, the four states are states in which one of the four data items D_11, D_01, D_10, and D_00 is stored. FIG. 8B shows an example of an Id-Vgs curve of the transistor M1 in a state in which the four data items are stored. The drain current Id is the drain current of the transistor M1, and the voltage Vgs is the gate-source voltage of the transistor M1. The threshold voltage of the transistor changes depending on the stored data. Therefore, when the gate-source voltage Vgs is set to a certain value (Vr in FIG. 8B), the drain current Id changes depending on the stored state. The stored data can be identified by reading the drain current Id.

[0162] 9A to 9C show timing charts corresponding to the operation of the memory cell 602. FIG.

[0163] First, an operation example of the semiconductor device will be described with reference to FIG.

[0164] 8(A) and the like, a first control gate (indicated as CG1 in the figure) is connected to a wiring WL1, and a second control gate (indicated as CG2 in the figure) is connected to a wiring WL2. A wiring BL is connected to one of the source and drain, and a wiring SL is connected to the other.

[0165] [Data D_11] At time t0 shown in FIG. 9A, in a state where data D_11 is stored, low potential L, low potential L, and potential V2 are applied to the wiring WL1, wiring WL2, and wiring BL, respectively. Also, the wiring SL is in a floating state. The state at time t0 corresponds to the state where data D_11 is stored in FIG. 8A (memory cell 602 shown in the upper left). At this time, no charge is stored in the charge storage layer (hereinafter referred to as the first charge storage layer) located between the first control gate and the semiconductor layer. Also, no charge is stored in the charge storage layer (hereinafter referred to as the second charge storage layer) located between the second control gate and the semiconductor layer.

[0166] [Action Wr1_1: Data D_01] Next, as shown in FIG. 9(A), at time t1, the potential applied to the wiring WL1 is changed from a low potential L to a high potential H, the potential applied to the wiring BL is changed from potential V2 to potential V1, and a low potential L is applied to the wiring SL, thereby changing the state in which data D_11 is stored to a state in which data D_01 (memory cell 602 shown in the upper right of FIG. 8(A)) is stored (operation Wr1_1). Data D_01 is a state in which charges are stored in the first charge storage layer. Note that in the following, the charges stored in the charge storage layer are, for example, electrons.

[0167] [Action Wr1_2: Data D_00] 9A, at time t2, the potential applied to the wiring WL2 is changed from a low potential L to a high potential H, thereby changing the state in which data D_01 is stored to a state in which data D_00 (memory cell 602 shown in the lower right of FIG. 8A) is stored (operation Wr1_2). Data D_00 is a state in which charges are stored in the first charge storage layer and the second charge storage layer.

[0168] <Semiconductor device operation example 1-2> FIG. 9(A) shows an example in which charges are stored in the first charge storage layer and then the second charge storage layer. However, by using the operation shown in FIG. 9(B), charges may be stored in the second charge storage layer and then the first charge storage layer.

[0169] [Data D_11] At time t10 shown in FIG. 9(B), data D_11 is stored, similarly to time t0 shown in FIG. 9(A).

[0170] [Action Wr2_1: Data D_10] At time t11 shown in Fig. 9B, the potential applied to the wiring WL2 is changed from a low potential L to a high potential H, the potential applied to the wiring BL is changed from a potential V2 to a potential V1, and a low potential L is applied to the wiring SL, thereby changing the state in which data D_11 is stored to a state in which data D_10 (memory cell 602 shown in the lower left of Fig. 8A) is stored (operation Wr2_1). Data D_10 is a state in which charges are stored in the second charge storage layer.

[0171] [Action Wr2_2: Data D_00] Next, at time t12 shown in Figure 9 (B), the potential applied to the wiring WL1 can be changed from a low potential L to a high potential H, thereby changing the state in which data D_10 is stored to a state in which data D_00 is stored (operation Wr2_2).

[0172] <Semiconductor device operation example 1-3> Figures 9(A) and 9(B) show examples in which the timing of the operation of providing charges to the first charge storage layer and the second charge storage layer is different, but the operation shown in Figure 9(C) may be used to accumulate charges in the first charge storage layer and the second charge storage layer by the same operation.

[0173] [Data D_11] At time t20 shown in FIG. 9C, data D_11 is stored, similarly to time t0 shown in FIG. 9A.

[0174] [Action Wr3: Data D_00] At time t21 shown in Figure 9 (C), the potential applied to wiring WL1 and wiring WL2 is changed from a low potential L to a high potential H, the potential applied to wiring BL is changed from potential V2 to potential V1, and a low potential L is applied to wiring SL, thereby changing the state in which data D_11 is stored to a state in which data D_00 is stored (operation Wr3).

[0175] In addition, in Figures 8(A), 9(A), 9(B), 9(C), etc., as examples of voltages, the low potential L, the high potential H, the potential V1, and the potential V2 are shown in the figures as 0 V, 10 V, 5 V, and 10 V, respectively, but the respective voltages are not limited to these.

[0176] In addition, when charges are stored in the charge storage layer of the transistor M1, the Id-Vgs curve shifts to a positive voltage side, i.e., when charges are stored in the charge storage layer, the voltage required for writing also becomes larger.

[0177] When the above-described transistor 500 is used as the transistor M1, for example, the conductive layer 560 can be used as the control gate CG1, and the conductive layer 114 can be used as the control gate CG2. Here, the area of ​​the conductive layer 560 overlapping with the oxide semiconductor layer 530 is larger than that of the conductive layer 114. Therefore, writing using the control gate CG1 has higher writing efficiency.

[0178] Therefore, it is preferable to perform writing using the control gate CG2 first, and then, in a state in which the voltage required for writing becomes higher due to the shift in the Id-Vgs curve, to perform writing using the control gate CG1, which has higher writing efficiency. That is, in terms of efficiency, it may be preferable to perform operations Wr2-1 and Wr2-2 in order rather than performing the above-mentioned operations Wr1-1 and Wr1-2 in order.

[0179] <Operation example 2-1 of semiconductor device> 10 and 11, after the charge is stored in the charge storage layer, the voltage applied to the control gate is reduced to such an extent that the stored charge is not lost, thereby reducing the power consumption of the semiconductor device. Also, the life of the memory cell 602 may be extended.

[0180] FIG. 10A shows a circuit diagram corresponding to the operation of the memory cell 602, and FIG. 10B shows a timing chart corresponding to the operation shown in FIG. 10A.

[0181] [Data D_11] At time t30 shown in FIG. 10(B), data D_11 is stored, similarly to time t0 shown in FIG. 10(A).

[0182] [Data D_01] Next, at time t31 shown in Fig. 10B, the state where data D_11 is stored is changed to the state where data D_01 is stored. For an explanation of the period from time t30 to time t31, the explanation of the period from time t0 to time t1 in Fig. 9A can be referred to.

[0183] [Data D_00] 10B, the potential applied to the wiring WL2 is changed from a low potential L to a high potential H, thereby changing the state in which data D_01 is stored to a state in which data D_00 is stored. At this time, the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, thereby reducing the power consumption of the semiconductor device. Here, the potential difference between the wiring WL1 and the wiring BL (the difference between the voltage of the low potential L and the voltage of the potential V1) can be set to a value at which the charges stored in the first charge storage layer are not released (erased), that is, the stored data is not rewritten.

[0184] <Operation example 2-2 of semiconductor device> FIG. 11A shows a circuit diagram corresponding to the operation of the memory cell 602, and FIG. 11B shows a timing chart corresponding to the operation shown in FIG. 11A.

[0185] [Data D_11] At time t40 shown in FIG. 11B, like time t10 shown in FIG. 9B, data D_11 is stored.

[0186] [Data D_10] Next, at time t41 shown in Fig. 11(B), the state changes from one in which data D_11 is stored to one in which data D_10 is stored. For an explanation of the period from time t40 to time t41, see the explanation of the period from time t10 to time t11 in Fig. 9(B).

[0187] [Data D_00] 11B, the potential applied to the wiring WL1 is changed from a low potential L to a high potential H, thereby changing the state in which data D_10 is stored to a state in which data D_00 is stored. At this time, the potential applied to the wiring WL2 is changed from a high potential H to a low potential L, thereby reducing the power consumption of the semiconductor device. Here, the potential difference between the wiring WL2 and the wiring BL (the difference between the voltage of the low potential L and the voltage of the potential V1) may be set to a value at which the charges stored in the second charge storage layer are not released (erased), that is, the stored data is not rewritten.

[0188] <Operation example 3-1 of semiconductor device> 12 shows four states of the memory cell 602 (states in which four data items, data D_11, data D_01, data D_10, and data D_00, are stored). Also, FIGS. 13A to 13C show timing charts corresponding to the operation of the memory cell 602. Note that the operation shown in FIGS. 12 and 13A to 13C may be called an erase operation because it releases electrons stored in the charge storage layer.

[0189] Although the emission of electrons will be described here, holes may be accumulated in addition to or instead of the emission of electrons.

[0190] First, an example of the operation of the semiconductor device will be described with reference to FIG. 12 and FIG.

[0191] [Data D_00] At time t50 shown in FIG. 13A, data D_00 is stored, and data can be stored using the operations described with reference to FIGS.

[0192] [Action Er1_1: Data D_01] Next, at time t51 shown in Figure 13(A), the potential applied to the wiring WL2 is changed from a high potential H to a low potential L, the potential applied to the wiring BL is changed from a potential V1 to a potential V2, and the wiring SL is put into a floating state, thereby releasing the charge in the second charge storage layer and changing the state from one in which data D_00 is stored to one in which data D_01 is stored (memory cell 602 shown in the upper right of Figure 12) (operation Er1_1).

[0193] [Action Er1_2: Data D_11] Next, at time t52 shown in Figure 13(A), the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, thereby discharging the charge in the first charge storage layer and changing the state from one in which data D_01 is stored to one in which data D_11 is stored (memory cell 602 shown in the lower right of Figure 12) (operation Er1_2).

[0194] <Operation example 3-2 of semiconductor device> FIG. 13(A) shows an example in which charges are released from the second charge storage layer and then the first charge storage layer. However, the operation shown in FIG. 13(B) may be used to release charges from the first charge storage layer and then the second charge storage layer.

[0195] [Data D_00] At time t60 shown in FIG. 13(B), data D_00 is stored, similar to time t50 shown in FIG. 13(A).

[0196] [Action Er2_1: Data D_10] At time t61 shown in Figure 13 (B), the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, the potential applied to the wiring BL is changed from a potential V1 to a potential V2, and the wiring SL is put into a floating state, thereby releasing the charge in the first charge storage layer and changing the state from one in which data D_00 is stored to one in which data D_10 is stored (memory cell 602 shown in the lower left of Figure 12) (operation Er2_1).

[0197] [Action Er2_2: Data D_11] Next, at time t62 shown in Figure 13 (B), the potential applied to wiring WL2 is changed from high potential H to low potential L, thereby releasing the charges stored in the second charge storage layer and changing the state from one in which data D_10 is stored to one in which data D_11 is stored (operation Er2_2).

[0198] <Operation example 3-3 of semiconductor device> Figures 13(A) and 13(B) show examples in which the timing of the operation to release charges from the first charge storage layer and the second charge storage layer is different, but the operation shown in Figure 13(C) may be used to release charges from the first charge storage layer and the second charge storage layer by the same operation.

[0199] [Data D_00] At time t70 shown in FIG. 13C, data D_00 is stored, similar to time t50 shown in FIG. 13A.

[0200] [Operation Er3: Data D_00] At time t71 shown in Figure 13 (C), the potential applied to wiring WL1 and wiring WL2 is changed from a high potential H to a low potential L, the potential applied to wiring BL is changed from a potential V1 to a potential V2, and wiring SL is brought into a floating state, thereby changing the state from one in which data D_00 is stored to one in which data D_11 is stored (operation Er3).

[0201] <Operation Example 4-1 of Semiconductor Device> In the above, an example of rewriting data from a state in which data D_00 is stored has been described. However, the timing charts shown in Figures 14(A) and 14(B) show an example of a data rewrite operation from a state in which data D_01 and data D_10 are stored, respectively.

[0202] The timing chart of FIG. 14(A) will be described.

[0203] [Data D_01] At time t80, the data D_01 has been saved, and the data can be saved using the operations described in FIGS.

[0204] [Data D_11] Next, at time t81, the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, the potential applied to the wiring BL is changed from a potential V1 to a potential V2, and the wiring SL is brought into a floating state, thereby changing the state from one in which data D_01 is stored to one in which data D_11 is stored.

[0205] [Data D_10] Next, at time t82, the state where data D_11 is stored is changed to the state where data D_10 is stored. For an explanation of the period from time t81 to time t82, the explanation of the period from time t10 to time t11 in FIG. 9B can be referred to.

[0206] <Operation example 4-2 of semiconductor device> Next, the timing chart of FIG. 14(B) will be described.

[0207] [Data D_10] At time t90, the data D_10 has been saved, and the data can be saved using the operations described in FIG. 8 and FIG.

[0208] [Data D_11] Next, at time t91, the potential applied to the wiring WL2 is changed from a high potential H to a low potential L, the potential applied to the wiring BL is changed from a potential V1 to a potential V2, and the wiring SL is brought into a floating state, thereby changing the state from one in which data D_10 is stored to one in which data D_11 is stored.

[0209] [Data D_01] Next, at time t92, the state where data D_11 is stored is changed to the state where data D_01 is stored. For an explanation of the period from time t91 to time t92, the explanation of the period from time t0 to time t1 in FIG. 9A can be referred to.

[0210] <Operation example 5-1 of semiconductor device> 15 and 16(A) to 16(C) are different from those in FIG. 12 and 13(A) to 13(C) in that the stored data is changed by changing the potential of the wiring SL. By using the wiring SL, the data of the memory cells 602 located in the same row can be changed at the same time. This operation may be called a batch erase operation.

[0211] First, an example of the operation of the semiconductor device will be described with reference to FIGS.

[0212] [Data D_00] At time t100 shown in FIG. 16A, data D_00 is stored (memory cell 602 shown in the upper left of FIG. 15), and data can be stored using the operations described in FIGS. 8 to 11.

[0213] [Action Er4_1: Data D_01] 16A, the potential applied to the wiring WL2 is changed from a high potential H to a low potential L, and the potential applied to the wiring SL is changed from a low potential L to a high potential H, and the wiring BL is put into a floating state, thereby discharging the charge in the second charge storage layer and changing the state from one in which data D_00 is stored to one in which data D_01 is stored (memory cell 602 shown in the upper right of FIG. 15) (operation Er4_1). This operation changes the data of all memory cells 602 connected to the same wiring WL2 and the same wiring SL.

[0214] [Action Er4_2: Data D_11] 16A, the potential applied to the wiring WL1 is changed from a high potential H to a low potential L to release the charge in the first charge storage layer, and the state in which data D_01 is stored can be changed to a state in which data D_11 is stored (memory cell 602 shown in the lower right of FIG. 15) (operation Er4_2). This operation can change the data in all memory cells 602 connected to the same wiring WL1 and the same wiring SL.

[0215] <Operation example 5-2 of semiconductor device> FIG. 16(A) shows an example in which charges are released from the second charge storage layer and then the first charge storage layer. However, the operation shown in FIG. 16(B) may be used to release charges from the first charge storage layer and then the second charge storage layer.

[0216] [Data D_00] At time t110 shown in FIG. 16(B), data D_00 is stored, similarly to time t100 shown in FIG. 16(A).

[0217] [Action Er5_1: Data D_10] 16B, the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, and the potential applied to the wiring SL is changed from a low potential L to a high potential H, and the wiring BL is put into a floating state, thereby discharging the charge in the first charge storage layer and changing the state from one in which data D_00 is stored to one in which data D_10 is stored (the memory cell 602 at the lower left in FIG. 15) (operation Er5_1). This operation changes the data of all the memory cells 602 connected to the same wiring WL1 and the same wiring SL.

[0218] [Action Er5_2: Data D_11] 16B, the potential applied to the wiring WL2 is changed from a high potential H to a low potential L to release the charges stored in the second charge storage layer, and the state in which data D_10 is stored can be changed to the state in which data D_11 is stored (operation Er5_2). This operation can change the data of all the memory cells 602 connected to the same wiring WL2 and the same wiring SL.

[0219] <Operation example 5-3 of semiconductor device> Figures 16(A) and 16(B) show examples in which the timing of the operation to release charges from the first charge storage layer and the second charge storage layer is different, but the operation shown in Figure 16(C) may be used to release charges from the first charge storage layer and the second charge storage layer by the same operation.

[0220] [Data D_00] At time t120 shown in FIG. 16C, data D_00 is stored, similar to time t100 shown in FIG. 16A.

[0221] [Action Er6: Data D_11] 16C, the potentials applied to the wirings WL1 and WL2 are changed from a high potential H to a low potential L, and the potential applied to the wiring SL is changed from a low potential L to a high potential H, and the wiring BL is put into a floating state, thereby changing the state in which data D_00 is stored to a state in which data D_11 is stored (operation Er6). This operation can change the data in all the memory cells 602 connected to the same wiring WL1, the same wiring WL2, and the same wiring SL.

[0222] <Operation example 6-1 of semiconductor device> In the above, a rewrite operation from a state in which data D_00 is stored has been described as an operation for changing stored data by changing the potential of the wiring SL. However, the timing charts shown in Figures 17(A) and 17(B) show an example of a data rewrite operation from a state in which data D_01 and data D_10 are respectively stored.

[0223] The timing chart of FIG. 17(A) will be described.

[0224] [Data D_01] At time t130, the data D_01 has been saved, and the data can be saved using the operations described with reference to FIGS.

[0225] [Data D_11] Next, at time t131, the potential applied to the wiring WL1 is changed from a high potential H to a low potential L, and the potential applied to the wiring SL is changed from a low potential L to a high potential H, and the wiring BL is put into a floating state, thereby changing the state from one in which data D_01 is stored to one in which data D_11 is stored.

[0226] [Data D_10] Next, at time t132, the potential applied to the wiring WL2 is changed from a low potential L to a high potential H, the potential applied to the wiring SL is changed from a high potential H to a low potential L, and the potential applied to the wiring BL is set to potential V1, thereby changing the state from one in which data D_11 is stored to one in which data D_10 is stored.

[0227] <Semiconductor device operation example 6-2> Next, the timing chart of FIG. 17(B) will be described.

[0228] [Data D_10] At time t140, the data D_10 has been saved, and the data can be saved using the operations described in FIGS.

[0229] [Data D_11] Next, at time t141, the potential applied to the wiring WL2 is changed from a high potential H to a low potential L, and the potential applied to the wiring SL is changed from a low potential L to a high potential H, and the wiring BL is brought into a floating state, thereby changing the state from one in which data D_10 is stored to one in which data D_11 is stored.

[0230] [Data D_01] Next, at time t142, the potential applied to the wiring WL1 is changed from a low potential L to a high potential H, the potential applied to the wiring SL is changed from a high potential H to a low potential L, and the potential applied to the wiring BL is set to potential V1, thereby changing the state from one in which data D_11 is stored to one in which data D_01 is stored.

[0231] <Example of semiconductor device operation: Read> An example of an operation for reading data stored in the memory cell 602 will be described with reference to a timing chart shown in FIG.

[0232] First, at time t161, a low potential L is applied to the wiring WL1, the wiring WL2, the wiring BL, and the wiring SL.

[0233] Next, the stored data is read by changing the potential of the wiring WL1. The threshold value of the transistor M1 in the memory cell 602 changes in response to the stored data. FIG. 17D shows an example of an Id-Vgs curve of the transistor M1 (this curve is a re-illustration of the example shown in FIG. 8B). The current flowing through the transistor changes by changing the potential at which reading is performed (shown as read potential Vread in the figure). The data stored in the transistor M1 can be determined by changing the read potential Vread and reading the current of the transistor.

[0234] In the following, an example will be described in which the potential applied to the line WL1 as the read potential Vread is changed in order from Vr1 to Vr2 to Vr3 to perform reading.

[0235] First, at time t162, a potential Vd is applied to the wiring BL as a predetermined potential. When the potential of the wiring WL1 is changed to a potential Vr1, a current flows between the wiring BL and the wiring SL when the data D_11 is stored in the memory cell 602.

[0236] Next, at time t163, when the potential of the wiring WL1 is changed to a potential Vr2, if the data D_10 is stored in the memory cell 602, a current flows between the wiring BL and the wiring SL.

[0237] Next, at time t164, when the potential of the wiring WL1 is changed to a potential Vr3, a current flows between the wiring BL and the wiring SL when data D_01 is stored in the memory cell 602. Note that when data D_00 is stored in the memory cell 602, no current flows between the wiring BL and the wiring SL. In this way, the stored data can be read out by measuring the current flowing between the wiring BL and the wiring SL.

[0238] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Each layer constituting the semiconductor device of this embodiment may have a single layer structure or a multilayer structure.

[0239] [Conductive layer] For the conductive layers (conductive layer 520, conductive layer 540, conductive layer 560, etc.) included in the semiconductor device, it is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. Furthermore, a nitride or oxide of the above-mentioned metal element may be used. Furthermore, as an alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium, and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0240] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0241] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high electrical conductivity.

[0242] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0243] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer functioning as a gate electrode. In this case, the conductive material containing oxygen can be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0244] Examples of the conductive material containing a metal element and nitrogen include tantalum nitride, titanium nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, etc. Examples of the conductive material containing a metal element and oxygen include ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc.

[0245] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

[0246] Titanium, tantalum, ruthenium, and materials containing one or more selected from these metal elements are preferable because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing the diffusion of oxygen, or materials that maintain their conductivity even when they absorb oxygen.

[0247] Since the conductive layer 520 and the conductive layer 540 are conductive layers in contact with the oxide semiconductor layer, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer.

[0248] As the conductive material containing oxygen, it is preferable to use, for example, ITO, ITSO, IZO (registered trademark), or the like.

[0249] In the case where the conductive layer 520 has a stacked-layer structure, a conductive material containing nitrogen and a conductive material containing oxygen may be used as an upper conductive layer in contact with the oxide semiconductor layer.

[0250] Furthermore, when the conductive layer 540 has a layered structure, for example, a lower layer can be made of a material having a higher conductivity than an upper layer, and the upper layer can be made of a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is difficult to oxidize, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains its conductivity even when it absorbs oxygen.

[0251] Specifically, for example, the conductive layer 540 is preferably made of ruthenium, tungsten, titanium nitride, or tantalum nitride as the lower layer and ITO or ITSO as the upper layer. In this case, ITO or ITSO is in contact with the oxide semiconductor layer. With such a structure, the conductive layer can maintain conductivity even when in contact with the oxide semiconductor layer. In addition, the conductivity of the conductive layer can be increased by using a material having a higher conductivity than the upper layer as the lower layer.

[0252] In the case where the conductive layer has a two-layer stack structure, a material having high conductivity may be used for the upper layer, and a conductive material containing nitrogen, a conductive material containing oxygen, a conductive material that is not easily oxidized, a conductive material that has a function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen may be used for the lower layer. In such a case, for example, by having a structure in which an oxide semiconductor layer is in contact with the upper surface of the conductive layer, the contact resistance between the conductive layer and the oxide semiconductor layer can be reduced.

[0253] [Insulation layer] For each of the insulating layers (insulating layer 210, insulating layer 481, insulating layer 482, insulating layer 483, insulating layer 283, insulating layer 285, insulating layer 551, insulating layer 553, etc.) included in the semiconductor device, an inorganic insulating film is preferably used. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for an insulating layer included in a semiconductor device.

[0254] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the permeation of impurities and oxygen. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material of the insulating layer having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0255] Specifically, it is preferable to use a barrier insulating layer against impurities such as water and hydrogen, and oxygen.

[0256] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property in which a corresponding substance is difficult to diffuse, a property in which a corresponding substance is difficult to permeate, a property in which the permeability of a corresponding substance is low, a function of suppressing the diffusion of a corresponding substance, or a function of suppressing the permeation of a corresponding substance. Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0257] Examples of the insulating layer having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Other examples include oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0258] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of an insulating layer that is likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0259] Furthermore, for example, as transistors become finer and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating layer. By using a material with a high relative dielectric constant (high-k) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. In addition, it is possible to thin the equivalent oxide thickness (EOT) of the gate insulating layer. In addition, by using a material with a high relative dielectric constant as the dielectric layer of a capacitance element, it is possible to make the element have a larger capacitance value. On the other hand, by using a material with a low relative dielectric constant for the insulating layer that functions as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, the material can be selected according to the function of the insulating layer. Note that a material with a low relative dielectric constant also has a high dielectric strength.

[0260] Examples of materials having a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0261] Examples of materials with a low relative dielectric constant include resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with a low relative dielectric constant include silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. Examples of silicon oxides include silicon oxides having vacancies. These silicon oxides may contain nitrogen.

[0262] Furthermore, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be applied to both layers in which a material with a high dielectric constant is preferably used, such as a gate insulating layer, and layers in which a material with a low dielectric constant is preferably used, such as an interlayer film. These materials have a relatively low dielectric constant compared to high-k materials such as hafnium oxide, and therefore may be referred to as materials with a low dielectric constant in this specification and the like.

[0263] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0264] In addition, examples of materials that can have ferroelectricity include metal nitrides having elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. In addition, metal oxides having elements M1 and nitrogen may have ferroelectricity even if they do not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0265] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0266] In the above description, metal oxides and metal nitrides are exemplified as materials that can have ferroelectricity, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0267] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change depending on not only the film formation conditions but also various processes, so in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of having ferroelectricity.

[0268] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0269] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer. In addition, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

[0270] It is said that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0271] In the insulating layer of one embodiment of the present invention, the concentration of impurities such as water and hydrogen is preferably reduced, which can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer.

[0272] The insulating layer 481, the insulating layer 482, and the insulating layer 483 preferably include a barrier insulating layer against hydrogen. The insulating layer 481, the insulating layer 482, and the insulating layer 483 are provided to surround the oxide semiconductor layer. When the insulating layer 481, the insulating layer 482, and the insulating layer 483 provided on the outer side of the oxide semiconductor layer have a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. For example, the insulating layer 481, the insulating layer 482, and the insulating layer 483 preferably include a silicon nitride film.

[0273] Note that silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layers 481, 482, and 483, oxygen can be prevented from being extracted from the oxide semiconductor layer and an excessive amount of oxygen vacancies can be prevented from being formed in the oxide semiconductor layer.

[0274] Furthermore, by using silicon nitride for the insulating layers 481, 482, and 483, excess oxygen can be prevented from being supplied to the oxide semiconductor layer. Thus, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer, which leads to improvement in the reliability of the transistor.

[0275] Each of the insulating layers 481, 482, and 483 preferably includes the above-described oxide insulating film, oxynitride insulating film, or insulating layer including a region containing excess oxygen.

[0276] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layers 481, 482, and 483. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer.

[0277] The insulating layer 481, the insulating layer 482, and the insulating layer 483 can have a stacked structure.

[0278] For example, the insulating layer may have a three-layer laminate structure in which the second insulating layer is sandwiched between the first insulating layer and the third insulating layer from above and below. Note that the insulating layer may not have either the first insulating layer or the third insulating layer.

[0279] The second insulating layer preferably has a region with a higher oxygen content than at least one of the first insulating layer and the third insulating layer, which makes it easier to form an i-type region in the oxide semiconductor layer nearby.

[0280] It is more preferable to use a film that releases oxygen by heating for the second insulating layer. By releasing oxygen from the insulating layer by heat applied during the manufacturing process of the transistor, oxygen can be supplied to the oxide semiconductor layer. By supplying oxygen to the oxide semiconductor layer, particularly to the channel formation region of the oxide semiconductor layer, oxygen vacancies and V O H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0281] In the insulating layers 481 and 483, the regions in contact with the source region and the drain region of the oxide semiconductor layer 530 preferably contain less oxygen. A low oxygen content reduces the amount of oxygen supplied to the oxide semiconductor layer, which makes it easier to reduce the resistance of the oxide semiconductor layer. Thus, in the first insulating layer and the third insulating layer sandwiching the second insulating layer from above and below, the insulating layer in contact with the conductive layer 520 and the insulating layer in contact with the conductive layer 540 preferably contain less oxygen than the second insulating layer.

[0282] The second insulating layer is preferably made of a material with a low dielectric constant, which can reduce the parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used.

[0283] The first insulating layer and the third insulating layer are preferably barrier insulating layers against oxygen, which can prevent the conductive layer 520 and the conductive layer 114 from being oxidized and the resistance of the conductive layer from increasing.

[0284] By using insulating layers having a function of trapping or fixing hydrogen as the first insulating layer and the third insulating layer, diffusion of hydrogen into the oxide semiconductor layer can be suppressed and hydrogen contained in the oxide semiconductor layer can be trapped or fixed. For example, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon can be used. Alternatively, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used.

[0285] [Insulating layer 551, insulating layer 553, insulating layer 554, insulating layer 556, charge storage layer 552, charge storage layer 555] The insulating layers 551, 553, 554, and 556 can each be formed using the above-described materials as appropriate.

[0286] When writing to the transistor 500, it is not preferable that charges are trapped in regions other than the charge accumulation layer, specifically, for example, in the insulating layers 551, 553, 554, and 556, at the interface between the insulating layer 551 and the semiconductor layer, at the interface between the insulating layer 554 and the semiconductor layer, etc. This is because there is a concern that charges trapped in such regions may cause the following: the trapped charges cannot be released at a desired voltage, which increases the power consumption required for the operation of the memory element; the trapped charges are easily released by a leakage current or the like, which makes it impossible to hold information; or the reliability of the transistor 500 may be reduced due to the trapped charges.

[0287] From the above viewpoint, it is preferable that insulating layers 551, 553, 554, and 556 are each a film having few defects that may cause leakage current or trapping of charges. In particular, it is more preferable that insulating layer 551, which has a thin film thickness, has few defects.

[0288] For the insulating layers 551 and 554, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, or the like is preferably used.

[0289] The insulating layers 551 and 554 can each have a thickness of, for example, 1 nm to 20 nm.

[0290] When a highly conductive material is used for the charge storage layer 552, the thickness of the insulating layer 551 can be set to, for example, 5 nm to 20 nm, more preferably 6 nm to 15 nm. When a highly insulating material is used for the charge storage layer 552, the thickness of the insulating layer 551 can be set to, for example, 1 nm to 6 nm, more preferably 1.5 nm to 4.5 nm.

[0291] When a highly conductive material is used for the charge storage layer 555, the thickness of the insulating layer 554 may be set to, for example, 5 nm to 20 nm, more preferably 6 nm to 15 nm. When a highly insulating material is used for the charge storage layer 555, the thickness of the insulating layer 554 may be set to, for example, 1 nm to 6 nm, more preferably 1.5 nm to 4.5 nm.

[0292] The insulating layer 553 preferably has a larger thickness than the insulating layer 551. The insulating layer 556 preferably has a larger thickness than the insulating layer 554, for example.

[0293] The insulating layer 553 and the insulating layer 556 can each have a thickness of, for example, 8 nm to 30 nm.

[0294] The insulating layer 553 and the insulating layer 556 can be formed using any of the materials exemplified above for the insulating layer. A stack of a plurality of materials can also be used. For example, the insulating layer 553 is preferably formed using silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, or the like.

[0295] A material having high conductivity can be used for the charge storage layer 552 and the charge storage layer 555. For example, the materials exemplified as the conductive layer described above can be appropriately used. Specifically, for example, one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing these metal elements as a component, or an alloy combining these metal elements can be used. In addition, a nitride or an oxide of the above-mentioned metal element can be used. In addition, as an alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy can be used.

[0296] A semiconductor material such as silicon or germanium can also be used for the charge accumulation layer 552 and the charge accumulation layer 555. When a semiconductor material is used, for example, a layer whose resistance is reduced by implanting an impurity may be used.

[0297] Moreover, a material having high insulating properties can be used for the charge storage layer 552 and the charge storage layer 555. For example, the materials exemplified as the insulating layer above can be used for the insulating layer having charge traps. Specifically, for example, silicon nitride, silicon oxynitride, etc. can be used. Also, a layer in which conductive nanodots are dispersed in the insulating layer can be used.

[0298] The insulating layer has an amorphous structure, which can suppress the formation of crystal grain boundaries. The suppression of the formation of crystal grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, and can reduce extremely thin portions, thereby improving the withstand voltage of the insulating layer. In addition, the film thickness distribution of the film provided on the insulating layer can be made uniform. In addition, the suppression of the formation of crystal grain boundaries in the insulating layer can reduce leakage current caused by defect levels in the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current. Therefore, it is preferable that the insulating layer used for the insulating layer 551, the insulating layer 553, and the like has an amorphous structure, for example.

[0299] The gate insulating layer of the transistor has the function of trapping and fixing hydrogen, so that the V O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0300] Furthermore, when the gate insulating layer of the transistor includes a barrier insulating layer against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed.

[0301] Furthermore, when the gate insulating layer of the transistor has an insulating layer having a structure stable against heat, such as silicon oxide or silicon oxynitride, the transistor characteristics can be stabilized.

[0302] Furthermore, when the gate insulating layer of the transistor is formed using a barrier insulating layer against oxygen, oxygen contained in the oxide semiconductor layer can be prevented from diffusing to surrounding layers and from being formed into oxygen vacancies in the oxide semiconductor layer.

[0303] [substrate] As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available. Furthermore, there is a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, etc. are available. As the conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. are available. Furthermore, there is a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or insulator is provided on a conductive substrate, etc. are available. Alternatively, these substrates on which elements are provided may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0304] <Oxide semiconductor layer> The transistor 500 preferably includes a metal oxide functioning as a semiconductor in the oxide semiconductor layer 530 including a channel formation region. That is, the transistor 500 is preferably an OS transistor.

[0305] In addition, the semiconductor device of this embodiment may be applied to a transistor using another semiconductor material in the channel formation region. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor. Examples of the semiconductor made of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include an organic semiconductor and a nitride semiconductor. The above-mentioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may include impurities as dopants.

[0306] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0307] The semiconductor layer of the transistor may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0308] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to group 16). Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0309] An oxide semiconductor layer that can be used as the oxide semiconductor layer 530 will be described below.

[0310] As the oxide semiconductor layer 530, the oxide semiconductor layer 30 described below can be used.

[0311] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystalline (polycrystal) structure, and a nanocrystalline (nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Thus, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0312] The oxide semiconductor layer of one embodiment of the present invention particularly preferably contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the ab plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as bright spots in a cross section of the oxide semiconductor layer observed using a TEM image.

[0313] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the film is formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the film is formed. In the region of the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the film is formed.

[0314] The polycrystalline structure has crystal grain boundaries. When a heat treatment is performed after forming an oxide semiconductor layer having a polycrystalline structure, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the oxide semiconductor layer, the electric resistance of the oxide semiconductor layer increases. This is because the electric resistance of the minute gap or the minute space is very high, for example, infinite. When an oxide semiconductor layer having a minute gap or a minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In the CAAC structure, a crystal grain boundary is not clearly observed in the ab plane, and therefore a highly reliable semiconductor device can be realized. In addition, since there are few crystal grain boundaries, an energy barrier against carrier conduction in the channel of the transistor is small, and an improvement in on-current is expected.

[0315] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0316] When an oxide semiconductor layer having a CAAC structure is subjected to electron beam diffraction, spots (bright points) indicating c-axis orientation are observed in the electron beam diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor layer is formed or the normal vector of the surface of the oxide semiconductor layer.

[0317] Furthermore, an FFT pattern obtained by subjecting a TEM image to a Fast Fourier Transform (FFT) process reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0318] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing for each region in the cross-sectional TEM image, and the direction of the crystal axis of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots that have high brightness and are approximately equal distances from the center among the spots observed in the created FFT pattern is taken as the direction of the crystal axis. A region in which the direction of the crystal axis of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and furthermore 85° to 95° (within 90°±5°) can be considered as a CAAC structure.

[0319] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the layer has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and typically, hexagonal Voronoi regions are observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0320] We will now explain how to create a Voronoi diagram. First, image analysis of a TEM image involves performing FFT processing, then filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT filtered image. Lattice points are extracted from the created FFT filtered image, and perpendicular bisectors of the lines connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal region surrounded by the lines connecting the Voronoi points is defined as the Voronoi region. In this way, a Voronoi diagram can be created.

[0321] In the creation of a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width may be observed as an example of the observation range of the TEM, but the observation range is not limited to this.

[0322] Furthermore, when the distribution of hexagonal lattice orientations is analyzed using lattice points extracted by image analysis of planar TEM images, the difference in hexagonal lattice orientations at the boundary between two structures with different hexagonal lattice orientations is small, the boundary is observed to be blurred, and the two structures appear to be connected in a manner that seems to interpenetrate. In other words, no clear boundary is observed in the CAAC structure.

[0323] The orientation of the hexagonal lattice can be calculated by calculating the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0324] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0325] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and more preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Also, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and more preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Here, element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0326] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms are observed as bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Also, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0327] Examples of the metal oxide according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum Indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, etc. can be used as the metal oxide according to one embodiment of the present invention.

[0328] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0329] The metal oxide may have one or more kinds of metal elements having a large period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more kinds of metal elements having a large period number in the periodic table in addition to indium. The greater the overlap of the orbits of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of a transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0330] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0331] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0332] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0333] In the present embodiment, an In-Ga-Zn oxide may be taken as an example of the metal oxide.

[0334] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using two kinds of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by using a first film formation method and a second film formation method. Note that an oxide semiconductor layer formed by using two kinds of film formation methods may be referred to as a hybrid OS.

[0335] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0336] In the formation of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is formed by the first film formation method. In particular, the metal oxide formed at this time preferably has a CAAC structure. For example, a metal oxide formed by a sputtering method is likely to have crystallinity.

[0337] When a metal oxide is formed by using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy given to the substrate by the sputtering particles or the like. There is a concern that the mixed layer may hinder the crystallization of the metal oxide.

[0338] For example, when an insulating layer having silicon, for example silicon oxide, is used as a surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide by using the first film formation method. There is a concern that the crystallization of the metal oxide may be hindered by the mixing of impurities such as silicon into the metal oxide.

[0339] In view of this, in one embodiment of the present invention, before forming a metal oxide by using the first film formation method, a metal oxide is formed by using the second film formation method. That is, after forming a metal oxide as a first layer by using the second film formation method, a metal oxide is formed as a second layer on the first layer by using the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface to be formed as the second film formation method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer that is the surface to be formed of the oxide semiconductor layer. In addition, since the inclusion of impurities such as silicon in the second layer can be suppressed, the crystallinity can be possibly increased. For example, an atomic layer deposition (ALD) method and a chemical vapor deposition (CVD) method are suitable as the second film formation method because they can suppress damage to a surface to be formed compared to a sputtering method.

[0340] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by forming the second layer and then performing heat treatment, the crystallinity of the first layer may be increased with the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0341] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0342] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0343] Examples of the second film formation method include the ALD method, the plasma enhanced CVD (PECVD) method, the thermal CVD (TCVD) method, the photo CVD (photo CVD) method, the metal organic CVD (MOCVD) method, and the molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film with a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface on which the film is formed. In addition, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that cause less damage to the surface on which the film is formed. For example, a spray coating method can be used as the wet method.

[0344] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, and then forming a metal oxide as a second layer by using the first film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure.

[0345] A third layer can also be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to have crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by using a film formation method that has higher coverage than the second layer as the third layer, the oxide semiconductor layer can have both high crystallinity and high coverage in the entire layer. Also, for example, by using a film formation method that causes less damage than the second layer as the third layer, damage to the second layer is reduced, and the oxide semiconductor layer can have high crystallinity in the entire layer.

[0346] In addition, the second layer has excellent crystallinity because the effect of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0347] Note that the third layer is the uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor described later. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0348] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, forming a metal oxide as a second layer by using the first film formation method, and forming a metal oxide as a third layer by using the second film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. In addition, the metal oxide formed by the first film formation method preferably has a CAAC structure. The ALD method is a film formation method with better coverage than the sputtering method, and the coverage of the oxide semiconductor layer can be improved by using the ALD method as the film formation method for the first layer and the third layer. Thus, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0349] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. There is also RF-superimposed DC sputtering, which superimposes RF and DC. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming a film using a conductive target. In addition to forming a conductive film, DC sputtering can also form an insulating film by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming a film of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows control of ion energy during film formation and control of the target side potential. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Also, a high-quality film can be obtained.

[0350] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0351] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it uses plasma, which allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amount of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of a high substrate temperature condition during film formation and an impurity removal treatment, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.

[0352] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0353] The plasma CVD method can produce high-quality films at relatively low temperatures. Thermal CVD is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. In addition, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0354] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0355] [Method for producing oxide semiconductor layer] The oxide semiconductor layer 30 can be manufactured, for example, by forming an oxide semiconductor layer 30a on a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor layer 30b on the oxide semiconductor layer 30a by a sputtering method, and forming an oxide semiconductor layer 30c on the oxide semiconductor layer 30b by an ALD method. After the oxide semiconductor layer 30 is formed, it is preferable to perform heat treatment. By performing the heat treatment, the crystallinity of the oxide semiconductor layer 30 can be improved. The heat treatment here is not limited to heating treatment. For example, it may be heat applied during a manufacturing process. The layer 229 is an insulating film, and is, for example, an insulating film such as silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In addition, a film to be described later as an insulator included in a semiconductor device can be used as the layer 229.

[0356] Alternatively, a conductive film may be used as the layer 229. For example, the oxide semiconductor layer 30 may be formed over a conductive film that functions as an electrode of a semiconductor device.

[0357] The layer 229 does not have to be crystalline. In other words, the layer 229 may have an amorphous structure. In addition, when the layer 229 has crystallinity, the layer 229 may have a crystal structure that has low lattice matching with the metal oxide of the oxide semiconductor layer 30.

[0358] An example of a method for manufacturing the oxide semiconductor layer 30 will be described with reference to FIGS.

[0359] First, an oxide semiconductor layer 30a is formed on the layer 229 (FIG. 22(A)). Then, an oxide semiconductor layer 30b is formed on the oxide semiconductor layer 30a (FIG. 22(B)).

[0360] The oxide semiconductor layer 30b is preferably formed by sputtering and has a composition suitable for forming a CAAC structure.

[0361] The oxide semiconductor layer 30a is preferably formed by a film formation method that causes less damage to the surface on which it is formed, as compared with the film formation method for the oxide semiconductor layer 30b. Here, the oxide semiconductor layer 30a is formed by the ALD method.

[0362] When a metal oxide film is formed by a sputtering method, the components contained in the metal oxide film may be alloyed with the components contained in the layer on which the film is formed due to damage to the surface on which the film is formed. When the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment described later is performed. In addition, there is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on which the film is formed.

[0363] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, after the oxide semiconductor layer 30a is formed over the layer 229, the oxide semiconductor layer 30b is formed by a sputtering method. At this time, the oxide semiconductor layer 30a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor layer 30a is to be formed. By forming the oxide semiconductor layer 30a between the oxide semiconductor layer 30b and the layer 229 by a deposition method that causes little damage to a surface on which the oxide semiconductor layer 30a is to be formed, alloying between a component contained in the oxide semiconductor layer 30 and a component contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 30 can be further improved.

[0364] With the above-mentioned configuration, the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Fig. 22(A) and Fig. 22(B) show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor layer 30a.

[0365] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0366] For example, the EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor layer 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor layer 30a contains In) that is the main component of the oxide semiconductor layer 30a and is not the main component of the layer that will be the surface to be formed (here, layer 229) becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor layer 30a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will be the surface to be formed and is not the main component of the oxide semiconductor layer 30a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will be the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0367] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm.

[0368] For example, when a silicon oxide layer is used as the layer 229 and a SIMS analysis is performed on the oxide semiconductor layer 30 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0369] By setting the thickness t_s2 to a value within the above range, the thickness of the alloyed region can be made thin, and thus the thickness t_s2 can be set to a value within the above range.

[0370] By reducing the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region from more than 0 nm to 3 nm or less, preferably more than 0 nm to 2 nm or less, more preferably 1 nm to 2 nm or less, approximately perpendicularly from the formation surface of the oxide semiconductor layer 30.

[0371] The CAAC structure near the formation surface may be observed by TEM observation. For example, in a cross-sectional observation of the oxide semiconductor layer 30 by high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed near the formation surface.

[0372] Alternatively, the CAAC structure near the surface to be formed may be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing FFT processing on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. The FFT pattern reflects reciprocal lattice space information similar to that of an electron beam diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is preferably 70° or more and 110° or less (within 90°±20°) relative to the surface to be formed, more preferably 75° or more and 105° or less (within 90°±15°), more preferably 80° or more and 100° or less (within 90°±10°), and even more preferably 85° or more and 95° or less (within 90°±5°) can be regarded as a CAAC structure.

[0373] When the oxide semiconductor layer 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has a lower crystallinity than the CAAC structure, may be formed. That is, in the manufacturing stage shown in FIG. 22(A), the oxide semiconductor layer 30a may have a region having a lower crystallinity than the oxide semiconductor layer 30b.

[0374] Here, a method of forming an In-M-Zn oxide as the oxide semiconductor layer 30a by the ALD method will be described. The formation of a metal oxide by the ALD method will be described later in detail.

[0375] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 229. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0376] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer in which indium and oxygen are combined by desorbing components other than indium while leaving indium adsorbed on the substrate. Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0377] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0378] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor to form a layer in which element M and oxygen are combined, while element M is still adsorbed on the substrate, by desorbing components other than element M. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0379] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer of the combined element M and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0380] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, for example, the substrate heating temperature is 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0381] Next, the introduction of the raw material gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed on the substrate, forming a layer in which zinc and oxygen are combined. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0382] Next, a layer of indium and oxygen is formed again on the layer of zinc and oxygen by the above-mentioned method. By repeating the above-mentioned method, an In-M-Zn oxide can be formed as the oxide semiconductor layer 30a on the layer 229 by the ALD method.

[0383] In the ALD method, the composition of the film obtained can be controlled by the amount of the raw material gas introduced. For example, in the ALD method, a film of any composition can be formed by adjusting the amount of the raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like. In addition, for example, in the ALD method, a film whose composition changes continuously can be formed by changing the raw material gas while forming the film. When forming a film while changing the raw material gas, the time required for film formation can be shortened by not requiring the time required for transport and pressure adjustment compared to the case of forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0384] After the oxide semiconductor layer 30a is formed by the ALD method, an In-M-Zn oxide is formed as the oxide semiconductor layer 30b on the oxide semiconductor layer 30a by the sputtering method.

[0385] Here, when the oxide semiconductor layer 30b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor layer 30a. In addition, when the oxide semiconductor layer 30b is formed, a minute crystal region may be formed in the mixed layer 231 due to sputtering particles or energy given to the substrate side by the sputtering particles or the like. In a subsequent heat treatment process, the mixed layer 231 or the minute crystal region formed in the mixed layer 231 may become a nucleus, and at least a part of the oxide semiconductor layer 30a may be crystallized.

[0386] In-M-Zn oxide can be used as a target for the sputtering method. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0387] Furthermore, there are cases where a metal oxide having higher crystallinity can be formed as the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as oxygen flow rate ratio) is higher.

[0388] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the metal oxide is formed. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0389] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to that of the sputtering target.

[0390] In forming the oxide semiconductor layer 30b by the sputtering method, it is preferable to heat the substrate. In forming the metal oxide, the substrate temperature (stage temperature) may be increased during the formation of the metal oxide to form a metal oxide with high crystallinity. In forming the oxide semiconductor layer 30b by the sputtering method, the substrate heating temperature is preferably 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0391] Through the above steps, as shown in FIG. 22B, the oxide semiconductor layer 30a can be formed over the layer 229, and the oxide semiconductor layer 30b can be formed over the oxide semiconductor layer 30a.

[0392] Next, the oxide semiconductor layer 30c is formed on the oxide semiconductor layer 30b (FIG. 22(C)). Here, the oxide semiconductor layer 30c is formed by the ALD method. The formation of the oxide semiconductor layer 30c by the ALD method can be referred to the formation method of the oxide semiconductor layer 30a.

[0393] When an oxide semiconductor layer 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor layer 30b having a CAAC structure by using an ALD method, the oxide semiconductor layer 30c may grow epitaxially around the oxide semiconductor layer 30b as a nucleus. Thus, when the oxide semiconductor layer 30c is formed, the oxide semiconductor layer 30c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor layer 30c.

[0394] A heat treatment step may then be performed.

[0395] The temperature of the heat treatment can be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the temperature can be 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) device is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment can repair the gaps in the crystal parts at the atomic level of the CAAC structure of the oxide semiconductor layer 30b by the oxide semiconductor layer 30c (in other words, the crystal molecules formed by the ALD method).

[0396] There is no particular limitation on the heating device used for the heat treatment, and it may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

[0397] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor layer 30c. In addition, if the region is formed only below the oxide semiconductor layer 30c after the ALD process, the heat treatment step may cause the region to expand upward (FIG. 22(D)). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire oxide semiconductor layer 30c.

[0398] In addition, the heat treatment process may further repair the oxide semiconductor layer 30b by the oxide semiconductor layer 30c (in other words, the crystal molecules formed by the ALD method) that fills gaps in the atomic-level crystal parts of the CAAC structure of the oxide semiconductor layer 30b.

[0399] It is also preferable that at least a part of the oxide semiconductor layer 30a is converted into CAAC by the heat treatment process (FIG. 22(D)). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor layer 30a during the deposition of the oxide semiconductor layer 30b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor layer 30a that is converted into CAAC is large, and it is preferable that the CAAC is converted to CAAC up to the vicinity of the layer 229.

[0400] Furthermore, because the CAAC process is performed from the top to the bottom of the oxide semiconductor layer 30a, the CAAC process can be performed up to the vicinity of the layer 229 without being limited to the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor layer 30a can be formed with high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0401] 22(A) to 22(D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIG. 22(A) to FIG. 22(D) can be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention. As shown in FIG. 22(A) to FIG. 22(D), the oxide semiconductor layer 30a and the oxide semiconductor layer 30c each have high crystallinity using the oxide semiconductor layer 30b having high crystallinity as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor layer 30a may be increased by heat treatment during the formation of the oxide semiconductor layer 30b or after the formation of the oxide semiconductor layer 30c. The crystallinity of the oxide semiconductor layer 30c may be increased by heat treatment during the formation of the oxide semiconductor layer 30c or after the formation of the oxide semiconductor layer 30c. The heat treatment has an assisting effect of increasing the crystallinity.

[0402] In this manner, in the metal oxide film formation method according to one embodiment of the present invention, the highly crystalline oxide semiconductor layer 30b (i.e., CAAC) can be used as a nucleus or seed to increase the crystallinity of the upper and lower oxide semiconductors (here, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c). This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown in a solid phase using the oxide semiconductor layer 30b as a nucleus or seed to form an oxide semiconductor with high crystallinity. The oxide semiconductor formed using such a film formation method, here a CAAC film, can be referred to as an axial growth CAAC (AG CAAC).

[0403] In the entire oxide semiconductor layer 30 including the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, it is preferable that the region having the CAAC structure is widely present throughout the entire layer. FIG. 23(A) shows the state in which the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c are crystallized. In the oxide semiconductor layer 30a, the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor layer 30b through crystals. In the oxide semiconductor layer 30c, the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor layer 30b through crystals. As a result, the boundary between the oxide semiconductor layer 30a and the oxide semiconductor layer 30b may not be observed. Also, the boundary between the oxide semiconductor layer 30b and the oxide semiconductor layer 30c may not be observed. The oxide semiconductor layer 30 may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer 30 may be expressed as a single layer.

[0404] In each of the oxide semiconductor layers 30a, 30b, and 30c, in the region having the CAAC structure, for example, in cross-sectional observation using a high-resolution TEM, bright points aligned parallel to the surface on which the oxide semiconductor layer is formed are confirmed. In addition, the c-axis of the CAAC structure in each of the oxide semiconductor layers 30a, 30b, and 30c is preferably approximately parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0405] Also, there are cases where a part of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is not crystallized. The example shown in Fig. 23(B) shows a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor layer 30a is not crystallized. Fig. 23(C) shows a state in which the vicinity of the surface in the oxide semiconductor layer 30c is not crystallized. Fig. 23(D) shows a state in which the vicinity of the interface with the layer 229 of the oxide semiconductor layer 30a and the vicinity of the surface of the oxide semiconductor layer 30c are not crystallized.

[0406] By increasing the crystallinity of the oxide semiconductor layer, an increase in the electrical resistance of a transistor using the oxide semiconductor layer can be suppressed or initial characteristics (particularly, on-state current) of the transistor can be improved, which is expected to make the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-state current can be increased.

[0407] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0408] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 30, the boundaries between the stacked films of the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c may not be observed. In particular, after heat treatment, it may be difficult to observe the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0409] As described above, by using a metal oxide with a high In content in a transistor, the field effect mobility of the transistor can be increased. On the other hand, an oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, crystals that reflect the crystal orientation of the oxide semiconductor layer 30b are formed, and polycrystallization can be suppressed.

[0410] In addition, it is preferable that the degree of lattice mismatch between the crystals of the oxide semiconductor layer 30b and the crystals of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is small. This allows the oxide semiconductor layer 30a or the oxide semiconductor layer 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor layer 30b. At this time, for example, in a cross-sectional observation of the oxide semiconductor layer 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor layer 30a or the oxide semiconductor layer 30c.

[0411] As long as the degree of lattice mismatch between the crystals of the oxide semiconductor layer 30b and the crystals of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is small, the crystal structure of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is not particularly limited. The crystal structure of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0412] [Composition of oxide semiconductor layer] The oxide semiconductor layer 30a preferably has a different composition from the oxide semiconductor layer 30b. The oxide semiconductor layer 30c preferably has a different composition from the oxide semiconductor layer 30b. The oxide semiconductor layer 30a may have the same composition as the oxide semiconductor layer 30c. Alternatively, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may have different compositions.

[0413] As described above, the oxide semiconductor layer 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor layer 30b can be formed by, for example, a sputtering method. The oxide semiconductor layer 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor layer 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor layer 30b preferably contains the element M in addition to zinc. By containing the element M in the oxide semiconductor layer 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, it is possible to improve the reliability of a transistor to which the oxide semiconductor layer is applied. Specifically, the oxide semiconductor layer 30b may be made of a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0414] The oxide semiconductor layer 30b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0415] The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be a metal oxide having a high ratio of In. The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher ratio of In than the element M. By using a metal oxide having a high ratio of In, when the oxide semiconductor layer is applied to a transistor, the on-current can be increased and the frequency characteristics can be improved.

[0416] Alternatively, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be configured to not contain the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be configured to contain a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0417] Moreover, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be made of a metal oxide having a higher proportion of In than the oxide semiconductor layer 30b.

[0418] For example, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be made of a metal oxide having a higher Ga ratio than the oxide semiconductor layer 30b. For example, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be made of a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. By increasing the Ga ratio, for example, the band gaps of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be made larger than that of the oxide semiconductor layer 30b. As a result, the oxide semiconductor layer 30b is sandwiched between the oxide semiconductor layer 30a and the oxide semiconductor layer 30c having a larger band gap, and the oxide semiconductor layer 30b mainly functions as a current path (channel). By sandwiching the oxide semiconductor layer 30b between the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, it is possible to reduce trap levels at the interface of the oxide semiconductor layer 30b and in the vicinity thereof. This makes it possible to realize a buried channel type transistor in which the channel is kept away from the insulating layer interface, and to increase the field effect mobility. In addition, the influence of the interface state that may be formed on the back channel side is reduced, and light degradation (e.g., negative bias light degradation) of the transistor can be suppressed, thereby improving the reliability of the transistor.

[0419] Alternatively, one of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor layer 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor layer 30b.

[0420] The oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c may each have a plurality of layers having the above-described compositions stacked together. For example, the oxide semiconductor layer 30c may have a configuration in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0421] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductor layer 30a and the oxide semiconductor layer 30c are formed using compositions that make it difficult to form a CAAC structure when they are formed as a single layer, crystal growth occurs with the oxide semiconductor layer 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductor layer 30a and the oxide semiconductor layer 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c and in a region including the oxide semiconductor layer 30b.

[0422] In particular, even when the oxide semiconductor layers 30a and 30c have a composition with a high In content, the oxide semiconductor layers 30a and 30c can have suitable crystallinity for use as semiconductor layers of transistors. In the oxide semiconductor layer of one embodiment of the present invention, the high In content can improve the on-state characteristics of the transistor, and the CAAC structure with high crystallinity can improve reliability.

[0423] The oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be made of a metal oxide having the same composition as the oxide semiconductor layer 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0424] In addition, an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have one or more of a higher dielectric constant, a higher film density, and a higher film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0425] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0426] The composition of the metal oxide used in the oxide semiconductor layer 30 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0427] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0428] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include deviations in the ratio of the number of atoms of the constituent elements (excess or shortage of constituent atoms) and impurities.

[0429] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0430] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0431] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide having a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0432] In addition, a metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transmission of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of a transistor can be increased.

[0433] [Impurities in oxide semiconductors] Here, the influence of each impurity in an oxide semiconductor will be described.

[0434] It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. O ) and impurities may cause electrical characteristics to fluctuate and reliability to deteriorate. In addition, hydrogen near the oxygen vacancy may cause V O H and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region, V OIt is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0435] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0436] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0437] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0438] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0439] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0440] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0441] The carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3It can be said that:

[0442] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0443] The crystal orientation can be obtained from the FFT pattern by performing FFT processing on the TEM image. Specifically, the crystal axis direction can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal space information similar to that of the electron diffraction pattern.

[0444] By performing FFT processing for each region in the TEM image of the oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal part. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0445] In the map showing the crystal orientation, the c-axis orientation rate can be calculated by calculating the ratio of the c-axis oriented region. The c-axis oriented region is defined here as a region whose orientation coincides with the c-axis, and a region whose difference from the c-axis is preferably within 20°, more preferably within 15°, more preferably within 10°, and even more preferably within 5°. Here, the angle of the c-axis is defined as the angle with respect to the surface to be formed.

[0446] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0447] In addition, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image may be, for example, a region having a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0448] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of a region whose difference from the c-axis is within 20°.

[0449] The c-axis orientation rates of the region formed as the oxide semiconductor layer 30a, the region formed as the oxide semiconductor layer 30b, and the region formed as the oxide semiconductor layer 30c are Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1. Here, the c-axis orientation rate is preferably calculated as the ratio of a region whose difference from the c-axis is within 20°, for example.

[0450] After the oxide semiconductor layer 30 is produced, the boundaries between the oxide semiconductor layers 30a, 30b, and 30c may not be clearly observed.

[0451] The oxide semiconductor layer 30 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from the top of the layer 229. Each region has a layer shape.

[0452] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation rate of the second region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of the region whose difference with the c-axis is within 20°, for example.

[0453] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 30 .

[0454] Or, the layer thickness in each region may be, for example, approximately the same.

[0455] <Example 1 of manufacturing method of semiconductor device> A method for manufacturing the semiconductor device will be described with reference to Figures 18(A) to 20(C). Note that, with regard to the materials and formation methods of each element, descriptions of parts similar to those described above may be omitted.

[0456] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, or the like.

[0457] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. There is also RF-superimposed DC sputtering, which superimposes RF and DC. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming a film using a conductive target. In addition to forming a conductive film, DC sputtering can also form an insulating film by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming a film of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows control of ion energy during film formation and control of the target side potential. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Also, a high-quality film can be obtained.

[0458] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is performed by self-bias or the like. In addition, long-throw sputtering can form anisotropic film by increasing the distance between the sputtering target and the substrate.

[0459] CVD methods can be classified into PECVD, thermal CVD, and photo-CVD, which use heat and light, respectively. They can also be further divided into metal CVD (MCVD) and metal-organic CVD, depending on the source gas used.

[0460] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0461] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0462] In addition, the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. The PEALD method may be preferable because it can form films at lower temperatures by using plasma. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of a high substrate temperature condition during film formation and an impurity removal treatment, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.

[0463] Unlike the film formation method in which particles emitted from a target are deposited, the CVD method and the ALD method are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method with a fast film formation speed or a CVD method. For example, when the metal oxide has a layered structure of a first metal oxide and a second metal oxide, a method of forming a film of the first metal oxide using a sputtering method and forming a film of the second metal oxide on the first metal oxide using an ALD method can be mentioned. For example, when the first metal oxide has a crystal part, the second metal oxide may grow as a crystal with the crystal part as a nucleus.

[0464] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gas. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transport and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0465] In addition, in the ALD method, a film of any composition can be formed by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), etc. In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0466] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0467] Furthermore, when processing a thin film constituting a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0468] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0469] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0470] For etching the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0471] First, a conductive layer 520 is formed over the insulating layer 210. Then, an insulating layer 481 is formed over the conductive layer 520 and the insulating layer 210. Then, a conductive layer 114 and an insulating layer 482 are formed over the insulating layer 481 (FIG. 18A).

[0472] The conductive layer 114 is provided so as to be embedded in the opening of the insulating layer 482. Top surfaces of the conductive layer 114 and the insulating layer 482 are preferably subjected to planarization treatment (also referred to as CMP treatment) by a chemical mechanical polishing (CMP) method or the like.

[0473] Next, openings (openings 590c and 590d) reaching the conductive layer 520 are formed in the conductive layer 114 and the insulating layer 481 (FIG. 18B). The openings 590d and 590c can be formed using the same mask.

[0474] Next, an insulating layer 556 and a charge storage layer 555 are formed in the openings 590c and 590d (FIG. 18C).

[0475] The insulating layer 556 and the charge storage layer 555 can be formed, for example, as follows. First, an insulating film to become the insulating layer 556 is formed in the openings 590c and 590d, on the insulating layer 482, and on the conductive layer 114. Then, a film to become the charge storage layer 555 is formed on the insulating film to become the insulating layer 556. The film to become the charge storage layer 555 is formed so as to fill the openings 590c and 590d. Then, the charge storage layer 555 and the insulating film to become the insulating layer 556 are formed by removing regions located on the insulating layer 482 and the conductive layer 114.

[0476] Next, an insulating layer 483 is formed over the charge accumulation layer 555, the insulating layer 556, the conductive layer 114, and the insulating layer 482. Then, a conductive layer 540 is formed over the insulating layer 483 (FIG. 18D).

[0477] Next, openings reaching the conductive layer 520 are provided in each of the conductive layer 540, the insulating layer 483, the charge accumulation layer 555, and the insulating layer 556 (FIG. 19A). The opening provided in the conductive layer 540 is designated as opening 590f. The opening provided in the insulating layer 483 is designated as opening 590e. By forming each opening using the same mask, the sidewalls of the upper and lower openings can be smoothly connected. Alternatively, an opening in the layer one level above may be used as a hard mask to provide the opening.

[0478] Next, an insulating layer 554 is formed to be in contact with sidewalls of the openings provided in the conductive layer 540, the insulating layer 483, the charge accumulation layer 555, and the insulating layer 556, the top surface of the conductive layer 520, and the top surface of the conductive layer 540 (Figure 19(B)).

[0479] Next, the insulating layer 554 is removed in a region located on the conductive layer 540. In addition, an opening 290c is formed in a region located on the conductive layer 520 (FIG. 19C).

[0480] The region of the insulating layer 554 located over the conductive layer 540 can be removed by, for example, planarization treatment or the like. Alternatively, etching using a mask can be performed. In the case where a mask is used, a part of the region of the insulating layer 554 over the conductive layer 540 may be left as shown in FIG. 19(D). In this manner, for example, the oxide semiconductor layer 530 covers the end of the conductive layer 540 on the opening 590f side with the insulating layer 554 sandwiched therebetween. This may improve the coverage of the oxide semiconductor layer 530.

[0481] Next, an oxide semiconductor layer 530 is formed so as to cover the top surface of the conductive layer 520, the top surface of the insulating layer 554, and the top surface of the conductive layer 540, and then an insulating layer 551, a charge storage layer 552, an insulating layer 553, a conductive layer 560, an insulating layer 283, and an insulating layer 285 are formed in this order, thereby manufacturing the semiconductor device shown in Figures 4(A) to 4(C).

[0482] Note that the insulating layer 554 may be formed as a sidewall insulating layer on sidewalls of openings provided in the conductive layer 540, the insulating layer 483, the charge accumulation layer 555, and the insulating layer 556. In this manner, the semiconductor device illustrated in FIG 6A can be manufactured.

[0483] Heat treatment can also be performed after one or more steps from the formation of the insulating layer 481 to the formation of the conductive layer 560. The heat treatment may be performed, for example, at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the treatment may be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour, or 10 minutes to 30 minutes.

[0484] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. It is preferable to perform the heat treatment before the formation of the oxide semiconductor layer 530 to reduce impurities such as water contained in the insulating layer or the like.

[0485] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulating layer as much as possible. Furthermore, by performing the heat treatment after the formation of the oxide semiconductor layer 530, the crystallinity of the oxide semiconductor layer 530 can be improved.

[0486] <Example 2 of manufacturing method of semiconductor device> A method for manufacturing the semiconductor device shown in Fig. 6B will be described with reference to Fig. 20. The semiconductor device shown in Fig. 6B does not include the insulating layer 482.

[0487] First, the conductive layer 520 is formed over the insulating layer 210. Then, the insulating layer 481 is formed over the conductive layer 520 and the insulating layer 210. Then, the conductive layer 114 is formed over the insulating layer 481.

[0488] Next, openings reaching the conductive layer 520 are formed in the conductive layer 114 and the insulating layer 481 (FIG. 20A).

[0489] Next, an insulating layer 556 and a charge accumulation layer 555 are formed in this order so as to cover side walls of the conductive layer 114 and the insulating layer 481, an upper surface of the conductive layer 520, an upper surface of the conductive layer 114, and an upper surface of the insulating layer 481. Then, an insulating layer 483 and a conductive layer 540 are formed in this order over the charge accumulation layer 555 and the insulating layer 556 (FIG. 20B).

[0490] Next, openings are provided in the conductive layer 540 and the insulating layer 483. The openings provided in the conductive layer 540 and the insulating layer 483 can be formed using the same mask.

[0491] Next, openings are provided in the insulating layer 556 and the charge storage layer 555, respectively, to expose the upper surface of the conductive layer 520 (FIG. 20C). In the example shown in FIG. 20C, the widths of the openings in the insulating layer 556 and the charge storage layer 555 are smaller than the openings in the conductive layer 540 and the insulating layer 483. Although not shown, in plan view, the openings in the insulating layer 556 and the charge storage layer 555 are included in the openings in the conductive layer 540 and the insulating layer 483, for example.

[0492] Next, an insulating layer 554 is formed to cover sidewalls of the openings of the conductive layer 540, sidewalls of the openings of the insulating layer 483, a top surface of the conductive layer 520, an upper surface of the charge accumulation layer 555, and side surfaces of the insulating layer 556. Subsequently, an oxide semiconductor layer 530, an insulating layer 551, a charge accumulation layer 552, an insulating layer 553, a conductive layer 560, an insulating layer 283, and an insulating layer 285 are formed in this order, whereby the semiconductor device illustrated in FIG.

[0493] <Configuration Example 2 of Semiconductor Device> As illustrated in FIG. 21, in a semiconductor device of one embodiment of the present invention, memory cells can be stacked over a layer having circuits for driving the memory cells.

[0494] In FIG. 21, a transistor 500 is provided above a transistor 300 .

[0495] The transistor 300 can be used, for example, as a transistor included in a sense amplifier, which will be described later.

[0496] For the transistor 500 in FIG. 21, the description of FIG. 4B and the like can be referred to.

[0497] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0498] Here, in the transistor 300 shown in FIG. 21, a semiconductor region 313 (part of a substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 sandwiched therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating layer that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0499] Note that the transistor 300 illustrated in FIG. 21 is just an example and is not limited to the structure. Any appropriate transistor can be used depending on the circuit configuration or driving method.

[0500] Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, the conductive layer functioning as a plug or wiring may be given the same reference symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0501] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. Note that the conductive layer 328 and the conductive layer 330 function as a plug or a wiring.

[0502] In addition, the insulating layer functioning as an interlayer film may also function as a planarizing film that covers the uneven shape below it. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0503] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. In the example structure shown in Fig. 21, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0504] For the insulating layers 352 and 354 which function as interlayer films, the description of the insulating layers that can be used in the above-mentioned semiconductor device can be referred to.

[0505] For the conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, the description of the conductive layers that can be used in the above-mentioned semiconductor device can be referred to.

[0506] The transistor 300 is connected to a circuit including the transistor 500 through the conductive layer 356, a conductive layer embedded in the insulating layer 648, and the like.

[0507] This embodiment mode can be combined with other embodiment modes as appropriate.

[0508] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can function as a memory device.

[0509] 24 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in FIG.

[0510] As the memory cell array 920, the memory cell array 601, the memory cell array 611, or the like described in the above embodiments can be used.

[0511] The memory cell array 920 includes one or more memory cells 950. The memory cells 602, 612, or the like described in the above embodiments can be used as the memory cells 950.

[0512] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0513] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0514] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0515] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed. The control circuit 912 may have a function of performing error detection and correction (also called ECC: Error Check and Correct) when data is read from the memory cell array 920.

[0516] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is provided as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0517] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0518] The row decoder 941 and the column decoder 942 have a function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has a function of selecting a row specified by the row decoder 941. The column driver 924 has a function of writing data to the memory cell 950, a function of reading data from the memory cell 950, a function of holding the read data, and the like.

[0519] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0520] PSW931 is the V to the peripheral circuit 915 DD The PSW 932 has the function of controlling the supply of V HM In this embodiment, the high power supply voltage of the semiconductor device 900 is V DD and the low power supply voltage is GND (ground potential). Also, V HM V DD 24, in the peripheral circuit 915, V DD Although the number of power domains to which the power is supplied is set to one, it is also possible to set it to multiple. In this case, a power switch may be provided for each power domain.

[0521] The driver circuit and the memory cell array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in Fig. 25A, the driver circuit and the memory cell array 920 may be provided so as to overlap each other. By providing the driver circuit and the memory cell array 920 so as to overlap each other, the signal propagation distance can be shortened.

[0522] In order to make the configuration of the semiconductor device 900 easier to understand, in FIG. 25A, a layer in which a driver circuit 910 is provided and a layer in which a memory cell array 920 is provided are shown separately.

[0523] As shown in FIG. 25B, a plurality of memory cell arrays 920 may be stacked on the driver circuit.

[0524] [Processing unit] An example of a processor that can include a semiconductor device such as the memory device will be described.

[0525] Fig. 26 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in Fig. 26 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.

[0526] 26 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may be provided on a separate chip.

[0527] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0528] As described later, a memory cell array 920 can be provided by stacking it on the arithmetic device 960. The memory cell array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory cell array 920 to the cache 999. In this case, it is preferable that a part of the cache interface 989 has a drive circuit 910.

[0529] It is also possible to use only the memory cell array 920 as a cache without providing the cache 999.

[0530] The arithmetic device 960 shown in FIG. 26 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on its application. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 26 as one core, and to use a so-called multi-core configuration in which the cores are included and each core operates in parallel. The more cores there are, the higher the arithmetic performance can be. The more cores there are, the more preferable it is, but for example, 2, preferably 4, more preferably 8, even more preferably 12, and even more preferably 16 or more. In addition, when very high arithmetic performance is required for server applications, it is preferable to use a multi-core configuration having 16 or more cores, preferably 32 or more, and even more preferably 64 or more. In addition, the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0531] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to an instruction decoder 993 , decoded, and then input to an ALU controller 992 , an interrupt controller 994 , a register controller 997 , and a timing controller 995 .

[0532] The ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 judges and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority and mask state while the arithmetic device 960 is executing a program. The register controller 997 generates an address for a register 996, and reads and writes data from and to the register 996 depending on the state of the arithmetic device 960.

[0533] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0534] In the arithmetic device 960 shown in FIG. 26, the register controller 997 selects a holding operation in the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 996. If holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 996. If holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 996 can be stopped.

[0535] The memory cell array 920 and the arithmetic device 960 can be provided overlapping each other. FIGS. 27A and 27B are perspective views of a semiconductor device 970A. The semiconductor device 970A includes a layer 930 in which a memory cell array is provided over an arithmetic device 960. A memory cell array 920L1, a memory cell array 920L2, and a memory cell array 920L3 are provided in the layer 930. The arithmetic device 960 and each memory cell array have an overlapping region. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic device 960 and the layer 930 are shown separately in FIG. 27B.

[0536] By overlapping the layer 930 having the memory cell array and the arithmetic device 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0537] As a method for stacking the layer 930 having the memory cell array and the arithmetic device 960, a method of stacking the layer 930 having the memory cell array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. Since the former does not require consideration of misalignment during bonding, it is possible to reduce not only the chip size but also the manufacturing cost.

[0538] Here, the arithmetic device 960 does not have a cache 999, and the memory cell arrays 920L1, 920L2, and 920L3 provided in the layer 930 can be used as caches. In this case, for example, the memory cell array 920L1 can be used as an L1 cache (also called a level 1 cache), the memory cell array 920L2 can be used as an L2 cache (also called a level 2 cache), and the memory cell array 920L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory cell arrays, the memory cell array 920L3 has the largest capacity and is accessed the least frequently. Also, the memory cell array 920L1 has the smallest capacity and is accessed the most frequently.

[0539] When the cache 999 provided in the arithmetic device 960 is used as an L1 cache, each memory cell array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0540] 27(B), a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory cell array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory cell array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory cell array 920L3 via a connection electrode 940L3.

[0541] Although the number of memory cell arrays functioning as a cache is three in this embodiment, the number may be one or two, or four or more.

[0542] When the memory cell array 920L1 is used as a cache, the drive circuit 910L1 may function as a part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989. Similarly, the drive circuit 910L2 and the drive circuit 910L3 may also function as a part of the cache interface 989, or may be configured to be connected thereto.

[0543] Whether the memory cell array 920 is caused to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the multiple memory cells 950 included in the semiconductor device 900 to function as a RAM based on a signal supplied from the arithmetic device 960.

[0544] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can have both a function as a cache and a function as a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0545] Furthermore, a layer 930 having one memory cell array 920 may be provided overlapping with the arithmetic device 960. Figure 28A shows a perspective view of a semiconductor device 970B.

[0546] In the semiconductor device 970B, one memory cell array 920 can be divided into multiple areas, and each area can be used for different functions. Fig. 28(A) shows an example in which the area L1 is used as an L1 cache, the area L2 is used as an L2 cache, and the area L3 is used as an L3 cache.

[0547] In addition, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. With this configuration, it is possible to improve the efficiency of the calculation process and the processing speed.

[0548] Moreover, a plurality of memory cell arrays may be stacked. Figure 28B shows a perspective view of a semiconductor device 970C.

[0549] The semiconductor device 970C has a layer 930L1 having a memory cell array 920L1, a layer 930L2 having a memory cell array 920L2 thereon, and a layer 930L3 having a memory cell array 920L3 thereon. The memory cell array 920L1, which is physically closest to the arithmetic device 960, can be used as a higher-level cache, and the memory cell array 920L3, which is the furthest away, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory cell array can be increased, thereby further improving the processing power.

[0550] This embodiment mode can be combined with other embodiment modes as appropriate.

[0551] (Embodiment 3) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0552] Generally, various storage devices are used in semiconductor devices such as computers depending on the purpose. FIG. 29(A) shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device is located in the hierarchy, the faster the operation speed is required, and the lower the storage device is located in the hierarchy, the larger the storage capacity and the higher the recording density are required. In FIG. 29(A), from the top layer, there are a memory integrated as a register in an arithmetic processing device such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, a storage, and the like. Note that, although an example having up to an L3 cache is shown here, a lower cache may also be included.

[0553] The memory embedded as a register in a processor such as a CPU is used for temporary storage of calculation results, and is accessed frequently by the processor. Therefore, a faster operating speed is required rather than a larger memory capacity. The register also has the function of storing setting information for the processor.

[0554] A cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the access speed to the data can be increased. The storage capacity required for a cache is smaller than that of the main memory, but it is required to operate faster than the main memory. In addition, data rewritten in the cache is duplicated and supplied to the main memory.

[0555] The main memory has a function of holding programs, data, etc. read from the storage.

[0556] Storage has the function of storing data that needs to be stored for a long time, various programs used by the processing unit, etc. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. For example, a high-capacity, non-volatile storage device such as 3D NAND can be used.

[0557] A storage device using an oxide semiconductor according to one embodiment of the present invention (OS memory) has a high operating speed and can retain data for a long period of time. Specifically, the OS memory can be, for example, a DOSRAM, a NOSRAM, or an OS-SRAM described in the above embodiment. As shown in FIG. 29A , the storage device according to one embodiment of the present invention can be preferably used in both the hierarchy where a cache is located and the hierarchy where a main memory is located. The storage device according to one embodiment of the present invention can also be applied to the hierarchy where a storage is located. For example, the storage device using the transistor 500 described in the above embodiment can be applied to the hierarchy where a storage is located.

[0558] FIG. 29B shows an example in which an SRAM is used as part of a cache, and an OS memory according to one embodiment of the present invention is used as the other part.

[0559] The lowest level cache can be called a Last Level cache (LLC). Although an LLC is not required to operate faster than higher level caches, it is desirable for the LLC to have a large storage capacity. The OS memory of one embodiment of the present invention has a high operating speed and is capable of retaining data for a long period of time, and therefore can be suitably used for an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to a Final Level cache (FLC).

[0560] For example, as shown in Fig. 29(B), a configuration can be adopted in which an SRAM is used for a higher-level cache (such as an L1 cache or an L2 cache) and an OS memory according to one embodiment of the present invention is used for an LLC. Also, as shown in Fig. 29(B), not only an OS memory but also a DRAM can be applied to the main memory.

[0561] This embodiment mode can be combined with other embodiment modes as appropriate.

[0562] (Embodiment 4) In this embodiment, application examples of the semiconductor device of one embodiment of the present invention will be described.

[0563] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, the electronic components, mainframes, space equipment, data centers, and various electronic devices can achieve low power consumption and high performance.

[0564] Further, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0565] Examples of electronic devices include electronic devices with relatively large screens, such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0566] The electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0567] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded on a recording medium, etc.

[0568] [Electronic components] FIG. 30A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 30A has a semiconductor device 710 in a mold 711. FIG. 30A omits some parts in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0569] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. By stacking the drive circuit layer 715 and the memory layer 716 monolithically, for example, a so-called on-chip memory configuration can be formed in which a memory is directly formed on a processor. The on-chip memory configuration makes it possible to speed up the operation of the interface between the processor and the memory.

[0570] In addition, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSV, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).

[0571] In addition, it is preferable that the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that in the case of a configuration using Si transistors in the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that the OS transistor has a superior structure to the Si transistor in the monolithic stacked configuration.

[0572] The semiconductor device 710 may also be referred to as a die. In this specification and the like, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape in the manufacturing process of a semiconductor chip. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0573] 30B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0574] In the electronic component 730, the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0575] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0576] The interposer 731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 also has a function of electrically connecting the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV may be used as the through electrode.

[0577] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0578] In addition, in SiP and MCM using silicon interposers, the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0579] On the other hand, when a silicon interposer, TSV, or the like is used to electrically connect multiple integrated circuits with different terminal pitches, a space is required for the width of the terminal pitch. Therefore, when trying to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSV and a monolithic stacking memory cell array.

[0580] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0581] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 30(B) shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0582] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0583] [Large computer] Next, Figure 31(A) shows a perspective view of a large scale computer 5600. The large scale computer 5600 shown in Figure 31(A) has a rack 5610 housing a plurality of rack-mounted computers 5620. The large scale computer 5600 may also be called a supercomputer.

[0584] The computer 5620 can have the configuration shown in the perspective view of Fig. 31(B), for example. In Fig. 31(B), the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, each of which is connected to the motherboard 5630.

[0585] A PC card 5621 shown in Fig. 31C is an example of a processing board including a CPU, a GPU, a storage device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in Fig. 31C, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to for these semiconductor devices.

[0586] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0587] The connection terminals 5623, 5624, and 5625 can be interfaces for supplying power and inputting signals to the PC card 5621, for example. They can also be interfaces for outputting signals calculated by the PC card 5621, for example. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0588] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0589] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0590] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring provided on the board 5622 by a reflow method. The semiconductor device 5628 can be, for example, a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0591] The mainframe 5600 can also function as a parallel computer. By using the mainframe 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference of artificial intelligence, for example.

[0592] [Space equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0593] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor has small variations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0594] Fig. 31(D) shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 includes a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 31(D) shows a planet 6804 in space.

[0595] 31D, a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The battery management system or the battery control circuit is preferably formed using an OS transistor because it consumes low power and has high reliability even in space.

[0596] Furthermore, outer space is an environment with radiation levels 100 times higher than on the ground. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0597] When sunlight is irradiated onto the solar panel 6802, power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight or where the amount of sunlight irradiated onto the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 is not generated. In order to operate the satellite 6800 even in a situation where the generated power is small, a secondary battery 6805 can be provided on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0598] The artificial satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. As described above, the artificial satellite 6800 can constitute a satellite positioning system.

[0599] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor according to one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0600] The artificial satellite 6800 can also be configured to have a sensor. For example, by configuring the artificial satellite 6800 to have a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected from an object on the ground. Or, by configuring the artificial satellite 6800 to have a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have a function as, for example, an earth observation satellite.

[0601] Note that in this embodiment, an artificial satellite is given as an example of space equipment, but the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0602] As described above, OS transistors have the excellent advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0603] [Data Center] The semiconductor device according to one embodiment of the present invention can be suitably used in a storage system applied to a data center or the like. The data center is required to perform long-term data management, such as ensuring data immutability. In order to manage long-term data, it is necessary to increase the size of the building, for example, to install storage and servers for storing a huge amount of data, to secure a stable power source for storing the data, or to secure cooling equipment required for storing the data.

[0604] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores data. This makes it possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. As a result, it is possible to reduce the space required for the data center.

[0605] In addition, the semiconductor device of one embodiment of the present invention consumes less power, and thus heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0606] Fig. 31(E) shows a storage system applicable to a data center. A storage system 7010 shown in Fig. 31(E) has a plurality of servers 7001sb as a host 7001 (illustrated as Host Computer). It also has a plurality of storage devices 7003md as a storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0607] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0608] Although the storage 7003 uses flash memory to reduce the data access speed, that is, the time required to store and output data, this time is significantly longer than the time required by DRAM that can be used as cache memory in the storage. In order to solve the problem of the long access speed of the storage 7003, the storage system normally provides cache memory in the storage to reduce the time required to store and output data.

[0609] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0610] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced. In addition, by stacking memory cell arrays, the size can be reduced.

[0611] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO2). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.

[0612] This embodiment mode can be combined with other embodiment modes as appropriate. [Explanation of symbols]

[0613] ADDR: signal, BL: wiring, BW: signal, CE: signal, CLK: signal, GW: signal, Id: current, RDA: signal, SL: wiring, WAKE: signal, WDA: signal, 30: oxide semiconductor layer, 30a: oxide semiconductor layer, 30b: oxide semiconductor layer, 30c: oxide semiconductor layer, 114: conductive layer, 210: insulating layer, 229: layer, 231: mixed layer, 283: insulating layer, 285: insulating layer, 290c: opening, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 3 22: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 481: insulating layer, 482: insulating layer, 483: insulating layer, 500: transistor, 520: conductive layer, 530: oxide semiconductor layer, 540: conductive layer, 551: insulating layer, 552: charge storage layer, 553: insulating layer, 554: insulating layer, 555: charge storage layer, 556: insulating layer, 560: conductive layer, 590c: opening, 590d: opening, 590e: opening, 590f: opening, 601: memory cell array, 602: memory Cell, 611: memory cell array, 612: memory cell, 648: insulating layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory cell array, 923: row driver, 9 24: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register,997: Register controller, 998: Bus interface, 999: Cache, 5600: Mainframe, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Storage device, 7010: Storage system,

Claims

1. a first conductive layer, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, an oxide semiconductor layer, a fourth conductive layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a first charge storage layer, and a second charge storage layer; the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer each have an opening reaching the first conductive layer; the third insulating layer has a region in contact with a sidewall of the opening of the first insulating layer, a region in contact with a sidewall of the opening of the second conductive layer, and a region in contact with a top surface of the first conductive layer; the first charge storage layer has a region covering a side wall of the opening of the second conductive layer with the third insulating layer interposed therebetween; the fourth insulating layer has a region covering a side wall of the opening of the second conductive layer with the third insulating layer and the first charge storage layer interposed therebetween; the fourth insulating layer has a region sandwiched between the oxide semiconductor layer and the first charge storage layer, the oxide semiconductor layer has a region in contact with an upper surface of the first conductive layer, a region covering a side wall of the opening of the second conductive layer with the third insulating layer, the first charge storage layer, and the fourth insulating layer sandwiched therebetween, and a region in contact with the third conductive layer; the fourth conductive layer has a region located within the opening of the second conductive layer; the second charge storage layer has a region sandwiched between the oxide semiconductor layer and the fourth conductive layer, the fifth insulating layer has a region sandwiched between the oxide semiconductor layer and the second charge storage layer, The sixth insulating layer has a region sandwiched between the second charge storage layer and the fourth conductive layer.

2. In claim 1, the fourth insulating layer and the fifth insulating layer each include one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

3. In claim 1, A semiconductor device, wherein at least one of the first charge storage layer and the second charge storage layer comprises one or more metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing these metal elements, or an alloy combining these metal elements.

4. In claim 1, At least one of the first charge storage layer and the second charge storage layer comprises a metal nitride or a metal oxide.

5. In claim 1, At least one of the first charge storage layer and the second charge storage layer comprises at least one selected from silicon and germanium.

6. In claim 1, At least one of the first charge storage layer and the second charge storage layer comprises at least one selected from silicon nitride and silicon oxynitride.

7. In claim 1, the first conductive layer functions as one of a source electrode and a drain electrode of a transistor; the third conductive layer functions as the other of the source electrode and the drain electrode of the transistor; the fourth conductive layer functions as a first control gate of the transistor; The second conductive layer functions as a second control gate of the transistor.

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