Semiconductor device

Abstract

To provide a semiconductor device capable of reducing a recovery loss.SOLUTION: A cell region 10 and a connection region 200 contain: a drift layer 31; a base layer 32 that is formed on a surface layer part of the drift layer 31; a collector layer 41 that is formed on an IGBT region 11 and the connection region 200; and a cathode layer 42 that is formed on an FWD region 12, and include: a semiconductor substrate 30 in which a front surface on the base layer 32 side is one surface 30a, and a surface of the side of the collector layer 41 and the cathode layer 42 is another surface 30b; a trench gate structure that is formed on the IGBT region 11, the FWD region 12, and the connection region 200; and a contact region 37 that is formed on the front surface layer part of the base layer 32 in an additional FWD region 12a and the connection region 200. In the one surface 30a of the semiconductor substrate 30, a formation area of the contact region 37 per unit area in the connection region 200 is constructed so as to be smaller than that of the contact region 37 per unit area in the additional FWD region 12a.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as an IGBT) element having an insulated gate structure and a free wheel diode (hereinafter referred to as an FWD) element are formed on a common semiconductor substrate. [Background technology]

[0002] Conventionally, a semiconductor device has been proposed that has an IGBT region where an IGBT element is formed and an FWD region where an FWD element is formed (see, for example, Patent Document 1). Specifically, this semiconductor device has a configuration that has a cell region and an outer peripheral region that surrounds the cell region. A plurality of IGBT regions and FWD regions are formed in the cell region, and gate pads and the like that are connected to the gate electrodes of the IGBT elements are formed in the outer peripheral region. The IGBT element is formed by a P-type base layer and a P-type base layer formed in the surface layer of the base layer. + Type contact area and N + The FWD element has a P-type emitter region, a base layer, a contact region, and a trench gate structure formed to penetrate the emitter region. The FWD element has a P-type base layer and a P-type + The semiconductor device has a contact region of a mold, and a trench gate structure formed so as to penetrate the base layer and the contact region.

[0003] In this semiconductor device, each IGBT region and each FWD region has a rectangular planar shape with one longitudinal direction, and the IGBT regions and FWD regions are alternately arranged along an intersecting direction intersecting the longitudinal direction. In this semiconductor device, the ends of the IGBT regions and FWD regions in the intersecting direction (i.e., arrangement direction) are IGBT regions. The pads are arranged in the intersecting direction relative to the cell regions. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-073911 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to prevent the electric field concentration in the peripheral region of the semiconductor device described above, the present inventors have been studying the following semiconductor device. That is, the present inventors have been considering a semiconductor device in which a P + The inventors are considering forming a deep layer of the same type. However, if the deep layer is placed near the cell region, holes as carriers tend to flow from the deep layer into the FWD element when the FWD element is in the on state, which increases the reverse current and therefore the recovery loss. For this reason, the inventors are considering the following configuration: the region of the peripheral region located on the cell region side is designated as the inner edge region, and the region located on the opposite side of the inner edge region from the cell region is designated as the outer edge region. That is, the inventors are considering forming a base layer, contact region, trench gate structure, etc., similar to those in the cell region, in the inner edge region, and forming a deep layer in the outer edge region.

[0006] According to this, a trench gate structure is also formed between the deep layer and the cell region, so that it is possible to suppress the occurrence of electric field concentration in the inner edge region.

[0007] Furthermore, the inventors have considered placing an additional FWD region next to the pad in order to increase the cell region in the semiconductor device. Hereinafter, the FWD region added next to the pad is also referred to as the additional FWD region. In the cell region of such a semiconductor device, the end of the cell region on the pad side in the cross direction includes the additional FWD region.

[0008] However, in a semiconductor device having such an additional FWD region, the edge of the pad portion in the cross direction includes the additional FWD region, which increases the area where the FWD region and the peripheral region are adjacent to each other. As a result, in such a semiconductor device, when the FWD element is in the on state, an inflow of holes as carriers from the peripheral region increases, which may increase recovery loss.

[0009] An object of the present disclosure is to provide a semiconductor device capable of reducing recovery loss. [Means for solving the problem]

[0010] According to one aspect of the present disclosure, a semiconductor device includes a semiconductor substrate (30) having a cell region (10) and a peripheral region (20) surrounding the cell region, an IGBT region (11) formed in the cell region and having an IGBT element, and an FWD region (12) formed in the cell region and having an FWD element, the IGBT region and the FWD region being alternately formed in one direction in the surface direction of the semiconductor substrate, and a pad portion (21) electrically connected to the IGBT element is formed in the peripheral region on one end side in the one direction, and the cell region is connected to the pad portion by a semiconductor substrate (30) with respect to the semiconductor substrate. The plate has an additional FWD region (12a) as an FWD region on the other side intersecting with one direction in the surface direction of the plate, and an end portion on the pad portion side in the one direction is configured to include the additional FWD region, the outer periphery region has an inner edge region (20a) on the cell region side and an outer edge region (20b) located on the opposite side to the cell region with the inner edge region in between, and the inner edge region has a connection region (200) located between the additional FWD region and the outer edge region, and the cell region and the connection region are configured to include a drift layer (31) of a first conductivity type, a base layer (32) of a second conductivity type formed in a surface layer portion of the drift layer, and an IGBT a semiconductor substrate including a collector layer (41) of a second conductivity type formed on the side of the drift layer opposite to the base layer side in the IGBT region and the connection region, and a cathode layer (42) of a first conductivity type formed on the side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (30a) and a surface on the collector layer and cathode layer side as the other surface (30b); and a gate insulating film (34) and a gate electrode (36) formed in a plurality of trenches (33) formed in the IGBT region, the FWD region, and the connection region, and formed deeper than the base layer to reach the drift layer. The semiconductor device has a trench gate structure in which a first conductive type emitter region (36) is formed in contact with the trench in a surface layer portion of the base layer in the IGBT region, and a second conductive type contact region (37) formed in a surface layer portion of the base layer in the additional FWD region and the connection region and having a higher impurity concentration than the base layer, and on one surface of the semiconductor substrate, the formation area of ​​the contact region per unit area in the connection region is smaller than the formation area of ​​the contact region per unit area in the additional FWD region.

[0011] According to this, the area of ​​the contact region per unit area in the connection region is smaller than the area of ​​the contact region per unit area in the additional FWD region, which prevents an increase in recovery loss even in a semiconductor device having an additional FWD region.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 2 is a perspective cross-sectional view of an IGBT region. [Figure 5] FIG. 2 is an enlarged plan view of region V in FIG. [Figure 6] FIG. 2 is a schematic diagram showing the flow of holes when the FWD element according to the first embodiment is in an on state. [Figure 7] FIG. 10 is a schematic diagram showing the flow of holes when the FWD element in the comparative example is in the on state. [Figure 8] 4 is a diagram showing reverse current characteristics of the semiconductor device according to the first embodiment and a semiconductor device of a comparative example. FIG. [Figure 9] FIG. 10 is a diagram illustrating the relationship between the connection area width ratio and recovery loss. [Figure 10] FIG. 11 is a plan view of the other surface side of the FWD region in the second embodiment. [Figure 11A] FIG. 11 is a plan view of the other surface side of the FWD region in a modified example of the second embodiment. [Figure 11B] FIG. 11 is a plan view of the other surface side of the FWD region in a modified example of the second embodiment. [Figure 12] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 13] FIG. 10 is a plan view of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0015] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use as a power switching element used in power supply circuits such as inverters and DC / DC converters.

[0016] 1, the semiconductor device has a cell region 10 and a peripheral region 20 surrounding the cell region 10. First, the planar configuration of the semiconductor device in this embodiment will be described.

[0017] The cell region 10 has an IGBT region 11 in which an IGBT element is formed, and an FWD region 12 in which an FWD element is formed. That is, the semiconductor device of this embodiment is an RC (abbreviation of Reverse Conducting)-IGBT in which the IGBT region 11 and the FWD region 12 are formed within a common semiconductor substrate 30, which will be described later. Note that, as will be described in detail later, in this embodiment, the portion on the collector layer 41 located on the other surface 30b of the semiconductor substrate 30 is the IGBT region 11, and the portion on the cathode layer 42 located on the other surface 30b of the semiconductor substrate 30 is the FWD region 12. Although FIG. 1 is not a cross-sectional view, the FWD region 12 is hatched for ease of understanding.

[0018] In this embodiment, the IGBT region 11 and the FWD region 12 are formed to have portions that are alternately arranged along one direction in the cell region 10. That is, the IGBT region 11 and the FWD region 12 are formed to have portions that are alternately arranged along one direction in the surface direction of the semiconductor substrate 30, which will be described later.

[0019] In this embodiment, the IGBT regions 11 and the FWD regions 12 are rectangular regions each having a longitudinal direction, and are alternately formed along an intersecting direction intersecting the longitudinal direction. In the following description, the longitudinal direction of the IGBT regions 11 and the FWD regions 12 is referred to as a first direction, and the intersecting direction is referred to as a second direction. In FIG. 1, the left-right direction on the paper surface is the first direction, and the up-down direction on the paper surface is the second direction.

[0020] The second direction can also be referred to as one direction in the surface direction of the semiconductor substrate 30 described later, and the first direction can also be referred to as another direction perpendicular to the second direction and along the surface direction of the semiconductor substrate 30 described later.

[0021] The peripheral region 20 is formed with a plurality of pads 21 connected to gate electrodes 35 (described later) and a temperature sensing element (not shown). In this embodiment, five pads 21 are arranged, and are lined up along the first direction at one end on the second direction side. In the following description, of the rectangular frame-shaped portion of the peripheral region 20 that follows the outline of the semiconductor device, the portion on the cell region 10 side will be referred to as an inner edge region 20a, and the region located on the opposite side of the inner edge region 20a from the cell region 10 will be referred to as an outer edge region 20b. The pads 21 are arranged in the inner edge region 20a.

[0022] In this embodiment, two cell regions 10 are arranged along the first direction, and the inner edge region 20a is a rectangular frame-shaped portion surrounding the two cell regions 10. Five IGBT regions 11 are formed along the second direction in each cell region 10. In each cell region 10, an FWD region 12 is formed between adjacent IGBT regions 11 along the second direction. Furthermore, the FWD region 12 is also formed in a portion located in the first direction relative to the pad portion 21, at one end side in the second direction where the pad portion 21 is arranged. Hereinafter, the FWD region 12 located at one end side in the second direction where the pad portion 21 is arranged is also referred to as an additional FWD region 12a.

[0023] In this embodiment, the additional FWD regions 12a in each cell region 10 are formed to sandwich the pad section 21 in the first direction. The portion of the cell region 10 facing the pad section 21 in the second direction is the IGBT region 11. That is, the length of the additional FWD region 12a in the first direction is shorter than the length of the IGBT region 11 and the other FWD regions 12 in the first direction. Hereinafter, the portion of the inner edge region 20a located between the additional FWD region 12a and the outer edge region 20b will be described as a connection region 200.

[0024] The above is the planar configuration of the semiconductor device in this embodiment. Next, the configuration of the semiconductor device will be described with reference to FIGS. 2 to 5. The additional FWD region 12a has the same basic configuration as the other FWD regions 12. For example, while FIG. 3 shows the configuration of the additional FWD region 12a as the configuration of the FWD region 12, the configuration of the other FWD regions 12 is also the same as the configuration of the additional FWD region 12a. In addition, in FIG. 4, an interlayer insulating film 38, an upper electrode 39, a lower electrode 43, and the like, which will be described later, are omitted. In addition, in FIG. 5, the interlayer insulating film 38 and the upper electrode 39, which will be described later, are omitted.

[0025] As shown in FIGS. 2 to 4, the semiconductor device -The semiconductor substrate 30 has a P-type drift layer 31. In this embodiment, the semiconductor substrate 30 is made of a silicon substrate. A P-type base layer 32 is formed on the drift layer 31 in the cell region 10 and the connection region 200 in the peripheral region 20. In the following description, the surface of the semiconductor substrate 30 on which the base layer 32 is formed is referred to as one surface 30a of the semiconductor substrate 30, and the surface opposite to the one surface 30a is referred to as the other surface 30b.

[0026] A plurality of trenches 33 are formed in the semiconductor substrate 30 so as to penetrate the base layer 32 from the one surface 30a side to reach the drift layer 31. As a result, the base layer 32 is separated into a plurality of parts by the trenches 33. In this embodiment, the plurality of trenches 33 are formed in the IGBT region 11, the additional FWD region 12a, and the connection region 200. Note that, as shown in FIG. 2 , the trenches 33 formed in the peripheral region 20 are not formed below the pad portion 21, etc. Furthermore, in this embodiment, the plurality of trenches 33 are formed in a stripe shape with the first direction as the longitudinal direction.

[0027] Each trench 33 is filled with a gate insulating film 34 formed to cover the wall surface of each trench 33, and a gate electrode 35 made of polysilicon or the like formed on this gate insulating film 34. This forms a trench gate structure.

[0028] 1 via a gate wiring (not shown), so that a predetermined gate voltage is applied to the gate electrode 35. The gate electrodes 35 disposed in the trenches 33 formed in the additional FWD region 12a (i.e., the FWD region 12) and the connection region 200 are electrically connected to an upper electrode 39 (described later). In other words, the gate electrodes 35 in the additional FWD region 12a and the connection region 200 are maintained at a predetermined potential.

[0029] The surface layer of the base layer 32 in the IGBT region 11 (i.e., the surface 30a side of the semiconductor substrate 30) is doped with N + The IGBT region 11, the FWD region 12, and the connection region 200 have a surface layer of the base layer 32, which is formed with a P + A mold contact region 37 is formed.

[0030] In this embodiment, the emitter regions 36 and contact regions 37 in the IGBT region 11 are formed so as to be alternately arranged along the first direction between trenches 33 adjacent to each other in the second direction, as shown in Fig. 4. The emitter regions 36 and contact regions 37 in the IGBT region 11 are also formed so as to be in contact with trenches 33 adjacent to each other in the second direction. Hereinafter, trenches 33 adjacent to each other in the second direction will also be simply referred to as adjacent trenches 33.

[0031] 5, the contact regions 37 in the additional FWD region 12a and the connection region 200 are formed to be scattered along the first direction. No emitter region 36 is disposed between adjacent contact regions 37 in the first direction, but a base layer 32 is disposed therebetween. That is, in the additional FWD region 12a and the connection region 200, the contact regions 37 and the base layers 32 are alternately disposed along the first direction between adjacent trenches 33.

[0032] Here, the additional FWD region 12a and the connection region 200 are formed so that the contact regions 37 satisfy the following relationship: Specifically, the contact regions 37 are formed so that the formation area of ​​the contact regions 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact regions per unit area in the additional FWD region 12a. In other words, the contact regions 37 of the additional FWD region 12a and the connection region 200 are adjusted such that the ratios of the contact regions 37 to the surface 30a of the semiconductor substrate 30 located between adjacent trenches 33 are adjusted as follows: Hereinafter, the ratio of the contact regions 37 to the surface 30a of the semiconductor substrate 30 located between adjacent trenches 33 is also simply referred to as the ratio of the contact regions 37. That is, the ratio of the contact regions 37 to the surface 30a of the semiconductor substrate 30 located between adjacent trenches 33 is smaller in the connection region 200 than in the additional FWD region 12a. In other words, in this embodiment, the area of ​​the additional FWD region 12a that can make ohmic contact with the upper electrode 39 (described later) is larger than that of the connection region 200.

[0033] In this embodiment, when the length along the first direction is defined as the width, the width d1 of the contact region 37 in the additional FWD region 12a is set wider than the width d2 of the contact region 37 in the connection region 200. In other words, the width d3 of the base layer 32 in the additional FWD region 12a is set narrower than the width d4 of the base layer 32 in the connection region 200.

[0034] 2 and 3, an interlayer insulating film 38 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on one surface 30a of the semiconductor substrate 30. The interlayer insulating film 38 has a contact hole 38a formed therein in the IGBT region 11, exposing the emitter region 36 and the contact region 37. The interlayer insulating film 38 has a contact hole 38b formed therein in the FWD region 12 and the connection region 200, exposing the contact region 37 and the base layer 32. The interlayer insulating film 38 also has a contact hole 38c formed therein in the FWD region 12 and the peripheral region 20, exposing the gate electrode 35. The interlayer insulating film 38 also has a contact hole 38d formed therein in the peripheral region 20, exposing a deep layer 44 (described later).

[0035] An upper electrode 39 is formed on the interlayer insulating film 38. Specifically, the upper electrode 39 is formed in the IGBT region 11 so as to be electrically connected to the emitter region 36 and the contact region 37 (i.e., the base layer 32) through a contact hole 38a formed in the interlayer insulating film 38. The upper electrode 39 is formed in the FWD region 12 and the connection region 200 so as to be electrically connected to the base layer 32 and the contact region 37 through a contact hole 38b formed in the interlayer insulating film 38. That is, the upper electrode 39 is formed on the interlayer insulating film 38 and functions as an emitter electrode in the IGBT region 11 and as an anode electrode in the FWD region 12. The upper electrode 39 is also formed in the FWD region 12 and the connection region 200 so as to be electrically connected to the gate electrode 35 through a contact hole 38c formed in the interlayer insulating film 38. As a result, the gate electrode 35 formed in the FWD region 12 and the connection region 200 is maintained at the same potential as the upper electrode 39. Moreover, the upper electrode 39 is formed in the peripheral region 20 so as to be electrically connected to a deep layer 44 (described later) through a contact hole 38d formed in the interlayer insulating film 38.

[0036] An N-type field stop layer (hereinafter referred to as an FS layer) 40 having a higher impurity concentration than the drift layer 31 is formed on the side of the drift layer 31 opposite to the base layer 32 side (i.e., the other surface 30b side of the semiconductor substrate 30).

[0037] In the IGBT region 11, a P + In the additional FWD region 12a, an N-type collector layer 41 is formed on the side opposite to the drift layer 31 with the FS layer 40 interposed therebetween. + A cathode layer 42 having a shaped cross section is formed in the additional FWD region 12a. That is, the IGBT region 11 and the additional FWD region 12a (i.e., the FWD region 12) are separated depending on whether the layer formed on the other surface 30b of the semiconductor substrate 30 is a collector layer 41 or a cathode layer 42. In the peripheral region 20, the collector layer 41 is formed on the opposite side of the drift layer 31 with the FS layer 40 interposed therebetween.

[0038] A lower electrode 43 electrically connected to the collector layer 41 and the cathode layer 42 is formed on the opposite side of the drift layer 31 (i.e., the other surface 30b of the semiconductor substrate 30) across the collector layer 41 and the cathode layer 42. That is, the lower electrode 43 functions as a collector electrode in the IGBT region 11 and as a cathode electrode in the FWD region 12. The lower electrode 43 is also connected to the collector layer 41 in the peripheral region 20.

[0039] With the above-described configuration, in the FWD region 12, a PN junction FWD element is configured, with the base layer 32 and the contact region 37 serving as the anode and the drift layer 31, the FS layer 40, and the cathode layer 42 serving as the cathode.

[0040] As described above, the connection region 200 in the peripheral region 20 has the same basic configuration on the one surface 30a as that of the additional FWD region 12a, and the collector layer 41 is disposed on the other surface 30b. However, as described above, the formation area of ​​the contact region 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact region 37 per unit area in the additional FWD region 12a.

[0041] The outer edge region 20b of the peripheral region 20 is connected to the base layer 32 and has a higher impurity concentration than the base layer. + A mold deep layer 44 is formed. In this embodiment, the deep layer 44 is formed deeper than the base layer 32, extends to a portion below the pad portion 21 in the inner edge region 20a, is connected to the base layer 32, and is formed in a frame shape so as to surround the inner edge region 20a.

[0042] Furthermore, although not shown, a guard ring or the like is appropriately formed in the outer peripheral region 20 so as to surround the deep layer 44. The guard ring has a multi-ring structure in which a plurality of guard rings are formed so as to surround the deep layer 44, for example.

[0043] A protective film 45 made of polyimide or the like is formed on one surface 30a of the semiconductor substrate 30. In the protective film 45, a contact hole 45a exposing the upper electrode 39 in the cell region 10 and a contact hole 45b exposing the pad portion 21 in the peripheral region 20 are formed. The contact hole 45a is formed, for example, in a substantially rectangular shape to match the cell region 10. In this case, the additional FWD region 12a is a portion arranged in addition to the substantially rectangular cell region 10, and therefore most of the additional FWD region 12a is covered with the protective film 45.

[0044] The above is the configuration of the semiconductor device in this embodiment. + Type, N - The first conductivity type corresponds to P type, P +In this embodiment, since the semiconductor device is configured as described above, the semiconductor substrate 30 includes a collector layer 41, a cathode layer 42, a drift layer 31, a base layer 32, an emitter region 36, a contact region 37, and the like.

[0045] Next, the operation of the semiconductor device will be explained, and the detailed configuration of the semiconductor device will be explained.

[0046] In the semiconductor device described above, when a voltage higher than that of the upper electrode 39 is applied to the lower electrode 43, the PN junction formed between the base layer 32 and the drift layer 31 becomes reverse conductive, forming a depletion layer. When a low-level gate voltage (e.g., 0 V) ​​that is lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35, no current flows between the upper electrode 39 and the lower electrode 43.

[0047] To turn the IGBT element on, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 35 of the IGBT region 11 while a voltage higher than that of the upper electrode 39 is applied to the lower electrode 43. As a result, in the IGBT region 11, an inversion layer is formed in the portion of the base layer 32 that contacts the trench 33 in which the gate electrode 35 is disposed. Then, in the IGBT element, electrons are supplied to the drift layer 31 from the emitter region 36 via the inversion layer, and holes are supplied to the drift layer 31 from the collector layer 41, and the resistance value of the drift layer 31 decreases due to conductivity modulation. As a result, a current flows between the upper electrode 39 and the lower electrode 43 in the IGBT element.

[0048] Furthermore, when the IGBT element is turned off and the FWD element is turned on (i.e., when the FWD element operates as a diode), the voltages applied to the upper electrode 39 and the lower electrode 43 are switched, and a forward voltage is applied to the upper electrode 39 such that a voltage higher than that of the lower electrode 43 is applied. As a result, holes are supplied to the base layer 32 and electrons are supplied to the cathode layer 42, causing the FWD element to operate as a diode.

[0049] In this case, the connection region 200 has the contact region 37 formed on the one surface 30a of the semiconductor substrate 30 as described above, and when the FWD element is turned on, holes are supplied to the base layer 32 via the contact region 37. However, in this embodiment, the formation area per unit area of ​​the contact region 37 in the connection region 200 in the periphery region 20 is smaller than the formation area per unit area of ​​the contact region in the additional FWD region 12a. Therefore, when the FWD element is turned on, the amount of holes supplied from the connection region 200 in the periphery region 20 to the additional FWD region 12a can be reduced, as shown in FIGS. 6 and 7 .

[0050] 6 shows the flow of holes when the FWD element of the semiconductor device of this embodiment is turned on, and FIG. 7 shows the flow of holes when the FWD element of the semiconductor device of the comparative example is turned on. The comparative semiconductor device of this embodiment refers to a semiconductor device in which the area of ​​contact regions 37 per unit area in the connection region 200 is equal to the area of ​​contact regions per unit area in the additional FWD region 12a. Arrows A and B in FIG. 6 and arrows A and C in FIG. 7 indicate the flow of holes.

[0051] Thereafter, when the FWD element is changed from the on state to the off state, a reverse voltage is applied to the lower electrode 43, that is, a voltage higher than that of the upper electrode 39. In other words, when a forward current is flowing through the FWD element and the current is to be cut off, a reverse voltage is applied to the lower electrode 43, that is, a voltage higher than that of the upper electrode 39. This puts the FWD element into a recovery state.

[0052] In this case, as described above, in this embodiment, when the FWD element is in the on state, the supply of holes from the connection region 200 in the peripheral region 20 to the additional FWD region 12 a is suppressed, thereby reducing the recovery current and the recovery loss Err.

[0053] Specifically, the inventors conducted a study and obtained the results shown in Fig. 8. As shown in Fig. 8, it was confirmed that the semiconductor device of this embodiment can reduce the maximum reverse current Irr and the tail current compared to the semiconductor device of the comparative example. Furthermore, since the integral value of the reverse current Ir in Fig. 8, that is, the area of ​​the region where the current value is negative, corresponds to the recovery loss Err, it was confirmed that it is possible to reduce the recovery loss Err by reducing the maximum reverse current Irr.

[0054] The inventors also conducted extensive research into the width of the connection region 200 and obtained the results shown in FIG. 9 . FIG. 9 shows the ratio of the width La of the connection region 200 to the thickness of the semiconductor substrate 30 as the connection region width ratio. The width La of the connection region 200 refers to the length along the second direction of a region in which the area of ​​the contact region 37 per unit area is smaller than the area of ​​the contact region per unit area in the additional FWD region 12a. In this embodiment, the entire region between the additional FWD region 12a and the deep layer 44 is defined as the connection region 200. Therefore, the width La of the connection region 200 corresponds to the length along the second direction between the additional FWD region 12a and the deep layer 44, as shown in FIG. 1 . The thickness of the semiconductor substrate 30 refers to the length between the one surface 30a and the other surface 30b of the semiconductor substrate 30.

[0055] 9, it is confirmed that the recovery loss Err gradually decreases as the connection region width ratio increases in the range of less than 1.2. Then, the recovery loss Err becomes almost unchanged when the connection region width ratio is 1.2 or more. For this reason, it is preferable that the semiconductor device has a connection region width ratio of 1.2 or more.

[0056] Note that although the magnitude of the recovery loss Err changes when the formation area of ​​the contact regions 37 in the connection region 200 is changed, the relationship between the recovery loss Err and the connection region width ratio does not change. In other words, the recovery loss Err can be appropriately changed as long as the formation area of ​​the contact regions 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact regions per unit area in the additional FWD region 12a. However, regardless of the formation area, it is preferable that the connection region width ratio be 1.2 or more.

[0057] The above is the operation of the semiconductor device according to this embodiment. Such a semiconductor device is used, for example, as follows. Specifically, the semiconductor device is used by disposing a nickel-plated film or the like on the portion of the upper electrode 39 that is exposed from the protective film 45, and by disposing other electrodes or the like on the nickel-plated film via solder or the like. In this case, the contact hole 45a formed in the protective film 45 has an opening that is generally rectangular in plan view, which makes it easier to suppress the spread of solder disposed on the nickel-plated film. For this reason, in this embodiment, the contact hole 45a has a generally rectangular plan view, and most of the additional FWD region 12a is covered by the protective film 45.

[0058] However, in this configuration, the protective film 45 is disposed on the additional FWD region 12a, which may impair the heat dissipation of the additional FWD region 12a. The inventors' investigations have confirmed that, when considering heat dissipation, the heat dissipation can be reduced if the width between the additional FWD region 12a and the outer edge region 20b (i.e., the deep layer 44) is approximately twice the thickness of the semiconductor substrate 30 or more. Therefore, if the additional FWD region 12a of the semiconductor device may become hot during use, it is preferable that the width between the additional FWD region 12a and the outer edge region 20b be approximately twice the thickness of the semiconductor substrate 30 or more. In this embodiment, since only the connection region 200 is disposed between the additional FWD region 12a and the outer edge region 20b, the width between the additional FWD region 12a and the outer edge region 20b is the width La of the connection region 200.

[0059] According to the present embodiment described above, the formation area of ​​the contact region 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact region 37 per unit area in the additional FWD region 12a. Therefore, even in a semiconductor device having the additional FWD region 12a, an increase in the recovery loss Err can be suppressed.

[0060] (1) In this embodiment, the connection region width ratio is set to 1.2 or more, which makes it possible to sufficiently suppress an increase in the recovery loss Err.

[0061] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that a suppression layer is added to the FWD region 12. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0062] 10, in the semiconductor device of this embodiment, an suppression layer 46 is formed in the cathode layer 42 on the other surface 30b side in the FWD region 12. In this embodiment, the suppression layer 46 is p + The suppression layer 46 has the same impurity concentration as the collector layer 41. Although not shown, the suppression layer 46 has the same depth as the collector layer 41. In this embodiment, a plurality of the suppression layers 46 extend along the first direction. The suppression layers 46 are formed simultaneously when the collector layer 41 is formed.

[0063] According to the present embodiment described above, the formation area of ​​the contact region 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact region 37 per unit area in the additional FWD region 12a. Therefore, the same effects as those in the first embodiment can be obtained.

[0064] (1) In this embodiment, the suppression layer 46 is formed in the cathode layer 42. Therefore, when the FWD device is in the on state, holes injected from the upper electrode 39 can be turned into inactive carriers when they reach the suppression layer 46, thereby suppressing the injection of electrons from the lower electrode 43. This further reduces the recovery loss Err.

[0065] (Modification of the second embodiment) A modification of the second embodiment will be described. As shown in FIG. 11A, a plurality of suppression layers 46 may be formed along the second direction. Alternatively, as shown in FIG. 11B, the suppression layers 46 may be scattered along the first and second directions. In other words, the suppression layers 46 may extend along the first or second direction, and the extended portions may be divided into a plurality of pieces. In other words, the suppression layers 46 may be formed so that the cathode layer 42 has a lattice pattern.

[0066] The suppression layer 46 may have any configuration as long as it suppresses the injection of electrons from the lower electrode 43 when the FWD element is in the on state. For this reason, the suppression layer 46 may be of N-type with a lower impurity concentration than the cathode layer 42.

[0067] (Third embodiment) A third embodiment will now be described. This embodiment differs from the first embodiment in that the width of the additional FWD region 12a and the width of the other FWD regions 12 are changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0068] 12, in the FWD region 12, the FWD region 12 different from the additional FWD region 12a is defined as the inner edge FWD region 12b. That is, the FWD region 12 sandwiched between the IGBT regions 11 in the second direction among the FWD regions 12 is defined as the inner edge FWD region 12b.

[0069] In the semiconductor device of this embodiment, when the lengths of the additional FWD region 12 a and the inner FWD region 12 b along the second direction are defined as widths da and db, respectively, the width da of the additional FWD region 12 a is narrower than the width db of the inner FWD region 12 b. In other words, the additional FWD region 12 a is configured to allow a smaller current to flow than the inner FWD region 12 b.

[0070] According to the present embodiment described above, the formation area of ​​the contact region 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact region 37 per unit area in the additional FWD region 12a. Therefore, the same effects as those in the first embodiment can be obtained.

[0071] (1) As described in the first embodiment, the protective film 45 is disposed on the additional FWD region 12a, which tends to result in a lower heat dissipation characteristic of the additional FWD region 12a than the inner FWD region 12b. Therefore, in this embodiment, the width da of the additional FWD region 12a is narrower than the width db of the inner FWD region 12b, so that the additional FWD region 12a can pass a smaller current than the inner FWD region 12b. In other words, the additional FWD region 12a is less likely to generate heat than the inner FWD region 12b. Therefore, the additional FWD region 12a can be prevented from becoming too hot and being destroyed.

[0072] (Fourth embodiment) A fourth embodiment will be described. In this embodiment, a connecting region is disposed between the additional FWD region and the IGBT region in comparison with the first embodiment. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0073] 13, in the semiconductor device of this embodiment, connection regions 13a and 13b are arranged between the FWD region 12 and the IGBT region 11. Hereinafter, the connection region arranged between the additional FWD region 12a and the IGBT region 11 will be referred to as a first connection region 13a, and the connection region arranged between the other FWD region 12 and the IGBT region 11 will be referred to as a second connection region 13b.

[0074] 14, the first connection region 13a has the same configuration as the connection region 200 on one surface 30a of the semiconductor substrate 30, and a collector layer 41 is disposed on the other surface 30b of the semiconductor substrate 30. That is, in the first connection region 13a, the formation area of ​​the contact region 37 per unit area is smaller than the formation area of ​​the contact region 37 per unit area in the IGBT region 11. Note that although the configuration of the second connection region 13b is not particularly shown, it has the same configuration as the first connection region 13a.

[0075] As described above, the contact hole 45a is formed in a substantially rectangular shape that matches the cell region 10. Therefore, most of the first connection region 13a is covered with the protective film 45, similar to the additional FWD region 12a.

[0076] The first and second connecting regions 13a and 13b have widths dc and dd, respectively, along the second direction, and the width dc of the first connecting region 13a is wider than the width dd of the second connecting region 13b.

[0077] According to the present embodiment described above, the formation area of ​​the contact region 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact region 37 per unit area in the additional FWD region 12a. Therefore, the same effects as those in the first embodiment can be obtained.

[0078] (1) In this embodiment, the first and second connection regions 13a and 13b are disposed between the FWD region 12 and the IGBT region 11. This prevents holes from being injected from the IGBT region 11 into the FWD region 12 when the FWD element is in the ON state. Furthermore, the area of ​​the contact region 37 formed per unit area in the first and second connection regions 13a and 13b is smaller than the area of ​​the contact region 37 formed per unit area in the IGBT region 11. This reduces the amount of holes supplied from the first and second connection regions 13a and 13b to the FWD region 12 when the FWD element is in the ON state, compared to when the FWD region 12 and the IGBT region 11 are in contact with each other. This further reduces the recovery loss Err.

[0079] Furthermore, in this embodiment, the width dc of the first connection region 13a is set wider than the width dd of the second connection region 13b. Therefore, when the FWD element is in the on state, injection of holes from the IGBT region 11 to the additional FWD region 12 can be further suppressed compared to when the widths dc and dd of the first and second connection regions 13a and 13b are the same. This further reduces the recovery loss Err.

[0080] The gate electrode 35 in the first and second connection regions 13a and 13b may be applied with the same gate voltage as that applied to the gate electrode 35 in the IGBT region 11. In this way, when the IGBT element is in an on-state, a channel is also formed on the side surface of the trench 33 in the first and second connection regions 13a and 13b, and an increase in on-resistance due to the provision of the first and second connection regions 13a and 13b can be suppressed.

[0081] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0082] For example, in each of the above embodiments, an example has been described in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type can also be P type and the second conductivity type can be N type.

[0083] Furthermore, in each of the above embodiments, the gate electrode 35 in the FWD region 12 and the gate electrode 35 in the connection region 200 may be connected to other electrodes instead of the upper electrode 39 so that the potential is maintained.

[0084] In each of the above embodiments, the emitter region 36 similar to the IGBT region 11 may be formed in the FWD region 12 and the connection region 200.

[0085] In each of the above embodiments, the number of cell regions 10 may be one, or may be three or more.

[0086] Furthermore, in each of the above embodiments, the pad sections 21 may be arranged together at one end in the second direction on one end side in the first direction, and the additional FWD region 12a may be provided in only one of the cell regions 10 adjacent to each other in the first direction.

[0087] Furthermore, in each of the above embodiments, the detailed configuration can be modified as appropriate as long as the formation area of ​​the contact regions 37 per unit area in the connection region 200 is smaller than the formation area of ​​the contact regions 37 per unit area in the additional FWD region 12a. For example, the width d1 of the contact regions 37 in the additional FWD region 12a and the width d2 of the contact regions 37 in the connection region 200 are set equal, but the contact regions 37 in the connection region 200 may be thinned out. That is, the width d1 of the contact regions 37 in the additional FWD region 12a and the width d2 of the contact regions 37 in the connection region 200 may be set equal, but the width d4 of the base layer 32 in the connection region 200 may be wider than the width d4 of the base layer 32 in the additional FWD region 12a.

[0088] In each of the above embodiments, the connection region width ratio may be less than 1.2.

[0089] In each of the above embodiments, another region may be disposed between the connection region 200 and the outer edge region 20b. For example, the configuration of the one surface 30a of the semiconductor substrate 30 may be the same as the configuration of the additional FWD region 12a, and an intermediate region in which the collector layer 41 is disposed may be disposed on the other surface 30b. In this case, as long as the connection region width ratio is 1.2 or greater, the formation area of ​​the contact region in the intermediate region is not particularly limited and may be, for example, greater than or equal to the formation area of ​​the contact region in the additional FWD region 12a. In other words, the connection region 200 can be considered a region disposed between the additional FWD region 12a and the outer edge region 20b, where the formation area of ​​the contact region 37 per unit area is smaller than that of the additional FWD region 12a.

[0090] The respective embodiments may be appropriately combined to form a semiconductor device. For example, the second embodiment may be combined with the third or fourth embodiment, so that the suppression layer 46 is disposed in the cathode layer 42. The third embodiment may be combined with the fourth embodiment, so that the width da of the additional FWD region 12a is narrower than the width db of the inner edge FWD region 12b. Furthermore, combinations of the respective embodiments may be further combined.

[0091] [Disclosure of the Invention] The present disclosure described above can be understood from the following viewpoints, for example. [First viewpoint] A semiconductor device, a semiconductor substrate (30) having a cell region (10) and a peripheral region (20) surrounding the cell region; an IGBT region (11) formed in the cell region and having an IGBT element; an FWD region (12) formed in the cell region and having an FWD element; the IGBT regions and the FWD regions are alternately formed in one direction in the surface direction of the semiconductor substrate, In the outer peripheral region, a pad portion (21) electrically connected to the IGBT element is formed on one end side in the one direction, the cell region has an additional FWD region (12a) as the FWD region on the other side of the pad portion in a surface direction of the semiconductor substrate that intersects with the one direction, and an end portion of the cell region on the pad portion side in the one direction is configured to include the additional FWD region; The outer peripheral region has an inner edge region (20a) on the cell region side and an outer edge region (20b) located on the opposite side of the cell region with the inner edge region in between, the inner edge region has a connection region (200) located between the additional FWD region and the outer edge region; The cell region and the connection region are a semiconductor substrate including a drift layer (31) of a first conductivity type, a base layer (32) of a second conductivity type formed in a surface layer portion of the drift layer, a collector layer (41) of the second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region and the connection region, and a cathode layer (42) of the first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (30a) and a surface on the collector layer and cathode layer sides as the other surface (30b); a trench gate structure in which a gate insulating film (34) and a gate electrode (35) are disposed in a plurality of trenches (33) formed in the IGBT region, the FWD region, and the connection region, the trenches (33) being deeper than the base layer and reaching the drift layer; an emitter region (36) of a first conductivity type formed in a surface layer portion of the base layer in the IGBT region so as to be in contact with the trench; a second conductivity type contact region (37) formed in a surface layer portion of the base layer in the additional FWD region and the connection region and having a higher impurity concentration than the base layer, A semiconductor device, wherein, on one surface of the semiconductor substrate, a formation area of ​​the contact region per unit area in the connection region is smaller than a formation area of ​​the contact region per unit area in the additional FWD region.

[0092] [Second perspective] The semiconductor device according to a first aspect, wherein the connection region has a ratio of the width of the inner edge region along one direction to the thickness of the semiconductor substrate of 1.2 or more.

[0093] [Third Perspective] The semiconductor device according to the first or second aspect, wherein in the FWD region, an inhibition layer (46) of a second conductivity type or a first conductivity type having a lower impurity concentration than the cathode layer is formed in the cathode layer.

[0094] [Fourth viewpoint] The semiconductor device according to any one of the first to third aspects, wherein the width (da) of the additional FWD region along the one direction is narrower than the width (db) of the other FWD regions along the one direction.

[0095] [Fifth viewpoint] a connecting region (13a, 13b) disposed between the FWD region and the IGBT region; the connecting region has the base layer formed in a surface layer portion of the drift layer and the contact region formed in a surface layer portion of the base layer, On one surface of the semiconductor substrate, a formation area of ​​the contact region per unit area in the joining region is smaller than a formation area of ​​the contact region per unit area in the IGBT region; If the connecting region arranged between the additional FWD region and the IGBT region is a first connecting region (13a), and the connecting region arranged between the other FWD region and the IGBT region is a second connecting region (13b), A semiconductor device according to any one of the first to fourth aspects, wherein the first connection region and the second connection region have a width (dc) along the one direction in the first connection region that is wider than a width (dd) along the one direction in the second connection region. [Explanation of symbols]

[0096] 10 cell area 11 IGBT area 12 FWD area 12a Additional FWD area 20 Outer area 20a Inner border region 20b Outer region 30 Semiconductor substrate 31 Drift Layer 32 base layer 33 Trench 34 Gate insulating film 35 gate electrode 36 Emitter Area 37 Contact Area 200 connection areas

Claims

1. A semiconductor device comprising: A semiconductor substrate (30) having a cell region (10) and an outer peripheral region (20) surrounding the cell region; an IGBT region (11) formed in the cell region and having an IGBT element; an FWD region (12) formed in the cell region and having an FWD element; the IGBT region and the FWD region are alternately formed in one direction in a surface direction of the semiconductor substrate, In the outer circumferential region, a pad portion (21) electrically connected to the IGBT element is formed on one end side in the one direction, the cell region has an additional FWD region (12a) as the FWD region on the other direction side intersecting with the one direction in the surface direction of the semiconductor substrate with respect to the pad portion, and an end portion on the pad portion side in the one direction is configured to include the additional FWD region, The outer peripheral region has an inner edge region (20a) on the cell region side and an outer edge region (20b) located on the opposite side of the cell region with the inner edge region therebetween, the inner edge region has a connection region (200) located between the additional FWD region and the outer edge region; The cell region and the connection region are a first conductivity type drift layer (31), a second conductivity type base layer (32) formed in a surface layer portion of the drift layer, a second conductivity type collector layer (41) formed on a side of the drift layer opposite to the base layer side in the IGBT region and the connection region, and a first conductivity type cathode layer (42) formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (30a) and a surface on the collector layer and cathode layer sides as the other surface (30b); a trench gate structure in which a gate insulating film (34) and a gate electrode (35) are disposed in a plurality of trenches (33) formed in the IGBT region, the FWD region, and the connection region, the trenches (33) being formed deeper than the base layer and reaching the drift layer; a first conductivity type emitter region (36) formed in a surface layer portion of the base layer in the IGBT region in a state of contact with the trench; a contact region (37) of a second conductivity type formed in a surface layer portion of the base layer in the additional FWD region and the connection region and having a higher impurity concentration than the base layer; A semiconductor device, wherein, on one surface of the semiconductor substrate, a formation area of ​​the contact region per unit area in the connection region is smaller than a formation area of ​​the contact region per unit area in the additional FWD region.

2. 2. The semiconductor device according to claim 1, wherein the connection region has a ratio of a width of the inner edge region along one direction to a thickness of the semiconductor substrate of 1.2 or more.

3. 3. The semiconductor device according to claim 1, wherein in the FWD region, an inhibition layer (46) of a second conductivity type or a first conductivity type having a lower impurity concentration than the cathode layer is formed in the cathode layer.

4. 3. The semiconductor device according to claim 1, wherein the FWD region has a width (da) in the one direction in the additional FWD region that is narrower than a width (db) in the one direction in the other FWD region.

5. A connecting region (13a, 13b) is disposed between the FWD region and the IGBT region, the connecting region has the base layer formed on a surface portion of the drift layer and the contact region formed on a surface portion of the base layer, On one surface of the semiconductor substrate, a formation area of ​​the contact region per unit area in the connection region is made smaller than a formation area of ​​the contact region per unit area in the IGBT region; If the connecting region arranged between the additional FWD region and the IGBT region is a first connecting region (13a), and the connecting region arranged between the other FWD region and the IGBT region is a second connecting region (13b), 3. The semiconductor device according to claim 1, wherein the first connection region and the second connection region have a width (dc) along the one direction in the first connection region that is wider than a width (dd) along the one direction in the second connection region.

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