Display control device, computing system, display control method, display method and program

Abstract

To enable representing a coupling of three or more quantum bits when displaying a problem handled by quantum computers in a graph.SOLUTION: A display control device comprises display control means that generates data for displaying variable nodes each indicating a state of at least three quantum bits, a parity node indicating a parity of the at least three quantum bits, and edges connecting between the variable nodes and the parity node.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a display control device, a computing system, a display control method, a display method, and a program.

Background Art

[0002] Problems to be handled by a quantum computer may be represented by a graph. For example, Patent Document 1 describes displaying, in a graph, a problem formulated as an Ising problem, which is a type of quantum computing, for solving a combinatorial optimization problem by quantum annealing. In the method described in Patent Document 1, Ising spins are represented by nodes of a graph, and the states of the Ising spins are represented by the colors of icons representing the nodes. Further, Patent Document 1 describes connecting two connected nodes with a solid edge and representing a connection not used in the annealing of the target problem with a dashed edge.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is preferable that not only the coupling of two qubits but also the coupling of three or more qubits can be represented.

[0005] An example of an object of the present invention is to provide a display control device, a computing system, a display control method, a display method, and a program that can solve the above-described problems.

Means for Solving the Problems

[0006] According to a first aspect of the present invention, a display control device includes display control means for generating data for displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes.

[0007] According to a second aspect of the present invention, an arithmetic system includes arithmetic means for performing arithmetic operations on a target problem, which is a problem to be handled by a quantum computer, and display control means. The display control means generates data for displaying variable nodes respectively indicating the states of a plurality of qubits of the target problem, parity nodes indicating the parity of at least three of the plurality of qubits, and edges connecting the variable nodes indicating the states of the at least three qubits and the parity nodes.

[0008] According to a third aspect of the present invention, a display control method includes a computer generating data for displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes.

[0009] According to a fourth aspect of the present invention, a display method includes a display device displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes.

[0010] According to a fifth aspect of the present invention, a program causes a computer to execute control for displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes.

Advantages of the Invention

[0011] According to the present invention, the coupling of three or more qubits can be represented.

Brief Description of the Drawings

[0012]

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Mode for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0014] <First Embodiment> FIG. 1 is a diagram showing an example of a configuration of an arithmetic system according to at least one embodiment. In the configuration shown in FIG. 1, the arithmetic system 1 includes an arithmetic device 100 and a terminal device 200.

[0015] The arithmetic system 1 performs quantum computing or quantum-like computing. Here, quantum computing refers to solving a problem expressed using quantum bits (Qubits) using a quantum computer. A quantum bit is a variable that can take two states and a superposition state of those two states. A problem expressed using quantum bits is also referred to as a problem to be handled by a quantum computer, or a target problem. Here, pseudo quantum computing is to simulate and calculate the behavior of a quantum computer using a classical computer (Neumann type computer).

[0016] The arithmetic system 1 can be used for quantum annealing or simulated annealing. However, the quantum computing or pseudo quantum computing performed by the arithmetic system 1 is not limited to quantum annealing or simulated annealing. The arithmetic system 1 can also be used for general quantum computing or pseudo quantum computing with state display and coupling.

[0017] The arithmetic device 100 solves the target problem according to the control by the terminal device 200. For example, when the target problem is a combinatorial optimization problem targeted by quantum annealing, the arithmetic device 100 searches for a solution such that the index value indicated by the evaluation function in the optimization problem becomes as good as possible (shows a good evaluation) by quantum annealing or simulated annealing. The target problem here may be expressed by an Ising model. The evaluation function here may be expressed as an Ising Hamiltonian (the Hamiltonian in the Ising model). The arithmetic device 100 may be configured using a quantum computer and perform quantum computing. Alternatively, the arithmetic device 100 may be configured using a classical computer and perform pseudo quantum computing.

[0018] The terminal device 200 controls the operation by the arithmetic device 100. In addition, the terminal device 200 generates and displays information indicating the target problem. The terminal device 200 corresponds to an example of a display control device. Hereinafter, the case where the terminal device 200 generates and displays a graph indicating the target problem will be described as an example.

[0019] The terminal device 200 may be configured using a classical computer. Also, the device that controls the operations by the arithmetic unit 100 and the device that displays the target problem as a graph may be configured as separate devices. The device that controls the operations by the arithmetic unit 100 may be configured as a part of the arithmetic unit 100. Alternatively, the arithmetic unit 100 and the terminal device 200 may be integrally configured.

[0020] FIG. 2 is a diagram showing an example of the configuration of the arithmetic unit 100. FIG. 2 shows an example in the case where the arithmetic unit 100 is configured using a quantum computer. Hereinafter, the case where the arithmetic unit 100 is used for quantum annealing will be described as an example. However, as described above, the arithmetic unit 100 can also be used for quantum computing or pseudo-quantum computing other than quantum annealing. In the configuration shown in FIG. 2, the arithmetic unit 100 includes a plurality of quantum bit devices 110 and a plurality of couplers 120.

[0021] The quantum bit device 110 is a device that represents a quantum bit. As described above for the quantum bit, the quantum bit device 110 can take two states and a superposition state of those two states. The quantum bit device 110 is not limited to a specific type of device. For example, the quantum bit device 110 may be configured using a Josephson Parametric Oscillator (JPO), but is not limited thereto.

[0022] A control parameter value based on the evaluation function in the target problem is set in the quantum bit device 110. For example, a control parameter value corresponding to the coefficient of the one-variable term by the variable indicated by the quantum bit device 110 is set in the quantum bit device 110. The variable indicated by the quantum bit device 110 here is the variable in the evaluation function indicating the quantum bit indicated by the quantum bit device 110.

[0023] The method of setting the control parameter values for the quantum bit device 110 is not limited to a specific method. For example, the control parameter values for the quantum bit device 110 may be set by inputting microwaves with a frequency corresponding to the control parameter values into the quantum bit device 110, but it is not limited to this.

[0024] The coupler 120 controls the interaction between quantum bits. Specifically, a control parameter value indicating the coupling strength (strength of interaction) of the quantum bits is set in the coupler 120. Then, the coupler 120 controls the quantum bit device 110 so that the quantum bit device 110 takes a state corresponding to the set value for the coupler 120 itself. The interaction between quantum bits is also referred to as the coupling of quantum bits. The fact that multiple quantum bits interact is also referred to as those quantum bits being coupled to each other, or those quantum bits being connected.

[0025] The coupling strength of the quantum bits is set based on the evaluation function in the target problem. For example, in the case of a two-body coupling where two quantum bits interact, the coupling strength is set according to the coefficient value of the term of two variables indicating those two quantum bits. When a transformation for implementing the target problem on a quantum computer is performed, the coupling strength of the quantum bits is set based on the evaluation function in the transformed target problem.

[0026] FIG. 3 is a diagram showing an example of the configuration of the terminal device 200. In the configuration shown in FIG. 3, the terminal device 200 includes a communication unit 210, a display unit 220, an operation input unit 230, a storage unit 280, and a processing unit 290. The processing unit 290 includes a problem conversion unit 291, an arithmetic control unit 292, a graph generation unit 293, and a display control unit 294.

[0027] As described above, the terminal device 200 corresponds to an example of a display control device. However, the display unit 220 and the operation input unit 230 are not essential for the display control device. The display unit 220 and the operation input unit 230 may be external components of the terminal device 200.

[0028] The communication unit 210 communicates with other devices. For example, the communication unit 210 transmits the set values of the control parameters for each qubit device 110 and the set values of the control parameters for each coupler 120 to the arithmetic unit 100. Further, the communication unit 210 receives the measured values of the states of each qubit device 110 from the arithmetic unit 100.

[0029] The display unit 220 includes a display screen such as a liquid crystal panel or an LED (Light Emitting Diode) panel, and displays various images. In particular, the display unit 220 displays a graph showing the target problem. The display unit 220 corresponds to an example of a display means. Note that the display unit 220 may be configured as a device installed at a location different from the processing unit 290 and connected via a network. In this case, the display control unit 294 may transmit image data, data serving as a basis for generating an image encoded in a language such as HTML (Hyper Text Markup Language), etc. to the display unit 220 via the network.

[0030] The operation input unit 230 includes input devices such as a keyboard and a mouse, and receives user operations. For example, the operation input unit 230 may be configured to receive user operations for inputting various set values related to quantum computing, such as the number of repetitions of solution search in quantum annealing. Note that the operation input unit 230 may be configured as a device installed at a location different from the processing unit 290 and connected via a network.

[0031] The storage unit 280 stores various data. The storage unit 280 is configured using a storage device included in the terminal device 200. For example, the storage unit 280 stores a graph showing the target problem. The processing unit 290 controls each part of the terminal device 200 to perform various processes. The functions of the processing unit 290 may be executed by a CPU (Central Processing Unit) included in the terminal layer 200 reading a program from the storage unit 280 and executing it.

[0032] The problem conversion unit 291 converts a target problem into a problem in a form that can be implemented in the arithmetic unit 100. The target problem before conversion is also referred to as a logical problem. The quantum bits used in the logical problem are also referred to as logical bits. The target problem after conversion is also referred to as a physical problem. The quantum bits used in the physical problem are also referred to as physical bits.

[0033] FIG. 4 is a diagram showing an example of a logical problem that the problem conversion unit 291 converts into a physical problem. In the example of FIG. 4, the logical problem is shown as a graph including nodes numbered from 1 to 6 and edges connecting two nodes. Each node represents a logical bit. Each edge represents a two-body coupling of logical bits. Here, the coupling of N quantum bits is referred to as an N-body coupling. Here, N is an integer where N ≧ 2.

[0034] FIG. 4 shows an example where the logical bits are fully connected by two-body couplings. The edge numbered ij represents the two-body coupling between the logical bit represented by the node numbered i and the logical bit represented by the node numbered j. Here, i is an integer where 1 ≦ i < 6, and j is an integer where i < j ≦ 6.

[0035] Problems represented by full connections, as in the example of Fig. 4, are being transformed into problems represented by sparse connections for implementation on a quantum computer. In particular, when the number of qubits is large, in the case of full connections, the total number of connections increases on the order of the square of the number of qubits N, making it difficult to directly implement on hardware. The number of connections here refers to the number of qubits that interact with each other. Therefore, the process of transforming problems represented by full connections into problems represented by sparse connections for implementation on a quantum computer is being carried out. Transforming problems represented by full connections into problems represented by sparse connections for implementation on a quantum computer is also referred to as embedding logical bits of full connections into physical bits of sparse connections.

[0036] Fig. 5 is a diagram showing an example of a physical problem obtained by the problem transformation unit 291 from a logical problem. Fig. 5 shows an example of a sparse connection model based on the LHZ model, which is a transformation of the full connection model in the example of Fig. 4. In the example of Fig. 5, the white circles (○) numbered with two digits such as "12", "13", ··· represent physical bits. The white circles without two-digit numbers represent physical bits that take constant values. Note that in the example of Fig. 5, the values of the physical bits are shown as "+1" or "-1", but the values of the qubits handled by the operation system 1 are not limited to this. For example, the two states of the qubits in the target problem may be represented by "0" and "1".

[0037] In the example of Fig. 5, the product of two logical bits in the example of Fig. 4 is represented by one physical bit. For example, the physical bit numbered 12 in the example of Fig. 5 represents the product of the logical bit numbered 1 and the logical bit numbered 2 in the example of Fig. 4. In the implementation of the physical problem in the example of Fig. 5 on the arithmetic device 100, the physical bits are represented by the qubit device 110.

[0038] Also, in the example of FIG. 5, the black circles (●) with four-digit numbers such as "1234", "1245",... and the black circles with three-digit numbers such as "123", "234",... all indicate four-body couplings. In these four-body couplings, the physical bits are controlled so that the parity of the values of the four physical bits becomes even parity (even parity). Here, it is assumed that parity is a concept representing whether it is even or odd.

[0039] When the value of a physical bit is represented by "+1" or "-1", as parity, the product of the values of the coupled physical bits is calculated. In this case, the fact that it is even parity corresponds to the value of the product of the values of the physical bits being "+1". Also, in this specification, the parity of the values of multiple bits may be simply referred to as "bit parity". The bits referred to here include logical bits, physical bits, and quantum bits.

[0040] Even when the value of each bit is not determined and is in a superposition state, the parity may be determined. The description of "bit parity" includes such cases. As an example, as will be described later, there are eight combinations in which four bits have odd parity, and cases where the values of the four bits are in a superposition state of those eight patterns can be cited.

[0041] When the value of a physical bit is represented by "+1" or "-1", "+1" of a physical bit indicates that the two logical bits represented by that physical bit are in the same direction. "-1" of a physical bit indicates that the two logical bits represented by that physical bit are in opposite directions. If there are an odd number of physical bits with a value of "-1" among the four physical bits that are four-body coupled, it becomes impossible to re-map the physical bits to logical bits.

[0042] For example, consider a case where among four physical bits numbered 13, 14, 23, and 24, the values of the three physical bits numbered 13, 14, and 23 are “+1”, and the value of the physical bit numbered 24 is “-1”. In this case, from the values “+1” of the physical bits numbered 13, 14, and 23, the four logical bits numbered 1, 2, 3, and 4 are in the same direction. On the other hand, from the value “-1” of the physical bit numbered 24, the logical bit numbered 2 and the logical bit numbered 4 are in opposite directions, which contradicts the fact that these physical bits are in the same direction.

[0043] As described above, when the parity in a four-body coupling is odd parity, a contradiction occurs in the values of the logical bits, and the physical bits cannot be rewritten as logical bits. Therefore, by controlling the physical bits so that the parity in the four-body coupling becomes even parity, it is possible to obtain the values of the physical bits that can specify the values of the logical bits.

[0044] In the example of FIG. 5, the physical bits not numbered in the upper left (the four physical bits in the bottom row) indicate fixed bits whose values are fixed to +1. Also, a four-body coupling with three-digit numbers can be regarded as a three-body coupling with even parity (even parity). In the example of FIG. 5, only a four-body coupler is used as the coupler, and by providing fixed bits whose values are fixed to +1, the constraint of even parity of the three-body coupling is realized. In the implementation of the physical problem arithmetic device 100 in the example of FIG. 5, the arithmetic device 100 includes a four-body coupler as the coupler 120, and the function of the four-body coupling is executed by the coupler 120.

[0045] As in the example of FIG. 5, many-body couplings may appear in physical problems. The many-body coupling here refers to a coupling of three or more bodies (that is, a coupling of three or more quantum bits). Also, many-body couplings may appear in logical problems. For example, consider a logical problem of quantum annealing in which the Hamiltonian H is expressed as in Equation (1).

[0046]

Number

[0047] x i indicates a logical bit. N is an integer where N ≥ 4, indicating the number of logical bits x i of. a i,j,k,l is the coefficient of the four-variable term "a i,j,k,l x i x j x k x l ". a i,j,k is the coefficient of the three-variable term "a i,j,k x i x j x k ". a i,j is the coefficient of the two-variable term "a i,j,k x i x j ". a i is the coefficient of the one-variable term "a i x i ". A is a constant term.

[0048] The four-variable product "x i,j,k,l x i x j x k x l " in the four-variable term "a i x j x k x l " is represented by a four-body combination. The three-variable product "x i,j,k x i x j x k " in the three-variable term "a i x j x k " is represented by a three-body combination. The two-variable product "x i,j x i x j " in the two-variable term "a i x j" is represented by a two-body bond. As described above, the parity of multiple variables corresponds to the product of the variables. According to the arithmetic system 1, even in a problem containing terms of products of three or more variables (a problem including multi-body bonds), it can be represented using parity.

[0049] The arithmetic control unit 292 controls the arithmetic operations performed by the arithmetic unit 100. For example, the arithmetic control unit 292 transmits the control parameter values for each quantum bit device 110 and the control parameter values for each coupler 120 to the arithmetic unit 100 via the communication unit 210.

[0050] The graph generation unit 293 generates a graph indicating the target problem. The graph generation unit 293 may output both a graph indicating a logical problem and a graph indicating a physical problem. Alternatively, the graph generation unit 293 may generate only a graph indicating either a logical problem or a physical problem.

[0051] The display control unit 294 controls the display unit 220 to display various images. In particular, the display control unit 294 causes the graph generated by the graph generation unit 293 to be displayed on the display unit 220. Specifically, the display control unit 294 generates data for displaying the graph. Then, the display control unit 294 outputs the generated data to the display unit 220, thereby controlling the display unit 220 to display the graph. The data for displaying the graph may be image data or data serving as a basis for generating an image symbolized in a language such as HTML. The display control unit 294 corresponds to an example of display control means.

[0052] FIG. 6 is a diagram showing an example of a display screen of a graph by the display unit 220. The display screen shown in FIG. 6 includes regions A11, A12, and A13. Region A11 is a display region for the graph. Region A12 is a display region for the legend of the input values. Region A13 is a display region for the legend of the output values.

[0053] The graph in region A11 includes variable nodes, parity nodes, and edges. A variable node is a node that represents a qubit. A parity node is a node that represents the parity of qubits that are connected to each other. An edge connects each variable node that represents qubits connected to each other and a parity node that represents the parity of those qubits. The variable nodes are represented by symbols with an upper triangle (△) or a lower triangle (▽) surrounded by a white circle (○). The parity nodes are represented by an upper triangle (△) or a lower triangle (▽). The edges are represented by straight lines.

[0054] Also, in the graph of FIG. 6, the input / output values of each node are shown. The input value to a variable node is the setting value for that variable node. For example, the input value to a variable node may be the setting value of a control parameter for qubit device 110. Alternatively, the input value to a variable node may be an evaluation function in quantum computing and the value of the coefficient of a one-variable term of the variable represented by the variable node. For example, in the above formula (1), the variable x i The input value to the variable node representing may be the value of the coefficient a i of.

[0055] The input value to a parity node is the setting value for that parity node. For example, the input value to a parity node may be the setting value of a control parameter for coupler 120. Alternatively, the input value to a parity node may be an evaluation function in quantum computing and the value of the coefficient of a product term of variables representing qubits that are connected to each other. For example, in the above formula (1), if the variables x i , x j , x k represent qubits that are connected to each other, the input value to the parity node indicating the parity of the variables x i , x j , x k is the coefficient a i of the product x j x k of these variables, i,j,k x i xj x k The coefficient a of i,j,k may also be the value of. The input value to the variable node and the input value to the parity node are both shown according to the legend shown in region A12.

[0056] The output value of the variable node is the value of the qubit indicated by that variable node. The output value of the variable node of the graph indicating the physical problem is the observed value of the physical bit indicated by that variable node. The output value of the variable node of the graph indicating the logical problem is the value of the logical bit calculated from the output value of the node of the graph indicating the physical problem by the conversion from the physical problem to the logical problem.

[0057] The output value of the parity node is the value of the parity indicated by that parity node. For example, in the graph of FIG. 6, the value of the parity node labeled "1-3-4-5" is the parity value of the variable node labeled "Bit1", the variable node labeled "Bit3", the variable node labeled "Bit4", and the variable node labeled "Bit5". The numbers shown for each variable node, such as "Bit1", "Bit2",... are also referred to as bit numbers. The bit number can be used as an identification number for identifying the variable node.

[0058] The parity takes either an odd parity or an even parity value. When the variable node takes a value of 0 or 1, the case where the number of variable nodes taking a value of 1 is odd corresponds to odd parity and is indicated by an output value of 1. Also, the case where the number of variable nodes taking a value of 1 is even corresponds to even parity and is indicated by an output value of 0. When the variable node takes a value of +1 or -1, the case where the number of variable nodes taking a value of -1 is odd corresponds to odd parity and is indicated by an output value of -1. Also, the case where the number of variable nodes taking a value of -1 is even corresponds to even parity and is indicated by an output value of +1.

[0059] The graph generation unit 293 may generate a graph that represents both the set value for the variable node and the set value for the parity node in terms of color or shading, or a combination thereof. For example, the graph generation unit 293 may generate a graph that indicates positive values of these set values in red, negative values in blue, and uses darker colors for larger magnitudes (absolute values) of the set values. However, the method of representing the set value (input value to the node) for the nodes in the graph generated by the graph generation unit 293 is not limited to a specific method.

[0060] Also, in the example of FIG. 6, both the output value of the variable node and the output value of the parity node are shown according to the legend shown in region A13. In the example of FIG. 6, the output value of the variable node takes either a value of +1 or -1. The output value of the parity node also takes either a value of +1 (even parity) or -1 (odd parity). +1 is shown by an upper triangle (△), and -1 is shown by a lower triangle (▽).

[0061] However, the method of representing the value of the node (output value of the node) in the graph generated by the graph generation unit 293 is not limited to a specific method. For example, the graph generation unit 293 may generate a graph that indicates the value of the variable node by the orientation of a triangle and the value of the parity node by the orientation of a pentagon, etc., showing the values of the variable node and the parity node in different graphical orientations. Also, the graph generation unit 293 may generate a graph that indicates different types of couplings with different shapes, such as indicating a two-body coupling with a triangle and a three-body coupling with a pentagon.

[0062] The graph generation unit 293 may determine the values of each node based on the solutions with the top occurrence counts among the multiple solutions obtained by repeatedly performing the calculation of solutions by quantum computing in the arithmetic unit 100, and show them in the graph. Alternatively, the graph generation unit 293 may determine the values of each node based on the value distribution for each node in the entire set of multiple solutions obtained by repeatedly performing the calculation of solutions by quantum computing in the arithmetic unit 100, and show them in the graph.

[0063] Here, in order to evaluate the operation of the quantum computer, it is necessary to examine the correspondence between the input values and the output values to the quantum computer. On the other hand, it is considered not easy to examine the correspondence between the input values and the output values due to, for example, the conversion from a logical problem to a physical problem. In particular, for a target problem with a large number of qubits, it is considered difficult to examine the correspondence between the input values and the output values. On the other hand, it is expected that by the display unit 220 displaying a graph as illustrated in FIG. 6, it will be helpful for the user (the person who sees the graph) to grasp the correspondence between the input values and the output values.

[0064] For example, when the target problem is a quantum annealing problem and the values of the qubits are represented by +1 or -1, for the variable nodes and parity nodes, if there are many red downward triangle nodes where the input value is positive and the output value is -1, or blue upward triangle nodes where the input value is negative and the output value is 1, it can be evaluated that the value of the Hamiltonian is small and the behavior is correct. In this way, by the display unit 220 displaying a graph as illustrated in FIG. 6, the user (the person who sees the graph) can visually grasp the relationship between the input and output values. For example, it is expected that grasping the relationship between such input and output values is useful during the calibration of the arithmetic system 1 and when checking the arithmetic result by the arithmetic unit 100.

[0065] Also, when the physical bit has redundancy in the correspondence between the logical bit and the physical bit, it is conceivable that the physical bit may take a value that cannot be converted into the value of the logical bit, even if it is a combination of values that the physical bit can take. Thus, when a contradiction occurs when converting the value of the physical bit into the value of the logical bit, it is conceivable to review the physical problem. For example, it is conceivable to check the presence or absence of an unintended coupling (whether a coupling not provided in the design of the target problem is provided in the physical problem).

[0066] On the other hand, it is expected that by the display unit 220 displaying a graph as illustrated in FIG. 6, it will be helpful for reviewing the physical problem. For example, it is expected that by the display unit 220 displaying a graph as illustrated in FIG. 6, it will be helpful for discovering a coupler 120 in which the set value of the coupling (the set value of the parity node) conflicts with the state of the quantum bits coupled to each other, and for discovering an unintended coupling.

[0067] The display unit 220 may display the parity of a set of quantum bits for which no coupling is set in the problem. For example, in the example of FIG. 6, the display unit 220 may display the parity between the value of the variable node with "Bit2" attached and the value of the variable node with "Bit4" attached. The display unit 220 may automatically display the parity of a set of quantum bits for which no coupling is set in the problem, or may display it according to a user's instruction.

[0068] Also, when three or more quantum bit devices 110 are connected to the coupler 120 detected as the conflicting coupler 120, it is expected that a graph as illustrated in FIG. 6 will be helpful for reviewing the input to those quantum bit devices 110, or for reviewing the coupling relationship of those quantum bit devices 110.

[0069] For example, in the graph of FIG. 6, the input to the parity node labeled "1-3-4-5" has odd parity. In contrast, the values of the four variable nodes labeled "Bit1", "Bit3", "Bit4", and "Bit5" that are connected to this parity node are two +1s and two -1s, and the parity output of this parity node is even parity. Therefore, there is a contradiction between the input and the output in the parity node labeled "1-3-4-5".

[0070] As one measure to resolve this contradiction, a measure can be taken to re-consider the input values of the four variable nodes labeled "Bit1", "Bit3", "Bit4", and "Bit5". It suffices to consider measures such that there is one +1 and three -1s, or three +1s and one -1 as the values of these four variable bits.

[0071] Here, the number of cases where the combinations of the values of these four variable bits are such that there is one +1 and three -1s, or three +1s and one -1 is 4 C 3 + 4 C 1 = 8, which is relatively large. Thus, in the case of parity constraint conditions of 3 bits or more, the number of solutions that satisfy the constraint conditions becomes significantly larger compared to the case of the constraint conditions of 2-bit connection relationships, and there are more options in the redesign of physical problems. In contrast, it is expected that by preferably displaying the input and output of the bit group of interest in the physical problem in a graph format that allows the user (the viewer of the display) to visually list multiple options and can be switched as needed, it will be easier for the user to perform an appropriate redesign. Hereinafter, the variable nodes labeled "Bit1", "Bit2", "Bit3", "Bit4", and "Bit5" will also be simply referred to as Bit1, Bit2, Bit3, Bit4, and Bit5, respectively.

[0072] As an example of a method for switchably displaying a plurality of options, for example, when the user designates and clicks on a parity node of interest with the mouse pointer, +1 or -1 is displayed on each of the variable bits directly connected to the parity node in a combination that satisfies the constraint condition, or a mark of an upper triangle (△) or a lower triangle (▽) is displayed, and the combination is switched each time it is clicked, and when it is clicked the number of times equal to the number of solutions, all the solutions are comprehensively displayed.

[0073] Also, as another example of a method for switchably displaying a plurality of options, a small window in which all solutions are summarized in a simple table format is displayed, and when the user designates and clicks on a solution with the mouse pointer in the small window, +1 or -1 corresponding thereto is displayed on each of the variable bits directly connected to the parity node.

[0074] In this way, even if the number of redesign options increases, the display unit 220 can display candidates for solutions that satisfy the parity constraint condition one by one on the variable bits directly connected to the parity node that the user is focusing on. Even if the number of redesign options increases, the user can view candidates for solutions that satisfy the parity constraint condition one by one, and at the same time, can also view the situation of other constraints further imposed on the graph structure. As a result, the user can sequentially compare and consider these solution candidates while switching the display of the solution candidates that satisfy the parity constraint condition.

[0075] For example, consider a case where the user compares and considers a plan to correct the value of Bit3 and a plan to correct the value of Bit4 among the candidates for the parity node labeled "1-3-4-5" in the example of FIG. 6 to become odd parity. In the plan to correct the value of Bit3, assume that the values of Bit1, Bit3, Bit4, and Bit5 are +1, +1, +1, and -1, respectively. In the plan to correct the value of Bit4, assume that the values of Bit1, Bit3, Bit4, and Bit5 are +1, -1, -1, and -1, respectively.

[0076] In the proposal to modify the value of Bit3, the two relationships between the input and output of parity marked with "2-3" (even parity) and the input and output of parity marked with "3-4" (even parity) are also improved. On the other hand, in the proposal to modify the value of Bit4, the relationship between the input and output of parity marked with "3-4" (even parity) is improved, but the relationship between the input and output of parity marked with "4-5" deteriorates. That is, it is conceivable that the input to the parity marked with "4-5" is negative (odd parity), while the output is +1 (even parity).

[0077] Therefore, the user can determine that the proposal to modify the value of Bit3 is a better proposal by referring to the display by the display unit 220. In this case, the user can take improvement measures to strongly change the input of Bit3 in a more positive direction. The user can easily perform such a comparative study by referring to the switchable screen display.

[0078] The memory unit 280 may store in advance the combinations of the values of the variable nodes that are candidates for solutions corresponding to parity. For example, the memory unit 280 may store the combinations of the values of the variable nodes in the form of table-form data. Then, the display control unit 294 may refer to the data stored in the memory unit 280 and cause the display unit 220 to switch and display the solution candidates.

[0079] For example, the memory unit 280 may name and store the eight combination patterns of (+1, +1, +1, -1), (+1, +1, -1, +1), ···, (-1, -1, -1, +1), (-1, -1, +1, -1) ···, which are the combinations that satisfy the 4-bit odd parity, as Pattern 1, Pattern 2, ···, Pattern 8.

[0080] Then, according to the control by the display control unit 294, the display unit 220 may display by sequentially assigning, in ascending order of bit numbers (the smaller ones), to the variable nodes connected to the parity node that the user is focusing on, in order from the left of pattern 1 (i.e., in order from the beginning of the combinations in the pattern).

[0081] Then, according to the control by the display control unit 294, the display unit 220 may use the mouse click as a trigger to sequentially switch the patterns to pattern 2, pattern 3, ··· and perform the display in the same manner as in the case of pattern 1 described above. After reaching pattern 8, in the next click, the display unit 220 may return to pattern 1 and perform the display according to the control by the display control unit 294.

[0082] Alternatively, according to the control by the display control unit 294, the display unit 220 may display the above eight patterns as a list on the screen and display the pattern selected by the user. For example, when the user designates pattern 2 with the mouse pointer, the display unit 220 may display by sequentially assigning, in ascending order of bit numbers, in order from the left of (+1, +1, -1, +1) in the same manner as described above according to the control by the display control unit 294.

[0083] Also, as will be described later, when the display form of the variable node is set to simultaneously represent the physical bits and the logical bits related to them, it is conceivable that the number of related bits will further increase, and in that case, there will be more options in the redesign of the physical problem. In contrast, by the operation system 1 displaying the graph of the physical problem and the graph of the logical problem, the user (the viewer of the display) can visually overview the overall input / output including the logical bits and consider the redesign of the physical problem, so it is expected that an appropriate redesign can be easily performed, and the merit of this embodiment is great.

[0084] Also, regarding the connection indicated by the parity node labeled "3-4" in the graph of FIG. 6, consider the case where, despite making a connection such that the value of the variable node labeled "Bit3" and the value of the variable node labeled "Bit4" are the same, the value of the variable node labeled "Bit3" and the value of the variable node labeled "Bit4" are different (values with opposite signs). In this case, it is conceivable that the connection indicated by the parity node labeled "3-4" is inappropriate. Thus, the user may edit the physical problem to exclude the connection indicated by the parity node labeled "3-4".

[0085] The graph generation unit 293 may generate a graph of the target problem before the execution of quantum computing by the arithmetic unit 100. In that case, the graph generation unit 293 may generate a graph showing only the input value to the node among the input value to the node and the output value of the node.

[0086] FIG. 7 is a diagram showing another example of the graph display screen by the display unit 220. FIG. 7 shows a display example of a graph showing only the input value to the node among the input value to the node and the output value of the node. The display screen shown in FIG. 7 includes regions A21 and A22. Region A21 is the display region of the graph. Region A22 is the display region of the legend of the input value. On the other hand, in the display screen shown in FIG. 7, the legend of the output value is not displayed.

[0087] In the graph of region A11 in FIG. 6, each node is shown using an upper triangle (△) or a lower triangle (▽), whereas in the graph of region A21 in FIG. 7, each node is shown using a circle (〇). For this reason, in the graph of region A21 in FIG. 7, the output value of the node is not displayed. Otherwise, the graph of region A21 in FIG. 7 is the same as the graph of region A11 in FIG. 6.

[0088] The graph generation unit 293 may generate a graph showing the correspondence between logical bits and physical bits. FIG. 8 is a diagram showing an example of the distinction in the representation method of logical bits. In the example of FIG. 8, three logical bits, namely, the logical bit numbered 1, the logical bit numbered 2, and the logical bit numbered 3, are shown. It is assumed that these three logical bits are represented in different representation methods in the graph of the logical problem. For example, the graph generation unit 293 may generate a graph in which the variable nodes of these three logical bits are shown in different colors.

[0089] FIG. 9 is a diagram showing an example of the representation method of physical bits associated with a plurality of logical bits. In the example of FIG. 9, the physical bit numbered 123 is the physical bit associated with the three logical bits shown in FIG. 8. This physical bit is represented using a combination of the representation methods of the three logical bits shown in FIG. 8. For example, in the example of FIG. 9, the physical bit numbered 123 may be represented using each of the colors used in the representation of the three logical bits shown in FIG. 8.

[0090] The association from a plurality of logical bits to one physical bit may occur when the problem conversion unit 291 converts a logical problem into a physical problem. For example, as described above, in the example of FIG. 5, the physical bit numbered 12 represents the product of the logical bit numbered 1 and the logical bit numbered 2 in the example of FIG. 4.

[0091] FIG. 10 is a diagram showing a first specific example of the representation method of physical bits associated with a plurality of logical bits. FIG. 10 shows a first specific example of the representation method of the physical bits shown in FIG. 9. In FIG. 10, the correspondence between the logical bits and the physical bits is shown by the representation method of the physical bits in the example of FIG. 9. Further, in FIG. 10, inside the circle (〇) indicating the physical bit, an upper triangle (△) is shown in the same manner as the representation method of the variable node in the example of FIG. 6. The output value of this physical bit is indicated by the upper triangle. Also, the input value to this physical bit is indicated by the representation method of the upper triangle. According to the method of representing physical bits illustrated in FIG. 10, the correspondence between logical bits and physical bits, the input value to the physical bits, and the output value of the physical bits can be visually shown.

[0092] FIG. 11 is a diagram showing a second specific example of the method of representing physical bits associated with a plurality of logical bits. FIG. 11 shows a second specific example of the method of representing physical bits shown in FIG. 9.

[0093] In FIG. 11, according to the method of representing physical bits in the example of FIG. 9, the correspondence between logical bits and physical bits is shown. Further, in FIG. 11, another circle (〇) is shown inside the circle (〇) indicating the physical bits in the example of FIG. 9, and an upper triangle (△) is shown inside that circle, similar to the method of representing variable nodes in the example of FIG. 6. The area between the inner circle and the upper triangle is painted white.

[0094] In the example of FIG. 11, a white-painted area is provided between the symbol indicating the correspondence between quantum bits and physical bits and the symbols indicating the input and output values of the physical bits, that is, the area where no special representation method is applied. Thereby, the correspondence between logical bits and physical bits, the input value to the physical bits, and the output value of the physical bits can be visually shown, and it is expected that the user (the person who sees the display illustrated in FIG. 11) can easily recognize the correspondence between logical bits and physical bits, the input value to the physical bits, and the output value of the physical bits.

[0095] FIG. 12 is a diagram showing a third specific example of the method of representing physical bits associated with a plurality of logical bits. FIG. 12 shows a third specific example of the method of representing physical bits shown in FIG. 9.

[0096] In FIG. 12, similar to the method of representing variable nodes in the example of FIG. 6, the variable node is shown as a symbol in which an upper triangle (△) is surrounded by a white circle (〇). Further, in FIG. 12, a symbol combining three squares (□) in which the method of representing three logical bits in the example of FIG. 8 is respectively applied is shown.

[0097] In the example of FIG. 12, symbols indicating the correspondence between logical bits and physical bits are provided separately from the symbols indicating the input and output values of the physical bits. As a result, the correspondence between logical bits and physical bits, the input value to the physical bits, and the output value of the physical bits can be visually shown, and it is expected that the user (the person who sees the display illustrated in FIG. 12) can easily recognize the correspondence between logical bits and physical bits, the input value to the physical bits, and the output value of the physical bits.

[0098] By the display unit 220 performing the display of a graph as illustrated in FIG. 6 or FIG. 7 and the display of the correspondence between logical bits and physical bits as illustrated in FIGS. 8 to 12, it is expected that the user can efficiently perform the performance evaluation of quantum bits and couplings. As a result, it is expected that the user can consider the conversion method from logical bits to physical bits and the formulation of the evaluation function, and improve the accuracy of solving in quantum computing.

[0099] The evaluation of the solution of a physical problem and the correction of the physical problem using the arithmetic system 1 are performed, for example, by the following procedure. (1) When the terminal device 200 receives the specification of the association between logical bits and physical bits, the graph generation unit 293 generates a display of the correspondence between logical bits and physical bits as illustrated in FIGS. 8 to 12. The display unit 220 displays the correspondence between logical bits and physical bits.

[0100] The specification of the association between logical bits and physical bits may be, for example, as in the examples of FIGS. 4 and 5, where the product of two logical bits is taken as one physical bit. The user may be allowed to specify the association between logical bits and physical bits. Alternatively, the data acquired by the terminal device 200 from another device may indicate the specification of the association between logical bits and physical bits.

[0101] (2) When the terminal device 200 receives the input of the set value for each node of the graph of the logical problem, the problem conversion unit 291 calculates the values of each node of the graph of the physical problem to generate a physical problem. The graph generation unit 293 generates the graph of the physical problem generated by the problem conversion unit 291. The display unit 220 displays the graph of the physical problem generated by the graph generation unit 293.

[0102] In this case, before the execution of quantum computing, the display unit 220 displays a graph showing only the input values to the nodes among the input values to the nodes and the output values of the nodes as illustrated in FIG. 7. The user may input the set value for each node of the graph of the logical problem. Alternatively, the set value for each node of the graph of the logical problem may be indicated in the data acquired by the terminal device 200 from another device.

[0103] (3) The arithmetic device 100 repeatedly executes the calculation of the physical problem. The graph generation unit 293 determines the values of each node of the graph of the physical problem based on the solutions with the top occurrence counts among the obtained multiple solutions, and generates the graph of the physical problem. The display unit 220 displays the graph of the physical problem generated by the graph generation unit 293.

[0104] For example, the graph generation unit 293 may generate the graph of the physical problem based on the solution with the highest occurrence count among the obtained multiple solutions. Alternatively, the graph generation unit 293 may generate the graph of the physical problem for each of a predetermined number of solutions with the top occurrence counts among the obtained multiple solutions.

[0105] Alternatively, the graph generation unit 293 may determine the value of each node based on the distribution of the values for each node in the entire obtained solutions and show it in the graph. Furthermore, the graph generation unit 293 may show, for each node, the probability that the value indicated by that node was obtained. For example, if there are 60,000 solutions where the value of a certain variable node is +1 and 40,000 solutions where the value is -1, the graph generation unit 293 may generate a graph that shows the value +1 as an upper triangle for the value of that variable node, and further shows the probability of 60%.

[0106] Also, the problem conversion unit 291 calculates the value of each node in the graph of the logical problem based on the value of each node in the graph of the physical problem. A graph of the logical problem showing the value of each node calculated by the problem conversion unit 291 is generated. The display unit 220 displays the graph of the logical problem generated by the graph generation unit 293.

[0107] (4) The user (the person who views the graph) checks the operation of the coupler 120 in the physical problem with reference to the graph of the logical problem and the graph of the physical problem. Also, the user determines the presence or absence of inappropriate connections or inappropriate physical bits in the physical problem, and if it is determined that there are inappropriate connections or inappropriate physical bits, detects that connection or physical bit.

[0108] The user may detect an unintended connection as an inappropriate connection. Also, when a connection provided as a constraint is not as intended, the user may detect that connection as an inappropriate connection. Also, the user may detect a qubit for which the control of the qubit, such as a local field for the qubit, and the effect of that control are reversed, as an inappropriate qubit.

[0109] When the user detects an inappropriate connection or an inappropriate physical bit, the physical problem may be edited so as to exclude that connection or physical bit. For example, the user may edit the physical problem by editing the graph of the physical problem displayed by the display unit 220 with an operation input from the operation input unit 230.

[0110] The graph generation unit 293 may generate a graph that displays a warning for a variable node or a parity node where the input value and the output value do not match. By the display unit 220 displaying the graph, it is possible to assist the user in editing physical problems. For example, the graph generation unit 293 may be configured to detect, as a variable node or a parity node where the input value and the output value do not match, a variable node or a parity node that shows input values and output values such that the value of the Hamiltonian becomes large.

[0111] FIG. 13 is a diagram showing an example of the procedure of the process performed by the terminal device 200. In the process of FIG. 13, the terminal device 200 acquires a logical problem (step S101). For example, the communication unit 210 may receive a logical problem from another device. Alternatively, the operation input unit 230 may receive a user operation for inputting a logical problem.

[0112] Next, the problem conversion unit 291 generates a physical problem for implementing the logical problem obtained in step S101 on a quantum computer (step S102). The generation of the physical problem by the problem conversion unit 291 can be regarded as the conversion from the logical problem to the physical problem.

[0113] Next, the display unit 220 displays a graph showing the target problem (step S103). Specifically, the graph generation unit 293 generates a graph showing only the input value among the input value to the node and the output value of the node, such as the graph illustrated in FIG. 7. Then, the display control unit 294 controls the display unit 220 to display the graph generated by the graph generation unit 293. The display unit 220 may be configured to display both a graph showing the logical problem and a graph showing the physical problem. Alternatively, the display unit 220 may be configured to display only one of the graph showing the logical problem and the graph showing the physical problem.

[0114] Next, the operation control unit 292 causes the arithmetic device 100 to execute the physical problem generated by the problem conversion unit 291 (step S104).

[0115] Next, the display unit 220 displays a graph showing the target problem and the execution result of quantum computing (step S105). For example, the graph generation unit 293 generates a graph showing the output value of each node by replacing the figure without direction distinction with a figure with direction distinction for each node of the graph generated in step S103.

[0116] In the case of the examples in FIGS. 6 and 7, the graph generation unit 293 generates a graph showing the output value of each node illustrated in FIG. 6 by replacing the circle (〇) with the input value representation method in the graph of FIG. 7 with an upper triangle (△) or a lower triangle (▽). Then, the display control unit 294 controls the display unit 220 to display the graph generated by the graph generation unit 293. The display unit 220 may display both the graph showing the logical problem and the graph showing the physical problem. Alternatively, the display unit 220 may display only one of the graph showing the logical problem and the graph showing the physical problem. After step S105, the terminal device 200 ends the process of FIG. 13.

[0117] As described above, the display control unit 294 generates data for displaying at least variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of those at least three qubits, and edges connecting the variable nodes and the parity nodes.

[0118] According to the terminal device 200, it is also possible to represent the coupling of three or more qubits. In particular, according to the terminal device 200, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and the edges associating the qubits with the parity.

[0119] In addition, the display control unit 294 generates data for displaying variable nodes that respectively indicate the states of a plurality of qubits of a target problem, which is a problem to be handled by the quantum computer. The at least three qubits described above are included in the plurality of qubits described above.

[0120] According to the terminal device 200, when displaying a problem to be handled by the quantum computer, it is possible to represent the coupling of three or more qubits. In particular, according to the terminal device 200, when displaying a problem to be handled by the quantum computer, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge that associates the qubits with the parity.

[0121] In addition, the display control unit 294 generates data for displaying a graph that represents both the set value for the variable node and the set value for the parity node in the target problem, either in color or shading, or a combination thereof, and represents both the value of the qubit indicated by the variable node and the parity indicated by the parity node in the orientation of the icon indicating the node.

[0122] According to the terminal device 200, both the set value for each node (the input value to each node) and the value of each node (the output value of each node) can be displayed on the graph. The user (the person who sees this graph) can relatively easily confirm whether the input-output relationship of each node is appropriate.

[0123] In addition, the display control unit 294 generates data for displaying a graph of a physical problem, which is the target problem converted so as to be implementable on the quantum computer. According to the terminal device 200, the user (the person who sees this graph) can relatively easily confirm whether the relationship between the implementation of the target problem on the quantum computer and the obtained solution is appropriate. In particular, the user can visually grasp not only the coupling of two qubits in the implementation of the target problem on the quantum computer but also the coupling of three or more qubits, and confirm whether the relationship between the implementation of the target problem on the quantum computer and the obtained solution is appropriate.

[0124] In addition, the display control unit 294 generates data for displaying a graph of a logical problem, which is the target problem before being converted so as to be implementable on a quantum computer. According to the terminal device 200, a user (a person who views this graph) can relatively easily confirm whether the relationship between the set logical problem and the obtained solution is appropriate. In particular, the user can visually grasp not only the coupling of two qubits in the logical problem but also the coupling of three or more qubits, and confirm whether the relationship between the logical problem and the obtained solution is appropriate.

[0125] In addition, the display control unit 294 generates data for displaying a graph of a physical problem, which shows the correspondence between a physical qubit, which is a qubit used in the physical problem, and a logical qubit, which is a qubit used in the logical problem that is the target problem before being converted into the physical problem, in a representation method in which the representation methods assigned to the logical qubits are combined.

[0126] According to the terminal device 200, a user (a person who views this graph) can relatively easily grasp the correspondence between the logical qubit and the physical qubit. For example, when the user reconsiders the implementation of the target problem on a quantum computer, the user can refer to the correspondence between the logical qubit and the physical qubit shown in the graph.

[0127] In addition, the display control unit 294 generates data for switchably displaying a plurality of combinations of qubit values corresponding to one value of a parity node, each associated with a respective variable node. According to the terminal device 200, a user (a person who views the display) can visually compare and consider a plurality of combinations of qubit values corresponding to the value of the parity node in order. In this regard, it is expected that the user can relatively easily obtain an appropriate combination of qubit values corresponding to the value of the parity node.

[0128] <Second Embodiment> FIG. 14 is a diagram showing an example of the configuration of a display control device according to at least one embodiment. In the configuration shown in FIG. 14, the display control device 610 includes a display control unit 611.

[0129] With such a configuration, the display control unit 611 generates data for displaying a variable node indicating the state of at least three qubits, a parity node indicating the parity of at least three of those qubits, and an edge connecting the variable node and the parity node. The display control unit 611 corresponds to an example of display control means.

[0130] According to the display control device 610, the coupling of three or more qubits can also be represented. In particular, according to the display control device 610, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge associating the qubits with the parity.

[0131] <Third Embodiment> FIG. 15 is a diagram showing an example of the configuration of an arithmetic system according to at least one embodiment. In the configuration shown in FIG. 15, the arithmetic system 620 includes an arithmetic unit 621 and a display control unit 622.

[0132] With such a configuration, the arithmetic unit 621 performs an operation on a target problem that is a problem to be handled by a quantum computer. The display control unit 622 generates data for displaying a variable node indicating the state of a plurality of qubits of the target problem, a parity node indicating the parity of at least three of those plurality of qubits, and an edge connecting the variable node indicating the state of at least three of those qubits and the parity node. The arithmetic unit 621 corresponds to an example of arithmetic means. The display control unit 622 corresponds to an example of display control means.

[0133] According to the computing system 620, it is also possible to represent the coupling of three or more qubits. In particular, according to the computing system 620, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge that associates a qubit with the parity.

[0134] <Fourth Embodiment> FIG. 16 is a diagram showing an example of a processing procedure in a display control method according to at least one embodiment. The display control method shown in FIG. 16 includes generating data (step S611).

[0135] In generating data (step S611), a computer generates data for displaying a variable node indicating the state of at least three qubits, a parity node indicating the parity of those at least three qubits, and an edge connecting the variable node and the parity node.

[0136] According to the display control method shown in FIG. 16, it is also possible to represent the coupling of three or more qubits. In particular, according to the display control method shown in FIG. 16, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge that associates a qubit with the parity.

[0137] <Fifth Embodiment> FIG. 17 is a diagram showing an example of a processing procedure in a display method according to at least one embodiment. The display method shown in FIG. 17 includes performing a display (step S621).

[0138] In performing the display (step S621), a display device displays a variable node indicating the state of at least three qubits, a parity node indicating the parity of those at least three qubits, and an edge connecting the variable node and the parity node.

[0139] According to the display method shown in FIG. 17, it is possible to represent the coupling of three or more qubits. In particular, according to the display method shown in FIG. 17, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge that associates the qubit with the parity.

[0140] <Sixth Embodiment> FIG. 18 is a diagram showing an example of a processing procedure in an arithmetic method according to at least one embodiment. The arithmetic method shown in FIG. 18 includes performing an operation (step S631) and generating data (step S632).

[0141] In performing the operation (step S631), the computer performs an operation on a target problem that is a problem to be handled by the quantum computer. In generating data (step S632), the computer generates data for displaying a variable node indicating the state of each of a plurality of qubits of the target problem, a parity node indicating the parity of at least three qubits among the plurality of qubits, and an edge connecting the variable node and the parity node.

[0142] According to the arithmetic method shown in FIG. 18, it is possible to represent the coupling of three or more qubits. In particular, according to the arithmetic method shown in FIG. 18, the coupling of three or more qubits can be represented by showing the parity of those three or more qubits and an edge that associates the qubit with the parity.

[0143] FIG. 19 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. In the configuration shown in FIG. 19, the computer 700 includes a CPU 710, a main storage device 720, an auxiliary storage device 730, an interface 740, and a non-volatile recording medium 750.

[0144] One or more or a part of any of the above-described arithmetic system 1, arithmetic unit 100, terminal device 200, display control device 610, and arithmetic system 620 may be implemented in computer 700. In that case, the operations of each of the above-described processing units are stored in auxiliary storage device 730 in the form of a program. CPU 710 reads the program from auxiliary storage device 730, expands it in main storage device 720, and executes the above processing according to the program. Also, CPU 710 secures a storage area corresponding to each of the above-described storage units in main storage device 720 according to the program. Communication between each device and other devices is executed by interface 740 having a communication function and performing communication under the control of CPU 710. Also, interface 740 has a port for non-volatile recording medium 750, and reads information from non-volatile recording medium 750 and writes information to non-volatile recording medium 750.

[0145] When arithmetic system 1 is implemented in computer 700, its operation is stored in auxiliary storage device 730 in the form of a program. CPU 710 reads the program from auxiliary storage device 730, expands it in main storage device 720, and executes the above processing according to the program.

[0146] Also, CPU 710 secures a storage area for arithmetic system 1 to perform processing in main storage device 720 according to the program. Communication between arithmetic system 1 and other devices is executed by interface 740 having a communication function and operating under the control of CPU 710. Interaction between arithmetic system 1 and the user is executed by interface 740 having an input device and an output device, presenting information to the user at the output device under the control of CPU 710, and receiving user operations at the input device.

[0147] When arithmetic unit 100 is implemented in computer 700, its operation is stored in auxiliary storage device 730 in the form of a program. CPU 710 reads the program from auxiliary storage device 730, expands it in main storage device 720, and executes the above processing according to the program.

[0148] Also, the CPU 710 secures a storage area for the arithmetic unit 100 to perform processing in the main storage device 720 according to a program. Communication between the arithmetic unit 100 and other devices is executed by the interface 740 having a communication function and operating according to the control of the CPU 710. Interaction between the arithmetic unit 100 and the user is executed by the interface 740 having an input device and an output device, presenting information to the user at the output device according to the control of the CPU 710, and receiving a user operation at the input device.

[0149] When the terminal device 200 is implemented in the computer 700, the operations of the processing unit 290 and its respective parts are stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, expands it in the main storage device 720, and executes the above processing according to the program.

[0150] Also, the CPU 710 secures a storage area for the storage unit 280 in the main storage device 720 according to a program. Communication with other devices by the communication unit 210 is executed by the interface 740 having a communication function and operating according to the control of the CPU 710. Display of an image by the display unit 220 is executed by the interface 740 including a display device and displaying various images according to the control of the CPU 710. Reception of a user operation by the operation input unit 230 is executed by the interface 740 including an input device and receiving a user operation according to the control of the CPU 710.

[0151] When the display control device 610 is implemented in the computer 700, the operation of the display control unit 611 is stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, expands it in the main storage device 720, and executes the above processing according to the program.

[0152] Also, the CPU 710 secures a storage area for the display control device 610 to perform processing in the main storage device 720 according to a program. Communication between the display control device 610 and other devices is executed by the interface 740 having a communication function and operating according to the control of the CPU 710. Interaction between the display control device 610 and the user is executed by the interface 740 having an input device and an output device, presenting information to the user at the output device according to the control of the CPU 710, and receiving a user operation at the input device.

[0153] When the arithmetic system 620 is implemented in the computer 700, the operations of the arithmetic unit 621 and the display control unit 622 are stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, expands it in the main storage device 720, and executes the above processing according to the program.

[0154] Also, the CPU 710 secures a storage area for the arithmetic system 620 to perform processing in the main storage device 720 according to a program. Communication between the arithmetic system 620 and other devices is executed by the interface 740 having a communication function and operating according to the control of the CPU 710. Interaction between the arithmetic system 620 and the user is executed by the interface 740 having an input device and an output device, presenting information to the user at the output device according to the control of the CPU 710, and receiving a user operation at the input device.

[0155] One or more of the above-described programs may be recorded on the non-volatile recording medium 750. In this case, the interface 740 may be configured to read the program from the non-volatile recording medium 750. Then, the CPU 710 may directly execute the program read by the interface 740, or may temporarily store it in the main storage device 720 or the auxiliary storage device 730 and then execute it.

[0156] Note that, among the processes performed by the arithmetic system 1, the arithmetic device 100, the terminal device 200, the display control device 610, and the arithmetic system 620, a program for executing all or part of the processes performed using a classical computer may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed to perform the processes of each part. Here, the "computer system" is assumed to include hardware such as an OS (Operating System) and peripheral devices. In addition, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM (Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), or a storage device such as a hard disk built into a computer system. Further, the above program may be for realizing a part of the aforementioned functions, and may also be for realizing the aforementioned functions in combination with a program already recorded in the computer system.

[0157] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and designs and the like within the scope not departing from the gist of the present invention are also included.

[0158] Some or all of the above embodiments may be described as follows in the following supplementary notes, but are not limited thereto.

[0159] (Supplementary Note 1) A display control means for generating data for displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes A display control device comprising:

[0160] (Supplementary Note 2) The display control means generates the data for displaying variable nodes each indicating the state of a plurality of qubits of a target problem which is a problem to be handled by a quantum computer. The at least three qubits are included in the plurality of qubits. The display control device according to Supplementary Note 1.

[0161] (Supplementary Note 3) The display control means generates the data for displaying a graph in which the set values for the variable nodes and the set values for the parity nodes in the target problem are each expressed in color or shading, or a combination thereof, and the value of the qubit indicated by the variable node and the parity indicated by the parity node are each expressed by the orientation of an icon indicating the node. The display control device according to Supplementary Note 2.

[0162] (Supplementary Note 4) The display control means generates the data for displaying a graph indicating a physical problem which is the target problem converted so as to be implementable on a quantum computer. The display control device according to Supplementary Note 2 or Supplementary Note 3.

[0163] (Supplementary Note 5) The display control means generates the data for displaying a graph indicating a logical problem which is the target problem before being converted so as to be implementable on a quantum computer. The information generation device according to any one of Supplementary Notes 2 to 4.

[0164] (Supplementary Note 6) The display control means generates the data for displaying the graph of the physical problem, in which the correspondence between a physical qubit which is a qubit used in the physical problem and a logical qubit which is a qubit used in the logical problem is indicated by a representation method in which the representation methods assigned to the logical qubits are combined. The information generation device according to Supplementary Note 4.

[0165] (Supplementary Note 7) The display control means generates the data for switchably displaying a plurality of combinations of values of the quantum bits corresponding to one value of the parity node, in association with the respective variable nodes. The display control device according to any one of Appendices 1 to 6.

[0166] (Appendix 8) An arithmetic system comprising arithmetic means for performing an operation on a target problem, which is a problem to be handled by a quantum computer, and display control means. The display control means variable nodes respectively indicating the states of a plurality of quantum bits of the target problem, parity nodes respectively indicating the parity of at least three quantum bits among the plurality of quantum bits, and edges connecting the variable nodes respectively indicating the states of the at least three quantum bits and the parity nodes generates data for displaying. Arithmetic system.

[0167] (Appendix 9) The display control means generates the data for displaying a graph in which the set values for the variable nodes and the set values for the parity nodes in the target problem are both expressed in terms of color or shading, or a combination thereof, and the values of the quantum bits indicated by the variable nodes and the parity indicated by the parity nodes are both expressed in terms of the orientation of icons indicating the nodes. The arithmetic system according to Appendix 8.

[0168] (Appendix 10) The display control means generates the data for displaying a graph of the physical problem, which is the target problem converted so as to be implementable on a quantum computer. The arithmetic system according to Appendix 8 or Appendix 9.

[0169] (Appendix 11) The display control means generates the data for displaying a graph of the logical problem which is the target problem before being converted so as to be implementable on a quantum computer. The arithmetic system according to any one of Appendices 8 to 10.

[0170] (Appendix 12) The display control means generates the data for displaying a graph of the physical problem, and shows a correspondence relationship between physical qubits which are qubits used in the physical problem and logical qubits which are qubits used in the logical problem, in a representation method in which the representation methods assigned to the logical qubits are combined. The arithmetic system according to Appendix 10.

[0171] (Appendix 13) The display control means generates the data for switchably displaying a plurality of combinations of values of the qubits corresponding to one value of the parity node, in association with the respective variable nodes. The arithmetic system according to any one of Appendices 8 to 12.

[0172] (Appendix 14) A computer generates data for displaying variable nodes respectively indicating states of at least three qubits, a parity node indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity node and includes generating data for displaying them.

[0173] (Appendix 15) Generating the data includes the computer generating data for displaying variable nodes respectively indicating states of a plurality of qubits of a target problem which is a problem to be handled by a quantum computer, wherein the at least three qubits are included in the plurality of qubits. The display control method according to Appendix 14.

[0174] (Appendix 16) Generating the data includes the computer generating the data for displaying a graph in which the set values for the variable nodes and the set values for the parity nodes in the target problem are both represented by colors or shades, or combinations thereof, and the values of the qubits indicated by the variable nodes and the parities indicated by the parity nodes are both represented by the orientations of the icons indicating the nodes. The display control device according to Appendix 15.

[0175] (Appendix 17) Generating the data includes the computer generating the data for displaying a graph indicating the physical problem that is the target problem converted so as to be implementable on a quantum computer. The display control method according to Appendix 15 or Appendix 16.

[0176] (Appendix 18) Generating the data includes the computer generating the data for displaying a graph of the logical problem that is the target problem before being converted so as to be implementable on a quantum computer. The display control method according to any one of Appendices 15 to 17.

[0177] (Appendix 19) Generating the data includes the computer generating the data for displaying a graph of the physical problem, in which the correspondence between the physical qubits that are the qubits used in the physical problem and the logical qubits that are the qubits used in the logical problem is indicated by a representation method in which the representation methods assigned to the logical qubits are combined. The display control method according to Appendix 17.

[0178] (Appendix 20) Generating the data includes the computer generating the data for switchably displaying a plurality of combinations of values of the qubits associated with one value of the parity node for each of the variable nodes. The display control method according to any one of Appendices 14 to 19.

[0179] (Appendix 21) A display device displays variable nodes respectively indicating the states of at least three qubits, parity nodes respectively indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes. A display method including this.

[0180] (Appendix 22) The displaying includes the display device displaying variable nodes respectively indicating the states of a plurality of qubits that are problems to be handled by a quantum computer, wherein the at least three qubits are included in the plurality of qubits. The display method according to Appendix 21.

[0181] (Appendix 23) The displaying includes the display device displaying a graph in which setting values for the variable nodes and setting values for the parity nodes in the target problem are both expressed in color or shading, or a combination thereof, and the value of the qubit indicated by the variable node and the parity indicated by the parity node are both expressed by the orientation of an icon indicating the node. The display method according to Appendix 22.

[0182] (Appendix 24) The displaying includes the display device displaying a graph of a physical problem that is the target problem converted to be implementable on a quantum computer. The display method according to Appendix 22 or Appendix 23.

[0183] (Appendix 25) Said displaying includes the display device displaying a graph of a logical problem which is the target problem before being converted so as to be implementable on a quantum computer. The display method according to any one of Appendices 22 to 24.

[0184] (Appendix 26) Said displaying includes the display device displaying a graph of the physical problem, wherein the correspondence between the physical qubits which are the qubits used in the physical problem and the logical qubits which are the qubits used in the logical problem is shown by a representation method in which the representation methods assigned to the logical qubits are combined. The display method according to Appendix 24.

[0185] (Appendix 27) Said displaying includes the display device switchably displaying, in association with each of the variable nodes, a plurality of combinations of values of the qubits corresponding to one value of the parity node. The display method according to any one of Appendices 21 to 26.

[0186] (Appendix 28) An operation system performs an operation on a target problem which is a problem to be handled by a quantum computer, generates data for displaying variable nodes respectively indicating states of a plurality of qubits of the target problem, parity nodes respectively indicating the parity of at least three qubits among the plurality of qubits, and edges connecting the variable nodes respectively indicating the states of the at least three qubits and the parity nodes, and an operation method including this.

[0187] (Appendix 29) Generating the data includes the operation system generating the data for displaying a graph in which the set values for the variable nodes and the set values for the parity nodes in the target problem are both represented by colors or shades, or combinations thereof, and the values of the qubits indicated by the variable nodes and the parities indicated by the parity nodes are both represented by the orientations of the icons indicating the nodes. The operation method according to Supplementary Note 28.

[0188] (Supplementary Note 30) Generating the data includes the operation system generating the data for displaying a graph of the physical problem, which is the target problem converted so as to be implementable on a quantum computer. The operation method according to Supplementary Note 28 or Supplementary Note 29.

[0189] (Supplementary Note 31) Generating the data includes the operation system generating the data for displaying a graph of the logical problem, which is the target problem before being converted so as to be implementable on a quantum computer. The operation method according to any one of Supplementary Notes 28 to 30.

[0190] (Supplementary Note 32) Generating the data includes the operation system generating the data for displaying the graph of the physical problem, in which the correspondence between the physical bits, which are the qubits used in the physical problem, and the logical bits, which are the qubits used in the logical problem, is indicated by a representation method in which the representation methods assigned to the logical bits are combined. The operation method according to Supplementary Note 30.

[0191] (Supplementary Note 33) Generating the data includes the operation system generating the data for switchably displaying a plurality of combinations of the values of the qubits, corresponding to one value of the parity node, in association with the respective variable nodes. The operation method described in any one of Supplementary Notes 28 to 32.

[0192] (Supplementary Note 34) To cause a computer to generate data for displaying variable nodes respectively indicating the states of at least three qubits, parity nodes indicating the parity of the at least three qubits, and edges connecting the variable nodes and the parity nodes A program. to execute.

[0193] (Supplementary Note 35) In generating the data, the program causes the computer to execute controlling the computer to display variable nodes respectively indicating the states of a plurality of qubits of a target problem, which is a problem to be handled by a quantum computer. The at least three qubits are included in the plurality of qubits. The program according to Supplementary Note 34.

[0194] (Supplementary Note 36) In generating the data, the program causes the computer to execute generating data for displaying a graph in which both the set values for the variable nodes and the set values for the parity nodes in the target problem are expressed in terms of color or shading, or a combination thereof, and both the value of the qubit indicated by the variable node and the parity indicated by the parity node are expressed in terms of the orientation of an icon indicating the node. The program according to Supplementary Note 35.

[0195] (Supplementary Note 37) In generating the data, the program causes the computer to execute generating data for displaying a graph of a physical problem, which is the target problem converted so as to be implementable on a quantum computer. The program according to Supplementary Note 35 or Supplementary Note 36.

[0196] (Appendix 38) In generating the data, the program causes the computer to generate data for displaying a graph of the logical problem, which is the target problem before being converted to be implementable on a quantum computer. The program according to any one of Appendices 35 to 37.

[0197] (Appendix 39) In generating the data, the program causes the computer to generate the data for displaying a graph of the physical problem, and shows the correspondence between the physical qubits used in the physical problem and the logical qubits used in the logical problem in a representation method in which the representation methods assigned to the logical qubits are combined. The program according to Appendix 37.

[0198] (Appendix 40) In generating the data, the program causes the computer to generate the data for switchably displaying a plurality of combinations of values of the quantum bits corresponding to one value of the parity node, each associated with the respective variable node. The program according to any one of Appendices 34 to 39.

Explanation of Signs

[0199] 1,620 computing system 100 computing device 110 qubit device 120 coupler 200 terminal device 210 communication unit 220 display unit 230 operation input unit 280 storage unit 290 processing unit 291 problem conversion unit 292 operation control unit 293 Graph generation unit 294, 611, 622 Display control unit 610 Display control device 621 Calculation unit

Claims

1. variable nodes each representing a state of at least three qubits; a parity node indicating the parity of the at least three quantum bits; an edge connecting the variable node and the parity node; A display control device comprising: a display control means for generating data for displaying the display.

2. the display control means generates the data for displaying variable nodes each indicating a state of a plurality of quantum bits of a target problem, which is a problem to be handled by a quantum computer; the at least three quantum bits are included in the plurality of quantum bits; The display control device according to claim 1 .

3. the display control means generates the data for displaying a graph showing the physical problem, which is the target problem, converted so as to be implementable on a quantum computer; The display control device according to claim 2 .

4. the display control means generates the data for displaying a graph showing the logic problem, which is the target problem, before being converted so as to be implementable on a quantum computer; The display control device according to claim 2 or 3.

5. the display control means generates the data for displaying a graph showing the physics problem, the graph showing a correspondence between physical bits, which are quantum bits used in the physics problem, and logical bits, which are quantum bits used in the logic problem, which is the target problem before being converted into the physics problem, in a representation method that combines representation methods assigned to logical bits; The display control device according to claim 3 .

6. the display control means generates the data for switchably displaying a plurality of combinations of the values ​​of the quantum bits corresponding to one value of the parity node in association with each of the variable nodes; The display control device according to claim 1 .

7. The present invention provides a quantum computing system that includes a computing means for computing a target problem, which is a problem to be handled by a quantum computer, and a display control means; The display control means A variable node indicating each of the states of a plurality of quantum bits of the target problem; a parity node indicating the parity of at least three quantum bits among the plurality of quantum bits; an edge connecting a variable node indicating each of the states of the at least three quantum bits to the parity node; Generate data to display Calculation system.

8. The computer variable nodes each representing a state of at least three qubits; a parity node indicating the parity of the at least three quantum bits; an edge connecting the variable node and the parity node; A display control method comprising: generating data for displaying the display.

9. The display device, variable nodes each representing a state of at least three qubits; a parity node indicating the parity of the at least three quantum bits; an edge connecting the variable node and the parity node; A display method comprising:

10. On the computer, variable nodes each representing a state of at least three qubits; a parity node indicating the parity of the at least three quantum bits; an edge connecting the variable node and the parity node; A program that causes a program to generate data for displaying the program.

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