Polishing compositions and methods of using the same

Abstract

To selectively polish a wide variety of materials (e.g., oxides such as silicon oxides) while achieving very low polishing / removal rates on silicon nitride and associated silicon and nitrogen based films like SiCN (silicon carbo-nitride).SOLUTION: A polishing composition comprises: at least one abrasive; at least one nitride removal rate reducing agent; an acid or a base; and water. The at least one nitride removal rate reducing agent includes a hydrophobic portion and a hydrophilic portion, where the hydrophobic portion includes a C12 to C40 hydrocarbon group and is separated by 0 to 10 alkylene oxide groups from the hydrophilic portion. The polishing composition has a pH of about 2 to about 6.5, and has a ratio of a removal rate for a silicon oxide to a removal rate for a silicon nitride of at least about 3:1 when polishing a patterned wafer comprising at least silicon nitride patterns overlaid with at least silicon oxide.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to polishing compositions and methods of using same.

[0002] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Utility Application Serial No. 16 / 356,685, filed March 18, 2019, which claims priority to U.S. Provisional Application No. 62 / 781,648, filed December 19, 2018, the contents of which are incorporated herein by reference in their entireties. [Background technology]

[0003] The semiconductor industry is constantly driven to improve chip performance by further scaling of devices through process and integration innovations. Chemical Mechanical Polishing / Planarization (CMP) is a powerful technology that enables many complex integration schemes at the transistor level, thereby facilitating increased chip density. Summary of the Invention

[0004] Transistors are generally fabricated in a Front End of Line (FEOL) transistor manufacturing process. The FEOL material stack typically includes a metal gate and multiple stacks of dielectric materials. Electrical isolation of the billions of active elements in each integrated circuit is a goal in FEOL and can be achieved using a shallow trench isolation (STI) process. A portion of the STI process is shown in FIG. 1 for illustrative purposes. As can be seen from FIG. 1, prior to the STI CMP process, thermal silicon oxide and SiN are deposited on silicon (e.g., silicon wafer) (FIG. 1(a)), then etched out to form trenches / isolation and "active" non-trench areas (forming transistor containing areas) (FIG. 1(b)), these trenches / isolation areas can then be filled (e.g., by depositing plasma-enhanced chemical vapor deposition (PECVD) silicon oxide (e.g., TEOS) in the trenches) such that the active non-trench areas in the trenches can be isolated by silicon oxide (FIG. 1(c)), and then the "overload / extra" silicon oxide above the active non-trench areas can be selectively removed while maintaining the silicon oxide in the shallow trenches (FIG. 1(d)). The selective removal of silicon oxide is achieved by a shallow trench isolation (STI) chemical mechanical polishing / planarization (CMP) process. Here, a CMP slurry composition (such as that described in this disclosure) having high material removal rate (MRR) selectivity of silicon oxide over silicon nitride (e.g., SiN) is preferably used to remove silicon oxide at a high rate without substantially removing silicon nitride (the stop-on layer). After the above STI CMP step, etching can be used to expose silicon to complete the isolation and prevent adjacent transistors formed in the active non-trench areas from contacting each other, thereby preventing shorting of electrical circuits.

[0005] The widely used dielectric films in STI are silicon nitride (e.g., SiN), silicon oxide (e.g., TEOS: tetraethyl orthosilicate), polysilicon (P-Si), silicon carbonitride (e.g., SiCN), and low-k / ultra-low-k dielectric films (e.g., SiCOH). With the introduction of high-k metal gate technology at 45 nm and FinFET technology at 22 nm chip production, SiN, TEOS, SiCN, and P-Si films are beginning to be used more frequently and in more applications in FEOL. In addition, at the BEOL, as the resistivity of traditional barrier materials (e.g., Ta / TaN or Ti / TiN) has been shown not to scale down effectively for advanced sub-10 nm manufacturing nodes, these barrier materials are becoming increasingly difficult to fabricate for various BEOL material stacks. For this purpose, dielectrics such as SiN, TEOS, SiCN, and P-Si can be substituted. Thus, for both FEOL and BEOL, these dielectric films can be used as etch stop layers, capping materials, spacer materials, additional liners, diffusion / passivation barriers, hardmasks, and / or stop-on layers.

[0006] In general, dielectric films are much more commonly used in advanced semiconductor manufacturing. From a CMP perspective, most of these integrations incorporating dielectrics require polishing compositions (slurries) that can process / polish and / or stop these films, such as slurries that can remove SiN but not TEOS / P-Si, or slurries that can remove TEOS / P-Si but not SiN.

[0007] The present disclosure relates to stable aqueous slurries capable of selectively polishing a wide variety of materials (e.g., oxides such as silicon oxide) while achieving very low polishing / removal rates on silicon nitrides such as SiCN (silicon carbonitride) and related silicon and nitrogen based films. For example, the polishing compositions can selectively polish silicon oxides (e.g., SiO ) with relatively high material removal rates (MRR). 2) and may stop or polish at a very slow rate on silicon nitride (e.g., SiN) or related films. For example, silicon oxides that can be removed by the polishing compositions described herein include silicon oxides selected from TEOS, thermal oxides (TOX) (e.g., caused by autoclave-induced oxidation of bare silicon), silicon oxides formed by plasma-enhanced PVD deposition (e.g., high-density plasma or high aspect ratio plasma), silicon oxides formed by CVD deposition after plasma surface hardening, carbon-doped silicon oxide (SiOC), and silicon oxides formed by liquid application of oxide precursors followed by light- or heat-induced hardening. In some instances, the target film to be removed with high MRR may not be a silicon oxide dielectric, but a metal or metal oxide or metal nitride. Common examples of metals, metal oxides, and metal nitrides include metals such as copper, cobalt, ruthenium, aluminum, titanium, tungsten, and tantalum, and metal oxides such as hafnium oxide, titanium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and nitrides of ruthenium, aluminum, titanium, tungsten, and tantalum. In such cases, the stop-on / low removal rate film may still be a silicon nitride film, and thus a polishing composition containing a nitride removal rate reducer from the present disclosure may be utilized to achieve the desired selectivity.

[0008] More specifically, the present disclosure relates to a polishing composition comprising an abrasive, a nitride removal rate reducing agent, an acid or base, water, and optionally a dishing reducing agent (e.g., an anionic dishing agent). The pH of the polishing compositions described herein can be in the range of 2 to 6.5, or more specifically, in the range of 2 to 4.5. The compositions of the present disclosure can also be diluted (e.g., at the point of use) to form a polishing composition without loss of performance. The present disclosure also discusses a method for polishing a semiconductor substrate using the aforementioned polishing compositions.

[0009] In one aspect, embodiments disclosed herein relate to a polishing composition that includes at least one abrasive, at least one nitride removal rate reducer, an acid or base, and water. The nitride removal rate reducer is C 12 From C 40 and a hydrophilic portion including at least one selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group, the hydrophobic portion and the hydrophilic portion being separated by 0 to 10 alkylene oxide groups. The polishing composition has a pH of about 2 to about 6.5.

[0010] In another aspect, the embodiments disclosed herein include a method for removing a nitride from a substrate comprising the steps of: at least one abrasive; at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion; an acid or base; and a water-based abrasive. wherein the polishing composition has a pH of about 2 to about 6.5, and wherein during polishing of a patterned wafer comprising at least a silicon nitride pattern, the ratio of silicon oxide removal rate to silicon nitride removal rate is at least about 3:1, and the silicon nitride pattern is covered with at least silicon oxide (and optionally other materials such as metal or dielectric).

[0011] In yet another aspect, embodiments disclosed herein relate to a polishing composition comprising at least one abrasive, at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion, an acid or a base, and water, wherein the polishing composition has a pH of about 2 to about 6.5, and wherein when a patterned wafer comprising at least a silicon nitride pattern covered with at least silicon oxide is polished with the polishing composition, less than about 1000 angstroms of silicon oxide dishing is produced, and the silicon nitride pattern on the patterned wafer is exposed by polishing.

[0012] In yet another aspect, embodiments disclosed herein relate to a polishing composition comprising at least one abrasive, at least one nitride removal rate reducing agent comprising a hydrophobic portion and a hydrophilic portion, an acid or a base, and water, wherein the polishing composition has a pH of about 2 to about 6.5, and when a patterned wafer comprising at least a silicon nitride pattern covered with at least a silicon oxide is polished with the polishing composition, less than about 500 angstroms of silicon nitride erosion occurs, and the silicon nitride pattern on the patterned wafer is exposed upon polishing.

[0013] In yet another aspect, embodiments disclosed herein relate to a method that includes applying a polishing composition described herein to a substrate having at least silicon nitride and at least silicon oxide on a surface of the substrate, contacting a pad with the surface of the substrate, and moving the pad relative to the substrate.

[0014] The synergistic use of an abrasive, a nitride RR reducing agent, and an optional dishing reducing agent in the same composition provides unique advantages not found in currently available slurries. Among other advantages, these advantages include:

[0015] 1. The compositions described herein can achieve very low silicon nitride (e.g., SiN) removal rates. Excellent silicon nitride protection can be achieved by judicious selection and formulation / loading of silicon nitride removal rate reducers. Furthermore, low silicon nitride removal rates are observed on both blanket wafers (i.e., wafers containing only silicon nitride films) and patterned wafers (i.e., wafers etched with a pattern of silicon nitride films and other films, e.g., TEOS), as demonstrated in this disclosure.

[0016] 2. Very low silicon nitride removal rates make it possible to obtain minimal loss of silicon nitride, thereby allowing for very low erosion post-polishing of silicon nitride on patterned wafers.

[0017] 3. The composition can achieve low silicon oxide dishing / step height. The dishing performance can be tuned by judicious selection and loading / concentration of dishing reducing agents.

[0018] 4. The composition is compatible with a wide variety of abrasives. Through particle modification, the zeta potential of the abrasive can be adjusted to further tune the removal rate on the target film. Anionic, cationic, and neutral abrasives can all form stable slurries with higher silicon oxide removal rates and relatively low silicon nitride removal rates.

[0019] 5. The composition forms a stable slurry with high purity colloidal silica as the abrasive This allows for the production of slurries with low trace metal counts and low large particle counts, resulting in reduced defects on the polished wafer, when compared to wafers polished with conventionally used ceria abrasives (which generally produce a large amount of defects on the polished wafer). Additionally, the compositions described herein may overcome certain shortcomings of conventional silica-based STI CMP compositions, such as their high silicon nitride removal rates and low removal selectivity between silicon oxide and silicon nitride.

[0020] 6. The composition produces low nitride removal rates across a range of polishing conditions. For example, silicon nitride removal rates remain low with both hard polishing pads (e.g., polyurethane-based pads) and soft polishing pads (e.g., poromeric and low Shore D hardness pads). In addition, it has been observed that down force and velocity do not significantly affect silicon nitride removal rates, which is a good CMP characteristic because the stop-on-film behavior is non-prestonian. The little variation in removal rate as a function of pressure and velocity of the disclosed compositions results in very good topography and high yield post-patterned wafer polishing. In the language of the art, the disclosed compositions result in low values ​​of silicon nitride erosion / loss, along with low values ​​of silicon oxide dishing and step height.

[0021] In contrast to currently available modern slurries, the polishing compositions and polishing concentrates of the present disclosure provide performance retention on current generation integrated circuit substrates while simultaneously representing significant advantages for next generation substrates and integration schemes.The compositions of the present disclosure can successfully and efficiently remove various metals and dielectrics with very high selectivity over silicon nitride removal.The compositions can be used in shallow trench isolation (STI) processes, self-aligned contact processes, or other processes where extremely low silicon nitride material removal rates are desired. [Brief description of the drawings]

[0022] [Figure 1]FIG. 1 is a schematic diagram of the process flow in a shallow trench isolation (including STI CMP) process in semiconductor manufacturing. FIG. 1(a) shows that thermal silicon oxide (TOX) and silicon nitride (SiN) are deposited on top of silicon (Si) before shallow trench isolation (STI) chemical mechanical planarization (CMP). This is followed by etching to form the active areas. FIG. 1(b) shows that a trench is created leaving the active areas of silicon covered by TOX and SiN. This is then filled with a dielectric - typically PE-CVD silicon oxide (SiO2). FIG. 1(c) shows that in the shallow trench the active areas are isolated by a silica dielectric. To complete the STI, the SiO2 is selectively removed from the active areas while keeping the SiO2 in the shallow trench. This can be done by STI CMP, the subject of the present invention, where the SiO2 is removed at a high rate and the SiN (the stop-on layer) is not removed. FIG. 1(d) shows that etching can be used to remove the SiN and expose the Si to complete the STI. The active area of ​​silicon will become a transistor once gate, metallization, and device fabrication is completed. [Diagram 2] FIG. 2 is a schematic diagram of the STI patterned wafer film stack before polishing. [Diagram 3] FIG. 3 is a wafer map showing gross defectivity after STI CMP using a silica-based polishing composition according to the present disclosure. [Figure 4] FIG. 4 is a wafer map showing gross defectivity after STI CMP using a commercial ceria abrasive-containing composition. Detailed Description of the Invention

[0023] The present disclosure relates to polishing compositions and methods for using same to polish semiconductor substrates. In some embodiments, the present disclosure relates to selectively polishing silicon oxide surfaces over silicon nitride surfaces. Selective polishing of silicon oxide over silicon nitride is an important step in semiconductor manufacturing. It is a critical process in the STI process and is commonly performed during shallow trench isolation (STI) processes. Traditionally, STI polishing compositions (slurries) utilize ceria abrasives to achieve the polishing performance (e.g., selectivity) required in STI processes because compositions using silica abrasives do not perform adequately (e.g., high silicon nitride removal rates). However, ceria abrasives are known to impart high defectivity and scratching when used in polishing compositions due to their "inorganic hard" nature. In addition, ceria-based polishing compositions exhibit shorter shelf life (e.g., lower storage capacity, lower usable period, and earlier expiration date), shorter pot life (e.g., activity after opening the container and / or in the holding tank or dispensing loop) than silica-based polishing compositions, and ceria has greater price volatility than silica. In addition, ceria contains rare earth metals and is more expensive than silica. The compositions according to the present disclosure allow for the use of silica abrasives, which are softer than ceria abrasives, for STI slurries. The silica-containing polishing composition can provide very good selectivity in the material removal rate (MRR) of silicon oxide (e.g., TEOS) on silicon nitride (e.g., SiN), and at the same time, can provide a polished wafer surface with a very low defectivity when compared with STI processes that utilize ceria abrasives. Thus, the polishing composition according to the present application can increase the device yield of the wafer compared with conventional polishing compositions that utilize ceria abrasives.

[0024] The polishing compositions described herein can include (a) an abrasive, (b) a nitride removal rate reducing agent, (c) an acid or base, (d) water, and optionally (e) a dishing reducing agent (e.g., an anionic dishing reducing agent). The polishing composition can have a pH of at least about 2 to a maximum of about 6.5. The polishing compositions of the present disclosure can have high selectivity for polishing dielectrics or metals over polishing silicon nitride. The present disclosure also provides methods of using the polishing compositions to polish semiconductor substrates. In particular, the present disclosure provides methods for polishing dielectrics or metals with high selectivity to silicon nitride.

[0025] In one or more embodiments, at least one (e.g., two or three) abrasives are selected from cationic abrasives, substantially neutral abrasives, and anionic abrasives. In one or more embodiments, at least one abrasive is selected from the group consisting of alumina, silica, titania, ceria, zirconia, co-formed products thereof, coated abrasives, surface-modified abrasives, and mixtures thereof. In some embodiments, at least one abrasive does not include ceria.

[0026] In one or more embodiments, the abrasive is a silica-based abrasive, such as one selected from the group consisting of colloidal silica, fumed silica, and mixtures thereof. In one or more embodiments, the abrasive has a surface modified with organic and / or non-siliceous inorganic groups. For example, the cationic abrasive can include an end group of formula (I):

[0027] -Om -X-(CH 2 )n -Y (I) where m is an integer from 1 to 3, n is an integer from 1 to 10, X is Al, Si, Ti, or Zr, and Y is a cationic amino or thiol group. As another example, the anionic abrasive can include an end group of formula (I):

[0028] -Om -X-(CH 2 )n -Y (I) where m is an integer from 1 to 3, n is an integer from 1 to 10, X is Al, Si, Ti, or Zr, and Y is an acid group. In some embodiments, the at least one abrasive is present in the polishing composition described herein in an amount of at least about 0.05 wt.% (e.g., at least about 0.1 wt.%, at least about 0.5 wt.%, at least about 1 wt.%, at least about 2 wt.%, at least about 3 wt.%, or at least about 5 wt.%) to up to about 20 wt.% (e.g., up to about 15 wt.%, up to about 10 wt.%, up to about 8 wt.%) based on the total weight of the composition. %, up to about 6% by weight, up to about 4% by weight, or up to about 2% by weight.

[0029] In one or more embodiments, the abrasives described herein can have an average particle size of at least about 1 nm (e.g., at least about 5 nm, at least about 10 nm, at least about 20 nm, at least about 40 nm, at least about 50 nm, at least about 60 nm, at least about 80 nm, or at least about 100 nm) to up to about 1000 nm (e.g., up to about 800 nm, up to about 600 nm, up to about 500 nm, up to about 400 nm, or up to about 200 nm). As used herein, average particle size (MPS) is determined by dynamic light scattering techniques.

[0030] In one or more embodiments, at least one (e.g., two or three distinct) nitride removal rate reducer is C 12 From C 40 and a hydrophilic portion containing at least one group selected from the group consisting of a sulfinite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group. In one or more embodiments, the hydrophobic portion and the hydrophilic portion contain 0 to 10 (e.g., 1, 2, 3, 4, 5, 6, 7, 8, or 9) alkylene oxide groups (e.g., —(CH 2 )nO-groups). In one or more embodiments, the nitride removal rate reducer has zero alkylene oxide groups separating the hydrophobic and hydrophilic portions. Without wishing to be bound by theory, it is believed that the presence of alkylene oxide groups in the nitride removal rate reducer is undesirable in some embodiments because it causes slurry stability issues and increases the silicon nitride removal rate.

[0031] In one or more embodiments, the nitride removal rate reducing agent is included in the polishing composition described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to up to about 1000 ppm (e.g., up to about 900 ppm, up to about 800 ppm, up to about 700 ppm, up to about 600 ppm, up to about 500 ppm, or up to about 250 ppm) based on the total weight of the composition.

[0032] In one or more embodiments, the nitride removal rate reducer comprises at least 12 carbon atoms (C 12 ) (e.g., at least 14 carbon atoms (C 14 ), at least 16 carbon atoms (C 16 ), at least 18 carbon atoms (C 18 ), at least 20 carbon atoms (C 20 ), or at least 22 carbon atoms (C 22 )) and / or up to 40 carbon atoms (C 34 ) (e.g., up to 38 carbon atoms (C 38 ), up to 36 carbon atoms (C 36 ), up to 34 carbon atoms (C 34 ), up to 32 carbon atoms (C 32 ), up to 30 carbon atoms (C 30 ), up to 28 carbon atoms (C 28 ), up to 26 carbon atoms (C 26 ), up to 24 carbon atoms (C 24 ), or up to 22 carbon atoms (C 22)). Hydrocarbon groups as referred to herein refer to groups containing only carbon and hydrogen atoms and can include both saturated groups (e.g., linear, branched, or cyclic alkyl groups) and unsaturated groups (e.g., linear, branched, or cyclic alkenyl groups; linear, branched, or cyclic alkynyl groups; or aromatic groups (e.g., phenyl or naphthyl)). In one or more embodiments, the hydrophilic portion of the nitride removal rate reducer includes at least one group selected from a phosphate group and a phosphonic acid group. It is noted that the term "phosphonate group" is expressly intended to include a phosphonic acid group.

[0033] In one or more embodiments, the nitride removal rate reducer is naphthalene sulfonic acid-formaldehyde condensate, lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecyl phosphate, or the like. The oleyl phosphate, behenyl phosphate, octadecyl sulfate, russyl phosphate, ole ...

[0034] In one or more embodiments, the polishing composition described herein optionally further comprises at least one (e.g., two or three) dishing reducing agent (e.g., anionic dishing reducing agent). In one or more embodiments, the at least one dishing reducing agent is a compound containing at least one group selected from the group consisting of hydroxy, sulfate, phosphonate, phosphate, sulfonate, amine, nitrate, nitrite, carboxylate, and carbonate groups. In one or more embodiments, the at least one dishing reducing agent is at least one selected from the group consisting of polysaccharides and substituted polysaccharides. In one or more embodiments, the at least one dishing reducing agent is at least one selected from the group consisting of carrageenan, xanthan gum, hydroxypropyl cellulose, methyl cellulose, ethyl cellulose, hydroxypropyl methyl cellulose, and carboxymethyl cellulose. In one or more embodiments, the at least one nitride removal rate reducing agent and the at least one dishing reducing agent are chemically different from each other.

[0035] In one or more embodiments, the dishing reducing agent is included in the polishing composition described herein in an amount of at least about 0.1 ppm (e.g., at least about 0.5 ppm, at least about 1 ppm, at least about 5 ppm, at least about 10 ppm, at least about 25 ppm, at least about 50 ppm, at least about 75 ppm, or at least about 100 ppm) to up to about 1000 ppm (e.g., up to about 900 ppm, up to about 800 ppm, up to about 700 ppm, up to about 600 ppm, or up to about 500 ppm) based on the total weight of the composition.

[0036] In one or more embodiments, the acid is selected from the group consisting of formic acid, acetic acid, malonic acid, citric acid, propionic acid, malic acid, adipic acid, succinic acid, lactic acid, oxalic acid, hydroxyethylidene diphosphonic acid, 2-phosphono-1,2,4-butanetricarboxylic acid, aminotrimethylenephosphonic acid, hexamethylenediaminetetra(methylenephosphonic acid), bis(hexamethylene)triaminephosphonic acid, aminoacetic acid, peracetic acid, potassium acetate, phenoxyacetic acid, glycine, bicine, diglycolic acid, glyceric acid, tricine, alanine, histidine, valine, phenylalanine, proline, glutamine, aspartic acid, glutamic acid, arginine, lysine, tyrosine, benzoic acid, nitric acid, sulfuric acid, sulfurous acid, phosphoric acid, phosphonic acid, hydrochloric acid, periodic acid, and mixtures thereof.

[0037] In one or more embodiments, the base is selected from the group consisting of potassium hydroxide, sodium hydroxide, cesium hydroxide, ammonium hydroxide, triethanolamine, diethanolamine, monoethanolamine, tetrabutylammonium hydroxide, tetramethylammonium hydroxide, lithium hydroxide, imidazole, triazole, aminotriazole, tetrazole, benzotriazole, tolyltriazole, pyrazole, isothiazole, and mixtures thereof.

[0038] In one or more embodiments, the acid or base can be present in the polishing compositions described herein in an amount of at least about 0.01 wt. % (e.g., at least about 0.05 wt. %, at least about 0.1 wt. %, at least about 0.5 wt. %, or at least about 1 wt. %) to up to about 10 wt. % (e.g., up to about 8 wt. %, up to about 6 wt. %, up to about 5 wt. %, up to about 4 wt. %, or up to about 2 wt. %) based on the total weight of the composition. For example, the acid or base can be added in an amount sufficient to adjust the pH of the polishing composition to a desired value.

[0039] In one or more embodiments, water can be present in the polishing compositions described herein (e.g., as a liquid medium or carrier) in an amount of at least about 50 wt % (e.g., at least about 55 wt %, at least about 60 wt %, at least about 65 wt %, at least about 70 wt %, or at least about 75 wt %) to up to about 99.9 wt % (e.g., up to about 99.5 wt %, up to about 99 wt %, up to about 97 wt %, up to about 95 wt %, or up to about 90 wt %) based on the total weight of the composition.

[0040] In one or more embodiments, the polishing compositions described herein can have a pH of at least about 2 (e.g., at least about 2.5, at least about 3, at least about 3.5, or at least about 4) to at most about 6.5 (e.g., at most about 6, at most about 5.5, at most about 5, or at most about 4.5). Without wishing to be bound by theory, it is believed that polishing compositions having a pH greater than 6.5 can reduce silicon oxide / silicon nitride removal rate selectivity and have stability issues.

[0041] In one or more embodiments, the polishing compositions described herein may be substantially free of one or more of certain components, such as salts (e.g., halide salts), polymers (e.g., cationic or anionic polymers, or polymers other than dishing reducing agents), surfactants (e.g., other than nitride removal rate reducing agents), plasticizers, oxidizers, corrosion inhibitors (e.g., azole or non-azole corrosion inhibitors), and / or certain abrasives (e.g., ceria abrasives or non-ionic abrasives). Halide salts that can be excluded from the polishing composition include alkali metal halides (e.g., sodium or potassium halides) or ammonium halides (e.g., ammonium chloride), which may be chlorides, bromides, or iodides. As used herein, a component that is "substantially free" from the polishing composition refers to a component that is not intentionally added to the polishing composition. In some embodiments, the polishing compositions described herein can have up to about 1000 ppm (e.g., up to about 500 ppm, up to about 250 ppm, up to about 100 ppm, up to about 50 ppm, up to about 10 ppm, or up to about 1 ppm) of one or more of the above components that make the polishing composition substantially free of the polishing composition. In some embodiments, the polishing compositions described can be completely free of one or more of the above components.

[0042] In one or more embodiments, the polishing compositions described herein have a ratio of silicon oxide (e.g., TEOS) removal rate to silicon nitride removal rate (i.e., removal rate selectivity) of at least about 3:1, or at least about 4:1, or at least about 5:1, or at least about 10:1, or at least about 25:1, or at least about 50:1, or at least about 60:1, or at least about 75:1, or at least about 100:1, or at least about 150:1, or at least about 200:1, or at least about 250:1, or at least about 300:1, or at least about 500:1, or at least about 750:1, or up to about 1000:1, or up to about 5000:1. In one or more embodiments, the above ratios may be applicable when measuring removal rates for polishing either blanket wafers or patterned wafers (i.e., wafers including at least a silicon nitride pattern, where the silicon nitride pattern is covered with at least silicon oxide (and optionally other materials such as metals and dielectrics)).

[0043] In one or more embodiments, silicon oxide (e.g., TEOS) dishing of up to about 1000 angstroms, up to about 500 angstroms, or up to about 375 angstroms, or up to about 250 angstroms, or up to about 200 angstroms, or up to about 100 angstroms, or up to about 50 angstroms, and / or at least about 0 angstroms occurs when polishing a patterned wafer (which may include at least a silicon nitride pattern covered with at least silicon oxide) with the polishing composition (e.g., when polishing removes the silicon nitride pattern on the patterned wafer). In one or more embodiments, at most about 500 angstroms, or at most about 400 angstroms, or at most about 300 angstroms, or at most about 250 angstroms, at most about 200 angstroms, at most about 100 angstroms, or at most about 75 angstroms, or at most about 65 angstroms, or at most about 50 angstroms, or at most about 32 angstroms, and / or at least about 0 angstroms of silicon nitride erosion occurs when a patterned wafer (which may include at least a silicon nitride pattern covered with at least silicon oxide) is polished with the polishing composition (e.g., until polishing exposes the silicon nitride pattern on the patterned wafer).

[0044] In one or more embodiments, the planarization efficiency (i.e., the change in silicon oxide step height removed during polishing divided by 100) is at least about 14% (e.g., at least about 20%, at least about 30%, at least about 38%, at least about 40%, at least about 46%, at least about 50%, at least about 60%, at least about 70%, or at least about 74%) and up to about 100% (e.g., up to about 99.9%, up to about 99%, up to about 95%, up to about 90%, up to about 80%, up to about 70%, and up to about 60%) when polishing a patterned wafer using a polishing composition according to the present disclosure. In one or more embodiments, when a polishing composition according to the present disclosure (e.g., a composition including a silica abrasive and a nitride removal rate reducing agent) is used to polish a patterned wafer, the total number of defects on a patterned wafer having a diameter of 12 inches (i.e., about 300 mm) is at most 175 (e.g., at most 170, at most 160, at most 150, at most 125, at most 100, at most 75, at most 50, at most 25, at most 10, or at most 5). As described herein, the defects counted are at least about 90 nm in size.

[0045] In one or more embodiments, the present disclosure features a polishing method that can include applying a polishing composition according to the present disclosure to a substrate (e.g., a wafer) having at least silicon nitride and silicon oxide on the surface of the substrate, contacting a pad with the surface of the substrate, and moving the pad relative to the substrate. In some embodiments, when the substrate includes at least a silicon nitride pattern coated with at least silicon oxide (e.g., silicon oxide in the presence of other materials such as silicon-based dielectrics (e.g., silicon carbide, etc.), metals, metal oxides, and nitrides), the above method can remove at least a portion of the silicon oxide (e.g., silicon oxide on active, non-trench areas) to expose the silicon nitride. It is noted that the terms "silicon nitride" and "silicon oxide" described herein are expressly intended to include both undoped and doped versions of silicon nitride and / or silicon oxide. For example, in one or more embodiments, silicon nitride and silicon oxide can be independently doped with at least one dopant selected from carbon, nitrogen (in the case of silicon oxide), oxygen, hydrogen, or any other known dopant for silicon nitride or silicon oxide. Examples of types of silicon oxide films include, for example, TEOS (Tetra-ethyl orthosilicate), SiOC, SiOCN, SiOCH, SiOH, SiON, etc. Some examples of types of silicon nitride films include SiN (pure silicon nitride), SiCN, SiCNH, and SiNH, to name a few.

[0046] In some embodiments, the method of using the polishing compositions described herein can further include one or more additional steps for fabricating a semiconductor device from a substrate treated with the polishing composition. For example, the method can include, prior to the above-mentioned polishing method, (1) depositing silicon oxide (e.g., thermal silicon oxide) on a substrate (e.g., a silicon wafer) to form a silicon oxide layer, (2) depositing silicon nitride on a silicon nitride layer to form a silicon nitride layer, and (3) polishing the substrate to form grooves and non-groove areas. and (4) depositing silicon oxide on the etched substrate to fill the trenches with silicon oxide. As another example, the method can include at least one additional step of exposing silicon and / or silicon oxide, or other inhomogeneous films, on the wafer substrate after the polishing method described above, such as etching the substrate (e.g., removing silicon nitride and silicon oxide). EXAMPLES

[0047] Examples are provided to further illustrate the capabilities of the polishing compositions and methods of the present disclosure. The examples provided are not intended to limit, and should not be interpreted as limiting, the scope of the present disclosure. The percentages listed are by weight (wt%) unless otherwise specified. The nitride removal rate reducers described in the examples were obtained from various suppliers and may in some cases contain small amounts of similar compounds with carbon chain lengths smaller or larger than those specified in the following table. The carbon chain lengths specified in the table identify the majority of the components of the nitride removal rate reducers.

[0048] Example 1: Demonstration of Nitride Stopping In this example, the polishing composition used in Samples 1A-1F mainly contained 3 w / w% neutral colloidal silica abrasive, malonic acid as a pH adjuster, a nitride removal rate reducer (if present), and water as the liquid carrier. The pH of the polishing composition was 2.3. An Applied Materials Mirra CMP polisher was used with a down force of 2 psi and a flow rate of 175 mL / min for polishing on Dow VP6000 pad 200 mm silicon oxide (TEOS) and silicon nitride (SiN) blanket wafers.

[0049] [Table 1]

[0050] The results in Table 1 showed that the control polishing composition (which did not contain a nitride removal rate reducer) had a removal rate selectivity between silicon oxide and silicon nitride of 8, which is too low for most applications requiring a low silicon nitride ratio. However, with the addition of the nitride removal rate reducer, the polishing composition had a silicon nitride removal rate as low as 1 Å / min, and the removal rate selectivity increased to 868.

[0051] Example 2: Demonstration of pH range and different abrasive surface charges In this example, the polishing compositions used in Samples 2A-2I contained 3 w / w% colloidal silica abrasive, an organic acid as a pH adjuster, n-octadecylphosphonic acid, and water as the liquid carrier. n-Octadecylphosphonic acid is representative of the class of nitride removal rate reducers described herein. Additionally, in this example, the charge of the colloidal silica was varied by using neutral, cationic, and anionic silica, as shown in Table 2. The pH of the polishing composition was varied from about 2.25 to about 4.25. An Applied Materials Mirra CMP polisher was used with a downforce of 2 psi and a flow rate of 175 mL / min on a Dow VP6000 pad to polish 200 mm silicon oxide (TEOS) and silicon nitride blanket wafers.

[0052] [Table 2]

[0053] As shown in Table 2, the nitride removal rate reducers were able to control silicon nitride removal rates over a pH range of about 2.25 to about 4.25 using neutral, cationic, and anionic silica. The robust nitride rate reduction of the above system regardless of the surface charge of the silica abrasive is surprising. For example, cationic abrasives are generally thought to be less compatible with anionic nitride removal rate reducers. In contrast, in this system, the slurry remained stable and the nitride removal rate reducer remained active.

[0054] Traditionally, silicon nitride removal rates using anionic abrasives are typically very high (~400 Å / min) and difficult to control. Significantly, the nitride removal rate reducers described herein can significantly reduce the silicon nitride removal rate. This type of system can be useful when low TEOS and silicon nitride removal rates are desired at high removal rates on films that are well polished by anionic abrasives (e.g., silicon carbide films).

[0055] Example 3: Demonstration of the effect of chain length and head type on nitride removal rate reducers In this example, the polishing composition used in samples 3A to 3L was 3 w / w% colloidal silica. The polishing compositions contained a carbide abrasive, malonic acid as a pH adjuster, a nitride removal rate reducer as shown in Table 3, and water as a liquid carrier. The pH of the polishing composition was 2.25. Specifically, the nitride removal rate reducers used in Samples 3A-3L contained the head type and hydrophobic material as shown in Table 3, and did not contain any alkylene oxide groups. Additionally, the nitride removal rate reducers used in Samples 3I, 3J, and 3K contained a mixture of surfactants, with lauryl / myristyl phosphate, stearyl phosphate, and lauryl phosphate as the major components, respectively.

[0056] An Applied Materials Mirra CMP polisher was used to polish 200 mm silicon oxide (TEOS) and silicon nitride blanket wafers on a Dow VP6000 pad with a down force of 2 psi and a flow rate of 175 mL / min.

[0057] [Table 3]

[0058] As shown in Table 3, the size of the hydrophobized moiety in the nitride removal rate reducer plays an important role in determining the efficiency of silicon nitride rate reduction. Table 3 shows that, among the agents tested, chain lengths of 12 or more perform best for effective nitride stopping under the conditions tested. Carbon chain lengths of 12 or more in the nitride removal rate reducer (see samples 3D, 3E, 3F, 3G, 3I, 3J, 3K, and 3L in Table 3) ensure low SiN RR (typically <5A / min) and generate high selectivity for TEOS:SiN RR (>250) for blanket films. Thus, such polishing compositions are ideally suited for STI CMP processes where high selectivity of silicon oxide to silicon nitride is desired.

[0059] Example 4: Demonstration of downforce effect In this example, the polishing compositions used in Samples 4A to 4C were 3 w / w% colloidal The polishing compositions contained silica abrasive, an organic acid as a pH adjuster, n-octadecylphosphonic acid, and water as the liquid carrier. The pH of the polishing compositions ranged from 2 to 6.5. An Applied Materials Mirra CMP polisher was used on a Dow IC1010 pad at downforces of 2, 3, and 4 psi and a flow rate of 175 mL / min to polish 200 mm high density plasma (HDP) silicon oxide, tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), and silicon nitride coated wafers.

[0060] [Table 4]

[0061] As shown in Table 4, silicon oxide films (HDP, TEOS, and BPSG) exhibited Prestonian behavior, while silicon nitride removal rates exhibited non-Prestonian behavior and remained well controlled regardless of the applied downforce. In CMP language, Prestonian behavior of removal rate means that the polishing rate increases linearly with increasing polishing pressure and / or polisher angular velocity / rpm (revolutions per minute). Prestonian behavior is desirable for high rate target films (here silicon oxide films). Non-Prestonian behavior means that the polishing rate does not change appreciably with changes in pressure or velocity. Non-Prestonian behavior is somewhat more desirable for stop on films (here SiN). As seen in Table 4, the removal rate of silicon oxide films increases linearly / Prestonian with increasing downforce (e.g. TEOS). RR increases from 1835 to 2324 to 3140 A / min with increasing down force from 2 to 3 to 4 psi pressure). Conversely, the SiN (stop on film) removal rate does not change appreciably with increasing pressure (i.e., SiN RR varies from 4 to 2 to 1 A / min with increasing down force from 2 to 3 to 4 psi pressure). Furthermore, this example demonstrates that the polishing composition has similar behavior on silicon oxide family films as defined above. For further clarification, in Table 4, three examples of silicon oxide films are shown: HDP, TEOS, and BPSG. The polishing composition of the present disclosure works very effectively in imparting high material removal rates to all different types of silicon oxide films. Equivalent experiments using examples of different types of silicon nitride films (SiN, SiCN, etc.) showed similar slurry stopping behavior to that achieved on the SiN films depicted in Table 4. For simplicity, only the SiN film rates are shown in Table 4.

[0062] Example 5: Demonstration of pad effect In this example, the polishing compositions used in Samples 5A-5C contained 3 w / w% colloidal silica abrasive, an organic acid as a pH adjuster, a nitride removal rate reducer, and water as the liquid carrier. The pH of the polishing compositions ranged from 2 to 6.5. 200 mm tetraethyl orthosilicate (TEOS) and silicon nitride (SiN) blanket wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 or Fujibo H800 pad at a downforce of 2 psi and a flow rate of 175 mL / min.

[0063] [Table 5]

[0064] The nitride removal rate reducers were effective in silicon nitride protection as shown in Table 5. On the Dow VP6000 pad, which has a medium hardness, all samples (5A-5C) provided effective nitride protection, as demonstrated by the low SiN removal rate and high TEOS / SiN removal rate selectivity. However, on the Fujibo H800 pad, which is a soft pad, only the samples containing nitride removal rate reducers with long-chain saturated hydrophobes (5A, 5B) provided effective nitride stopping. Thus, this example demonstrates that the polishing composition of the present disclosure works effectively on all types of polishing pads. Furthermore, this example suggests a trend for increased nitride protection when the nitride removal rate reducer contains longer hydrophobes, is more saturated, and / or is more hydrophobic.

[0065] Example 6: Demonstration of dishing reduction In this example, the polishing composition used in Samples 6A-6D contained 3 w / w% colloidal silica abrasive, an organic acid as a pH adjuster, n-octadecylphosphonic acid, an anionic dishing reducing polymer (if present), and water as the liquid carrier. The pH of the polishing composition was 3.0. 200 mm STI 1 silicon oxide / silicon nitride patterned wafers were polished using an Applied Materials Mirra CMP polisher on a Dow VP6000 pad with a downforce of 2 psi and a flow rate of 175 mL / min. After approximately 50 seconds and 20 seconds of overpolishing, the wafer was tip-to-tip by laser measurement.

[0066] [Table 6]

[0067] As shown in Table 6, the addition of anionic dishing reducing polymers is effective in controlling oxide dishing, especially for small features. Sample 6A did not contain a dishing reducing agent, while Samples 6B, 6C, and 6D contained three different types of dishing reducing agents. As can be seen from Table 6, the silicon oxide dishing values ​​for both 5 μm and 20 μm features are much smaller for Samples 6B, 6C, and 6D when compared to Sample 6A.

[0068] Example 7: Demonstration of concentrates In this example, the polishing compositions used in Samples 7A-7C contained concentrates corresponding to point-of-use formulations of 3 w / w% neutral colloidal silica abrasive, organic acid and / or potassium hydroxide as pH adjusters, n-octadecylphosphonic acid, and water as the liquid carrier. The single-pot solutions contained all the ingredients required for polishing, while the two-part systems contained all the ingredients except the organic acid. Mean particle size (MPS) is a reliable indicator of slurry stability. In an unstable system, particles will aggregate over time, causing measurable MPS growth. MPS was measured on a Malvern tool using dynamic light scattering. The slurries were stored in an oven set at 60°C and measured every 7 days. According to the Arrhenius relationship for accelerated aging testing, a full test run of 21 days corresponds to roughly 1 year of room temperature aging. In other words, if the slurry is kept at 60°C for 21 days and the MPS of the silica does not grow significantly, it can be proven that the slurry has a real-time shelf life / expiration date of 1 year.

[0069] [Table 7]

[0070] As shown in Table 7, all formulations are stable throughout the complete test run. Stability in the acidic range of neutral silica is typically difficult to achieve. Single pot solutions were stable at pH from about 2 to about 6.5 at 2x concentration (selected data shown in Table 7) and other concentration levels (e.g., 3x, 4x and up to 10x concentrations) (not shown). In the two-part solution (7C), all components except the acid were concentrated to a much higher degree and remained stable (up to 10x). At the point of use, acid and water are added to reconstitute the slurry before pouring it on the abrasive tool.

[0071] Example 8: Demonstration of patterned wafer removal rate selectivity In this example, the polishing compositions used for Samples 8A, 8B, and 8C containing colloidal silica abrasives and nitride removal rate reducers shown in Tables 1, 3, and 5 were used to polish 200 mm STI patterned wafers in which the patterned silicon nitride was filled with high density silicon oxide, as shown in Figure 2. The patterns in the silicon nitride were arrays of wide line spaces, squares, checkers, and mesh arrays of varying density distributed across the entire wafer surface. It was like being lined up.

[0072] Polishing was performed on an Applied Materials 200mm Mirra polishing tool equipped with a DowDupont VP6000 pad, 3M A165 CIP1 conditioning disk, and employing 2 PSI wafer back pressure. Polishing time was varied based on in situ endpoint detection by both motor torque and red laser (650 nm) absorbance. During polishing, both features of the endpoint signal indicating removal of silicon oxide in the active lines of the film stack and exposure of the underlying silicon nitride can be observed. The patterned silicon oxide removal rate was calculated based on the amount of material removed prior to silicon nitride exposure divided by the polishing time. Conversely, the patterned silicon nitride removal rate is calculated by the amount of material removed divided by the time after exposure to the polishing composition. Once polishing was completed, the wafers were cleaned via a 200mm OnTrack post-CMP cleaning tool (from Lam Research) using Fujifilm Wako 8901 post-CMP cleaning chemistry. All wafer film thickness measurements (eg, to determine removal rate) were taken using a KLA Tencor F5X ellipsometer.

[0073] [Table 8]

[0074] From the data presented in Table 8, the high selectivity between silicon oxide and silicon nitride material removal rates previously observed on blanket wafers is also observed on patterned wafers containing both silicon oxide (top) and silicon nitride (bottom). As can be seen from Table 8, for sample 8A, the selectivity from silicon oxide to silicon nitride varies across the board from 86 to 190 depending on the size, density and pitch of the pattern. For sample 8B, the selectivity of silicon oxide to silicon nitride is 54, whereas for sample 8C, the selectivity is 4. Table 8 provides only a representative example of performance on patterned wafers. In our in-house experiments, we observed that the selectivity ratio varies from 3 (considered satisfactory for patterned wafers) to about 1000 on patterned test wafers depending on the complexity of the film. Moreover, the selectivity of the polishing composition containing the nitride removal rate reducer presented herein exceeds that of many legacy, industry standard, commercially available ceria-based STI polishing compositions presented in the prior art.

[0075] Example 9: Demonstration of dishing and erosion of patterned wafers In this example, patterned wafers similar to those used in Example 8 were measured on a Park Systems AFM tool to quantify the silicon oxide dishing / step height and silicon nitride erosion / loss at the endpoint. The polishing compositions used for Samples 9A and 9B contained the nitride removal rate reducers shown in Tables 1, 3, and 5 and were used to polish the patterned wafers whose stacks are depicted in FIG. 2. The silicon oxide dishing / step height and silicon nitride erosion / loss results are shown in Table 9. Planarization efficiency (PE) is reported as a percentage and is equal to the change in silicon oxide step height divided by the amount of oxide removed during polishing, then multiplied by 100 (to convert to a percentage).

[0076] [Table 9]

[0077] As can be seen from Table 9, silicon oxide dishing and silicon nitride erosion are very small. Typically, very low numbers are preferred for dishing and erosion. The dishing and erosion numbers represent the flatness of the final topography after CMP polishing of the patterned wafer. Thus, low values ​​of these numbers (in Å) are desirable since these numbers measure the separation at the peaks and valleys of the film on the wafer containing multiple film types in the patterned wafer. The lower the number, the less separation there is between the peaks and troughs, meaning a flatter wafer surface, which is the overall goal of the CMP process step in semiconductor manufacturing. Ideally, zero dishing and erosion values ​​are preferred (meaning a perfectly flat wafer surface). However, conventionally, these numbers are generally at values ​​of hundreds or thousands of Å on actual device / product patterned wafers. Thus, the data shown in Table 9 shows that the polishing composition provides unique / extraordinary performance in providing very low dishing and erosion values ​​and therefore very good topography of the patterned wafer. As can be seen from Table 9, silicon oxide dishing can be as low as 35 Å and as high as 375 Å. SiN erosion is much better than dishing, with erosion numbers as low as 30 Å and as high as 74 Å. Again, these are representative examples, and in our experiments we have seen dishing and erosion numbers as high as 1000 Å and as low as 1 Å. This is still satisfactory for the purposes of this invention and acceptable to semiconductor manufacturers.

[0078] For planarization efficiency (PE), the higher the number, the better. Ideally, a PE of 100% is desired, meaning that the entire wafer is planarized and flat, i.e., there are no steps between the peaks and valleys. From the data in Table 9, it can be seen that the PE varies from a low of 14% all the way up to 74%. Thus, these polishing compositions provide good planarization efficiency on patterned wafers.

[0079] Furthermore, the data presented in Table 9 show that the polishing compositions presented herein exceed the oxide dishing, silicon nitride erosion and planarization efficiency of state-of-the-art commercially available ceria-based STI polishing compositions.

[0080] Example 10: Demonstration of Defectivity of Patterned Wafers After Polishing In this example, defects of patterned wafers similar to those used in Examples 8 and 9 were measured on a KLA-AIT XUV defect counter tool by using a commercial ceria-based STI formulation and composition 8A (which is a silica-based polishing composition containing a nitride removal rate reducer) described in Example 8. The wafer map for the wafer polished by using composition 8A is shown in Figure 3. The wafer map of the wafer polished using a commercial ceria-based STI polishing composition is shown in Figure 4.

[0081] As demonstrated by FIG. 4, the ceria-based formulation was prone to heavy arc scratches with many defects spreading across the wafer due to the relative hardness and size of the abrasives (total defect count was greater than 10,000). Closer inspection of the defects showed the presence of many macro- and micro-scratches with many residues, many of which could be considered global device killer defects. However, FIG. 3 shows that polishing composition 8A, which contains high purity colloidal silica as the abrasive, has much fewer scratches than the ceria-based composition (FIG. 4). In fact, the silica polishing composition is close to "defect free" and shows a clean surface. The total defect count is about 175 for defects at least 90 nm in size. Defects are important to the final device yield, and to the production of saleable chips. In the patterned wafer shown in FIG. 4, assume that there are 1000 dies (each square) per patterned wafer. Each of the dies with defects may prove unsalable if the defect is a device killer defect. Thus, the ceria-based polishing composition exhibits a high amount of defects, resulting in a low yield of saleable chips per wafer. Conversely, the polishing composition of the present disclosure exhibits significantly fewer defects, and therefore a significantly higher yield of saleable chips per wafer.

[0082] Therefore, the low defectivity obtained by using the polishing composition of the present disclosure is very attractive to semiconductor companies because it increases their top-line and bottom-line revenue. From a technical point of view, ceria abrasives are inorganic in nature (e.g., cerium lanthanide metal-based oxides), generally hard, and larger in size than silica abrasives, so they tend to give a large amount of scratches and defects to the wafer surface. Conversely, colloidal silica abrasives are organic in nature (silicon non-metal-based oxides and colloidal dispersion forms), generally soft, and therefore do not produce scratches or defects during polishing.

[0083] Those skilled in the art have been unable to develop a silica-based STI polishing composition with sufficient removal selectivity of silicon oxide over silicon nitride.As disclosed herein, the present inventors have found a synergistic combination of silica and silicon nitride removal rate reducer that can provide silica-based STI polishing compositions to industry.In addition, the invention described in this disclosure can be applied to abrasives other than silica (alumina, titania, etc.).

[0084] While the present disclosure has been described with reference to the examples set forth herein, the appended claims are intended to provide It will be understood that other modifications and variations are possible without departing from the spirit and scope of the present disclosure as defined. The present disclosure relates to the following aspects: <1> ~ <24> Also includes. <1> At least one abrasive; C 12 From C 40 at least one nitride removal rate reducer comprising a hydrophobic portion comprising a hydrocarbon group and a hydrophilic portion, said hydrophobic portion and said hydrophilic portion being separated by 0 to 10 alkylene oxide groups; Acid or base; and water; and having a pH of about 2 to about 6.5, and having a ratio of silicon oxide removal rate to silicon nitride removal rate of at least about 3:1 when polishing a patterned wafer comprising at least a silicon nitride pattern covered with at least a silicon oxide. <2> The hydrophobic portion is C 14 From C 32 containing a hydrocarbon group of <1> The polishing composition according to claim 1 . <3> The hydrophobic portion is C 16 From C 22 containing a hydrocarbon group of <1> The polishing composition according to claim 1 . <4> The hydrophilic moiety comprises at least one group selected from the group consisting of a sulfite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group; <1> The polishing composition according to claim 1 . <5> the hydrophilic moiety comprises a phosphate or phosphonate group; <1> The polishing composition according to claim 1 . <6> the at least one nitride removal rate reducer is selected from the group consisting of naphthalenesulfonic acid-formalin condensates, lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecylphosphonic acid, oleyl phosphate, behenyl phosphate, octadecyl sulfate, russyl phosphate, oleyl-3-phosphate, and oleyl-10-phosphate; <1> The polishing composition according to claim 1 . <7> The at least one abrasive is selected from the group consisting of alumina, silica, titania, ceria, zirconia, co-formed products thereof, coated abrasives, surface-modified abrasives, and mixtures thereof. <1> The polishing composition according to claim 1 . <8> the at least one abrasive is selected from the group consisting of cationic abrasives, essentially neutral abrasives, and anionic abrasives; <1> The polishing composition according to claim 1 . <9> The abrasive is a silica-based abrasive. <1> The polishing composition according to claim 1 . <10> further comprising at least one dishing reducing agent; the at least one dishing reducing agent is a compound comprising at least one group selected from the group consisting of a hydroxyl group, a sulfate group, a phosphonate group, a phosphate group, a sulfonate group, an amine group, a nitrate group, a nitrite group, a carboxylate group, and a carbonate group; <1> The polishing composition according to claim 1 . <11> The at least one dishing reducing agent is at least one selected from the group consisting of polysaccharides and substituted polysaccharides; <10> The polishing composition according to claim 1 . <12> When polishing a patterned wafer including at least a silicon nitride pattern covered with at least a silicon oxide layer, the polishing composition has a ratio of silicon oxide removal rate to silicon nitride removal rate of at least about 4:1. <1> The polishing composition according to claim 1 . <13> a silicon oxide to silicon nitride removal rate selectivity of at least about 5:1 and at most about 1000:1; <1> The polishing composition according to claim 1 . <14> The composition has a silicon oxide dishing of at most about 1000 Å and at least about 0 Å. <1> The polishing composition according to claim 1 . <15> The composition has a silicon oxide dishing of at most about 375 Å. <1> The polishing composition according to claim 1 . <16> The composition has a silicon nitride erosion of at most about 500 Å and at least about 0 Å. <1> The polishing composition according to claim 1 . <17> The composition has a silicon nitride erosion of at most about 75 Å. <1> The polishing composition according to claim 1 . <18> The composition has a planarization efficiency of at least about 14%. <1> The polishing composition according to claim 1 . <19> The composition has a planarization efficiency of at least about 14% and at most 100%. <1> The polishing composition according to claim 1 . <20> when the composition is used to polish a patterned wafer, the composition produces at most 175 defects on a patterned wafer having a diameter of about 300 mm. <1> The polishing composition according to claim 1 . <21> on a surface of a substrate having at least silicon nitride and at least silicon oxide, <1> applying the polishing composition according to contacting a pad with a surface of the substrate and moving the pad relative to the substrate. <22> At least one of the silicon nitride and the silicon oxide is doped with at least one dopant selected from the group consisting of carbon, nitrogen, oxygen, and hydrogen. <21> The method described above. <23> forming a semiconductor device from the substrate. <21> The method described above. <24> forming a semiconductor device from the substrate. <22> The method described above.

Claims

1. at least one abrasive; C １２ From C ４０ at least one nitride removal rate reducer comprising a hydrophobic portion comprising a hydrocarbon group and a hydrophilic portion, said hydrophobic portion and said hydrophilic portion being separated by 0 to 10 alkylene oxide groups; an acid or base; and water; and having a pH of about 2 to about 6.5 and a ratio of silicon oxide removal rate to silicon nitride removal rate of at least about 3:1 when polishing a patterned wafer comprising at least a silicon nitride pattern covered with at least a silicon oxide.

2. The hydrophobic portion is C １４ From C ３２ The polishing composition of claim 1 , comprising a hydrocarbon group of the formula:

3. The hydrophobic portion is C １６ From C ２２ The polishing composition of claim 1 , comprising a hydrocarbon group of the formula:

4. 2. The polishing composition of claim 1, wherein the hydrophilic portion comprises at least one group selected from the group consisting of a sulfite group, a sulfate group, a sulfonate group, a carboxylate group, a phosphate group, and a phosphonate group.

5. The polishing composition of claim 1 , wherein the hydrophilic portion comprises a phosphate or phosphonate group.

6. 2. The polishing composition of claim 1, wherein the at least one nitride removal rate reducing agent is selected from the group consisting of naphthalenesulfonic acid-formalin condensates, lauryl phosphate, myristyl phosphate, stearyl phosphate, octadecylphosphonic acid, oleyl phosphate, behenyl phosphate, octadecyl sulfate, russyl phosphate, ole ...

7. 2. The polishing composition of claim 1, wherein the at least one abrasive is selected from the group consisting of alumina, silica, titania, ceria, zirconia, co-formed products thereof, coated abrasives, surface-modified abrasives, and mixtures thereof.

8. 10. The polishing composition of claim 1, wherein the at least one abrasive is selected from the group consisting of cationic abrasives, essentially neutral abrasives, and anionic abrasives.

9. The polishing composition of claim 1 , wherein the abrasive is a silica-based abrasive.

10. further comprising at least one dishing reducing agent; 2. The polishing composition of claim 1, wherein the at least one dishing reducing agent is a compound containing at least one group selected from the group consisting of a hydroxyl group, a sulfate group, a phosphonate group, a phosphate group, a sulfonate group, an amine group, a nitrate group, a nitrite group, a carboxylate group, and a carbonate group.

11. The polishing composition of claim 10 , wherein the at least one dishing reducing agent is at least one selected from the group consisting of polysaccharides and substituted polysaccharides.

12. A patterned wafer including at least a silicon nitride pattern covered with at least a silicon oxide layer.

10. The polishing composition of claim 1, wherein when polishing a har, the polishing composition has a ratio of silicon oxide removal rate to silicon nitride removal rate of at least about 4:

1.

13. 2. The polishing composition of claim 1, wherein the selectivity of removal rate of silicon oxide to silicon nitride is at least about 5:1 and at most about 1000:

1.

14. 2. The polishing composition of claim 1, wherein the composition has a silicon oxide dishing of at most about 1000 Å and at least about 0 Å.

15. 10. The polishing composition of claim 1, wherein the composition has at most about 375 Å of silicon oxide dishing.

16. 2. The polishing composition of claim 1, wherein the composition has a silicon nitride erosion of at most about 500 Å and at least about 0 Å.

17. 10. The polishing composition of claim 1, wherein the composition has an erosion of silicon nitride of at most about 75 Å.

18. 10. The polishing composition of claim 1, wherein the composition has a planarization efficiency of at least about 14%.

19. 10. The polishing composition of claim 1, wherein the composition has a planarization efficiency of at least about 14% and at most 100%.

20. 10. The polishing composition of claim 1, wherein when the composition is used to polish a patterned wafer, the composition produces at most 175 defects on a patterned wafer having a diameter of about 300 mm.

21. 13. Applying the polishing composition of claim 1 onto a surface of a substrate having at least silicon nitride and at least silicon oxide; contacting a pad with a surface of the substrate and moving the pad relative to the substrate.

22. 22. The method of claim 21, wherein at least one of the silicon nitride and the silicon oxide is doped with at least one dopant selected from the group consisting of carbon, nitrogen, oxygen, and hydrogen.

23. The method of claim 21 , further comprising forming a semiconductor device from the substrate.

24. The method of claim 22 further comprising forming a semiconductor device from the substrate.

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