Semiconductor device

Abstract

To provide a semiconductor device that can be of a small size in a configuration that makes an electric connection between a semiconductor chip provided on a conductive substrate and a printed board.SOLUTION: A semiconductor device comprises: a conductive substrate 1a; a plurality of semiconductor chips provided on the conductive substrate 1a; a printed board which has a first conductive layer 12f provided on the conductive substrate 1a, an insulation layer 11 provided on the first conductive layer 12f, and a second conductive layer 12a provided on the insulation layer 11 and electrically connected to first electrodes of the plurality of semiconductor chips; and a first external terminal 4a which is provided on the second conductive layer 12a and extends above the second conductive layer 12a.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device (power semiconductor module) mounted with a power semiconductor element.

Background Art

[0002] Patent Document 1 and Patent Document 2 each disclose a configuration in which a gate layer is disposed via an insulating layer on a main surface metal layer, and a gate terminal is connected to the gate layer via a bonding wire. Patent Document 3 discloses a configuration in which an insulating circuit board includes a ceramic substrate and a circuit layer formed on one surface of the ceramic substrate, and the circuit layer has a laminated structure having a first circuit layer joined to one surface of the ceramic substrate and a second circuit layer joined to the surface of the first circuit layer.

[0003] Patent Document 4 discloses a method in which a bonding material is sandwiched and disposed between each of both surfaces of a ceramic base material and metal plates having the same shape and the same thickness made of the same material, and after joining these laminates by pressurizing and heating them in the lamination direction, the laminate is cooled to form symmetrically shaped circuit layers and metal layers via the ceramic base material. Patent Document 5 discloses an insulating circuit board in which a circuit layer having a circuit pattern formed on one surface of a ceramic substrate is joined, and a metal layer is joined to the other surface, and the circuit layer has a first circuit layer joined to the ceramic substrate and a second circuit layer joined to the upper surface of the first circuit layer, and the metal layer has a first metal layer joined to the ceramic substrate and a second metal layer joined to the upper surface of the first metal layer.

[0004] Patent Document 6 discloses a configuration in which a first conductor layer, a first insulating substrate, a second conductor layer, and a second insulating substrate are laminated in this order, and a third conductor layer and a fourth conductor layer are laminated on the second insulating substrate. Patent Document 7 discloses a wiring board including a heat sink, an insulating layer fixed to the heat sink, and a conductive wiring circuit portion fixed to a surface of the insulating layer opposite to the heat sink, the insulating layer including at least one resin layer, and the heat sink and the wiring circuit portion having the same coefficient of thermal expansion and thickness.

[0005] Patent Document 8 discloses a configuration having an insulating substrate, a first heat transfer body and a second heat transfer body disposed on the insulating substrate, a first substrate and a second substrate disposed on the first heat transfer body and the second heat transfer body, and a first signal terminal and a second signal terminal disposed on the first substrate and the second substrate. Patent Document 9 discloses a configuration in which a gate layer is disposed on a conductive plate via a substrate, and a gate terminal is connected to the gate layer via a bonding wire.

[0006] Patent Document 10 discloses a configuration in which a gate wiring layer is disposed on a wiring layer via an insulating plate, and a gate terminal is connected to the gate wiring layer via a wire. Patent Document 11 discloses a configuration in which a gate layer is disposed on a conductive member via an insulating substrate, and a gate terminal is connected to the gate layer via a wire.

[0007] Patent Document 12 discloses a configuration in which a control signal pattern is disposed on a conductor plate via an insulating plate, and a control signal terminal is connected to the control signal pattern via a bonding wire. Patent Document 13 discloses a configuration in which a gate electrode terminal extends below a plurality of chips.

[0008] Patent Document 14 discloses a configuration in which an end portion of a gate terminal and a gate relay layer are connected by a gate wiring. Patent Document 15 discloses a configuration including a control wiring substrate disposed between semiconductor chips and having a gate wiring layer and a source wiring layer, and a gate terminal and the gate wiring layer are connected by a gate wiring.

[0009] Patent Document 16 discloses a configuration including a substrate, a first switching element and a second switching element provided on the substrate, and a conductor line provided on the substrate and connected to a signal terminal of the first switching element. Patent Document 17 discloses a configuration in which a warp is formed in a silicon nitride substrate in a silicon nitride circuit board in which metal plates are joined to both surfaces of the silicon nitride substrate.

[0010] Patent Document 18 and Patent Document 19 each disclose a configuration in which semiconductor chips are arranged on both sides of a printed wiring board. Patent Document 20 discloses a configuration in which a lead pattern is provided on an aluminum plate via an adhesive resin, and an insertion terminal having a press-fit portion is inserted into a through-hole of the lead pattern.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Patent Document 10

Patent Document 11

Patent Document 12

Patent Document 13

Patent Document 14

Patent Document 15

Patent Document 16

Patent Document 17

Patent Document 18

Patent Document 19

Patent Document 20

Summary of the Invention

Problems to be Solved by the Invention

[0012] In a conventional power semiconductor module, when a semiconductor chip is mounted on a conductive substrate and electrical connection between the semiconductor chip and a printed circuit board provided on the conductive substrate is made using a lead frame, bonding wires, etc., the size increases when the printed circuit board and the external terminals are connected by wire bonding or a lead frame.

[0013] In view of the above problems, an object of the present disclosure is to provide a semiconductor device capable of reducing the size in a configuration for making an electrical connection between a semiconductor chip provided on a conductive substrate and a printed circuit board.

Means for Solving the Problems

[0014] One embodiment of the present invention is a semiconductor device including a conductive substrate, a plurality of semiconductor chips having first electrodes and provided on the conductive substrate, a first conductive layer provided on the conductive substrate, an insulating layer provided on the first conductive layer, and a second conductive layer provided on the insulating layer and electrically connected to the first electrodes of the plurality of semiconductor chips, and a first external terminal provided on the second conductive layer and extending above the second conductive layer.

[0015] The semiconductor device may include a support portion provided on the second conductive layer, and an extension portion supported by the support portion and extending above the second conductive layer as the first external terminal.

[0016] The semiconductor device may have a support portion with an opening, and an end portion of the extending portion may be press-fitted into the opening.

[0017] The semiconductor device may have a planar pattern in which an insulating layer includes a first region extending in one direction between a plurality of semiconductor chips and a second region extending in a direction orthogonal to the first region.

[0018] The semiconductor device may have a second conductive layer provided across the first region and the second region.

[0019] The semiconductor device may have a plurality of second conductive layers provided side by side on the second region, and a first external terminal provided on each of the plurality of second conductive layers, and the plurality of first external terminals may form a column.

[0020] The semiconductor device may further include a plurality of semiconductor chips each having a second electrode, a sealing resin that seals the plurality of semiconductor chips, and a second external terminal electrically connected to the second electrodes of the plurality of semiconductor chips, and a part of the first external terminal may protrude from the upper surface of the sealing resin, and a part of the second external terminal may protrude from the side surface of the sealing resin.

[0021] Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, sub-combinations of these feature groups may also be inventions.

Advantages of the Invention

[0022] According to the present disclosure, a semiconductor device capable of reducing the size can be provided in a configuration for electrically connecting a semiconductor chip provided on a conductive substrate and a printed circuit board.

Brief Description of the Drawings

[0023]

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Embodiments for Carrying Out the Invention

[0024] Hereinafter, the first and second embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Also, it goes without saying that there are portions where the dimensional relationships and ratios are different between the drawings.

[0025] In addition, the definitions of directions such as "upper", "lower", "vertical", "left", "right", "horizontal", etc. in the following description are merely definitions for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated 90° and observed, "vertical" is read as "horizontal", and if it is rotated 180° and observed, "vertical" is read in the reverse. Also, "upper surface" and "lower surface" may be read as "front surface" and "back surface" respectively. Also, the "first main surface" and the "second main surface" of each member are main surfaces facing each other. For example, if the "first main surface" is the upper surface, the "second main surface" is the lower surface.

[0026] (First Embodiment) <Structure of Semiconductor Device> FIG. 1 is a perspective view of a semiconductor device (power semiconductor module) according to the first embodiment, and FIG. 2 is a plan view of the semiconductor device according to the first embodiment. As shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment includes a sealing resin 10 that seals a power semiconductor element (semiconductor chip), and a second external terminal (negative terminal) 2a, a second external terminal (positive terminal) 2b, a second external terminal (output terminal) 2c, and first external terminals (control terminals) 4a to 4g that respectively protrude from the sealing resin 10.

[0027] The encapsulating resin 10 has a substantially rectangular parallelepiped shape. The negative terminal 2a and the positive terminal 2b protrude from a side surface which is a common surface of the substantially rectangular parallelepiped shape of the encapsulating resin 10. The output terminal 2c protrudes from a side surface which is a surface opposite to the surface from which the negative terminal 2a and the positive terminal 2b of the substantially rectangular parallelepiped shape of the encapsulating resin 10 protrude. The control terminals 4a to 4g protrude from an upper surface which is a surface between the surface from which the negative terminal 2a and the positive terminal 2b of the substantially rectangular parallelepiped shape of the encapsulating resin 10 protrude and the surface from which the output terminal 2c protrudes.

[0028] The encapsulating resin 10 is made of an insulating resin such as an epoxy resin. The output terminal 2c, the positive terminal 2b, the negative terminal 2a, and the control terminals 4a to 4g are made of a conductive material such as copper (Cu), a Cu alloy, aluminum (Al), or an Al alloy.

[0029] FIG. 3 is a perspective view of a semiconductor device according to the first embodiment in which the encapsulating resin 10 shown in FIGS. 1 and 2 is omitted. FIG. 4 is a plan view corresponding to FIG. 3, FIG. 5 is a side view corresponding to FIG. 3, and FIG. 6 is an enlarged side view of region A in FIG. 5.

[0030] As shown in FIGS. 3 to 6, the semiconductor device according to the first embodiment includes conductive substrates 1a and 1b that are arranged apart from each other. The conductive substrates 1a and 1b have a substantially rectangular planar pattern. The conductive substrates 1a and 1b are made of a conductive material such as copper (Cu) or aluminum (Al). The lower surfaces of the conductive substrates 1a and 1b are exposed from the encapsulating resin 10 shown in FIGS. 1 and 2.

[0031] The output terminal 2c has a flat plate shape that bends in an L shape and is joined to the conductive substrate 1a via a joining material such as solder or a sintering material, or by direct joining. The positive terminal 2b has a flat plate shape that bends in an L shape and is joined to the conductive substrate 1b via a joining material such as solder or a sintering material, or by direct joining. The negative terminal 2a is arranged side by side with the positive terminal 2b and has an external connection portion 24 with a flat plate shape that bends in an L shape. The negative terminal 2a extends toward the output terminal 2c side and is provided so as to span the conductive substrate 1a and the conductive substrate 1b. The control terminals 4a to 4g are provided so as to extend parallel to each other in a direction perpendicular to the upper surfaces of the conductive substrate 1a and the conductive substrate 1b.

[0032] Although not shown in FIGS. 3 and 4, a conductive member 6 (also referred to as an "intermediate clip" or a "lead frame") shown in FIG. 11 is provided between the negative terminal 2a, the conductive substrate 1a, and the conductive substrate 1b. The conductive member 6 is provided so as to face a part of the negative terminal 2a and be separated from the negative terminal 2a. A part of the negative terminal 2a and a part of the conductive member 6 are covered with a resin member 8.

[0033] The negative terminal 2a, the conductive member 6, and the resin member 8 are integrally formed by integral molding or the like to form an integrated structure (2a, 6, 8). A part of the resin member 8 is provided so as to be sandwiched between the negative terminal 2a and the conductive member 6. By integrally forming the negative terminal 2a, the conductive member 6, and the resin member 8 and maintaining the gap between the negative terminal 2a and the conductive member 6 by the resin member 8, low inductance, ensuring insulation characteristics, and void management (evaluation) are made possible. Further, by making the negative terminal 2a, the conductive member 6, and the resin member 8 into one part, an increase in cost due to complication of jigs and lead frames can be suppressed, leading to a reduction in man-hours. The structures of the negative terminal 2a, the conductive member 6, and the resin member 8 will be described later.

[0034] FIG. 7 is a perspective view in which the sealing resin 10 of the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 is omitted, and further, the integrated structure (2a, 6, 8) composed of the negative terminal 2a, the conductive member 6, and the resin member 8 is omitted, and FIG. 8 is a plan view corresponding to FIG. 7.

[0035] As shown in FIGS. 7 and 8, the semiconductor device according to the first embodiment includes a plurality (six) of power semiconductor elements (semiconductor chips) 3a to 3f disposed on the upper surface side of the conductive substrate 1a, and a plurality (six) of power semiconductor elements (semiconductor chips) 3g to 3l disposed on the upper surface side of the conductive substrate 1b. The semiconductor chips 3a to 3f are joined on the conductive substrate 1a via a joining material such as solder or a sintered material. The semiconductor chips 3a to 3f are arranged in parallel on the conductive substrate 1a so as to form first and second columns. The semiconductor chips 3g to 3l are joined on the conductive substrate 1b via a joining material such as solder or a sintered material. The semiconductor chips 3g to 3l are arranged in parallel on the conductive substrate 1b so as to form first and second columns.

[0036] In the semiconductor device according to the first embodiment, a MOSFET is exemplified as the semiconductor chips 3a to 3l, and a 2-in-1 type power semiconductor module in which six MOSFETs are connected in parallel and two pairs are connected in series is exemplified. The semiconductor chips 3a to 3f constitute the lower arm of a half-bridge circuit for one phase of a three-phase inverter circuit, and the semiconductor chips 3g to 3l constitute the upper arm. Note that the semiconductor device according to the first embodiment is not limited to a 2-in-1 type semiconductor module, and may be, for example, a 6-in-1 type semiconductor module.

[0037] The semiconductor chips 3a to 3l have a semiconductor substrate, a first main electrode (drain electrode) provided on the lower surface side of the semiconductor substrate, and second main electrodes (source electrodes) 31a to 31l and a control electrode (gate electrode) provided on the upper surface side of the semiconductor substrate. The respective drain electrodes of the semiconductor chips 3a to 3f are electrically connected to the conductive substrate 1a. The respective drain electrodes of the semiconductor chips 3g to 3l are electrically connected to the conductive substrate 1b.

[0038] The semiconductor substrates of the semiconductor chips 3a to 3l are, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3) It is composed of etc. The arrangement positions and numbers of the semiconductor chips 3a to 3l are not particularly limited. In addition to field effect transistors (FETs) such as MOSFETs, the semiconductor chips 3a to 3l may also be insulated gate bipolar transistors (IGBTs), reverse conducting insulated gate bipolar transistors (RC-IGBTs) in which a diode is connected in anti-parallel to an IGBT, static induction (SI) thyristors, gate turn-off (GTO) thyristors, etc.

[0039] On the upper surface side of the conductive substrate 1a, printed circuit boards (11, 12a to 12f) for control wiring are arranged. This printed circuit board is also referred to as a control wiring board. The printed circuit boards (11, 12a to 12f) include an insulating layer 11, conductive layers 12a to 12e arranged separately from each other on the upper surface side of the insulating layer 11, and a conductive layer 12f (see FIG. 9) having a width narrower than that of the insulating layer 11 on the lower surface side of the insulating layer 11.

[0040] The insulating layer 11 includes a first region extending in one direction (the vertical direction in FIG. 8) between the semiconductor chips 3a to 3f and a second region extending in a direction orthogonal to the first region (the left-right direction in FIG. 8). In FIGS. 7 and 8, the case where the insulating layer 11 has a T-shaped planar pattern is illustrated, but it is not limited thereto. For example, the insulating layer 11 may have an L-shaped planar pattern. The conductive layers 12a to 12e are provided in a row on the second region of the insulating layer 11. The conductive layers 12a and 12b are provided across the first region and the second region of the insulating layer 11. The control terminals 4a to 4d are provided in a row on the conductive layers 12a to 12d.

[0041] The insulating layer 11 is, for example, a ceramic plate mainly composed of aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), boron nitride (BN), etc., or a resin insulating layer using a polymer material or the like. The resin insulating layer may be a layer in which glass fibers are impregnated with an epoxy resin. The conductive layers 12a to 12f are composed of, for example, copper (Cu), aluminum (Al), etc.

[0042] FIG. 9 is a cross-sectional view of a printed circuit board (11, 12a to 12f) disposed between semiconductor chips 3b and 3e of the mounting structure of the semiconductor device of FIGS. 7 and 8. The semiconductor chip 3b is joined to the upper surface side of the conductive substrate 1a via a joining material 98a. The semiconductor chip 3e is joined to the upper surface side of the conductive substrate 1a via a joining material 98b. The conductive layer 12f of the printed circuit board (11, 12a to 12f) is joined to the upper surface side of the conductive substrate 1a via a joining material 98c. As the joining materials 98a to 98c, solder or a sintered material can be used.

[0043] Since the conductive layer 12f is narrower than the insulating layer 11, as shown by the broken line, it is possible to ensure a long creepage distance from the end of the conductive layer 12f to the ends of the conductive layers 12a and 12b via the lower surface, side surface, and upper surface of the end of the insulating layer 11. That is, since the lower surface and the upper surface of the end of the insulating layer 11 overlap, the distance between the semiconductor chip 3b and the semiconductor chip 3e can be made shorter than when the insulating layer 11 is directly disposed on the upper surface of the conductive substrate 1a. Since the cross-section of the printed circuit board (13, 14a, 14b) between the semiconductor chips 3h and 3k shown in FIGS. 7 and 8 is the same, the overlapping description is omitted. Although not shown, on the lower surface side of the insulating layer 13 of the printed circuit board (13, 14a, 14b), a conductive layer narrower than the insulating layer 13, similar to the conductive layer 12f of the printed circuit board (11, 12a to 12f), is disposed.

[0044] The insulating layer 11 and the conductive layer 12a are provided so as to extend from the end of the conductive substrate 1a between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f. The wide regions of the conductive layer 12a and the conductive layer 12b are alternately arranged. The wide region of the conductive layer 12a is electrically connected to a part of each of the source electrodes 31a to 31f of the semiconductor chips 3a to 3f via the control wirings (bonding wires) 72a to 72f. A control terminal 4a is joined to the conductive layer 12a using a joining material such as solder or a sintered material. The control terminal 4a stands upward from the conductive layer 12a and extends in a direction perpendicular to the upper surface of the conductive layer 12a. The control terminal 4a applies a control signal to each of the source electrodes 31a to 31f of the semiconductor chips 3a to 3f via the conductive layer 12a and the bonding wires 72a to 72f.

[0045] The conductive layer 12b is provided so as to extend from the end of the conductive substrate 1a between the semiconductor chips 3a to 3c and the semiconductor chips 3d to 3f in parallel with the conductive layer 12a. The wide region of the conductive layer 12b is electrically connected to each gate electrode (not shown) of the semiconductor chips 3a to 3f via the control wirings (bonding wires) 71a to 71f. A control terminal 4b is joined to the conductive layer 12b using a joining material such as solder or a sintered material. The control terminal 4b stands upward from the conductive layer 12b and extends in a direction perpendicular to the upper surface of the conductive layer 12b. The control terminal 4b is electrically connected to the gate electrodes of the semiconductor chips 3a to 3f via the bonding wires 71a to 71f and the conductive layer 12b. When the semiconductor chips 3a to 3f are turned ON, a voltage is applied to the control terminal 4a, and a voltage obtained by adding a voltage value equal to or higher than the threshold value of the semiconductor chips 3a to 3f to the voltage value of the control terminal 4a is applied to the control terminal 4b.

[0046] A temperature detection chip 5 having two electrodes (not shown) on its surface is joined to the conductive layer 12e using a joining material such as solder or a sintered material.

[0047] The control terminal 4c is joined to the conductive layer 12c using a joining material such as solder or a sintering material. The control terminal 4c stands upward from the conductive layer 12c and extends in a direction perpendicular to the upper surface of the conductive layer 12c. The conductive layer 12c is connected to one electrode of the temperature detection chip 5 via a control wiring (bonding wire) 73a.

[0048] The control terminal 4d is joined to the conductive layer 12d using a joining material such as solder or a sintering material. The control terminal 4d stands upward from the conductive layer 12d and extends in a direction perpendicular to the upper surface of the conductive layer 12d. The conductive layer 12d is connected to the other electrode of the temperature detection chip 5 via a control wiring (bonding wire) 73b.

[0049] The control terminals 4c and 4d transmit the temperature detection signal from the temperature detection chip 5 to the outside via the bonding wires 73a and 73b and the conductive layers 12c and 12d.

[0050] Pad portions 15a to 15c are provided on the upper surface side at a position adjacent to the conductive substrate 1b of the conductive substrate 1a. The pad portions 15a to 15c are joined to the upper surface of the conductive substrate 1a using a joining material such as solder or a sintering material. The pad portions 15a to 15c are made of a conductive material such as copper (Cu) or aluminum (Al), for example. The pad portions 15a to 15c may be integrally formed with the conductive substrate 1a.

[0051] On the upper surface side of the conductive substrate 1b, printed circuit boards (13, 14a to 14c) for control wiring are arranged. The printed circuit boards (13, 14a to 14c) include an insulating layer 13 and conductive layers 14a to 14c that are arranged spaced apart from each other on the upper surface side of the insulating layer 13. The insulating layer 13 can use the same material as the insulating layer 11, and the conductive layers 14a to 14c can use the same material as the conductive layers 12a to 12e.

[0052] The insulating layer 13 includes a first region extending in one direction (the vertical direction in FIG. 8) between the semiconductor chips 3g to 3l, and a second region extending in a direction orthogonal to the first region (the left-right direction in FIG. 8). In FIGS. 7 and 8, the case where the insulating layer 13 has a T-shaped planar pattern is illustrated, but it is not limited thereto. For example, the insulating layer 13 may have an L-shaped planar pattern. The conductive layers 14a to 14c are provided side by side in a row on the second region of the insulating layer 13. The conductive layers 14a and 14b are provided across the first region and the second region of the insulating layer 13. The control terminals 4e to 4g are provided side by side in a row on the conductive layers 14a to 14c.

[0053] The insulating layer 13 and the conductive layer 14a are provided so as to extend between the semiconductor chips 3g to 3i and the semiconductor chips 3j to 3l from the end of the conductive substrate 1b. The wide regions of the conductive layer 14a and the conductive layer 14b are alternately arranged. The wide region of the conductive layer 14a is electrically connected to a part of the source electrodes 31g to 31l of the semiconductor chips 3g to 3l via the control wirings (bonding wires) 71g to 71l. The control terminal 4e is joined to the conductive layer 14a using a joining material such as solder or a sintering material. The control terminal 4e stands upward with respect to the conductive layer 14a and extends in a direction perpendicular to the upper surface of the conductive layer 14a. The control terminal 4e applies a control signal to the source electrodes 31g to 31l of the semiconductor chips 3g to 3l via the conductive layer 14a and the bonding wires 72g to 72l.

[0054] The conductive layer 14b is provided in parallel with the conductive layer 14a so as to extend from the end of the conductive substrate 1b between the semiconductor chips 3g to 3i and the semiconductor chips 3j to 3l. The wide region of the conductive layer 14b is electrically connected to the respective gate electrodes (not shown) of the semiconductor chips 3g to 3l via the control wirings (bonding wires) 71g to 71l. A control terminal 4f is joined to the conductive layer 14b using a joining material such as solder or a sintered material. The control terminal 4f stands upward with respect to the conductive layer 14b and extends in a direction perpendicular to the upper surface of the conductive layer 14b. The control terminal 4f is electrically connected to the gate electrodes of the semiconductor chips 3g to 3l via the bonding wires 71g to 71l and the conductive layer 14b. When the semiconductor chips 3j to 3l are turned ON, a voltage is applied to the control terminal 4e, and a voltage obtained by adding a voltage value equal to or higher than the threshold value of the semiconductor chips 3j to 3l to the voltage value of the control terminal 4e is applied to the control terminal 4f.

[0055] The conductive layer 14c is connected to the conductive substrate 1b via a control wiring (bonding wire) 74. A control terminal 4g is joined to the conductive layer 14c using a joining material such as solder or a sintered material. The control terminal 4g stands upward with respect to the conductive layer 14c and extends in a direction perpendicular to the upper surface of the conductive layer 14c. The control terminal 4g transmits an electric current signal flowing through the drain electrodes of the semiconductor chips 3g to 3l to the outside via the bonding wire 74 and the conductive layer 14c.

[0056] FIG. 10 is a cross-sectional view of the control terminal 4a shown in FIGS. 7 and 8. The control terminal 4a is provided on the upper surface side of the conductive substrate 1a via the conductive layer 12f, the insulating layer 11, and the conductive layer 12a of the printed substrates (11, 12a to 12f). The control terminal 4a includes a support portion 41 and extending portions (42, 43, 44) supported by the support portion 41. The support portion 41 is formed of, for example, a cylindrical sleeve having an opening. The support portion 41 is joined to the conductive layer 12a using a joining material such as solder or a sintered material.

[0057] The extension parts (42, 43, 44) are composed of, for example, press-fit pins. The extension parts (42, 43, 44) include a first end part (lower end part) 42 supported by the support part 41, a central part 43 continuous with the first end part 42, and a second end part (upper end part) 44 continuous with the central part 43. The shape of the first end part 42 is not particularly limited as long as it can be press-fitted into the opening of the support part 41 and fixed. The central part 43 extends in a direction perpendicular to the upper surface of the conductive substrate 1a. The shape of the central part 43 is not particularly limited and may be a flat plate shape, a pin shape, a rod shape, a cylindrical shape, a polygonal prism shape, or the like. The second end part 44 has a wide part that can be press-fitted into the through-hole of the external member. The shape of the second end part 44 is not particularly limited as long as it can be electrically connected to the external member. The control terminals 4b to 4g shown in FIGS. 7 and 8 also have the same configuration as the control terminal 4a shown in FIG. 10.

[0058] FIG. 11 shows a perspective view of the conductive member 6 which is a component of the integrated structure (2a, 6, 8). As shown in FIG. 11, the conductive member 6 includes pad joints 61a to 61c, a connection part 62 connected to the pad joints 61a to 61c, chip joints 63a to 63c connected to the connection part 62, connection parts 64a to 64c connected to the chip joints 63a to 63c, and chip joints 63d to 63f connected to the connection parts 64a to 64c. The pad joints 61a to 61c and the chip joints 63a to 63f are curved and connected so as to protrude downward with respect to the connection part 62 and the connection parts 64a to 64c. The connection parts 64a to 64c have a striped planar pattern that is spaced apart from each other and extends in parallel.

[0059] At least the lower surfaces of the pad joints 61a to 61c are exposed from the resin member 8 shown in FIGS. 3 to 6. The pad joints 61a to 61c are joined to the pad portions 15a to 15c on the upper surface side of the conductive substrate 1a shown in FIGS. 7 and 8 using a joining material such as solder or a sintered material. The connection portions 62 and 64a to 64c are covered with the resin member 8 shown in FIGS. 3 to 6. At least the lower surfaces of the chip joints 63a to 63f are exposed from the resin member 8 shown in FIGS. 3 to 6. The chip joints 63a to 63f are joined to the source electrodes 31g to 31l of the semiconductor chips 3g to 3l shown in FIGS. 7 and 8 using a joining material such as solder or a sintered material.

[0060] FIG. 12 shows a perspective view of the negative electrode terminal 2a which is a component of the integrated structure (2a, 6, 8). As shown in FIG. 12, the negative electrode terminal 2a includes chip joints 21a to 21c, connection portions 22a to 22c connected to the chip joints 21a to 21c, chip joints 21d to 21f connected to the connection portions 22a to 22c, a connection portion 23 connected to the chip joints 21d to 21f, and an external connection portion 24 connected to the connection portion 23. The chip joints 21a to 21f, the connection portions 22a to 22c, and the external connection portion 24 are exposed from the resin member 8 shown in FIGS. 3 to 6. A part of the connection portion 23 is exposed from the resin member 8 shown in FIGS. 3 to 6, and another part of the connection portion 23 is covered with the resin member 8.

[0061] The chip joints 21a to 21f shown in FIG. 12 are curved and connected so as to protrude downward with respect to the connection portions 22a to 22c. The chip joints 21a to 21f are joined to the respective source electrodes 31a to 31f of the semiconductor chips 3a to 3f shown in FIGS. 7 and 8 using a joining material such as solder or a sintered material. The connection portions 22a to 22c have a stripe-shaped planar pattern that is spaced apart from each other and extends in parallel.

[0062] The connection part 23 has a substantially rectangular planar pattern. The connection part 23 is arranged to face the pad joint parts 61a - 61c, the connection part 62, the chip joint parts 63a - 63f, and the connection parts 64a - 64c of the conductive member 6 shown in FIG. 11. In the connection part 23, openings 23a and 23b penetrating from the upper surface to the lower surface of the connection part 23 are provided. The openings 23a and 23b have a substantially rectangular planar pattern. The opening 23a is provided so as to overlap with the space between the connection parts 64a and 64b shown in FIG. 11. The opening 23b is provided so as to overlap with the space between the connection parts 64b and 64c shown in FIG. 11.

[0063] In a plan view, the opening 23a is arranged so as to overlap with the control wiring region including the bonding wires 71h, 71k, 72h, and 72k connected to the semiconductor chips 3h and 3k shown in FIGS. 7 and 8. The opening 23b is arranged so as to overlap with the control wiring region including the bonding wires 71i, 71l, 72i, and 72l connected to the semiconductor chips 3i and 3l shown in FIGS. 7 and 8.

[0064] Note that, among the negative terminal 2a, the part of the external connection part 24 may be defined as the "negative terminal", and the chip joint parts 21a - 21c, the connection parts 22a - 22c, the chip joint parts 21d - 21f, and the connection part 23, which are the parts other than the external connection part 24, may be defined as a "lead frame" integrated with the "negative terminal".

[0065] FIG. 13 shows a perspective view of the resin member 8 which is a component of the integrated structure (2a, 6, 8). As shown in FIG. 13, the resin member 8 includes a main body part 80 having a substantially rectangular parallelepiped shape. On the side surface of the main body part 80, an opening 82 and openings 83a - 83c are provided. A part of the connection part 23 of the negative terminal 2a is exposed from the opening 82. The pad joint parts 61a - 61c of the resin member 8 are exposed from the openings 83a - 83c. In the main body part 80, openings 81a and 81b penetrating from the upper surface to the lower surface of the main body part 80 are provided. The openings 81a and 81b are provided so as to overlap with the openings 23a and 23b of the negative terminal 2a shown in FIG. 12.

[0066] As shown in FIGS. 3 and 4, when the integrated structures (2a, 6, 8) are arranged on the upper surface sides of the conductive substrates 1a and 1b, in a plan view, the opening 81a of the resin member 8 is positioned so as to overlap with a control wiring region including the bonding wires 71h, 71k, 72h, and 72k connected to the semiconductor chips 3h and 3k. The opening 23b is arranged so as to overlap with a control wiring region including the bonding wires 71i, 71l, 72i, and 72l connected to the semiconductor chips 3i and 3l.

[0067] As shown in FIGS. 4 to 6, a support portion 84 and support portions 85a to 85e are provided on the lower surface side of the main body portion 80. In FIG. 4, the support portions 85a to 85e hidden under the main body portion 80 are schematically shown by broken lines. The support portion 84 and the support portions 85a to 85e are integrally formed with the main body portion 80. The support portion 84 is arranged on the upper surface side of the conductive substrate 1a. The support portions 85a to 85e are arranged on the upper surface side of the conductive substrate 1b. The shapes of the support portions 85a to 85e are, for example, columnar, but are not particularly limited. The arrangement positions and the number of the support portions 85a to 85e are not particularly limited.

[0068] By providing the support portion 84 and the support portions 85a to 85e on the lower surface side of the main body portion 80, when soldering the chip bonding portions 21a to 21f of the negative electrode terminal 2a and the chip bonding portions 63a to 63f of the conductive member 6 to the source electrodes of the semiconductor chips 3a to 3l, the inclination of the integrated structures (2a, 6, 8) including the chip bonding portions 21a to 21f and the chip bonding portions 63a to 63f can be suppressed, and the height of the integrated structures (2a, 6, 8) can be controlled.

[0069] The surface of the resin member 8 may be roughened by performing a process for roughening the surface such as embossing. By roughening the surface of the resin member 8, peeling between the resin member 8 and the sealing resin 10 can be prevented, and the adhesion can be improved. The entire surface of the resin member 8 may be roughened, or a part of the surface of the resin member 8 may be partially roughened.

[0070] FIG. 14 is a schematic side view of the mounting structure of the semiconductor device 101 according to the first embodiment. The semiconductor device 101 corresponds to the semiconductor device shown in FIGS. 1 and 2, and the lower surfaces of the conductive substrates 1a and 1b are exposed on the lower surface side of the semiconductor device 101. A cooler (base) 103 is disposed on the lower surface side of the semiconductor device 101 via a sheet-like resin layer (resin sheet) 102.

[0071] The resin sheet 102 has functions of insulating and bonding the semiconductor device 101 and the cooler 103 while ensuring heat dissipation from the semiconductor device 101 to the cooler 103. As the material of the resin sheet 102, for example, an epoxy resin or the like can be used. As the material of the cooler 103, for example, copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), a composite material of magnesium (Mg) and silicon carbide (MgSiC), or the like can be used.

[0072] According to the mounting structure of the semiconductor device 101, compared with the case where an insulating circuit board is joined to a cooler with solder, the functions of insulation, bonding, and heat dissipation can be concentrated on the resin sheet 102, so that costs can be reduced.

[0073] FIG. 15 shows an equivalent circuit of the semiconductor device according to the first embodiment. As shown in FIG. 15, the semiconductor device according to the first embodiment constitutes a part of a three-phase bridge circuit. The drain electrode of the transistor T1 on the upper arm side is connected to the positive terminal P, and the source electrode of the transistor T2 on the lower arm side is connected to the negative terminal N. The source electrode of the transistor T1 and the drain electrode of the transistor T2 are connected to the output terminal U and the auxiliary source terminal S1. An auxiliary source terminal S2 is connected to the source electrode of the transistor T2. Gate control terminals G1 and G2 are connected to the gate electrodes of the transistors T1 and T2. Body diodes D1 and D2 serving as freewheeling diodes (FWD) are connected in anti-parallel and built in the transistors T1 and T2.

[0074] The output terminal U, the positive electrode terminal P, and the negative electrode terminal N shown in FIG. 15 correspond to the output terminal 2c, the positive electrode terminal 2b, and the negative electrode terminal 2a shown in FIGS. 7 and 8. The transistors T1 and body diodes D1 shown in FIG. 15 correspond to the semiconductor chips 3g to 3l shown in FIGS. 7 and 8. The transistors T2 and body diodes D2 shown in FIG. 15 correspond to the semiconductor chips 3a to 3f shown in FIGS. 7 and 8. The gate control terminals G1 and G2 shown in FIG. 15 correspond to the control terminals 4b and 4f shown in FIGS. 7 and 8. The auxiliary source terminals S1 and S2 shown in FIG. 15 correspond to the control terminals 4b, 4f, 4a, and 4e shown in FIGS. 7 and 8.

[0075] Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. As shown in FIGS. 7 and 8, an output terminal 2c, semiconductor chips 3a to 3f, printed boards (11, 12a to 12e), and pad portions 15a to 15c are joined to the upper surface of a conductive substrate 1a using a joining material such as solder or a sintered material. Further, control terminals 4a to 4d and a temperature detection chip 5 are joined to the upper surface of the printed boards (11, 12a to 12e) using a joining material such as solder or a sintered material. At this time, as shown in FIG. 10, a support portion 41 is joined to the upper surface of the conductive layer 12a via a joining material such as solder or a sintered material. Then, by press-fitting the first end portion 42 of the extending portions (42, 43, 44) into the support portion 41, the control terminal 4a is provided so as to stand perpendicular to the upper surface of the conductive layer 12a. The control terminals 4b to 4d are provided in the same manner as the control terminal 4a. Further, gate electrodes (not shown) of the semiconductor chips 3a to 3f and the conductive layer 12b of the printed board 11 are connected to each other using bonding wires 71a to 71f for gate signals, and source electrodes (not shown) of the semiconductor chips 3a to 3f and the conductive layer 12a of the printed board 11 are connected to each other using bonding wires 72a to 72f for auxiliary sources, and one electrode of the temperature detection chip 5 and the conductive layer 12c of the printed board 11 are connected to each other using a bonding wire 73a for temperature signals, and the other electrode of the temperature detection chip 5 and the conductive layer 12d of the printed board 11 are connected to each other using a bonding wire 73b for temperature signals.

[0076] Also, as shown in FIGS. 7 and 8, a positive electrode terminal 2b, semiconductor chips 3g to 3l, and printed circuit boards (13, 14a to 14c) are joined to the upper surface of the conductive substrate 1b using a joining material such as solder or a sintering material. Further, control terminals 4e to 4g are joined to the upper surfaces of the printed circuit boards (13, 14a to 14c) using a joining material such as solder or a sintering material. The control terminals 4e to 4g are also provided so as to stand perpendicular to the upper surfaces of the conductive layers 14a to 14c in the same manner as the control terminal 4a. Further, a gate electrode (not shown) of the semiconductor chips 3g to 3l and the conductive layer 14b of the printed circuit board 13 are connected to each other using bonding wires 71g to 71l for gate signals, and a source electrode (not shown) of the semiconductor chips 3g to 3l and the conductive layer 14a of the printed circuit board 13 are connected to each other using bonding wires 72g to 72l for auxiliary sources. Then, the conductive substrate 1b and the conductive layer 14c of the printed circuit board 13 are connected to each other using a bonding wire 74.

[0077] Also, an integrated structure (2a, 6, 8) is produced by integrally molding the conductive member 6 shown in FIG. 11, the negative electrode terminal 2a shown in FIG. 12, and the resin member 8 shown in FIG. 13 using a mold.

[0078] Next, as shown in FIGS. 3 to 6, the conductive substrate 1a to which semiconductor chips 3a to 3f etc. are joined and the conductive substrate 1b to which semiconductor chips 3g to 3l etc. are joined are opposed to the integrated structure (2a, 6, 8). Then, the chip bonding portions 21a to 21f of the negative electrode terminal 2a of the components of the integrated structure (2a, 6, 8) are joined to the source electrodes 31a to 31f of the semiconductor chips 3a to 3f using a joining material such as solder or a sintering material. Also, the chip bonding portions 63a to 63f of the conductive member 6 of the components of the integrated structure (2a, 6, 8) are joined to the source electrodes 31g to 31l of the semiconductor chips 3g to 3l using a joining material such as solder or a sintering material. Further, the pad bonding portions 61a to 61c of the conductive member 6 are joined to the pad portions 15a to 15c on the upper surface side of the conductive substrate 1a using a joining material such as solder or a sintering material.

[0079] Next, as shown in FIG. 1, semiconductor chips 3a to 3l and the like are encapsulated with an encapsulating resin 10 by a transfer mold. Thus, the semiconductor device according to the first embodiment is completed.

[0080] According to the semiconductor device according to the first embodiment, a negative terminal 2a, a conductive member 6, and a resin member 8 are integrally formed to constitute an integrated structure (2a, 6, 8), the main wiring circuit is three-dimensionally wired, and a printed circuit board (11, 12a to 12e) and a printed circuit board (13, 14a to 14c) for control wiring are used to separate the control wiring circuit onto a separate board.

[0081] Thereby, compared with a conventional semiconductor device in which a semiconductor chip is mounted on a circuit pattern of an insulating circuit board and electrical connection between the semiconductor chip and the circuit pattern of the insulating circuit board is performed using a lead frame, bonding wires, etc., the wiring area can be reduced. Therefore, an increase in chip size and cost can be reduced, and low inductance characteristics can be realized.

[0082] Also, control terminals 4a to 4g are directly provided on the printed circuit boards (11, 12a to 12e) provided on the conductive substrates 1a, 1b and the printed circuit boards (13, 14a to 14c), and the control terminals 4a to 4g are extended above the printed circuit boards (11, 12a to 12e) and the printed circuit boards (13, 14a to 14c). Thereby, compared with the case where the control terminals 4a to 4g are connected to the printed circuit boards (11, 12a to 12e) and the printed circuit boards (13, 14a to 14c) via bonding wires or a lead frame, the size of the semiconductor device can be reduced, and the control terminals 4a to 4g can be firmly joined to the printed circuit boards (11, 12a to 12e) and the printed circuit boards (13, 14a to 14c).

[0083] In addition, compared with a conventional semiconductor device in which a printed circuit board is disposed above a semiconductor chip mounted on an insulating circuit board and the semiconductor chip and the printed circuit board are electrically connected using pin terminals, the reliability of the connection portion can be ensured, inspection becomes easy, and cost reduction can be achieved. Further, there are no problems with warping or thermal deformation of the printed circuit board, mountability and reliability can be ensured, and handling becomes easy.

[0084] In addition, compared with a conventional semiconductor device in which an insulating circuit board is surrounded by a case and resin is injected and sealed by potting, the case becomes unnecessary, and space, man-hours, and cost can be reduced.

[0085] As described above, according to the semiconductor device according to the first embodiment, it is possible to realize a wiring technique that is low-cost and easy to manufacture without using a complicated member position accuracy control technique, maintain heat dissipation characteristics, and realize a low inductance characteristic that maximizes the switching characteristics of a semiconductor chip made of silicon carbide (SiC) or the like. For example, when using a semiconductor chip made of SiC, in order to compress costs, there may be a case where a large number of small chips are connected in parallel. In such a case where a large number of semiconductor chips are mounted, the effect of reducing the wiring area is large, which is particularly effective.

[0086] (Second Embodiment) The semiconductor device according to the second embodiment has the same appearance as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2. FIG. 16 is a perspective view of the semiconductor device according to the second embodiment in which the encapsulating resin 10 shown in FIGS. 1 and 2 is omitted, and FIG. 17 is a plan view corresponding to FIG. 16. The semiconductor device according to the second embodiment includes a printed circuit board similar to the printed circuit board of the semiconductor device according to the first embodiment.

[0087] As shown in FIGS. 16 and 17, the semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that it includes a resin member 9 disposed so as to be sandwiched between a negative electrode terminal 2a and a conductive member 6. In the semiconductor device according to the second embodiment, a laminate structure (2a, 6, 9) in which the negative electrode terminal 2a, the conductive member 6, and the resin member 9 are laminated is configured. The negative electrode terminal 2a and the conductive member 6, which are components of the laminate structure (2a, 6, 9), have the same structures as the negative electrode terminal 2a shown in FIG. 12 and the conductive member 6 shown in FIG. 11, respectively.

[0088] FIG. 18 shows a perspective view of a resin member 9 which is a component of the laminate structure (2a, 6, 9). As shown in FIG. 18, the resin member 9 includes a flat portion 90 and stripe portions 91a to 91c connected to the flat portion 90. The flat portion 90 is disposed between the connection portion 62 of the conductive member 6 shown in FIG. 11 and the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12. A protruding portion 94 is provided on the lower surface side of the flat portion 90. The protruding portion 94 is fitted into pad bonding portions 61a to 61c that curve downward of the conductive member 6 shown in FIG. 11. Note that the protruding portion 94 may not be provided.

[0089] The stripe portion 91a is disposed between the chip bonding portions 63a, the connection portion 64a, and the chip bonding portion 63d of the conductive member 6 shown in FIG. 11 and a stripe portion on the end side rather than the opening 23a of the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12. Protruding portions 95a and 95d are provided on the lower surface side of the stripe portion 91a. The protruding portions 95a and 95d are fitted into the chip bonding portions 63a and 63d that curve downward of the conductive member 6 shown in FIG. 11.

[0090] The stripe portion 91b is disposed between the chip bonding portions 63b, the connection portion 64b, and the chip bonding portion 63e of the conductive member 6 shown in FIG. 11 and a stripe portion between the openings 23a and 23b of the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12. Protruding portions 95b and 95e are provided on the lower surface side of the stripe portion 91b. The protruding portions 95b and 95e are fitted into the chip bonding portions 63b and 63e that curve downward of the conductive member 6 shown in FIG. 11.

[0091] The stripe portion 91c is disposed between the chip bonding portions 63c, the connection portions 64c, the chip bonding portion 63f of the conductive member 6 shown in FIG. 11, and the stripe portion on the end side rather than the opening 23b of the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12. Protrusions 95c and 95f are provided on the lower surface side of the stripe portion 91c. The protrusions 95c and 95f are fitted into the chip bonding portions 63c and 63f that curve downward of the conductive member 6 shown in FIG. 11.

[0092] The space between the stripe portions 91a and 91b is provided so as to overlap with the space between the connection portions 64a and 64b of the conductive member 6 shown in FIG. 11 and the opening 23a of the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12. The space between the stripe portions 91b and 91c is provided so as to overlap with the space between the connection portions 64b and 64c of the conductive member 6 shown in FIG. 11 and the opening 23b of the connection portion 23 of the negative electrode terminal 2a shown in FIG. 12.

[0093] FIG. 19 is a side view of the laminate structure (2a, 6, 9). As shown in FIG. 19, the upper surface sides of the chip bonding portions 63c and 63f of the conductive member 6 are in contact with the protrusions 95c and 95f of the resin member 9. Similarly, the upper surface sides of the chip bonding portions 63a, 63b, 63d, and 63e of the conductive member 6 are in contact with the protrusions 95a, 95b, 95d, and 95e of the resin member 9. Further, as shown in FIG. 19, the upper surface sides of the flat portion 90 and the stripe portion 91c of the resin member 9 are in contact with the lower surface of the connection portion 23 of the negative electrode terminal 2a. Similarly, the upper surface sides of the stripe portions 91a and 91b of the resin member 9 are in contact with the lower surface of the connection portion 23 of the negative electrode terminal 2a.

[0094] FIG. 20 shows an enlarged side view of the region A surrounded by a broken line around the protrusion 95c of the resin member 9 in FIG. 19. Engagement portions (convex portions) 92a and 92b are provided on the side surface of the protrusion 95c of the resin member 9. Engagement portions (concave portions) 65a and 65b are provided on the curved portion of the chip bonding portion 63c of the conductive member 6. By engaging (fitting) the convex portions 92a and 92b of the resin member 9 with the concave portions 65a and 65b of the conductive member 6, the conductive member 6 can be fixed to the resin member 9.

[0095] FIG. 19 shows an example of a method of assembling a laminate structure (2a, 6, 9) in FIG. 21. Prepare a negative electrode terminal 2a, a resin member 9, and a conductive member 6. As shown in FIG. 21, bond (fix) the upper surface of the resin member 9 to the lower surface of the negative electrode terminal 2a by pressure bonding or the like. Next, with the upper surface side of the conductive member 6 facing the lower surface side of the resin member 9 fixed to the negative electrode terminal 2a, fix the upper surface of the conductive member 6 to the lower surface of the resin member 9 by pressure bonding or the like. At this time, by engaging (fitting) the convex portions 92a, 92b of the resin member 9 with the concave portions 65a, 65b of the conductive member 6, the upper surface of the conductive member 6 can be firmly fixed to the lower surface of the resin member 9.

[0096] Other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant descriptions are omitted.

[0097] According to the semiconductor device according to the second embodiment, a laminate structure (2a, 6, 9) is constituted by a negative electrode terminal 2a, a conductive member 6, and a resin member 9 to three-dimensionally wire the main wiring circuit, and a printed circuit board (11, 12a to 12e) and a printed circuit board (13, 14a to 14c) for control wiring are used to separate the control wiring circuit onto a separate board. Thereby, since the wiring area can be reduced, an increase in chip size and cost can be reduced, and low inductance characteristics can be realized.

[0098] FIG. 22 is a perspective view of another example of the conductive member 6 which is a component of the laminate structure (2a, 6, 9). The conductive member 6 shown in FIG. 22 is different from the conductive member 6 shown in FIG. 11 in that it further includes a connection portion 65 connected to the chip bonding portions 63d to 63f. FIG. 23 is a perspective view of another example of the resin member 9 which is a component of the laminate structure (2a, 6, 9). The resin member 9 shown in FIG. 23 is different from the conductive member 6 shown in FIG. 18 in that it further includes a connection portion 97 connected to the stripe portions 91a to 91c. In the semiconductor device according to the second embodiment, the laminate structure (2a, 6, 9) may be constituted by the conductive member 6 shown in FIG. 22, the resin member 9 shown in FIG. 23, and the negative electrode terminal 2a shown in FIG. 12.

[0099] (Other Embodiments) As described above, the present disclosure has been described by the first and second embodiments, but the discussions and drawings that form part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0100] For example, in the first and second embodiments, the case where the conductive substrates 1a and 1b are provided has been illustrated. However, the conductive substrates 1a and 1b may be directly formed by circuit patterns on the upper surface side of an insulating circuit board such as a direct copper bonding (DCB) substrate. When configured with an insulating circuit board, the insulating circuit board may include an insulating substrate such as a ceramic plate, the conductive substrates 1a and 1b provided on the upper surface side of the insulating substrate, and a heat dissipation plate provided on the lower surface side of the insulating substrate.

[0101] In addition, the configurations disclosed in the first and second embodiments can be appropriately combined within a range where no contradiction occurs. Thus, the present disclosure naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention specific matters according to the legitimate claims based on the above description.

Description of Reference Numerals

[0102] 1a, 1b... Conductive substrates 2a... Negative terminal 2b... Positive terminal 2c... Output terminal 3a~3l... Semiconductor chips 4a~4g... Control terminals (first external terminals) 5... Temperature detection chip 6... Conductive member 8, 9... Resin members 10... Encapsulating resin 11... Insulating layer 12a~12e... Conductive layers (second conductive layers) 12f... Conductive layer (first conductive layer) 13... Insulating layer 14a~14c... Conductive layers (second conductive layers) 15a to 15c... Pad portion 21a to 21f... Chip bonding portion 22a to 22c, 23... Connection portion 23a, 23b... Opening portion 24... External connection portion 31a to 31l... Source electrode 41... Support portion 42... First end portion 43... Central portion 44... Second end portion 61a to 61c... Pad bonding portion 62... Connection portion 63a to 63f... Chip bonding portion 64a to 64c... Connection portion 65... Connection portion 65a, 65b... Concave portion 71a to 71l, 72a to 72l, 73a, 73b, 74... Bonding wire 80... Body portion 81a, 81b, 82, 83a to 83c... Opening portion 84... Support portion 85a to 85e... Support portion 90... Flat portion 91a to 91c... Stripe portion 92a, 92b... Convex portion 94, 95a to 95f... Protruding portion 97... Connection portion 98a to 98c... Bonding material 101... Semiconductor device 102... Resin layer (resin sheet) 103... Cooler (base) D1, D2... Body diode G1, G2... Gate control terminal N... Negative terminal (second external terminal) P... Positive terminal (second external terminal) S1, S2... Auxiliary source terminal T1, T2... Transistor U... Output terminal (second external terminal)

Claims

1. A conductive substrate, a plurality of semiconductor chips having a first electrode and provided on the conductive substrate, a printed circuit board having a first conductive layer provided on the conductive substrate, an insulating layer provided on the first conductive layer, and a second conductive layer provided on the insulating layer and electrically connected to the first electrodes of the plurality of semiconductor chips, a first external terminal provided on the second conductive layer and extending above the second conductive layer, A semiconductor device comprising.

2. The first external terminal is, a support portion provided on the second conductive layer, an extension portion supported by the support portion and extending above the second conductive layer, Comprising The semiconductor device according to claim 1.

3. The support portion has an opening, An end portion of the extension portion is press-fitted into the opening The semiconductor device according to claim 2.

4. The insulating layer is, a first region extending in one direction between the plurality of semiconductor chips, a second region extending in a direction orthogonal to the first region, Having a planar pattern comprising The semiconductor device according to claim 1 or 2.

5. The second conductive layer is provided across the first region and the second region. The semiconductor device according to claim 4.

6. A plurality of the second conductive layers are provided side by side on the second region, The first external terminals are respectively provided on the plurality of second conductive layers, and the plurality of first external terminals form a column. The semiconductor device according to claim 4.

7. The plurality of semiconductor chips further have a second electrode, a sealing resin for sealing the plurality of semiconductor chips, a second external terminal electrically connected to the second electrodes of the plurality of semiconductor chips, Further comprising, A part of the first external terminal protrudes from the upper surface of the sealing resin, A part of the second external terminal protrudes from the side surface of the sealing resin. The semiconductor device according to claim 1 or 2.

Images