Magnetic tunneling junction switching with parallel spin-momentum locked spin current

Abstract

To provide methods and apparatuses for magnetic random access memory (MRAM) devices utilizing spin transfer torque.SOLUTION: A device includes a substrate and / or ground layer; a magnetic tunneling junction (MTJ) formed over the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; and a parallel spin-momentum (PSM) layer 201 formed over the free layer of the MTJ. The PSM layer, i.e., a chiral material layer, may be formed adjacent to a free layer or adjacent to a texture breaking layer (TBL), which is adjacent to the free layer of the MTJ, providing an additional source of spin-transfer-torque, and providing MTJ devices that are operable with lower switching current.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to the field of magnetic random access memory (MRAM), and more particularly to MRAM devices that utilize spin transfer torque. [Background technology]

[0002] Magnetic memories such as MRAM store information using magnetic materials as information storage media. For example, magnetic tunneling junctions (MTJs) may be used in MRAMs such as spin-transfer torque MRAM (STT-MRAM). MTJs typically include a reference layer, a free layer, and a tunnel barrier layer between the reference layer and the free layer. The reference layer and the free layer are magnetic layers. The magnetic moment of the reference layer is generally fixed or immobilized in a particular direction. The free layer has a variable magnetic moment and is used to store information. A bottom contact below the MTJ and a top contact above the MTJ are used to drive a current through the MTJ in the current-perpendicular-to-plane (CPP) direction in STT-MRAM. For an MTJ with positive tunnel magnetoresistance (TMR), when sufficient current is driven in one direction perpendicular to the plane (e.g., from top to bottom), the magnetic moment of the free layer switches to be parallel to the magnetic moment of the reference layer. When sufficient current is driven in the opposite direction (e.g., from bottom to top), the magnetic moment of the free layer switches to be antiparallel to the magnetic moment of the reference layer. Different magnetic structures correspond to different magnetoresistances and therefore different logic states of the MTJ (e.g., logic "0" and logic "1").

[0003] More specifically, STT-MRAM changes the magnetic orientation of the free layer by passing a spin-polarized current directly through the MTJ. This gives STT-MRAM scalability, meaning that as the size of the MTJ becomes smaller, the threshold current for state reversal will decrease. This property also gives STT-MRAM a greater tolerance to stray magnetic fields compared to toggling MRAM.

[0004] STT-MRAM has the advantages of lower power consumption and better scalability than conventional MRAM, so it can replace low-density dynamic random access memory (DRAM) and static random access memory (SRAM), for example, in mobile and storage devices. Another advantage of MRAM over DRAM and SRAM is its non-volatility, i.e., MRAM retains written data even in a power-off state.

[0005] However, in an STT-MRAM, when the magnetic layer has a magnetization perpendicular to the layer surface, ie, perpendicular magnetic anisotropy (PMA), a smaller switching current is required than in the case of an in-plane magnetized MTJ.

[0006] Furthermore, for low-power STT-MRAM products capable of operating in the nanosecond regime (eg, 2-50 ns), lower switching currents are required.

[0007] Dual MTJ structures have been proposed to provide an additional source of spin-transfer torque, but they require thicker MTJ stacks, which pose fabrication challenges and require significant improvements in the stability of the top reference layer.

[0008] Furthermore, spin-orbit coupling torque (SOT) assisted STT-MRAM has been proposed, where an additional source of spin torque is provided by SOT material adjacent to the free layer of the MTJ. However, in these prior art techniques, the SOT is generated by an in-plane electrical current flowing through the SOT lines, which extend laterally, and also presents additional fabrication challenges. Summary of the Invention

[0009] Accordingly, one aspect of the present disclosure provides an apparatus and method for obtaining lower switching currents in MTJ devices.

[0010] Another aspect of the present disclosure is to provide an additional source of spin-transfer torque for MTJ devices without the associated fabrication difficulties.

[0011] According to one aspect of the present disclosure, there is provided a device that includes a substrate; an MTJ formed on the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; and a parallel spin-momentum layer formed on the free layer of the MTJ, the PSM layer including a chiral material.

[0012] According to another aspect of the present disclosure, there is provided a device that includes: a substrate; a PSM layer formed on the substrate, the PSM layer comprising a chiral material; and an MTJ layer formed on the PSM layer, the MTJ comprising a free layer, a tunnel barrier layer, and a reference layer.

[0013] According to another aspect of the present disclosure, there is provided a method including providing a substrate and forming an MTJ layer and a PSM layer on the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer, the PSM layer being formed adjacent to the free layer of the MTJ and including a chiral material.

[0014] According to another aspect of the present disclosure, there is provided an electronic device including a processor and a memory device, the memory device including an MTJ including a reference layer, a tunnel barrier layer, and a free layer, and a PSM layer formed on the free layer of the MTJ, the PSM layer including a chiral material. [Brief description of the drawings]

[0015] The above and other aspects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Figure 1A] FIG. 1A shows a left-handed PSM layer on top of a free layer of an MTJ according to an embodiment. [Figure 1B] FIG. 1B shows a right-handed PSM layer on top of a free layer of an MTJ according to an embodiment. [Figure 2A] FIG. 2A is a cross-sectional side view of a top free layer MTJ stack including a PSM layer, according to an embodiment. [Figure 2B] FIG. 2B is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to another embodiment. [Figure 3A] FIG. 3A is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer, according to an embodiment. [Figure 3B] FIG. 3B is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to another embodiment. [Figure 4] FIG. 4 illustrates an electronic device according to an embodiment. [Diagram 5] FIG. 5 is a flow chart illustrating a method of forming a top free layer MTJ stack including a PSM layer, according to an embodiment. [Figure 6] FIG. 6 is a flow chart illustrating a method of forming a bottom free layer MTJ stack including a PSM layer, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be understood by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter disclosed herein.

[0017] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or item described in connection with that embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases of similar import) in various places in this specification may not necessarily all refer to the same embodiment. Moreover, particular features, structures, or items may be combined in any suitable manner in one or more embodiments. In this regard, the word "exemplary" as used herein means "serving as an example, example, or illustration." Any embodiment described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments.

[0018] Furthermore, the particular features, structures, or elements may be combined in any suitable manner in one or more embodiments. Also, singular terms may include their corresponding plural forms, and plural terms may include their corresponding singular forms, depending on the context of the discussion herein. Similarly, hyphenated terms (e.g., "2-D," "pre-defined," "pixel-specific," etc.) may sometimes be used interchangeably with their corresponding unhyphenated versions (e.g., "2-D," "pre-defined," "pixel-specific," etc.), and capitalized entries (e.g., "Counter Clock," "Row Select," "PIXOUT," etc.) may sometimes be used interchangeably with their corresponding non-capitalized versions (e.g., "Counter Clock," "Row Select," "Pixout," etc.). Such occasional interchangeable usages should not be construed as mutually inconsistent.

[0019] Also, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It is further noted that the various figures (including component figures) shown and described herein are for illustrative purposes only and are not drawn to scale. For clarity, the dimensions of some elements may be exaggerated relative to other elements. For example, the dimensions of layers and regions may be exaggerated for clarity of explanation.

[0020] Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding and / or similar elements. That is, the same reference numeral may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. However, such usage is for simplicity of illustration and ease of discussion only; it does not imply that the configuration or architectural details of such components or units are the same across all embodiments, or that such commonly referenced parts / modules are the only way to implement some exemplary embodiments disclosed herein.

[0021] The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be a limitation of the claimed subject matter. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0022] As used herein, the terms "comprises," "comprising," "includes," "including," "having," "having," "including," or "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, product, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent in such composition, mixture, process, method, product, or apparatus.

[0023] When an element or layer is referred to as being on, "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] The terms "first," "second," etc., as used herein, are used as labels for the nouns to which they apply and do not imply any type of ordering (e.g., spatial, temporal, logical), unless expressly defined as such.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of this application pertains. Furthermore, it will be understood that terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not in an idealized or overly formal sense unless expressly defined as such in this application.

[0026] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein with respect to the module. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any implementation described herein may include, for example, alone or in any combination, an assembly, a hardwired circuit, a programmable circuit, a state machine circuit, and / or firmware that stores instructions executed by a programmable circuit. Modules may be embodied as circuits that collectively or individually form part of a larger system, such as, but not limited to, an IC, a system-on-chip (SoC), an assembly, etc.

[0027] TECHNICAL FIELD Embodiments of the present disclosure relate to MTJ devices and methods for manufacturing MTJ devices.

[0028] The embodiments relate to magnetic junctions that can be used in magnetic devices such as magnetic memories, and devices that use such magnetic junctions. The magnetic memories may include STT-MRAM, SOT memories, and may be used in electronic devices that use non-volatile memories. Other devices that include magnetic junctions, particularly STT or SOT programmable magnetic junctions, include, but are not limited to, logic, neuromorphic computing cells, and other devices. Electronic devices include, but are not limited to, mobile phones, smart phones, tables, laptops, and other portable and non-portable computing devices.

[0029] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the structures and methods being described as orientations in the drawings. Terms such as "overlying," "on," "located on," "positioned on," or "located on" mean that a first element, such as a first structure, is above a second element, such as a second structure, where an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconducting layer. It should be noted that the term "selective," such as "a first element selective to a second element," means that the first element may be etched and that the second element may act as an etch stop.

[0030] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without showing details of the well-known processes.

[0031] In general, the various processes used to form the microchips that are packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto the wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical vapor deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), and others. Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, typically by diffusion and / or by ion implantation. These doping processes are followed by a furnace anneal or rapid thermal anneal (RTA). The annealing serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and insulate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered by the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the formation of three-dimensional relief images or patterns on a semiconductor substrate in order to later transfer the pattern to the substrate. In semiconductor lithography, the patterns are formed by light-sensitive polymers called photoresists. The lithography and etch pattern transfer steps are repeated multiple times to build the structures that make up an IC device. Each pattern printed on the wafer is aligned to the previously formed patterns, and gradually, conductors, insulators, and selectively doped regions are built up to form the final device.

[0032] As mentioned above, one aspect of the present disclosure provides an apparatus and method for obtaining lower switching currents in MTJ devices. More specifically, the present disclosure provides an additional source of spin transfer torque for MTJ devices, thereby enabling lower switching currents.

[0033] According to an embodiment, a PSM layer, i.e., a chiral material layer, can be formed additively to the free layer of the MTJ device to provide an additional source of spin-transfer torque. By utilizing a chiral layer, the spin current induced by the chiral material is non-reciprocal and the spin and momentum are locked in parallel, making the chiral layer compatible with a magnetic structure having perpendicular magnetic anisotropy.

[0034] Furthermore, the PSM layer can be positioned adjacent to the perpendicularly magnetized magnetic free layer, which is consistent with conventional two-terminal MTJ devices, thereby mitigating fabrication issues associated with previous sources of additional spin-transfer torque for MTJ devices.

[0035] Furthermore, compared to conventional double tunnel junctions, MTJs including PSM layers according to embodiments offer more margin and fewer interface concerns, and there are a greater number of materials available for fabrication.

[0036] FIG. 1A shows a left handed PSM layer on top of a free layer of an MTJ according to an embodiment.

[0037] Referring to FIG. 1A, a left-handed PSM layer 101 is formed, eg, grown, on a free layer of an MTJ that includes, eg, a free layer, a reference layer, and a tunnel barrier layer between the reference layer and the free layer.

[0038] The spin currents 102 and 103 generated from the PSM layer 101 are non-reciprocal. The resulting torque from the spin currents 102 and 103 serves to switch the free layer in both directions by simply reversing the current flow direction. That is, the spin currents 102 and 103 and their associated torque induced by the PSM layer 101 can be added to the STT current from the reference layer, thus amplifying the total torque. Furthermore, since the handedness of the PSM layer 101, e.g., left-handed in FIG. 1A, is robust and fixed, the spin currents 102 and 103 and the spin polarization are determined only by the current direction.

[0039] FIG. 1B shows a right-handed PSM layer on top of a free layer of an MTJ according to an embodiment.

[0040] Referring to FIG. 1B, a right-handed PSM layer 101 is formed, eg, grown, on a free layer of an MTJ that includes, eg, a free layer, a reference layer, and a tunnel barrier layer between the reference layer and the free layer.

[0041] The spin currents 105 and 106 generated from the PSM layer 104 are non-reciprocal. Similar to Figure 1A, the resulting torque from the spin currents 105 and 106 serves to switch the free layer in both directions by simply reversing the direction of current flow. That is, the spin currents 105 and 106 and their associated torque induced by the PSM layer 104 can be added to the STT current from the reference layer, thus amplifying the total torque.

[0042] As shown in Figures 1A and 1B, depending on the magnetism and chirality of the reference layer of the PSM layer material, the spin transfer torques from the PSM layer and the reference layer add up to each other. That is, by changing the current direction, the spin transfer torque from the PSM layer can be added to the spin transfer torque from the reference layer, thereby allowing lower switching currents. The choice of chiral material with left-handed or right-handed chirality in the PSM layer is based on the magnetization of the reference layer, i.e., it is selected to match the magnetization of the reference layer.

[0043] FIG. 2A is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to an embodiment.

[0044] 2A, the top free layer MTJ stack includes a PSM layer 201, a PMA magnetic layer (ML) 202, a tunnel barrier layer 203, a PMA ML 204, a dusting layer 205, a synthetic anti-ferromagnet (SAF) layer 206, and an underlayer (and / or substrate) 207. The PMA ML 202 is the free layer of the MTJ stack, and the PMA ML 204, dusting layer 205, and SAF layer 206 form the reference layers of the MTJ stack.

[0045] The free layer of the MTJ stack, PMA ML202, may be formed as a CoFeB layer, which refers to an alloy of Co, Fe, and B without reference to a specific stoichiometry.

[0046] PMA ML202 is Mn 3 In one or more embodiments, the Heusler compound may be in the form of a Heusler compound such as AlMnGe, or a C38 compound such as AlMnGe. In one or more embodiments, the Heusler compound is Mn where Z is Ge, Sn, or Sb. 3 Z. In one or more embodiments, the Heusler compound may be a tetragonal Heusler compound such as Mn 3 Sn,Mn 3 Sb,Mn2 CoSn, Mn 2 FeSb, Mn 2 CoAl, Mn 2 CoGe, Mn 2 CoSi, Mn 2 CuSi, Co 2 CrAl, Co 2 CrSi, Co 2 MnSb, or Co 2 It may also be MnSi. All Heusler compounds are listed in stoichiometric formulas, and these compounds can be grown with some variations from the stoichiometric composition.

[0047] The tunnel barrier layer 203 may contain MgO. Also, magnesium-aluminum oxide may be a suitable alternative to MgO, and the magnesium-aluminum oxide is Mg 1-z Al 2+(2 / 3)z O 4 having a form of (-0.5 < z < 0.5).

[0048] The capping layer 205, for example a layer of Ta, is a thin film of a material, for example 0.3 nm thick, which can be inserted into the structure to magnetically couple the magnetic layer 204 to the SAF 206. Alternatively, Ta may be replaced by Ir, Ru, Mo.

[0049] The SAF layer 206 may include two magnetic layers separated by a spacer.

[0050] The underlayer 207 is TaN / IrMn 3 , TaN / IrMn 3 / TaN, CoGa, or CoAl may be included. The underlayer 207 may include Pt, Ru, Ir, Ta, CoFeB, CoFeBTa, TaB, TiN, or TaN. The underlayer 207 may include a combination of at least two of the above materials to form a bilayer structure or a multilayer structure.

[0051] As mentioned above, by changing the direction of the applied current, the spin transfer torque from the PSM layer 201 is added to the spin transfer torque from the reference layers, i.e., PMA ML 204, dusting layer 205, and SAF layer 206, thereby enabling lower switching currents. The choice of chiral material with left-handed or right-handed chirality in the PSM layer 201 is selected to match the reference layers.

[0052] The PSM layer 201 may include a material selected from the B20 or C40 structures or other chiral structures (cubic, trigonal, tetragonal and hexagonal) and may have a thickness greater than 2-3 nm (thickness>2-3 nm).

[0053] The B20 structure is a cubic structure with low internal symmetry. It has neither four-fold rotational symmetry nor inversion symmetry in the lattice. The B20 structure can be completely determined by three parameters: the lattice parameter a and two internal parameters u and v. Specific examples of the B20 structure include PtAl, BeAu, CoGe, CoSi, FeGe, PdGa, MnGe, RhGe, HfSb, HfSn, ZrSb, MnSi, FeSi, PtGa, RhSi, RuSi, NiSi, MnGe, CrSi, CrGe, PtMg, ReSi, RhSn, ZrSb, PdAl, and PtAl.

[0054] C40 is P6 2 It is part of the hexagonal space group #180 with the short name 22. Examples of C40 structures include: TaGe 2 ,TaSi 2 ,VGe 2 ,HfSn 2 ,NbGe 2 ,MoSi 2 ,VSi 2 ,WSi 2 ,CrSi 2 ,WAl 2 ,HfSn 2 , and NiMg 2 .

[0055] Examples of other chiral structures with chiral symmetry groups that may be used include: IrGe 4 ,Hf5Ir 3 ,NbGe 2 ,WAl 2 ,β-RhSi,Mg 3 Ru 2 , and YSb 2 .

[0056] The PSM layer 201 may also include low symmetry topology materials.

[0057] The PSM layer 201 includes a chiral material having greater than 50% of either left-handed or right-handed chirality, for example, the chiral material may be PtAl or PtGa.

[0058] FIG. 2B is a cross-sectional side view of a top free layer MTJ stack including a PSM layer according to another embodiment.

[0059] Referring to Figure 2B, the top free layer MTJ stack includes a PSM layer 201, a PMA ML 202, a tunnel barrier layer 203, a PMA ML 204, a dusting layer 205, a SAF layer 206, and an underlayer 207, similar to Figure 2A, but also includes a texture breaking layer (TBL) 208 interposed between the PSM layer 201 and the PMA ML 202. That is, the PSM layer 201 may directly interface with the PMA ML 201, similar to that shown in Figure 2A, or may be separated by a spacer layer, such as the TBL 208, as shown in Figure 2B.

[0060] The TBL 208 may be used to induce larger magnetic anisotropy in the CoFeB, i.e., PMA ML 202. Thus, the TBL 208 may include a high spin conductance layer, such as NiO.

[0061] As mentioned above, the PSM layer is compatible with the top free layer MTJ with many advantages, for example, the reference layer is highly thermally stable with a relatively large magnetic exchange coupling to the PMA magnetic layer, Hex, etc. Current MRAM products often use top free layer MTJs, however, the PSM layer can also be incorporated into the bottom free layer in the MTJ.

[0062] FIG. 3A is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to an embodiment.

[0063] 3A, the bottom free layer MTJ stack includes an SAF layer 306, a dusting layer 305, a PMA ML 304, a tunnel barrier layer 303, a PMA ML 302, a PSM layer 301, and an underlayer 307. The PMA ML 302 is the free layer of the MTJ stack, and the PMA ML 304, the dusting layer 305, and the SAF layer 306 form the reference layers of the MTJ stack.

[0064] In Figure 3A, the structure of the bottom free layer MTJ stack is similar to that of the top free layer MTJ stack shown in Figure 2A and described above, except that the order of the layers above the underlayer 307 is reversed, so a repeated description of each layer will be omitted here.

[0065] FIG. 3B is a cross-sectional side view of a bottom free layer MTJ stack including a PSM layer according to another embodiment.

[0066] 3B, the bottom free layer MTJ stack includes the SAF layer 306, the dusting layer 305, the PMA ML 304, the tunnel barrier layer 303, the PMA ML 302, the PSM layer 301, and the underlayer 307, similar to that of FIG 3A, but also includes a TBL 308 interposed between the PSM layer 301 and the PMA ML 302. That is, the PSM layer 301 may directly interface with the PMA ML 301, similar to that shown in FIG 3A, or may be separated by a spacer layer such as the TBL 308, as shown in FIG 3B.

[0067] A capping layer may be present on the MTJ stacks shown in Figures 2A, 2B, 3A, and 3B.

[0068] FIG. 4 illustrates an electronic device according to an embodiment.

[0069] 4, an electronic device 400, such as a user equipment (UE) or mobile terminal, includes a processor 401 and a memory 402. Although not shown in FIG 4, depending on the type of electronic device 400, the electronic device 400 may include various additional components, such as an input device, an audio output device, a display device, an audio module, a sensor module, an interface, a haptic module, a camera module, a power management module, a battery, a communication module, a subscriber identity module (SIM), and / or an antenna module.

[0070] The processor 401 may, for example, execute software (e.g., programs) to control at least one other component (e.g., hardware or software component) of the electronic device 400, and may also perform various data processing or calculations. As at least a part of the data processing or calculations, the processor 401 may load commands or data received from another component into the volatile memory 403, process the commands or data stored in the volatile memory 403, and store the resulting data in the non-volatile memory 404. The processor 401 may include a main processor (e.g., a central processing unit (CPU) or an application processor) and auxiliary processors (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that may operate independently or in cooperation with the main processor.

[0071] The memory 402 can store various data used by at least one component (e.g., the processor 401) of the electronic device 400. The various data may include, for example, software (e.g., programs) and input or output data for commands associated therewith. The memory 402 may include a volatile memory 403 or a non-volatile memory 404. The non-volatile memory 404 may include, for example, an MTJ stack including a PSM layer as shown in FIGS. 2A, 2B, 3A, and 3B.

[0072] FIG. 5 is a flow chart illustrating a method of forming a top free layer MTJ stack including a PSM layer according to an embodiment.

[0073] 5, in step 501, an underlayer is provided. The underlayer is TaN / IrMn 3 ,TaN / IrMn 3 / TaN, CoGa, or CoAl. Underlayer 207 may include Pt, Ru, Ir, Ta, CoFeB, CoFeBTa, TaB, TiN, or TaN. Underlayer 207 may include a combination of at least two of the above materials forming a bilayer or multilayer structure.

[0074] A reference layer is formed on the underlayer in step 503. The reference layer may include a SAF layer, a dusting layer, and a PMA ML.

[0075] In step 505, a tunnel barrier layer, for example MgO, is formed over the reference layer.

[0076] In step 507, a free layer, for example another PMA ML, is formed over the tunnel barrier layer.

[0077] In step 509, a TBL may be formed on the free layer.

[0078] In step 511, a PSM layer is formed over the TBL.

[0079] As mentioned above, the PSM layer may interface directly with the free layer, similar to that shown in Figure 2A, or may be separated by a spacer layer, such as a TBL, as shown in Figure 2B, and therefore step 509 may be optional.

[0080] If step 509 is not performed, then in step 511, a PSM layer is formed over the free layer.

[0081] 6 is a flow chart illustrating a method of forming a bottom free layer MTJ stack including a PSM layer according to an embodiment. Essentially, the method of FIG. 6 is the reverse of the method of FIG. 5, except for the initial underlayer.

[0082] Referring to FIG. 6, in step 601, an underlayer is provided.

[0083] In step 603, a PSM layer is formed over the underlayer.

[0084] In step 605, a TBL may be formed on the PSM layer.

[0085] In step 607, a free layer, e.g., a PMA ML, is formed on the TBL. As mentioned above, the PSM layer may interface directly with the free layer, similar to that shown in Figure 3A, or may be separated by a spacer layer, such as a TBL, as shown in Figure 3B. Thus, step 605 may be optional.

[0086] If step 605 is not performed, then in step 607 a free layer is formed over the PSM layer.

[0087] In step 609, a tunnel barrier layer, for example MgO, is formed over the free layer.

[0088] A reference layer is formed on the tunnel barrier layer in step 611. The reference layer may include a PMA ML, a dust layer, and a SAF layer.

[0089] According to the above-described embodiments, a PSM layer, i.e., a chiral material layer, may be additionally formed to the free layer (or adjacent to the TBL adjacent to the free layer) of an MTJ device to provide an additional source of spin transfer torque and provide an MTJ device capable of operating at a lower switching current.

[0090] Embodiments of the subject matter and operations described herein may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed herein and their structural equivalents, or in one or more combinations thereof. Embodiments of the subject matter described herein may be implemented as one or more computer programs, i.e., as one or more modules of computer program instructions encoded on a computer storage medium for execution by or to control the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded in an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiving apparatus for execution by a data processing apparatus. A computer storage medium may be or may be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. Additionally, while a computer storage medium is not a propagated signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium may be or be contained in one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described herein may be implemented as operations performed by a data processing apparatus on data stored in one or more computer-readable storage devices or data received from other sources.

[0091] Although the specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather as descriptions of features specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in a particular combination, and even initially claimed as such, one or more features from a claimed combination may, in some cases, be deleted from that combination, and the claimed combination may be directed to a subcombination or variation of the subcombination.

[0092] Similarly, although operations are depicted in a particular order in the figures, this should not be understood as requiring that such operations be performed in the particular order or sequential order depicted, or that all of the depicted operations be performed, to achieve desired results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, it should be understood that the division of various system components in the above-described embodiments is not to be understood as requiring such a division in all embodiments, and that the program components and systems described may generally be integrated together in a single software product or packaged in multiple software products.

[0093] That is, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0094] Although the present disclosure has been shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. substrate; a magnetic tunnel junction (MTJ) formed on the substrate, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; and a parallel spin momentum (PSM) layer formed on the free layer of the MTJ, the PSM layer comprising a chiral material; The device that contains

2. 2. The device of claim 1, wherein the chiral material has left-handed or right-handed chirality corresponding to a magnetization direction of the reference layer of the MTJ.

3. 10. The device of claim 1, wherein the chiral material comprises PtAl or PtGa.

4. 10. The device of claim 1, wherein the PSM layer has a thickness greater than 2-3 nm.

5. 10. The device of claim 1, wherein the PSM layer comprises a chiral material having greater than 50% left-handed or right-handed chirality.

6. 10. The device of claim 1, further comprising a texture breaking layer (TBL) formed between the free layer and the PSM layer of the MTJ layer.

7. 10. The device of claim 1, wherein the tunnel barrier layer of the MTJ comprises MgO.

8. 10. The device of claim 1, wherein the free layer of the MTJ comprises an alloy of Co, Fe, and B.

9. 10. The device of claim 1, wherein the free layer of the MTJ comprises a Heusler compound.

10. 10. The device of claim 9, wherein the Heusler compound is Mn 3 Devices, including Ge.

11. 10. The device of claim 1, wherein the free layer of the MTJ comprises a C38 compound.

12. 12. The device of claim 11, wherein the C38 compound comprises AlMnGe.

13. substrate; a parallel spin momentum (PSM) layer formed on the substrate, the PSM layer comprising a chiral material; and a magnetic tunnel junction (MTJ) formed on the PSM layer, the MTJ including a free layer, a tunnel barrier layer, and a reference layer; The device that contains

14. 14. The device of claim 13, wherein the chiral material has left-handed or right-handed chirality corresponding to a magnetization direction of the reference layer of the MTJ.

15. 14. The device of claim 13, wherein the chiral material comprises PtAl or PtGa.

16. 14. The device of claim 13, wherein the PSM layer has a thickness greater than 2-3 nm.

17. 14. The device of claim 13, wherein the PSM layer comprises chiral material having greater than 50% left-handed or right-handed chirality.

18. 14. The device of claim 13, further comprising a texture breaking layer (TBL) formed between the free layer and the PSM layer of the MTJ layer.

19. Providing a substrate; forming a magnetic tunnel junction (MTJ) and a parallel spin momentum (PSM) layer on the substrate; the MTJ includes a reference layer, a tunnel barrier layer, and a free layer; The method, wherein the PSM layer is formed adjacent to the free layer of the MTJ and includes a chiral material.

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