Method for manufacturing semiconductor device

Abstract

To avoid damage during element partitioning and improve the quality of a semiconductor device containing compound semiconductor sections.SOLUTION: A method for manufacturing a semiconductor device performs a step for preparing a semiconductor substrate (11) on which a first semiconductor part (S1) is formed above a main substrate, a step for dividing the first semiconductor part (S1) into a plurality of base semiconductor parts (8) by forming a plurality of trenches (TR) in the first semiconductor part (S1), and a step for forming a compound semiconductor part (9) above at least one of the plurality of base semiconductor parts (8).SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method of performing PEC etching on an element formation layer in order to separate semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-136476 A Summary of the Invention

[0004] A manufacturing method for a semiconductor device according to the present disclosure includes the steps of preparing a semiconductor substrate on which a first semiconductor portion is formed above a main substrate, dividing the first semiconductor portion into a plurality of base semiconductor portions, and forming a compound semiconductor portion above at least one of the plurality of base semiconductor portions. [Brief description of the drawings]

[0005] [Figure 1] 2 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment. [Diagram 2] 1A to 1C are plan views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 3] 2 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 1A to 1C are plan views showing a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1 is a block diagram showing a semiconductor device manufacturing apparatus according to a first embodiment. [Figure 7]FIG. 2 is a partial cross-sectional view of an element portion of the first embodiment. [Figure 8] FIG. 2 is a partial plan view of an element portion according to the first embodiment. [Figure 9] FIG. 2 is a partial cross-sectional view of an element portion of the first embodiment. [Figure 10] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 11] 1 is a cross-sectional view showing an example of the configuration of a template substrate. [Figure 12] 4 is a cross-sectional view showing an example of lateral growth of a first semiconductor portion. FIG. [Figure 13] 5 is a plan view showing another example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] 6 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 15 is a plan view showing a method for manufacturing the semiconductor device shown in FIG. 14. [Figure 16] 15A to 15C are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. [Figure 17] 6 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 6 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 6 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 20 is a plan view illustrating a method for manufacturing the semiconductor device shown in FIG. 19. [Figure 21] 6 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 22 is a plan view showing a method for manufacturing the semiconductor device shown in FIG. 21. [Diagram 23] FIG. 2 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. [Figure 24] FIG. 2 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. [Diagram 25]FIG. 2 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. [Figure 26] FIG. 2 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. [Figure 27] FIG. 2 is a perspective view showing the configuration of a semiconductor device obtained in Example 1. [Figure 28] FIG. 2 is a schematic diagram showing the configuration of an electronic device including a semiconductor device obtained in Example 1. [Figure 29] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Diagram 30] 11A to 11C are plan views showing a method for manufacturing a semiconductor device according to a second embodiment. [Diagram 31] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment. [Diagram 32] FIG. 11 is a block diagram showing a semiconductor device manufacturing apparatus according to a second embodiment. [Figure 33A] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. [Figure 33B] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a third embodiment. [Diagram 34] 11A to 11C are plan views showing a method for manufacturing a semiconductor device according to a third embodiment. [Diagram 35] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment. [Diagram 36] FIG. 11 is a block diagram showing a semiconductor device manufacturing apparatus according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Fig. 1 is a flowchart showing a method for manufacturing a semiconductor device according to this embodiment. Fig. 2 is a plan view showing a method for manufacturing a semiconductor device according to this embodiment. As shown in Figs. 1 and 2, the method for manufacturing a semiconductor device according to this embodiment includes the steps of preparing a semiconductor substrate 11 having a first semiconductor portion S1 formed on a template substrate 7 including a main substrate, dividing the first semiconductor portion S1 into a plurality of base semiconductor portions 8, and forming a compound semiconductor portion 9 above at least one of the plurality of base semiconductor portions 8.

[0007] In the conventional method of etching the element formation layer, there was a risk of the element formation layer being damaged by the etching. In this embodiment, the first semiconductor portion S1 is divided into a plurality of base semiconductor portions 8 before the compound semiconductor portion 9 is formed. In this manner, the first semiconductor portion S1 is divided, for example, by forming trenches TR before the active layer of the compound semiconductor portion 9 is formed, and by not performing etching to divide the elements after the active layer is formed, damage to the active layer can be avoided. This can improve the quality of a semiconductor device including the compound semiconductor portion 9.

[0008] The template substrate 7 may have a main substrate and a mask pattern 6 including m5 and an opening K, and the first semiconductor portion S1 may be formed from the opening K (the seed portion 3 exposed in the opening K) onto the mask portion 5. The first semiconductor portion S1 as well as the base semiconductor portion 8 and the compound semiconductor portion 9 may include a nitride semiconductor (for example, a GaN-based semiconductor).

[0009] Specific examples of semiconductor devices include light emitters (LED chips, semiconductor laser chips, etc.), light emitting elements with light emitters submounted, light emitting modules with light emitting elements packaged, etc., but are not limited to these light emitting semiconductor devices. For example, a light receiving element (photo diode) may also be used, in which case the same effects as those of light emitting semiconductor devices can be obtained.

[0010] The nitride semiconductor can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductor, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). The GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor portion 8 may be a doped type (e.g., n-type containing donors) or a non-doped type (i-type).

[0011] The first semiconductor portion S1 including a nitride semiconductor can be formed by using an ELO (Epitaxial Lateral Overgrowth) method. In the ELO method, the first semiconductor portion S1 is grown laterally on a template substrate 7 having a mask pattern 6 (selective growth mask pattern). In this way, even if the main substrate included in the template substrate 7 is a heterogeneous substrate (a substrate having a different lattice constant from that of the first semiconductor portion S1), a low defect portion having a low threading dislocation density can be formed on the mask portion 5. Since the number of threading dislocations (dislocations extending in the thickness direction) inherited by the compound semiconductor portion 9 on the low defect portion is reduced, the light emission efficiency is increased in the case of a light emitting semiconductor device.

[0012] Example 1 (Method of manufacturing semiconductor devices) Fig. 3 is a flowchart showing a method for manufacturing a semiconductor device according to the embodiment 1. Fig. 4 is a plan view showing the method for manufacturing a semiconductor device according to the embodiment 1. Fig. 5 is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment 1.

[0013] 3 to 5, the method for manufacturing the semiconductor device of Example 1 includes the steps of preparing a template substrate 7 having a main substrate 1 and a mask pattern 6 including an opening K and a mask portion 5, forming a first semiconductor portion S1 including a nitride semiconductor (e.g., a GaN-based semiconductor) from the opening K to the mask portion 5, dividing the first semiconductor portion S1 into a plurality of base semiconductor portions 8 by forming a plurality of trenches TR in the first semiconductor portion S1, forming a compound semiconductor portion 9 including a nitride semiconductor (e.g., a GaN-based semiconductor) on each base semiconductor portion 8, forming a first electrode E1 and a second electrode E2, and transferring an element portion (device laminate) DS including the base semiconductor portion 8 and the compound semiconductor portion 9 from the template substrate 7 to a support substrate SK. By transferring the element portion DS to the support substrate SK (holding it on the support substrate SK), the mask portion 5 of the template substrate 7 and the base semiconductor portion 8 are separated from each other. The mask pattern 6 may be a mask layer pattern, the first semiconductor portion S1 may be a first semiconductor layer, the base semiconductor portion 8 may be a base semiconductor layer, and the compound semiconductor portion 9 may be a compound semiconductor layer.

[0014] For example, in the conventional method, if the element formation layer is not completely protected, unintended areas may be etched by the etchant in the PEC etching, which may reduce the quality of the semiconductor device. In addition, when forming chips of 100 μm or less in size such as micro LEDs, elements are sometimes isolated by dry etching, but in the case of small chips such as those mentioned above, the dry-etched side of the chip may be physically and chemically damaged by ion atoms of the etchant. When the chip size is about 20 μm or less, the ratio of side damage to the light-emitting area of ​​the chip increases, which may reduce the light-emitting efficiency. Side damage to the active layer (e.g., the light-emitting layer of a light-emitting chip, the light-receiving layer of a light-receiving chip) may cause a serious decrease in efficiency.

[0015] In the first embodiment, for example, the first semiconductor portion S1 is divided into a plurality of base semiconductor portions 8 before forming the compound semiconductor portion 9 including the active layer, and etching for element division is not performed after the active layer is formed, thereby avoiding etching damage. This makes it possible to improve the quality of the semiconductor device including the compound semiconductor portion 9.

[0016] FIG. 6 is a block diagram showing a semiconductor device manufacturing apparatus according to the first embodiment. As shown in FIG. 6, the semiconductor device manufacturing method of the first embodiment can be realized by a semiconductor device manufacturing apparatus 40 that executes each process. The semiconductor device manufacturing apparatus 40 of the first embodiment may include an apparatus 40A for preparing a template substrate 7, an apparatus 40B for forming a first semiconductor portion S1, an apparatus 40C for forming a plurality of trenches TR in the first semiconductor portion S1, an apparatus 40D for forming a compound semiconductor portion 9, an apparatus 40E for forming a first electrode E1 and a second electrode E2, an apparatus 40F for transferring an element portion DS to a support substrate SK, and an apparatus 40G for controlling the apparatuses 40A to 40F. For example, an MOCVD apparatus may be used for the apparatus 40B and 40D. The apparatus 40B may be used as the apparatus 40D. For example, an etching apparatus may be used for the apparatus 40C. For example, a sputtering apparatus may be used for the apparatus 40E. The apparatus 40C and 40E may include a photolithography apparatus. The apparatus 40G may include a processor and a memory. Device 40G may be configured to control at least one of devices 40A to 40F by executing a program stored in, for example, an internal memory, a communicable external device, or an accessible network, and this program as well as a recording medium and an external device on which this program is stored are also included in Example 1.

[0017] In the first embodiment, the compound semiconductor portion 9 is formed after dividing the first semiconductor portion S1 into a plurality of base semiconductor portions 8. Therefore, for the reasons explained above, the condition of the side surface of the compound semiconductor portion 9 can be improved compared to a configuration in which the first semiconductor portion that will become the base semiconductor portion and the second semiconductor portion that will become the compound semiconductor portion are laminated together, and then the first and second semiconductor portions are etched (a configuration in which the side surface of the second semiconductor portion is affected by etching).

[0018] In the first embodiment, it is not necessary to form all the trenches before forming the active layer. The trenches for chip peeling may be formed after forming the compound semiconductor portion 9. On the other hand, the trenches for chip peeling, for example, the trenches for removing the bonded portion (neck portion) of the base semiconductor portion 8, may be formed before forming the active layer.

[0019] 4 and 5, the template substrate 7 has a main substrate 1, a seed portion 3 located on the main substrate 1, and a mask pattern 6 located on the seed portion 3. The mask pattern 6 includes a mask portion 5 and an elongated opening portion K. In the template substrate 7, the seed portion 3 is exposed from the opening portion K, and the first semiconductor portion S1 starts crystal growth from above the seed portion 3 and is bonded to the seed portion 3.

[0020] In the first embodiment, the ELO method is used to form the first semiconductor portion S1 including a nitride semiconductor in a linear shape extending in, for example, the Y direction. In this case, the growth of semiconductor crystals growing in the lateral direction (X direction) in opposite directions on the mask portion 5 is stopped before they meet on the mask portion 5. Thus, a gap (gap) GP is formed between the first semiconductor portions S1 adjacent in the X direction. The X direction is the <11-20> direction (a-axis direction) of the base semiconductor portion 8, the Y direction is the <1-100> direction (m-axis direction) of the base semiconductor portion 8, and the Z direction is the <11-20> direction (a-axis direction) of the base semiconductor portion 8. <0001> It may be in the direction (c-axis direction).

[0021] In the first embodiment, a plurality of trenches TR can be formed in the first semiconductor portion S1 by etching. At least one of the plurality of trenches TR may extend in the width direction (X direction) of the opening portion K. At least one of the plurality of trenches TR may extend in the longitudinal direction (Y direction) of the opening portion K. The plurality of trenches TR and gaps GP surrounding the base semiconductor portion 8 may make the base semiconductor portion 8 into an island shape (not connected to the surroundings).

[0022] The etching of the first semiconductor portion S1 is dry etching, and this dry etching may be stopped at the mask portion 5. In this case, the mask portion 5 functions as an etching stopper, and the mask portion 5 is exposed at the bottom of the trench TR. In this case, the etching does not necessarily have to stop at the surface of the mask portion 5, but it is sufficient that the etching stops within the mask portion 5. The mask portion 5 is formed of a material that is more difficult to etch than the first semiconductor portion S1, and as long as it can fulfill the role of stopping the etching, part of the mask portion 5 may be etched.

[0023] Each compound semiconductor portion 9 may be formed in an island shape corresponding to each base semiconductor portion 8. When the base semiconductor portion 8 is made island-shaped by a plurality of trenches TR and gaps GP, the base semiconductor portion 8 is surrounded by the mask portion 5 in a plan view (as viewed in the Z direction). Since nitride semiconductor is unlikely to be deposited on the mask portion 5, which is a selective growth mask, and the compound semiconductor portion 9 grows on the upper surface and side surfaces of the base semiconductor portion 8 (including the nitride semiconductor), the compound semiconductor portion 9 can be made island-shaped. This can avoid patterning damage and improve the condition of the compound semiconductor portion 9. In addition, the manufacturing process is simplified.

[0024] In addition, as shown in FIG. 4, when the trench TR is formed to extend in the width direction (X direction) of the opening K, the warpage of the wafer can be reduced. This is remarkable when a heterogeneous substrate having a thermal expansion coefficient different from that of the base semiconductor portion 8 is used for the main substrate 1. The main substrate 1 or the template substrate 7 may be called a wafer, and the template substrate 7 and the semiconductor portion thereon may be collectively called a wafer. For example, as shown in FIG. 4, the first semiconductor portions S1 adjacent to each other in the X direction are separated by a gap GP. Therefore, the warpage of the wafer in the X direction is small. However, since the first semiconductor portion S1 is formed continuously in the Y direction longer than the size (width) in the X direction, the warpage of the wafer in the Y direction is large. However, by dividing the first semiconductor portion S1 extending in the Y direction by the trench TR in the X direction before forming the active layer, the stress is relieved and the warpage of the wafer in the Y direction is reduced. Therefore, when forming the active layer, the wafer is less warped and the temperature of the wafer surface during film formation is easily kept uniform within the plane. Therefore, when the temperature variation on the wafer surface is small and, for example, the active layer contains In (indium), the variation in the In concentration can be reduced, and the variation in the emission wavelength within the wafer surface can be improved. This effect can be obtained even when the trench TR does not reach the bottom surface of the base semiconductor portion 8 (stops halfway in the depth direction). In this case, the center of the trench TR is dry-etched again with a width smaller than the first trench width while protecting the side surface of the active layer, thereby peeling off the semiconductor chip from the wafer. In this way, the trench TR dug before the active layer is formed does not have to reach the mask portion 5.

[0025] FIG. 7 is a partial cross-sectional view of the element portion of the first embodiment. FIG. 8 is a partial plan view of the element portion of the first embodiment. As shown in FIG. 7, the compound semiconductor portion 9 may include an active portion (active layer) 9K. By dividing the first semiconductor portion S1 and forming the base semiconductor portion 8 before forming the compound semiconductor portion 9, the state of the side surface of the active portion 9K can be improved. The compound semiconductor portion 9 may be formed in this order on the base semiconductor portion 8 as an n-type portion 9N, an active portion 9K, and a p-type portion 9P. The thickness of the compound semiconductor portion 9 may be ½ or less of the thickness of the base semiconductor portion 8. The total thickness of the active portion 9K and the p-type portion 9P may be ½ or less of the thickness of the base semiconductor portion 8. By making the thickness of the compound semiconductor portion 9 equal to or less than half the thickness of the base semiconductor portion 8, the trenches are less likely to be filled when the compound semiconductor portion 9 is formed on the base semiconductor portion 8, and the peeling yield (successful peeling rate) is improved.

[0026] A regrowth layer (for example, a buffer layer including an n-type GaN-based semiconductor) may be formed on the first semiconductor portion S1, and a plurality of trenches TR may be formed in the first semiconductor portion S1 and the regrowth layer to form a plurality of base semiconductor portions 8 and a plurality of n-type portions obtained by dividing the regrowth layer. In this case, an active portion 9K and a p-type portion 9P may be formed as the compound semiconductor portion 9 on the n-type portion on the base semiconductor portion 8. That is, the trenches TR for dividing the first semiconductor portion S1 may be formed before the active portion 9K is formed, and the n-type portion may be formed on the first semiconductor portion S1 and then the trenches TR may be formed.

[0027] The base semiconductor portion 8 includes a low defect portion SD located above the mask portion 5, and the density of threading dislocations (dislocations extending in the Z-axis direction) in the low defect portion SD is 5×10 6 / cm 2 The threading dislocation density here can be determined, for example, by measuring the wafer surface (for example, the surface of the base semiconductor portion 8 or the compound semiconductor portion 9) by CL (cathode luminescence) (for example, by counting the number of black spots). The threading dislocation density of the low defect portion SD may be 1 / 5 or less of the threading dislocation density of the dislocation inheritance portion HD located on the opening K (on the seed portion 3). 8 / cm 2 or less. The basal plane dislocations may extend parallel to the c-plane (XY plane) of the base semiconductor portion 8. The basal plane dislocation density here can be obtained, for example, by dividing the wafer to expose the side surface of the low defect portion SD and subjecting the side surface to CL measurement of the dislocation density.

[0028] 7 and 8, the active portion 9K of the compound semiconductor portion 9 may include a light emitting portion LS, and the entire light emitting portion LS may overlap the low defect portion SD in a plan view. The size Ly of one side of the light emitting portion LS (for example, a side perpendicular to the adjacent trench TR) may be 80 μm or less, 40 μm or less, 20 μm or less, 10 μm or less, or 5 μm or less. In the first embodiment, since etching damage to the compound semiconductor portion 9 (particularly the active portion 9K) is avoided, the size Ly of one side of the light emitting portion LS may be small.

[0029] Fig. 9 is a partial cross-sectional view of the element portion of Example 1. As shown in Fig. 9, in the element portion DS, the compound semiconductor portion 9 (including the active portion 9K) may be in contact with at least a part of the side surface of the base semiconductor portion 8 (for example, the side surface exposed by the trench TR and the side surface facing the gap GP).

[0030] The first electrode E1, which is an anode, may be formed so as to overlap the low defect portion SD in a plan view and to be in contact with the compound semiconductor portion 9 (p-type portion 9P). When the nitride semiconductor of the base semiconductor portion 8 is an n-type, the second electrode E2, which is a cathode, may be formed so as to be in contact with the base semiconductor portion 8. The second electrode E2 may be formed so as to be in contact with the n-type portion 9N of the compound semiconductor portion 9.

[0031] 10 is a cross-sectional view showing the configuration of the semiconductor device of Example 1. The element portion DS transferred to the support substrate SK is peeled off from the support substrate SK to obtain a light emitting body 21 (e.g., an LED chip). Furthermore, the support substrate SK is divided to obtain a light emitting element 22 including the light emitting body 21 and its support body ST. Each of the light emitting body 21 and the light emitting element 22 can be referred to as a semiconductor device 20.

[0032] In the first embodiment, the element portion DS is bonded to the template substrate 7 through the opening portion K. Therefore, in order to increase the peeling yield, the width of the opening portion K may be reduced to weaken the bonding force. Specifically, the width of the opening portion K may be set to 8 μm or less, or may be set to 4 μm or less.

[0033] (template substrate) A heterogeneous substrate having a lattice constant different from that of a GaN-based semiconductor can be used as the main substrate 1. Examples of heterogeneous substrates include single crystal silicon (Si) substrates, sapphire (Al 2 O 3 ) substrate, silicon carbide (SiC) substrate, etc. The surface orientation of the main substrate 1 is, for example, the (111) surface of a silicon substrate, the (0001) surface of a sapphire substrate, and the 6H-SiC(0001) surface of a SiC substrate. These are merely examples, and any main substrate and surface orientation may be used as long as the first semiconductor portion S1 can be grown by the ELO method. The main substrate 1 may also be a SiC (bulk crystal) substrate, a GaN (bulk crystal) substrate, or an AlN (bulk crystal) substrate.

[0034] FIG. 11 is a cross-sectional view showing an example of the configuration of the template substrate. The template substrate 7 may be configured such that a seed portion 3 (e.g., AlN) and a mask pattern 6 are formed in this order on a main substrate 1 (e.g., a silicon substrate), or a multi-layered seed portion 3 (e.g., a lower layer portion including at least one of AlN and SiC, and an upper layer portion including a GaN-based semiconductor) and a mask pattern 6 are formed in this order on a main substrate 1 (e.g., a silicon substrate). The seed portion 3 may be formed locally (e.g., in a stripe shape) so as to overlap with the opening K in a plan view. The seed portion 3 may include a nitride semiconductor formed at a low temperature of 600° or less. In this way, warping of the semiconductor substrate (template substrate 7 and element portion DS) caused by the stress of the seed portion 3 can be reduced. The seed portion 3 can also be formed using a sputtering device (PSD: pulse sputter deposition, PLD: pulse laser deposition, etc.). Using a sputtering device has the advantages of low-temperature film formation and large-area film formation, and cost reduction. As shown in FIG. 11, the template substrate 7 may have a configuration in which a mask pattern 6 is formed on a main substrate 1 (for example, a SiC bulk crystal substrate or a GaN bulk crystal substrate).

[0035] The opening K of the mask pattern 6 functions as a growth initiation hole that exposes the seed portion 3 and initiates the growth of the first semiconductor portion S1, and the mask portion 5 of the mask pattern 6 functions as a selective growth mask that causes the first semiconductor portion S1 to grow laterally. In other words, the region of the seed portion 3 that is exposed at the opening K is the seed region, and the mask portion 5 is the growth inhibition region or selective growth region.

[0036] The mask portion 5 may be a single layer film including one of a silicon oxide film (SiOx), a titanium nitride film (TiN, etc.), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), and a metal film having a high melting point (e.g., 1000 degrees or higher), or a laminated film including at least two of these.

[0037] For example, a silicon oxide film having a thickness of about 100 nm to about 4 μm (preferably about 150 nm to about 2 μm) is formed on the entire surface of the seed portion 3 by using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. After that, the resist is patterned by using a photolithography method to form a resist having a plurality of stripe-shaped openings. After that, a part of the silicon oxide film is removed by a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form a plurality of openings K, and the resist is removed by organic cleaning to form the mask pattern 6. As another example, a silicon nitride film may be formed by using a sputtering device or a PECVD device. The silicon nitride film can withstand the film formation temperature of about 1000 degrees of the base semiconductor portion 8 even if it is thinner than the silicon oxide film. The thickness of the silicon nitride film can be about 5 nm to 4 μm.

[0038] The longitudinal (slit-shaped) openings K can be periodically arranged in the X direction. The width of the openings K may be about 0.1 μm to 20 μm. As the width of the openings K becomes smaller, the number of threading dislocations propagating from the openings K to the first semiconductor portion S1 decreases. Also, the low defect portion SD can be made larger.

[0039] Although a small amount of silicon oxide film may decompose and evaporate during the formation of the first semiconductor portion S1 and may be taken into the first semiconductor portion S1, a silicon nitride film and a silicon oxynitride film have the advantage of being difficult to decompose and evaporate at high temperatures. Therefore, the mask portion 5 may be a single layer film of silicon nitride film or silicon oxynitride film, or may be a laminated film in which a silicon oxide film and a silicon nitride film are formed in this order on the seed portion 3, or may be a laminated film in which a silicon nitride film and a silicon oxide film are formed in this order on the seed portion 3, or may be a laminated film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in this order on the base portion. In addition, the composition of oxygen and nitrogen in SiON may be controlled to form a desired oxynitride film.

[0040] Pinholes and other abnormalities in the mask portion 5 can be eliminated by performing organic cleaning after film formation, and then re-introducing the mask portion 5 into the film formation apparatus to form a film of the same type. A good quality mask portion 5 can also be formed by using a general silicon oxide film (single layer) and using such a film formation method again.

[0041] As an example of the template substrate 7, the main substrate 1 may be a silicon substrate having a (111) surface, the seed portion 3 may be an AlN layer (approximately 30 nm to 300 nm, for example 150 nm) as a lower layer, the seed portion 3 may be a GaN-based graded layer as an upper layer, and the mask portion 5 may be a laminated mask in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) are formed in this order. The GaN-based graded layer may be a first layer, an AlN layer (approximately 30 nm to 300 nm, for example 150 nm), a GaN-based graded layer as an upper layer, and a silicon oxide film (SiO2) and a silicon nitride film (SiN) as a second layer. 0.6 Ga 0.4 It may include an N layer (e.g., 300 nm) and a second GaN layer (e.g., 1 to 2 μm). For the mask portion 5, a CVD method (plasma chemical vapor deposition method) is used for forming the silicon oxide film and the silicon nitride film, and the thickness of the silicon oxide film can be, for example, 0.3 μm, and the thickness of the silicon nitride film can be, for example, 70 nm.

[0042] (First semiconductor part) In Example 1, the first semiconductor portion S1 (base semiconductor portion 8) was a GaN layer, and an MOCVD apparatus was used to perform ELO deposition of gallium nitride (GaN) on the above-mentioned template substrate 7. An example of the ELO deposition conditions is as follows: substrate temperature: 1120° C., growth pressure: 50 kPa, TMG (trimethylgallium): 22 sccm, NH 3 : 15 slm, V / III=6000 (ratio of the supply amount of group V raw material to the supply amount of group III raw material) can be adopted.

[0043] In this case, the first semiconductor portion S1 is selectively grown (vertical growth) on the seed portion 3 exposed in the opening portion K, and then grows laterally on the mask portion 5. Then, before the GaN crystal films growing laterally from both sides on the mask portion 5 meet each other, the lateral growth is stopped.

[0044] The width (size in the X direction) of the mask portion 5 was 50 μm, the width (size in the X direction) of the opening K was 5 μm, the horizontal width (size in the X direction) of the first semiconductor portion S1 was 53 μm, the width (size in the X direction) of the low defect portion SD was 24 μm, and the layer thickness (size in the Z direction) of the first semiconductor portion S1 was 5 μm. The aspect ratio of the first semiconductor portion S1 was 53 μm / 5 μm=10.6, which is a very high aspect ratio. The width of the mask portion 5 can be set according to the specifications of the compound semiconductor portion 9, etc. (for example, about 10 μm to 200 μm).

[0045] In the formation of the first semiconductor portion S1 in the first embodiment, a vertically grown layer growing in the Z direction (c-axis direction) is formed on the seed portion 3 exposed from the opening K, and then a laterally grown layer growing in the X direction (a-axis direction) is formed. At this time, by setting the thickness of the vertically grown layer to 10 μm or less, 5 μm or less, or 3 μm or less, the thickness of the laterally grown layer can be kept low and the lateral film formation rate can be increased.

[0046] FIG. 12 is a cross-sectional view showing an example of lateral growth of the first semiconductor portion (ELO semiconductor layer). As shown in FIG. 12, it is preferable to form an initial growth layer SL on the seed portion 3 (upper GaN layer) exposed from the opening K, and then grow the first semiconductor portion S1 laterally from the initial growth layer SL. The initial growth layer SL becomes the starting point of the lateral growth of the first semiconductor portion S1. The initial growth layer SL can be formed to a thickness of 20 nm to 5000 nm, for example, 50 nm to 400 nm, or 70 nm to 350 nm. By appropriately controlling the ELO film formation conditions, it is possible to control the growth of the first semiconductor portion S1 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0047] Here, deposition of the initial growth layer SL may be stopped just before the edge of the initial growth layer SL rises onto the upper surface of the mask portion 5 (at the stage where it is in contact with the upper end of the side surface of the mask portion 5) or just after it rises onto the upper surface of the mask portion 5 (i.e., at this timing, the ELO deposition conditions may be switched from the c-axis direction deposition conditions to the a-axis direction deposition conditions). In this way, the initial growth layer SL is grown laterally from a state in which it slightly protrudes from the mask portion 5, thereby suppressing the growth of the first semiconductor portion S1 in the c-axis direction (thickness direction), and the first semiconductor portion S1 can be grown laterally at high speed with high crystallinity, and raw material consumption is also reduced. This allows the first semiconductor portion S1 (crystal of a nitride semiconductor such as GaN) with low defects to be formed thinly, widely, and at low cost. The aspect ratio of the first semiconductor portion S1 (ratio of size in the X direction to thickness) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more.

[0048] (Compound semiconductor part and electrodes) The compound semiconductor section 9 can be formed by, for example, MOCVD. In the compound semiconductor section 9 of Fig. 7, for example, the n-type section 9N is an n-GaN layer, the active section 9K including the light emitting section LS is an MQW (Multi-Quantum Well) including an InGaN layer and a GaN layer, and the p-type section 9P is a laminated structure of a p-AlGaN layer and a p-GaN layer, so that the element section DS can be an LED (Light Emitting Diode). As described above, the n-type section 9N may be formed from a regrowth layer on the first semiconductor section S1.

[0049] The first electrode E1 (anode) and the second electrode E2 (cathode) may have a single-layer structure or a multi-layer structure containing at least one of Al, Ag, Cr, Pd, Pt, Au, Ni, Ti, V, W, Cu, Zn, Sn, and In, and may include an alloy layer. At least one of the first and second electrodes E1 and E2 may have a laminated structure of a transparent conductive film (such as ITO (Indium Tin Oxide)) and a light-reflective metal film (such as Ag, Al, Ti).

[0050] (Modification) FIG. 13 is a plan view showing another example of the method for manufacturing the semiconductor device according to the first embodiment. As shown in FIG. 13, the first semiconductor portion S1 including a nitride semiconductor may be formed in a planar shape by using the ELO method. In this case, during film formation by the ELO method, semiconductor crystals growing in the lateral direction (X direction) in opposite directions on the mask portion 5 may be caused to meet on the mask portion 5. The meeting occurs at approximately the center of the adjacent openings K (the center of the mask portion 5), and a void (air gap) may be formed immediately below the meeting portion. This void is formed inside the first semiconductor portion S1 generated by the meeting, and plays a role of releasing the distortion after the meeting. In addition, a plurality of trenches TR extending in the X direction and a plurality of trenches TR extending in the Y direction are formed in the first semiconductor portion S1, thereby forming a plurality of island-shaped base semiconductor portions 8.

[0051] Fig. 14 is a flow chart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 15 is a plan view showing the method for manufacturing the semiconductor device according to Fig. 14. Fig. 16 is a cross-sectional view showing the method for manufacturing the semiconductor device according to Fig. 14. As shown in Figs. 14 to 16, a joint portion between the first semiconductor portion S1 and the seed portion 3 (a portion exposed from the opening portion K) may be removed by at least one of the plurality of trenches TR formed in the first semiconductor portion S1. In this case, an anchor film AF can be formed after forming the plurality of trenches TR, and then a compound semiconductor portion 9 can be formed, so that the plurality of island-shaped base semiconductor portions 8 are not dispersed on the template substrate 7.

[0052] The anchor film AF contacts the side surface of the base semiconductor portion 8 and the mask portion 5, and anchors the base semiconductor portion 8 to the template substrate 7. As the anchor film AF, a dielectric film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, a silicon oxynitride film, an aluminum oxide-silicon film, an aluminum oxynitride film, a zirconium oxide film, a titanium oxide film, or a tantalum oxide film can be used. By using a silicon oxide film, a silicon nitride film, an aluminum oxide-silicon film, a silicon oxynitride film, or a titanium nitride film as the anchor film AF, the nitride semiconductor of the compound semiconductor portion 9 does not grow on the anchor film AF, and therefore the compound semiconductor portion 9 can be formed in an island shape. When the element portion DS is transferred, at least a part of the anchor film AF may remain on the template substrate 7 or may be attached to the element portion DS.

[0053] For example, a resist mask is used to form a trench TR by dry etching, an anchor film AF is formed on the entire surface by sputtering or EB (Electron Beam Deposition), and then the resist mask is removed to lift off unnecessary parts of the anchor film AF. By using the anchor film AF to fix the chip, it also functions to protect the chip side (it is known that etching damage occurs on the side of a trench formed by dry etching) and to recover damage. Because the anchor film AF is not conductive, there is no risk of electrical leakage even if it ultimately remains on the chip.

[0054] Fig. 17 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the embodiment 1. In Fig. 14, the anchor film AF is formed before the formation of the compound semiconductor portion 9, but this is not limited to this. As shown in Fig. 17, the anchor film AF can also be formed after the formation of the compound semiconductor portion 9.

[0055] 18 is a flowchart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. In the examples shown in FIGS. 14 and 16, the second electrode is formed on the top surface of the base semiconductor portion 8. 18, the first electrode E1 may be formed after the compound semiconductor portion 9 is formed, and the second electrode E2 (cathode) may be formed on the lower surface (rear surface) of the base semiconductor portion 8 after the element portion DS is transferred to the support substrate SK.

[0056] FIG. 19 is a flow chart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a plan view showing the method for manufacturing the semiconductor device according to FIG. 19. As shown in FIGS. 19 and 20, the mask portion 5 may be removed after the base semiconductor portion 8 is formed. For example, the mask portion 5 can be removed by etching by injecting an etchant into the trenches TR. This makes it easier to transfer the element portion DS to the support substrate SK. To increase the peeling (transfer) yield, the width of the opening portion K may be reduced to weaken the bonding force between the base semiconductor portion 8 and the template substrate 7. Specifically, the width of the opening portion K may be set to 8 μm or less, or 4 μm or less.

[0057] FIG. 21 is a flow chart showing another example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a plan view showing the method for manufacturing the semiconductor device according to FIG. 21. As shown in FIGS. 21 and 22, after the compound semiconductor portion 9 is formed, the base semiconductor portion 8 and the compound semiconductor portion 9, which are nitride semiconductor crystals, may be cleaved, for example, at the m-plane ((1-100) plane) HF having a normal parallel to the Y direction. When the element portion DS is to be a semiconductor laser, two cleavage planes facing each other in the Y direction (m-axis direction) may be formed in the compound semiconductor portion 9, and these cleavage planes may be used as cavity end faces. In FIG. 21, cleavage is performed at the m-plane HF before transfer to the support substrate SK, and transfer is performed after cleavage, but this is not limited to the above. Cleavage may also be performed on the support substrate SK after transfer. In this case, each of the n-type portion 9N and the p-type portion 9P of the compound semiconductor portion 9 may include an optical guide layer and a cladding layer having a refractive index larger than that of the active portion 9K, and the p-type portion 9P may have a ridge (current confinement portion). Specifically, the n-type portion 9N may include a first contact layer (e.g., an n-type GaN layer), a first cladding layer (e.g., an n-type AlGaN layer), and a first optical guide layer (e.g., an n-type GaN layer). The active layer 9K may include an MQW (Multi-Quantum Well) structure including an InGaN layer. The p-type portion 9P may include an electron blocking layer (e.g., a p-type AlGaN layer), a second optical guide layer (e.g., a p-type GaN layer), a second cladding layer (e.g., a p-type AlGaN layer), and a second contact layer (e.g., a p-type GaN layer). As described above, the n-type portion 9N may be formed from a regrowth layer on the first semiconductor portion S1.

[0058] (Semiconductor Devices) 23 to 27 are perspective views showing the configuration of a semiconductor device obtained in Example 1. The manufacturing method of FIG. 3 can obtain, for example, the light emitter (LED chip) 21 shown in FIG. 23 or FIG. 24. In FIG. 23, the second electrode E2 is in contact with the base semiconductor portion 8, and in FIG. 24, the second electrode E2 is in contact with the n-type portion 9N of the compound semiconductor portion 9. The manufacturing method of FIG. 14 can obtain, for example, the light emitter 21 shown in FIG. 25. The manufacturing method of FIG. 18 can obtain, for example, the light emitter 21 shown in FIG. 26. The manufacturing method of FIG. 21 can obtain, for example, the light emitter 21 (semiconductor laser chip) shown in FIG. 27. The ridge RJ is a current confinement portion, and laser light is emitted from the cleavage plane (m-plane) of the active portion 9K of the compound semiconductor portion 9. The ridge RJ can be formed by dry etching the p-type portion 9P, and there is little risk that this etching will adversely affect the active portion 9K. A light reflecting film may be formed on the cleavage plane (m-plane) of the active portion 9K in FIG. 27. The light reflecting film can be formed, for example, of a plurality of dielectric films. The material of the dielectric film is SiO 2 , Al 2 O 3 , AlN, AlON, SiON, Nb 2 O 5 , Ta 2 O5 , ZrO 2 Also, a laminated film containing a plurality of these materials can be used as the light reflecting film.

[0059] Fig. 28 is a schematic diagram showing the configuration of an electronic device including the semiconductor device obtained in Example 1. The electronic device 70 in Fig. 28 includes the semiconductor device 20 obtained in Example 1 (e.g., the light emitter 21, the light emitting element 22), a drive circuit 50 that drives the semiconductor device 20, and a control circuit 60 that controls the drive circuit 50. The control circuit 60 includes, for example, a processor and a memory. Examples of the electronic device 70 include a display device, a lighting device, a light receiving device, a communication device, a measuring device, an information processing device, a medical device, an electric vehicle (EV), and the like.

[0060] Example 2 Fig. 29 is a flowchart showing a method for manufacturing a semiconductor device according to Example 2. Fig. 30 is a plan view showing the method for manufacturing a semiconductor device according to Example 2. Fig. 31 is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 2.

[0061] 29 to 31, the following steps are performed: preparing a template substrate 7 including a main substrate 1 and a mask pattern 6 including an opening K and a mask portion 5; forming a first semiconductor portion S1 including a nitride semiconductor (e.g., a GaN-based semiconductor) from the opening K to the mask portion 5; dividing the first semiconductor portion S1 into a plurality of base semiconductor portions 8 by cleaving the first semiconductor portion S1 at an m-plane 8F of the nitride semiconductor; forming a compound semiconductor portion 9 including a nitride semiconductor (e.g., a GaN-based semiconductor) above at least one of the plurality of base semiconductor portions 8; forming a first electrode E1 and a second electrode E2; and transferring an element portion (device stack) DS including the base semiconductor portion 8 and the compound semiconductor portion 9 from the template substrate 7 to a support substrate SK. The compound semiconductor portion 9 may include an active portion (active layer) 9K.

[0062] By dividing the elements by cleavage, the volume of the first semiconductor portion S1 that is lost is smaller than in the case of dividing the elements by dry etching, for example, and the wafer can be used effectively (as elements).

[0063] For example, when a heterogeneous substrate (such as a Si substrate) is used for the main substrate 1, the substrate (template substrate 7 and first semiconductor portion S1) may be warped due to stress resulting from a difference in thermal expansion coefficient between the main substrate 1 and the first semiconductor portion S1. If this warping occurs when forming the compound semiconductor portion 9, the temperature of the growth surface becomes non-uniform, and the composition of the compound semiconductor portion 9 (for example, the indium concentration of the active portion 9K) may vary within the surface, which may deteriorate the light emission characteristics. By cleaving the first semiconductor portion S1 before forming the compound semiconductor portion 9, the stress of the first semiconductor portion S1 is relaxed and the warping of the substrate is reduced, which may improve the light emission characteristics (for example, the uniformity of the light emission wavelength within the surface). The first semiconductor portion S1 may be scribed to naturally cause the cleavage of the first semiconductor portion S1. The m-plane cleavage of the nitride semiconductor crystal may naturally proceed with the release of the internal stress. The compound semiconductor portion 9 may be formed by forming an n-type portion 9N, an active portion 9K, and a p-type portion 9P in this order.

[0064] Since an island-shaped base semiconductor portion 8 separated from its surroundings is formed by cleavage of the first semiconductor portion S1, an island-shaped compound semiconductor portion 9 can be formed on the base semiconductor portion 8. If the compound semiconductor portion 9 does not have an island shape (a state separated from its surroundings), it is possible to obtain the island-shaped compound semiconductor portion 9 by again cleaving or patterning the nitride semiconductor crystal that is the basis of the compound semiconductor portion 9.

[0065] A regrowth layer (e.g., an n-type GaN-based semiconductor) may be formed on the first semiconductor portion S1, and the first semiconductor portion S1 and the regrowth layer may be cleaved to form a plurality of base semiconductor portions 8 and a plurality of n-type portions obtained by dividing the regrowth layer. In this case, an active portion 9K and a p-type portion 9P may be formed as the compound semiconductor portion 9 on the n-type portion on the base semiconductor portion 8.

[0066] 32 is a block diagram showing a semiconductor device manufacturing apparatus of Example 2. The semiconductor device manufacturing apparatus 40 may include an apparatus 40A for preparing a template substrate 7, an apparatus 40B for forming a first semiconductor portion S1, an apparatus 40H for cleaving the first semiconductor portion S1, an apparatus 40D for forming a compound semiconductor portion 9, an apparatus 40E for forming a first electrode E1 and a second electrode E2, an apparatus 40F for transferring an element portion DS to a support substrate SK, and an apparatus 40G. The apparatus 40G controls the apparatuses 40A, 40B, 40H and the apparatuses 40D to 40F.

[0067] When the device portions DS separated on the wafer by cleavage are transferred to the support substrate SK, selective peeling may be performed across a plurality of device portions, for example, every two or three device portions. This is possible because the base semiconductor portion 8 is separated into small pieces on the wafer. Furthermore, when device separation is performed by cleavage, the interval between adjacent device portions is narrow, but each device portion is bonded to the template substrate 7 through an opening, so that only the desired device portion can be selectively peeled off.

[0068] Furthermore, by selectively transferring every few element portions onto the support substrate SK, the size of each element portion can be increased when dividing the support substrate SK into multiple pieces each mounting one chip (e.g., a light-emitting element, a light-receiving element) after transfer onto the support substrate SK, making it easier to handle the pieces and mount them in the desired package.

[0069] Example 3 Fig. 33A and Fig. 33B are a flowchart showing a method for manufacturing a semiconductor device according to Example 3. Fig. 34 is a plan view showing the method for manufacturing a semiconductor device according to Example 3. Fig. 35 is a cross-sectional view showing the method for manufacturing a semiconductor device according to Example 3.

[0070] In Example 3, as shown in FIG. 33A, the following steps may be performed: preparing a semiconductor substrate 11 in which a first semiconductor portion S1 including a nitride semiconductor is formed on a template substrate 7; forming a second semiconductor portion S2 on the first semiconductor portion S1; and separating the first and second semiconductor portions S1 and S2 into a plurality of element portions DS by cleaving the first and second semiconductor portions S1 and S2.

[0071] 33B, the steps include preparing a template substrate 7 including a main substrate 1 and a mask pattern 6 including an opening K and a mask portion 5, forming a first semiconductor portion S1 including a nitride semiconductor (e.g., a GaN-based semiconductor) from the opening K to the mask portion 5, forming a second semiconductor portion (second semiconductor layer) S2 including a nitride semiconductor on the first semiconductor portion S1, forming a first electrode E1 and a second electrode E2, separating the first and second semiconductor portions S1 and S2 into a plurality of element portions DS by cleaving the first and second semiconductor portions S1 and S2 at the m-plane HF of the nitride semiconductor, and transferring the element portion (device stack) DS including a base semiconductor portion 8 and a compound semiconductor portion 9 from the template substrate 7 to a support substrate SK. The compound semiconductor portion 9 may include an active portion 9K.

[0072] The element portion DS may be an LED or a semiconductor laser. When the element portion DS is a semiconductor laser, two cleavage planes HF facing each other in the Y direction (m-axis direction) are formed in the compound semiconductor portion 9, and these cleavage planes HF can be used as cavity end faces.

[0073] A second semiconductor portion S2 can be formed on the first semiconductor portion S1 via a regrowth layer (e.g., an n-type GaN-based semiconductor), and multiple element portions DS can be formed by cleaving the first semiconductor portion S1, the regrowth layer, and the second semiconductor portion S2.

[0074] 36 is a block diagram showing a semiconductor device manufacturing apparatus according to the third embodiment. The semiconductor device manufacturing apparatus 40 may include an apparatus 40A for preparing a template substrate 7, an apparatus 40B for forming a first semiconductor portion S1, an apparatus 40S for forming a second semiconductor portion S2, an apparatus 40E for forming a first electrode E1 and a second electrode E2, an apparatus 40J for cleaving the first and second semiconductor portions S1 and S2, an apparatus 40F for transferring an element portion DS to a support substrate SK, and an apparatus 40G. The apparatus 40G controls the apparatuses 40A, 40B, 40S, 40E, 40J, and 40F.

[0075] When the device portions DS separated on the wafer by cleavage are transferred to the support substrate SK, selective peeling may be performed across a plurality of device portions, for example, every two or three device portions. This is possible because the base semiconductor portion 8 is separated into small pieces on the wafer. Furthermore, when device separation is performed by cleavage, the interval between adjacent device portions is narrow, but each device portion is bonded to the template substrate 7 through an opening, so that only the desired device portion can be selectively peeled off.

[0076] Furthermore, by selectively transferring every few element parts onto the support substrate SK, the size of each piece can be increased when dividing the support substrate SK into multiple pieces each carrying one chip after transfer onto the support substrate SK, making it easier to handle the pieces and mount them in the desired package.

[0077] Example 4 In the first to third embodiments, the first semiconductor portion S1 may be a GaN layer, but is not limited thereto. The first semiconductor portion S1 in the first to third embodiments may be an InGaN layer, which is a GaN-based semiconductor layer. The lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000° C. This is because at high temperatures, the vapor pressure of indium increases and indium is not effectively incorporated into the film. The low deposition temperature has the effect of reducing the mutual reaction between the mask portion 5 and the InGaN layer. In addition, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable for indium to be incorporated into the InGaN layer at an In composition level of 1% or more, since this further reduces the reactivity with the mask portion 5. It is preferable to use triethylgallium (TEG) as the gallium source gas.

[0078] The above-described technical aspects are intended to be illustrative and explanatory, and not restrictive. Based on these examples and descriptions, many variations are possible, as will be apparent to those skilled in the art. [Explanation of symbols]

[0079] 1 Main Board 3 Seed Section 5 Mask section 6 Mask Pattern 7 Template Substrate 8 Base Semiconductor Section 9. Compound Semiconductor Department 9K active part 11 Semiconductor substrate 20 Semiconductor Devices 21 Luminous object 22 Light emitting element 40 Semiconductor device manufacturing equipment K opening S1 First Semiconductor Division S2 Second Semiconductor Department TR Trench DS element part RJ Ridge SD Low dislocation area HD Transposition Succession E1 1st electrode E2 Second Electrode ST Support SK Support Substrate

Claims

1. preparing a semiconductor substrate having a template substrate and a plurality of first semiconductor portions located on the template substrate and including a nitride semiconductor, each of the plurality of first semiconductor portions having an elongated shape whose longitudinal direction is a direction perpendicular to an m-plane of the nitride semiconductor, and the plurality of first semiconductor portions being arranged adjacent to each other in a direction parallel to the m-plane; forming a second semiconductor portion on at least one of the plurality of first semiconductor portions; and separating, on the template substrate, at least one of the plurality of first semiconductor portions and the second semiconductor portion along the m-plane into a plurality of element portions.

2. the plurality of element portions include a first element portion and a second element portion, The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of transferring the first element portion to a supporting substrate without transferring the second element portion.

3. the plurality of element portions are aligned in a direction perpendicular to the m-plane, The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of transferring every several element portions onto a support substrate.

4. The method for manufacturing a semiconductor device according to claim 2 , further comprising the step of dividing the support substrate into a plurality of individual pieces after the transferring step.

5. the template substrate has a main substrate, a mask portion and an opening portion located above the main substrate; the mask portion and the opening have a longitudinal direction perpendicular to the m-plane, the mask portion and the opening portion are aligned in a direction parallel to the m-plane, The method for manufacturing a semiconductor device according to claim 1 , wherein at least one of the plurality of first semiconductor portions is located across from the opening onto the mask portion.

6. the semiconductor device is a laser element; 4. The method for manufacturing a semiconductor device according to claim 1, wherein the cleavage plane formed by cleavage along the m-plane is a cavity end facet.

7. The template substrate includes a main substrate, 4. The method for manufacturing a semiconductor device according to claim 1, wherein the main substrate is not divided when at least one of the plurality of first semiconductor portions is cleaved.

8. 4. The method for manufacturing a semiconductor device according to claim 1, wherein each element portion includes an active portion and a p-type portion.

9. The method of claim 5 , wherein the gaps between the first semiconductor portions extend in a longitudinal direction of the opening.

10. The method for manufacturing a semiconductor device according to claim 5 , wherein the template substrate includes a seed portion exposed from the opening, and at least one of the plurality of first semiconductor portions is bonded to the seed portion.

11. The opening is a slit, The method for manufacturing a semiconductor device according to claim 10 , wherein the seed portion is formed in an elongated shape so as to overlap the opening portion.

12. The method for manufacturing a semiconductor device according to claim 10 , wherein in at least one of the first semiconductor portions, a portion located above the mask portion has a lower threading dislocation density than a portion located above the seed portion.

13. 4. The method for manufacturing a semiconductor device according to claim 1, wherein cleavage is allowed to proceed naturally by scribing at least one of the first semiconductor portions.

14. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming one or more electrodes above the second semiconductor portion before forming the plurality of element portions.

15. The method for manufacturing a semiconductor device according to claim 14 , wherein the one or more electrodes include a first electrode and a second electrode aligned in a direction parallel to an m-plane.

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