Electrostatic chuck

The electrostatic chuck with a dielectric substrate and sealing rings of varying surface roughness addresses the issue of plasma-induced by-product adhesion on substrates, enhancing gas flow and reducing particle contamination.

JP2025082880APending Publication Date: 2025-05-30TOTO LTD
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Patent Information

Application Number
JP2023196394
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-11-20
Publication Date
2025-05-30

AI Technical Summary

Technical Problem

During semiconductor processing, plasma can reach the back surface of substrates and adhere as by-products, leading to particle contamination.

Method used

The electrostatic chuck incorporates a dielectric substrate with a mounting surface and multiple sealing rings, where the first sealing ring has a larger surface roughness than the second, enhancing gas flow and suppressing plasma movement.

Benefits of technology

This configuration increases the gas flow rate through the first sealing ring, effectively suppressing the adhesion of by-products to the substrate's back surface and maintaining consistent processing conditions over time.

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Abstract

To provide an electrostatic chuck which can suppress a by-product from adhering to a substrate.SOLUTION: An electrostatic chuck 10 comprises: a dielectric substrate 100; and a plurality of seal rings 150 which is annular protrusions formed on the dielectric substrate 100. The plurality of seal rings 150 includes: a first seal ring 151 located at a position at the outermost peripheral end; and a second seal ring 152 located at a position on the inner side of the first seal ring 151. In the electrostatic chuck 10, the surface roughness of the first seal ring 151 is greater than that of the second seal ring 152.SELECTED DRAWING: Figure 1
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Description

Technical Field

[0001] The present invention relates to an electrostatic chuck.

Background Art

[0002] For example, in a semiconductor manufacturing apparatus such as an etching apparatus, an electrostatic chuck is provided as a device for adsorbing and holding a substrate such as a silicon wafer to be processed. As described in Patent Document 1 below, the electrostatic chuck includes a dielectric substrate provided with an adsorption electrode and a base plate for supporting the dielectric substrate, and these have a configuration joined to each other. When a voltage is applied to the adsorption electrode, an electrostatic force is generated, and the substrate placed on the dielectric substrate is adsorbed and held.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] During the processing of a substrate in a semiconductor manufacturing apparatus, a part of the plasma may reach the back surface of the substrate or the like and adhere as a by-product (deposit). Such adhesion of by-products is not preferable because it becomes a source of particles.

[0005] The present invention has been made in view of such problems, and an object thereof is to provide an electrostatic chuck capable of suppressing the adhesion of by-products to a substrate.

Means for Solving the Problems

[0006] In order to solve the above problems, the electrostatic chuck according to the present invention includes a dielectric substrate having a mounting surface on which an object to be adsorbed is placed, and a plurality of sealing rings formed on the dielectric substrate, which are annular protrusions and the tip surfaces of which are part of the mounting surface. The plurality of sealing rings include a first sealing ring disposed at the outermost peripheral end position of the mounting surface, and a second sealing ring disposed at a position inside the first sealing ring without sandwiching another sealing ring between the first sealing ring and the second sealing ring. In this electrostatic chuck, the surface roughness of the first sealing ring is larger than the surface roughness of the second sealing ring.

[0007] In the electrostatic chuck having such a configuration, during the processing of the substrate, the flow rate of the gas leaking to the outside through the first sealing ring increases. On the back surface side of the substrate and in the outer peripheral portion, since the gas flow as described above continuously occurs, the movement of the plasma toward the back surface and side surfaces of the substrate is suppressed by the gas flow. As a result, the adhesion of by-products to the back surface of the substrate and the like can be suppressed as compared with the conventional case.

Effects of the Invention

[0008] According to the present invention, it is possible to provide an electrostatic chuck capable of suppressing the adhesion of by-products to a substrate.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. For ease of understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and redundant descriptions are omitted.

[0011] The electrostatic chuck 10 according to this embodiment adsorbs and holds a substrate W to be processed by electrostatic force inside a semiconductor manufacturing apparatus (not shown) such as an etching apparatus. The substrate W to be adsorbed is, for example, a silicon wafer. The electrostatic chuck 10 may be used in apparatuses other than semiconductor manufacturing apparatuses.

[0012] FIG. 1 shows, as a schematic cross-sectional view, the configuration of the electrostatic chuck 10 in a state where the substrate W is adsorbed and held. The electrostatic chuck 10 includes a dielectric substrate 100 and a base plate 200.

[0013] The dielectric substrate 100 is a substantially disk-shaped member made of a ceramic sintered body. The dielectric substrate 100 contains, for example, high-purity aluminum oxide (Al 2 O 3 ), but may contain other materials. The purity, type, additives, etc. of the ceramics in the dielectric substrate 100 can be appropriately set in consideration of the plasma resistance, etc. required for the dielectric substrate 100 in the semiconductor manufacturing apparatus.

[0014] The upper surface 110 of the dielectric substrate 100 in FIG. 1 is the "placement surface" on which the substrate W is placed. Also, the lower surface 120 of the dielectric substrate 100 in FIG. 1 is the "surface to be joined" that is joined to the base plate 200 via the joining layer 300. The direction along the direction perpendicular to the surface 110 and the viewpoint when viewing the electrostatic chuck 10 from the surface 110 side will also be referred to as "top view" hereinafter.

[0015] An adsorption electrode 130 is embedded inside the dielectric substrate 100. The adsorption electrode 130 is a thin flat plate-like layer formed of a metal material such as tungsten, for example, and is arranged to be parallel to the surface 110. As the material of the adsorption electrode 130, in addition to tungsten, molybdenum, platinum, palladium, etc. may also be used. When a voltage is applied to the adsorption electrode 130 from the outside through a power supply path (not shown), an electrostatic force is generated between the surface 110 and the substrate W, and thereby the substrate W is adsorbed and held. As the configuration of the above power supply path, various known configurations can be adopted. The adsorption electrode 130 may be provided only one as a so-called "unipolar" electrode as in this embodiment, or may be provided two as a so-called "bipolar" electrode.

[0016] As shown in FIG. 1, a space SP is formed between the dielectric substrate 100 and the substrate W. When a process such as etching is performed in the semiconductor manufacturing apparatus, helium gas for temperature adjustment is supplied to the space SP from the outside through a gas hole 114 (not shown in FIG. 1, refer to FIG. 2). By interposing helium gas between the dielectric substrate 100 and the substrate W, the thermal resistance between the two is adjusted, and thereby the temperature of the substrate W is maintained at an appropriate temperature. Note that the gas for temperature adjustment supplied to the space SP may be a gas of a type different from helium.

[0017] FIG. 2 is a top view of the dielectric substrate 100. As shown in the figure, a seal ring 150 and dots 113 are provided on the surface 110 which is the mounting surface, and the above space SP is formed around these. Note that the illustration of the dots 113 is omitted in FIG. 1.

[0018] The seal ring 150 is an annular protrusion provided as a wall partitioning the space SP. A plurality of seal rings 150 are provided and arranged substantially concentrically in a top view. The front end surface (the upper end surface in FIG. 1) of each seal ring 150 forms part of the surface 110 and abuts against the substrate W. In the present embodiment, a total of two seal rings 150 are provided, whereby the space SP is divided into two. With such a configuration, the pressure of the helium gas in each space SP can be individually adjusted, and the surface temperature distribution of the substrate W during processing can be made closer to uniform.

[0019] The seal ring 150 arranged on the outer side is hereinafter also referred to as the "first seal ring 151". Further, the seal ring 150 arranged on the inner side is hereinafter also referred to as the "second seal ring 152".

[0020] The first seal ring 151 is the seal ring 150 arranged at the outermost peripheral end position of the placement surface, which is the surface 110. The second seal ring 152 is the seal ring 150 arranged at a position inside the first seal ring 151 without sandwiching another seal ring 150 between the first seal ring 151. Another seal ring 150 may be further provided inside the second seal ring 152.

[0021] The portion marked with the reference numeral "116" in FIGS. 1 and 2 is the bottom surface of the space SP. Hereinafter, this portion is also referred to as the "bottom surface 116". The seal ring 150, together with the dots 113 described below, is formed as a result of digging down a part of the surface 110 to the position of the bottom surface 116.

[0022] The dot 113 is a circular protrusion protruding from the bottom surface 116. As shown in FIG. 2, a plurality of dots 113 are provided and are arranged substantially evenly and dispersedly on the placement surface of the dielectric substrate 100. The upper end surface of each dot 113 forms part of the surface 110 and abuts against the substrate W. By providing a plurality of such dots 113, the deflection of the substrate W is suppressed.

[0023] As shown in FIG. 2, a plurality of gas holes 114 are formed in the dielectric substrate 100. In FIG. 1, the illustration of the gas holes 114 is omitted. The gas holes 114 are holes for supplying helium gas to the space SP, and are through holes formed so as to extend vertically from the surface 120 toward the surface 110 side. The helium gas supplied from the outside passes through a gas flow path (not shown) formed inside the base plate 200 and is then supplied to the space SP through the gas holes 114.

[0024] In the present embodiment, a plurality of gas holes 114 are connected to each of the two divided spaces SP. A porous body formed of, for example, alumina or the like may be disposed inside the gas holes 114. With such a configuration, it is possible to suppress the occurrence of dielectric breakdown in the path through the gas holes 114 while ensuring the gas flow in the gas holes 114.

[0025] Grooves may be formed on the bottom surface 116 of the space SP for the purpose of increasing the in-plane diffusion rate of helium gas.

[0026] Lift pin holes are formed in the dielectric substrate 100 and the base plate 200 so as to penetrate them linearly, but their illustration is omitted in FIGS. 1 and 2. A total of three lift pin holes are formed and are arranged so as to be equally spaced at 120 degrees. The substrate W is attached to and detached from the surface 110 of the dielectric substrate 100 by lift pins that move up and down through the lift pin holes. A seal surface may be formed around the lift pin holes to separate the inside of the lift pin holes from the space SP.

[0027] The base plate 200 is a substantially disk-shaped member that supports the dielectric substrate 100. The base plate 200 is formed of a metal material such as aluminum, for example. The upper surface 210 of the base plate 200 in FIG. 1 is a "surface to be joined" that is joined to the dielectric substrate 100 via the joining layer 300.

[0028] The bonding layer 300 is a layer provided between the dielectric substrate 100 and the base plate 200 and bonds the two together. The bonding layer 300 is formed by curing an adhesive made of an insulating material. In the present embodiment, a silicone adhesive is used as the above adhesive. However, the bonding layer 300 may be formed by curing other types of adhesives. In any case, as the material of the bonding layer 300, it is preferable to use a material having as high a thermal conductivity as possible so that the thermal resistance between the dielectric substrate 100 and the base plate 200 is reduced.

[0029] An insulating film may be formed on the surface of the base plate 200. As the insulating film, for example, an alumina film formed by thermal spraying can be used. By covering the surface of the base plate 200 with an insulating film, the dielectric breakdown voltage of the base plate 200 can be increased.

[0030] A refrigerant flow path 250 for passing a refrigerant is formed inside the base plate 200. When a process such as etching is performed in the semiconductor manufacturing apparatus, the refrigerant is supplied from the outside to the refrigerant flow path 250, and thereby the base plate 200 is cooled. The heat generated in the substrate W during the process is transmitted to the refrigerant through the helium gas in the space SP, the dielectric substrate 100, and the base plate 200, and is discharged to the outside together with the refrigerant.

[0031] The configurations of the first seal ring 151 and the second seal ring 152 will be further described. In the dielectric substrate 100 according to the present embodiment, the surface roughness at the tip surface of the outer first seal ring 151 is larger than the surface roughness at the tip surface of the inner second seal ring 152. The "tip surface" of the first seal ring 151 or the second seal ring 152 refers to the surface that is part of the mounting surface 110. The surface roughness at the tip surface of the first seal ring 151 is hereinafter simply referred to as the "surface roughness of the first seal ring 151". Similarly, the surface roughness at the tip surface of the second seal ring 152 is hereinafter simply referred to as the "surface roughness of the second seal ring 152".

[0032] The surface roughness of the first seal ring 151 falls within a range of, for example, from 0.10 μm to 0.20 μm in terms of arithmetic mean roughness (Ra). The surface roughness of the second seal ring 152 falls within a range of, for example, from 0.05 μm to 0.10 μm in terms of arithmetic mean roughness (Ra). These numerical values are merely examples. Each surface roughness may not fall within the above range as long as it can achieve the effects to be described later.

[0033] As a method for making the surface roughness of the first seal ring 151 different from that of the second seal ring 152, for example, after simultaneously forming the first seal ring 151 and the second seal ring 152 by processing such as sandblasting, while masking the whole except the first seal ring 151, further blasting treatment, etching treatment, etc. may be performed only on the tip surface of the first seal ring 151.

[0034] In the present embodiment, the width of the first seal ring 151 (the dimension along the radial direction, the same applies hereinafter) is larger than the width of the second seal ring 152. The width of the first seal ring 151 is a dimension that falls within a range of, for example, from 3.0 mm to 4.0 mm, and the width of the second seal ring 152 is a dimension that falls within a range of, for example, from 0.2 mm to 1.0 mm. These numerical values are merely examples, and any of the dimensions may be outside the above range.

[0035] The reason for the above configuration will be described. During the processing of the substrate W in the semiconductor manufacturing apparatus, a part of the plasma used for etching or the like reaches up to the back surface of the substrate W (the surface on the side of the dielectric substrate 100) and may adhere as a by-product (depo). It is known that the adhesion of such by-products can be a source of particles, so it is preferable to suppress it as much as possible.

[0036] Therefore, in the electrostatic chuck 10 according to the present embodiment, the surface roughness of the first seal ring 151 is made larger than the surface roughness of the second seal ring 152. In the electrostatic chuck 10 configured in this way, during the processing of the substrate W, the flow rate of the helium gas leaking to the outside through the first seal ring 151 increases. On the back surface side and the outer peripheral side portion of the substrate W, since the flow of the helium gas as described above continuously occurs, the movement of the plasma toward the back surface and side surfaces of the substrate W is suppressed by the flow of the helium gas. As a result, the adhesion of by-products to the back surface or the like of the substrate W can be suppressed as compared with the conventional case.

[0037] Further, when the flow rate of the helium gas leaking from the first seal ring 151 is increased as in the present embodiment, depending on the pressure range of the helium gas, the heat of the outer peripheral side portion of the substrate W (specifically, the portion outside the second seal ring 152) is easily taken away by the helium gas. By efficiently cooling the outer peripheral side portion of the substrate W where the temperature is likely to rise by the flow of the helium gas, an effect of making the in-plane temperature distribution of the substrate W during processing closer to uniform can also be expected.

[0038] In a conventional electrostatic chuck, the tip surface of the seal ring at the outermost periphery may be gradually eroded from the outer peripheral side as the plasma reaches, and its surface roughness may gradually increase. Such a change in surface roughness is not preferable because it causes the leakage amount of helium gas to change with time. On the other hand, in the present embodiment, since the surface roughness of the first seal ring 151 at the outermost periphery is large from the beginning, it is difficult for a change in surface roughness over time due to the arrival of plasma to occur. Therefore, an effect that the processing of the substrate W by the semiconductor manufacturing apparatus can be performed under the same conditions for a relatively long period can also be expected.

[0039] The change in the surface roughness of the first seal ring 151 as described above progresses from the outer peripheral side end portion of the first seal ring 151 toward the inside. Therefore, after a long period of time, the width of the range that can function as the so-called "sealing surface" among the upper end surfaces of the first seal ring 151 may become narrow.

[0040] Therefore, in the present embodiment, as described above, the width of the first seal ring 151 is made larger than the width of the second seal ring 152. As a result, it is possible to maintain the sealing performance of the first seal ring 151 for an even longer period of time.

[0041] As described above, the present embodiment has been described with reference to specific examples. However, the present disclosure is not limited to these specific examples. As long as those skilled in the art appropriately make design changes to these specific examples and have the features of the present disclosure, they are included in the scope of the present disclosure. Each element included in the above-described specific examples, as well as its arrangement, conditions, shape, etc. are not limited to those illustrated and can be changed as appropriate. Each element included in the above-described specific examples can be appropriately combined as long as no technical contradiction occurs.

Description of Reference Numerals

[0042] 10: Electrostatic chuck 100: Dielectric substrate 150: Seal ring 151: First seal ring 152: Second seal ring

Claims

1. A dielectric substrate having a mounting surface on which an object to be attracted is placed; A plurality of seal rings which are annular protrusions formed on the dielectric substrate and whose tip surfaces form part of the mounting surface; The plurality of seal rings are: A first seal ring disposed at the outermost peripheral end position of the mounting surface; A second seal ring disposed at a position inside the first seal ring without sandwiching any other seal ring between the first seal ring and the second seal ring; An electrostatic chuck, characterized in that the surface roughness of the first seal ring is greater than the surface roughness of the second seal ring.

2. The electrostatic chuck according to claim 1, characterized in that the width of the first seal ring is greater than the width of the second seal ring.

Citation Information

Patent Citations

  • Electrostatic chuck

    JP2010135851A