Semiconductor device

Abstract

To provide a manufacturing process which can obtain a semiconductor device having a semiconductor element such as a transistor inexpensively and achieve high productivity.SOLUTION: A manufacturing method of a laminated oxide material comprises the steps of: forming an oxide component on a base component; performing a heat treatment to form a first oxide crystal component which grows as crystals from a surface toward the inside; and laminating a second oxide crystal component on the first oxide crystal component. Specifically, the first oxide crystal component and the second oxide crystal component are subjected to axial growth of homoepitaxial growth or heteroepitaxial growth where the first oxide crystal component and the second oxide crystal component share c-axis.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a laminated oxide material used in the manufacture of semiconductor devices by performing laminated film formation and its crystallization heat treatment by a sputtering method. For example, it provides a material suitable for semiconductor applications such as transistors and diodes. Further, it relates to a semiconductor device having a circuit composed of semiconductor elements such as transistors and a method for manufacturing the same. For example, a power device mounted on a power supply circuit, a semiconductor integrated circuit including a memory, a thyristor, a converter, an image sensor, etc., and an electronic device mounted with an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element as a component. In addition, in this specification, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

[0002]

Background Art

[0003] As a semiconductor material, a typical material is Si, but in addition, the development of SiC, GaN, etc. is also in progress. However, these require a temperature of 1500°C or higher for the treatment of single crystal members and cannot be used for thin film devices or three-dimensional devices.

[0004] On the other hand, in recent years, a technique for constructing a transistor using a semiconductor thin film (having a thickness of about several to several hundred nm) formed at a relatively low temperature on a substrate having an insulating surface has attracted attention. Transistors are widely applied to electronic devices such as ICs and electro-optical devices, and in particular, the development as a switching element for image display devices is being accelerated.

[0005] ​​​​​​​​​​​​In addition, metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as an electrode material with light-transmitting properties required for liquid crystal displays and the like. Among metal oxides, some exhibit semiconductor characteristics. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and lead. A transistor using such a metal oxide exhibiting semiconductor characteristics as a channel formation region is already known (Patent Document 1 and Patent Document 2).

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] One aspect of the present invention is to provide a material suitable for semiconductor applications such as transistors and diodes by a sputtering method.

[0008] Another aspect of the present invention is to provide a transistor having a high field-effect mobility and a low off-current. Another object is to realize a so-called normally-off switching element and provide a semiconductor device with low power consumption. Another object is also to provide a transistor having high transistor performance and high reliability.

[0009] Another aspect of the present invention is to inexpensively obtain a semiconductor device having a semiconductor element such as a transistor. Another object is to provide a highly productive manufacturing process that can be achieved.

[0010] Another aspect of the present invention has an object of providing a transistor having high reliability. as one of the problems.

Means for Solving the Problems

[0011] One aspect of the present invention disclosed in this specification is to form an oxide member on a base member and perform a heat treatment to form a first oxide crystal member that grows in crystal from the surface toward the inside, and stack and provide a second oxide crystal member on the first oxide crystal member. It is a manufacturing method of a laminated oxide material. In particular, the first oxide crystal member and the second oxide crystal member have a coaxial (axial) growth of homoepitaxial growth or heteroepitaxial growth with a common c-axis. That is. Note that the first oxide crystal member has a c-axis orientation in a direction perpendicular to the surface of the first oxide crystal member. In particular, a second oxide member is crystal-grown using a first non-single crystal thin film that epitaxially grows (grows one crystal structure) as a seed. Note that a plurality of elements of adjacent planes on the a-b plane in each oxide crystal member are the same. Also, the c-axis direction of the first oxide crystal member coincides with the depth direction or the upward direction. That is.

[0012] Note that the first oxide crystal member has a c-axis orientation in a direction perpendicular to the surface of the first oxide crystal member. In particular, a second oxide member is crystal-grown using a first non-single crystal thin film that epitaxially grows (grows one crystal structure) as a seed. Note that a plurality of elements of adjacent planes on the a-b plane in each oxide crystal member are the same. Also, the c-axis direction of the first oxide crystal member coincides with the depth direction or the upward direction. In particular, a second oxide member is crystal-grown using a first non-single crystal thin film that epitaxially grows (grows one crystal structure) as a seed. Note that a plurality of elements of adjacent planes on the a-b plane in each oxide crystal member are the same. Also, the c-axis direction of the first oxide crystal member coincides with the depth direction or the upward direction. film as a seed. In each oxide crystal member, a plurality of elements of adjacent planes on the a-b plane are the same. Also, the c-axis direction of the first oxide crystal member coincides with the depth direction or the upward direction. In each oxide crystal member, a plurality of elements of adjacent planes on the a-b plane are the same. Also, the c-axis direction of the first oxide crystal member coincides with the depth direction or the upward direction.

[0013] The greatest feature of the above manufacturing method is a configuration in which crystal growth is performed on an amorphous insulator (for example, an oxide) having an arbitrary base surface. is grown.

[0014] Another invention is to form an oxide member on a base member, perform a heat treatment to form a first oxide crystal member that grows in crystal from the surface toward the inside, and directly above the surface of the base member. from the surface toward the inside to form a first oxide crystal member that grows in crystal, and An amorphous component remains, and a second oxide crystal member made of the same material and having homo-crystalline growth is laminated on the first oxide crystal member. This is a method for producing a laminated oxide material in which a second oxide crystal member is laminated and provided.

[0015] Another invention is to form an oxide member on a base member, perform a heat treatment, and form a first oxide crystal member that grows in crystal from the surface toward the inside, and an amorphous component remains immediately above the surface of the base member, and a second oxide crystal member made of a different material and having hetero-crystalline growth is laminated on the first oxide crystal member. This is a method for producing a laminated oxide material in which a second oxide crystal member is laminated and provided. .

[0016] In each of the above production methods, homo-crystalline growth or hetero-crystalline growth is obtained by growing crystals while heating the temperature to 200 °C or higher and 600 °C or lower during film formation.

[0017] In each of the above production methods, the first oxide crystal member and the second oxide crystal member are highly pure true conductive types.

[0018] In each of the above production methods, the carrier concentration of the laminated oxide material is 1.0×10 12 c m -3 less than, preferably less than 1.45×10 10 cm -3 . .

[0019] In each of the above production methods, the crystal-oriented lower interface of the first oxide crystal member is provided spaced apart from the base member. By appropriately adjusting the film thickness of the oxide member or the conditions of the heat treatment, etc., the crystal-oriented lower interface of the first oxide crystal member and the base member are intentionally separated. Adjusting the film thickness of the oxide member or the conditions of the heat treatment, etc., the crystal-oriented lower interface of the first oxide crystal member and the base member are intentionally ​Leave an amorphous region of the oxide member between them to function as a buffer, and the crystal region is provided spaced apart from the surface of the base member. When a device is fabricated, the influence caused by interface scattering with the base member can be reduced. For example, when fabricating a bottom gate type transistor in which the above-mentioned laminated oxide material is formed on a gate insulating layer, the channel formation region is not formed at the interface of the gate insulating layer, but is formed in a polycrystalline layer spaced apart from the surface of the gate insulating layer, and the influence of interface scattering between the gate insulating layer and the oxide crystal member is reduced. Therefore, a transistor having a crystal layer spaced apart from the

[0020] surface of the gate insulating layer can also be called a buried channel transistor. One of the technical ideas of the present invention is to purify the oxide semiconductor itself by intentionally removing impurities such as water and hydrogen that are inadvertently present without further adding them to the oxide semiconductor. That is, by removing water or hydrogen that constitutes the donor level, further reducing oxygen vacancies, and sufficiently supplying oxygen

[0021] which is the main component material of the oxide semiconductor, the oxide semiconductor is 20 cm -3 purified to a high purity. When an oxide semiconductor film is formed, hydrogen at the level of 10 is measured by SIMS (secondary ion mass spectrometry). By intentionally removing the water or hydrogen that causes this donor level, and further adding oxygen (one of the components of the oxide semiconductor) that decreases simultaneously with the removal of water or hydrogen to the oxide semiconductor, the oxide semiconductor is purified to a high purity and made into an

[0022] intrinsic (i-type) semiconductor electrically.Also, in one of the technical ideas of the present invention, the amount of water and hydrogen in the oxide semiconductor is preferably as small as possible, and the fewer carriers, the better. That is, the carrier density is less than 1×10 1×10 12 cm -3 −1 10 cm - 3 −1, more preferably less than the measurement limit of 1.45×10 . In particular, the oxide semiconductor is heat-treated in an atmosphere of oxygen, nitrogen, or ultra-dry air (air with a water content of 20 ppm or less , preferably 1 ppm or less, preferably 10 ppb or less) at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower, to remove water or hydrogen that becomes an n-type impurity and achieve high purity. Also, by removing impurities such as water or hydrogen, the oxide semiconductor is purified to a high purity, and the carrier density can be made less than 1×10 1×10 12 cm -3 −1, more preferably less than the measurement limit of 1.45×10 10 cm -3 −1.

[0023] Furthermore, when the heat treatment is at a high temperature of 450°C or higher and 850°C or lower, preferably 600°C or higher and 700°C or lower , the oxide semiconductor can be purified and crystallized, and crystal growth occurs from the surface to the inside of the oxide semiconductor, resulting in an oxide semiconductor having a non-single crystal region with a c-axis direction.

[0024] The present invention uses the oxide semiconductor having a non-single crystal region with the c-axis direction as a seed crystal, and a second oxide semiconductor is provided thereon, at 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower, and heat treatment is performed to grow a single crystal of the second oxide semiconductor on the seed crystal, By performing heat treatment at 750 °C or lower, the second oxide semiconductor can be made into a non-single crystal region having the same c-axis orientation as the seed crystal. That is, ideal axial growth or epitaxial growth can be achieved in which the c-axes of the seed crystal and the second oxide semiconductor are coaxial. Moreover, the second oxide semiconductor that is coaxial with the seed crystal does not undergo solid-phase growth by heat treatment after film formation, but is heated at 200 °C or higher and 600 °C or lower, preferably 200 °C or higher and 550 °C or lower, while forming the second oxide semiconductor, typically by sputtering, so that crystal growth can be achieved while depositing. Furthermore, by reducing and preferably eliminating the carriers in the oxide semiconductor, the oxide semiconductor functions as a path for carriers to pass through in the transistor. As a result, the oxide semiconductor is a highly purified i-type (intrinsic) semiconductor with no or extremely few carriers, and one of the technical concepts of the present invention is that the off-current can be made extremely low in the off state of the transistor.

[0025] Also, when the second oxide semiconductor that is coaxial with the seed crystal is made into a highly purified i-type (intrinsic) with no or extremely few carriers so that it functions as a path, carriers are supplied through the source electrode and the drain electrode. By appropriately selecting the electron affinity χ and the Fermi level, ideally the Fermi level that coincides with the intrinsic Fermi level, of the oxide semiconductor and the work functions of the source and drain electrodes, it becomes possible to inject carriers from the source electrode and the drain electrode, and n-type and p-type transistors can be appropriately fabricated.

[0026]

[0027]

[0027] ​ It is possible.

[0028] All of the above oxide crystal members and oxide members are metal oxides, which are quaternary metal oxides such as an In-Sn-Ga-Zn-O-based film, or a ternary metal oxide In-Ga-Zn-O-based film , an In-Sn-Zn-O-based film, an In-Al-Zn-O-based film, an Sn-Ga-Zn-O-based film, an Al-Ga-Zn-O-based film, an Sn-Al-Zn-O-based film, or a binary metal oxide such as an In -Zn-O-based film, an Sn-Zn-O-based film, an Al-Zn-O-based film, a Zn-Mg-O-based film, an Sn -Mg-O-based film, an In-Mg-O-based film, or a single-component metal oxide such as an In-O-based film, an Sn- O-based film, a Zn-O-based film, etc. can be used. Here, for example , an In-Sn-Ga-Zn-O film means an oxide film containing indium (In), tin (Sn), gallium (G a), and zinc (Zn), and its stoichiometric ratio is not particularly limited .

[0029] In addition, the above oxide crystal members and oxide members can also be expressed as materials represented by InMO 3 (ZnO) m (where m > 0 and m is not a natural number). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, G a and Al, Ga and Mn, or Ga and Co, etc.

[0030] In addition, an oxide semiconductor material represented by In-A-B-O may also be used. Here, A is one or more elements selected from Group 13 elements such as gallium (Ga) and aluminum (Al), and Group 14 elements represented by silicon (Si) and germa nium (Ge), etc. Yes. Further, B represents one or more types of elements selected from Group 12 elements typified by zinc (Zn). The contents of In, A, and B are arbitrary, including the case where the content of A is zero. . On the other hand, the contents of In and B are not zero. That is, the above notations include In-Ga -Zn-O, In-Zn-O, and the like. Further, the oxide semiconductor material represented by In-Ga-Zn- O in this specification is InGaO 3 (ZnO) m (m > 0, and m is not a natural number), and the fact that m is not a natural number can be confirmed by using ICP-MS analysis or RBS analysis.

[0031] Conventional oxide semiconductors are generally n-type, and current easily flows between the source electrode and the drain electrode even when the gate voltage is 0V, so-called normally-on. Even if the field-effect mobility is high, it is difficult to control the transistor as a circuit when the transistor is normally-on. When the oxide semiconductor is n-type, the Fermi level (E ) is located away from the intrinsic Fermi level (E ) at the center of the bandgap and is located closer to the conduction band. It is known that hydrogen is a donor and is one of the factors for n-type formation in oxide semiconductors. Also, oxygen deficiency is known to be one of the factors for n-type formation. F i In oxide semiconductors, hydrogen is known to be a donor and one of the factors for n-type formation. Also, oxygen deficiency is known to be one of the factors for n-type formation.

[0032] Therefore, in order to make the oxide semiconductor layer i-type, hydrogen, which is an n-type impurity, is removed from the oxide semiconductor, and it is made highly pure so that impurities other than the main components of the oxide semiconductor are not contained as much as possible, and oxygen deficiency is removed to make it intrinsic (i-type) or intrinsic type. That is, instead of adding impurities to make it i-type, by removing impurities such as hydrogen and water and oxygen deficiency as much as possible, it is made i-type not by adding impurities, but by removing impurities such as hydrogen and water and oxygen deficiency as much as possible.​​​​​​ It is characterized by being highly purified to type I (intrinsic semiconductor) or approaching it. By doing so , the Fermi level (E F ) can be made to the same level as the intrinsic Fermi level (E i ). This can be achieved.

[0033] By highly purifying the oxide semiconductor layer, the threshold voltage value of the transistor can be made positive , and a so-called normally-off switching element can be realized.

[0034] As one of the processes for highly purification, it is preferable to remove moisture etc. in the sputtering apparatus before, during, or after forming the oxide semiconductor film. To remove moisture in the sputtering apparatus, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump . Also, as the exhaust means, a turbo pump with a cold trap added may be used . The film formation chamber of the sputtering apparatus evacuated using a cryopump exhausts, for example, hydrogen atoms and compounds containing hydrogen atoms such as water (H O), etc., so that the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. Furthermore, the relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably 95% or more, and more preferably 99. 9% or more is preferable. Using a target with a high relative density can reduce the impurity concentration in the formed oxide semiconductor film. (H 2 O), etc. When impurities are mixed into the formed oxide semiconductor film, the heat treatment for crystallization performed later ... ... ...

[0035] ... In fact, since there is a risk of inhibiting crystal growth in one direction, i.e., crystal growth downward from the surface, it is desirable to have a state where there are no impurities (impurities that create p-type or n-type) in the oxide semiconductor film. Also, impurity elements such as heavy metals that do not constitute semiconductors, Fe, Ni, etc., should also be 15 cm -3 or less. It is ideal to purify the oxide semiconductor by dehydration and dehydrogenation, or to perform this process particularly strongly while crystallizing the oxide semiconductor. This is extremely important.

[0036] Also, before forming the oxide semiconductor film, a preheating process may be performed to remove moisture or hydrogen from the inner wall of the sputtering apparatus, the target surface, or the target material. As the preheating process, a method of heating the inside of the film-forming chamber to 200°C to 600°C under reduced pressure is effective. Also, a method of adsorbing moisture etc. on the inner wall of the chamber by film-forming while heating the substrate to be processed is also effective. In this case, the target coolant should preferably be grease or the like instead of water. Repeating the introduction and exhaust of nitrogen without heating can obtain a certain effect, but it is even better to perform while heating. After finishing the preheating process, cool the substrate or the sputtering apparatus and form the oxide semiconductor film.

[0037] Also, for the oxide semiconductor film or the material film formed in contact therewith, the sputtering gas such as argon or oxygen used during film formation should also be a high-purity gas from which impurities such as hydrogen, water, compounds containing hydroxyl groups, or hydrides have been removed to a concentration expressed in ppm units or a concentration expressed in ppb units.

[0038] Also, during the formation of the oxide semiconductor film by sputtering, the substrate may be heated to 200°C or higher and 600°C or lower. When heated to 200°C or higher and 600°C or lower, if a first non-single crystal layer has been previously formed, coaxial crystal growth (particularly c-axis crystal growth) can be expected during film formation.

[0039] Also, as one of the processes for purification, a first heat treatment is performed in an atmosphere containing almost no hydrogen and moisture (nitrogen atmosphere, oxygen atmosphere, dry air atmosphere (for example, for moisture, dew point -40°C or lower, preferably dew point -50°C or lower), etc.). This first heat treatment can also be called dehydration or dehydrogenation to remove H, OH, etc. from the oxide semiconductor layer. When performing a heat treatment with a temperature increase in an inert atmosphere and switching to an atmosphere containing oxygen midway, or when performing a heat treatment in an oxygen atmosphere, it can also be called an oxidation treatment.

[0040] The first heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using a heated gas, or an LRTA (La mp Rapid Thermal Anneal) method using lamp light, etc., which are instant heating methods. Also, the first heat treatment may simultaneously perform heating by irradiating light with a wavelength of 450 nm or less. The first heat treatment for purification is performed under conditions such that when measuring up to 450°C on the oxide semiconductor layer after the first heat treatment by TDS (Thermal Desorption Spectroscopy), at least one of the two peaks of water does not appear near 300°C. Therefore, the heat treatment for purification is performed For the transistor using the obtained oxide semiconductor layer, measurements were carried out by TDS up to 450 °C and the peak of water that appears at least around 300 °C is not detected.

[0041] Since the first heat treatment performs crystal growth in a state without crystal growth seeds, it is preferable to heat at a high temperature for a short time so that only crystal growth from the surface toward the inside occurs. Further, if the surface of the oxide semiconductor layer is flat, a good plate-like non-single crystal layer can be obtained. Therefore, it is desirable that the flatness of the underlying member, for example, the insulating layer or the substrate, is as high as possible. For example, the flatness is comparable to that of a commercially available silicon wafer. For example, the height difference in AFM measurement in a region of 1 μm square on the surface is 1 nm or less, preferably 0.2 nm or less.

[0042] The non-single crystal layer increases the electrical conductivity σ by the overlapping and connection of the electron clouds of In in the oxide semiconductor. Therefore, a transistor having a non-single crystal layer can achieve a high field-effect mobility.

[0043] One method of further performing crystal growth using the non-single crystal layer formed by the first heat treatment as a seed is shown below with reference to FIGS. 1(A), 1(B), and 1(C).

[0044] To explain the outline of the process order, after forming the first oxide semiconductor layer on the underlying member, a first heat treatment for purification is performed. By the same process as the first heat treatment for purification, a non-single crystal layer with relatively aligned crystal orientations is formed on the surface of the first oxide semiconductor layer, and a second oxide semiconductor layer is laminated thereon. Further, by performing a second heat treatment for crystallization the second oxide semiconductor layer is crystallized using the non-single crystal layer on the surface of the first oxide semiconductor layer as a seed ​​ It is performed in the order of crystallization.

[0045] In the first heat treatment, crystal growth occurs from the surface in a state without crystal growth seeds, whereas in the second heat treatment, since there is a flat non-single crystal layer serving as a seed, heating at the lowest temperature for a long time can obtain good crystallinity, which is preferable. The direction of crystal growth performed by the second heat treatment is from bottom to top, from the substrate side to the surface side (also called the recrystallization direction), which is different from the direction of crystal growth in the first heat treatment. In addition, since the non-single crystal layer obtained by the first heat treatment is heated again in the second heat treatment, the crystallinity is further improved.

[0046] FIG. 1(A) shows the state after the first heat treatment for crystallizing the first oxide semiconductor layer formed on the base member 520. Depending on conditions such as the materials of the first oxide semiconductor layer and the base member 520, the heating temperature, and the heating time, even if crystal growth occurs from the surface by the first heat treatment, the tip of the first oxide crystal member 521b does not reach the interface of the base member 520, leaving an amorphous region 521a.

[0047] Further, FIG. 1(B) is a cross-sectional view immediately after the formation of the second oxide member 522. The second oxide member 522 is formed by sputtering, and the metal oxide target thereof is In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] metal oxide target or In 2 O 3 :G a 2 O 3 :ZnO = 1:1:4 [mole ratio] metal oxide target may be used.

[0048] Also, during the film formation of the second oxide member 522 by sputtering, the substrate may be heated to 200°C or higher and 600°C or lower. When film formation is performed at this substrate temperature, the second oxide member 522 can form a pre-array . Also, it can directly epitaxially grow.

[0049] In addition, a structure corresponding to FIG. 1(B) was actually fabricated, and a TEM photograph of the cross section is shown in FIG. 4(A ). A schematic diagram is shown in FIG. 4(B). The TEM photograph was observed with a high-resolution transmission electron microscope (Hitachi, Ltd.'s "H9000-NAR": TEM) at an acceleration voltage of 300 kV and is a high-magnification photograph (4 million times). The sample for taking the photograph in FIG. 4(A) has an insulating layer formed on a glass substrate, and a first In-Ga-Zn-O film with a film thickness of 5 nm is formed thereon. Heat treatment is performed at 650°C for 6 minutes in a nitrogen atmosphere, and then a second In-Ga-Z n-O film with a film thickness of 30 nm is laminated and formed. The insulating layer uses a silicon oxynitride film with a film thickness of 100 nm formed by a high-density plasma device (also called SiOxNy, where x > y > 0). In FIG. 4(A ), it can be confirmed that the first In-Ga-Zn-O film is c-axis oriented in the vertical direction with respect to the surface of the first In-Ga-Zn-O film, and the interface between the first In-Ga-Zn-O film and the insulating layer is not crystallized. As the metal oxide semiconductor layer, a material represented by InGa Zn O can be used . Here, x, y, and z are arbitrary numbers. Also, x, y, and z do not have to be integers and

[0050] can be non-integers. Note that x can be 0, but it is desirable that y is not 0. x Zn y O z . Here, x, y, and z are arbitrary numbers. Also, x, y, and z do not have to be integers and can be non-integers. Note that x can be 0, but it is desirable that y is not 0. ​​For example, the notation includes In-Zn-O where x is 0. It also includes In-Zn-O where x=1 and y=1. In addition, oxide semiconductors are also known as In order to obtain a crystal with a c-axis oriented in a direction perpendicular to the conductor layer surface, for example a non-single crystal, high purification is required. It is preferable to use an oxide semiconductor having a low impurity content. By this process, a non-single crystal with high crystallinity can be obtained. The plate-like crystals in the layer are In 2 Ga 2 ZnO 7 (In:Ga:Zn:O=2:2 The carrier of the metal oxide semiconductor layer having the flat crystal structure is The concentration is 1×10 12 cm -3 Less than 1.45 x 10 10 cm -3 is less than .

[0051] In addition, the first In-Ga-Zn-O film and the second In- The Ga-Zn-O film was sputtered using the same sputtering equipment with an oxide semiconductor target (In-Ga -Zn-O oxide semiconductor target (In 2 O 3 :Ga 2 O 3 :ZnO=1:1:2 [molar ratio] was used, the pressure was 0.6 Pa, the direct current (DC) power was 0.5 kW, and oxygen and argon were The substrate temperature was 20 The film was formed at 0°C and a film formation rate of 4 nm / min. For example, In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1 [molar ratio] target When using it, In 2 Ga 2 ZnO 7 It is easy to obtain a non-single crystal of

[0052] In 2 Ga 2 ZnO 7 The crystal structure of can be regarded as a laminated structure of layers parallel to the a-axis (a-a xis) and the b-axis (b-axis), containing any of In, Ga, and Zn. In 2 Ga 2 ZnO 7 Since the electrical conduction of the crystal of is mainly controlled by In, the electrical properties of the layer containing In in the directions parallel to the a-axis and the b-axis are good In 2 Ga 2 ZnO 7 The crystal of has overlapping and connected electron clouds of In, forming carrier

[0053] Also, instead of the above target, In 2 O 3 :Ga 2 O 3 :ZnO = 2:1:8 [mol ratio] metal oxide target may be used.

[0054] Also, an In 2 O 3 :ZnO = 1:2 [mol ratio] metal oxide target may be used. When a bottom-gate type transistor is used, since the oxide of Ga is an insulator compared with the case of using the first In-Ga-Zn-O film, the field-effect mobility can be increased when using the In-Zn-O film case.

[0055] Also, FIG. 1(C) is a cross-sectional view after the second heat treatment. By the second heat treatment, the first Using the non-single crystal layer of the oxide crystal member 521b as a seed, crystal growth occurs upward toward the surface of the second oxide member 522, and the second oxide crystal member 523b is formed. The crystal members have the same crystal axis.

[0056] The materials of the first oxide member and the second oxide member are not particularly limited as long as a non-single crystal with a c-axis orientation in the direction perpendicular to the surface can be obtained. Different materials may be used, or materials containing the same components may be used. Containing the same components means having the same elements.

[0057] In addition, when using an oxide semiconductor material containing the same components for the first oxide member and the second oxide member, as shown by the dotted line in Fig. 1(C), the boundary between the first oxide crystal member 523a and the second oxide crystal member 523b becomes unclear.

[0058] Also, in Fig. 1(C), in contact with the base member 520, a three-layer structure can be said to be formed in the order of the amorphous region 52 3c, the first oxide crystal member 523a, and the second oxide crystal member 523b.

[0059] This second heat treatment can also be called dehydration or dehydrogenation to remove H, OH, etc. from the oxide semiconductor layer. When heating is performed under an inert atmosphere and the atmosphere is switched midway to an atmosphere containing oxygen, or when heat treatment is performed under an oxygen atmosphere, it can also be called oxidation treatment.

[0060] The hydrogen concentration in the oxide semiconductor layer is preferably 1×10 18 cm -3 or less, 1×10 16 cm -3 or less, and more preferably substantially 0. Also, the carrier density of the oxide semiconductor layer is 1×10​​​​​​1 2 cm -3 less than, more preferably 1.45×10 below the measurement limit 10 cm -3 and less That is, the carrier density of the oxide semiconductor layer is almost zero. Also, the band gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. Note that measurement of the hydrogen concentration in the oxide semiconductor layer can be performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy). The carrier density can be measured by Hall effect measurement. Also, measurement of a lower carrier density can be obtained from the measurement results of CV measurement (Capacitance-Voltage-Measurement ) and Equation 1.

[0061]

Equation

[0062] Thus, the polycrystalline layer composed of the stack of the first oxide crystal member 523a and the second oxide crystal member 523b can be crystallized in two steps.

[0063] In fact, after the formation of the second In-Ga-Zn-O film, heat treatment was performed at 650 °C for 6 minutes in a nitrogen atmosphere, and the TEM photograph of the cross section taken is shown in Fig. 5(A). The schematic diagram is shown in Fig. 5 (B). In Fig. 5(A), it can be confirmed that the entire second In-Ga-Zn-O film is crystallized. Also, it can be confirmed that the polycrystalline layer of the second In-Ga-Zn-O film is c-axis oriented in the direction perpendicular to the surface of the second In-Ga-Zn-O film. Also, the first (B). In Fig. 5(A), it can be confirmed that the entire second In-Ga-Zn-O film is crystallized. Also, it can be confirmed that the polycrystalline layer of the second In-Ga-Zn-O film is c-axis oriented in the direction perpendicular to the surface of the second In-Ga-Zn-O film. Also, the first (B). In Fig. 5(A), it can be confirmed that the entire second In-Ga-Zn-O film is crystallized. Also, it can be confirmed that the polycrystalline layer of the second In-Ga-Zn-O film is c-axis oriented in the direction perpendicular to the surface of the second In-Ga-Zn-O film. Also, the first a-Zn-O film is perpendicular to the surface of the second In-Ga-Zn-O film, and it can be confirmed that the c-axis is oriented. Also, the first Even after the heat treatment at 2, it can be confirmed that the vicinity of the interface between the first In-Ga-Zn-O film and the insulating layer is not crystallized. It can be confirmed that it is not.

[0064] In FIG. 1(A), the relatively crystal-orientation-uniform amorphous layer on the surface of the first oxide semiconductor layer can be formed without being affected by the underlying member because it grows in the depth direction from the surface. Since it grows in the depth direction from the surface, it can be formed without being affected by the underlying member. It can be formed.

[0065] As an example, the mechanism by which a relatively crystal-orientation-uniform amorphous layer is formed on the surface of the first oxide semiconductor layer, for example, an In-Ga-Zn-O film, will be described. By heat treatment, zinc contained in the In-Ga-Zn-O film diffuses and accumulates near the surface, serving as seeds for crystal growth. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. As an example, the mechanism by which a relatively crystal-orientation-uniform amorphous layer is formed on the surface of the first oxide semiconductor layer, for example, an In-Ga-Zn-O film, will be described. By heat treatment, zinc contained in the In-Ga-Zn-O film diffuses and accumulates near the surface, serving as seeds for crystal growth. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. The crystal growth is stronger in the lateral direction (parallel to the surface) than in the depth direction (perpendicular to the surface), so a flat amorphous layer is formed. That is, the a-b plane direction is more likely to crystallize than the c-axis direction. Also, the respective a-b planes do not coincide. Above the surface of the In-Ga-Zn-O film is free space, and there is no crystal growth upward here. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. These are inferred from the fact that when the measurement by TDS is performed up to 450 °C, In and Ga are not detected, but zinc is detected as a peak especially near 300 °C under vacuum heating conditions. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C. The measurement by TDS is performed in vacuum, and it can be confirmed that the desorption of zinc is detected from around 200 °C.

[0066] Also, as a comparative example, a TEM photograph of a cross-section of a sample obtained by forming an In-Ga-Zn-O film with a thickness of 50 nm and then heating it at 700 °C for 1 hour is shown in FIG. 6(A). In addition, a TEM photograph of a cross-section of a sample obtained by forming an In-Ga-Zn-O film with a thickness of 50 nm and then heating it at 700 °C for 1 hour is shown in FIG. 6(A). , the schematic diagram is shown in Fig. 6(B). The TEM photograph in Fig. 6(A) was taken at an acceleration voltage of 300 kV and observed with a high-resolution transmission electron microscope (Hitachi Ltd.'s "H9000-NAR": TEM) at a high magnification (2 million times). In Fig. 6(A), about 5 nm from the surface of the In-Ga-Zn-O film is crystallized, and it can be confirmed that there are many amorphous parts and a plurality of randomly oriented crystals in the interior of the In-Ga-Zn-O film. Therefore, after forming a film with a thickness of 50 nm and then performing a heat treatment at 700 °C, which is higher than 650 °C, for 1 hour, which is longer than 6 minutes, even if it is performed once, it is difficult to make the entire 50-nm-thick film into a non-single crystal layer with high orientation.

[0067] From these experimental results, it can be said that a thick non-single crystal layer can be formed by forming the film in two steps, forming a non-single crystal layer that serves as a seed for crystal growth, then forming the film again, and then growing the crystal. It can be seen that the method disclosed in this specification is extremely useful. By forming the film in two steps and performing two heat treatments, for the first time, a non-single crystal layer with high orientation, that is, a non-single crystal layer with c-axis orientation perpendicular to the surface of the oxide crystal member can be obtained thickly.

[0068] In addition, one aspect of the invention disclosed in this specification is a laminated oxide material formed by laminating a first oxide crystal member that grows crystals from the surface inward on a base member and a second oxide crystal member on the first oxide crystal member. Note that the first oxide crystal member that grows crystals from the surface inward has a c-axis orientation perpendicular to the surface of the first oxide crystal member.

[0069] The above configuration is characterized by disposing an oxide member containing amorphous material between the base member and the first oxide crystal member. Moreover, by intentionally disposing an oxide member containing amorphous material between the base member and the first oxide crystal member, heat treatment can be performed under conditions where crystal growth does not reach the surface of the base member, thus improving productivity.

[0070] Also, one aspect of the invention disclosed in this specification is a laminated oxide material characterized by growing at least a part of a second oxide crystal member having the same crystal structure on the surface of the first oxide crystal member above the surface of the first oxide crystal member.

[0071] Another invention is a method for manufacturing a semiconductor device, the configuration of which is to form a gate electrode layer having a flat surface on the surface of a base member, form a gate insulating layer on the gate electrode layer, form a first oxide semiconductor layer on the gate insulating layer, perform a first heat treatment to cause crystal growth from the surface of the first oxide semiconductor layer inward to form a first non-single crystal layer, form a second oxide semiconductor layer on the first non-single crystal layer, perform a second heat treatment to cause crystal growth from the first non-single crystal layer toward the surface of the second oxide semiconductor layer above it to form a second non-single crystal layer, form a source electrode layer or a drain electrode layer on the laminate of the first non-single crystal layer and the second non-single crystal layer, and the crystal-oriented lower interface of the first non-single crystal layer is separated from the surface of the gate insulating layer.

[0072] In the above configuration, the first non-single crystal layer is characterized by having a c-axis orientation perpendicular to the surface of the first non-single crystal layer.

[0073] ​​​​​​​​​​​​​Another aspect of the present invention is a semiconductor device, the configuration of which is a flat surface on a surface of a base member. a gate electrode layer having a gate insulating layer on the gate electrode layer; A metal oxide layer containing amorphous material and a metal oxide layer containing amorphous material are formed on the metal oxide layer with c-axis orientation perpendicular to the surface. a first non-single crystal layer having a first non-single crystal layer and a second non-single crystal layer extending in a direction perpendicular to the surface of the first non-single crystal layer; A second non-single crystal layer having a c-axis orientation in the first direction and a stack of the first non-single crystal layer and the second non-single crystal layer. a source electrode layer or a drain electrode layer on the first non-single crystal layer and a second non-single crystal layer The semiconductor device is characterized in that the crystal layer is a metal oxide layer.

[0074] In the above structure, the height difference of the region of the surface of the second non-single crystal layer overlapping with the gate electrode layer is 1n It is characterized in that the thickness is 0.05 nm or less, preferably 0.2 nm or less.

[0075] In addition, devices using metal oxides, typically In-Ga-Zn-O films, are not suitable for single-crystal Si This is completely different from devices that use silicon carbide, silicon carbide, or GaN. It is.

[0076] Known wide-gap semiconductors are SiC (3.26 eV) and GaN (3.39 eV). However, SiC and GaN are expensive materials. In addition, SiC has a low resistance region. In order to selectively form the region, phosphorus or aluminum is doped and then activated. In other words, SiC and GaN require a temperature of 1000°C or higher. The processing temperature is 1000°C, and the thin film is formed on the glass substrate or on the substrate on which the LSI is formed. Film formation is virtually impossible.

[0077] In addition, SiC and GaN are only available as single crystals, and control by PN junction is required, making it possible to obtain a more complete single crystal. Therefore, there is a possibility that trace amounts of impurities may be mixed in during the manufacturing process. By introducing the electrons, they become donors or acceptors, so there is no lower limit to the carrier concentration. On the other hand, metal oxides can exist in any crystal structure, whether amorphous, polycrystalline, or single crystal. It is possible to use φ without using PN junction control. MS Against χ OS +1 / 2E g OS , φ MD Against χ OS +1 / 2Eg OS and the work functions of the source and drain, and the metal oxide. By utilizing the electron affinity and the energy band width of the compound, a bandgap equivalent to a PN junction can be realized. One of the characteristics of metal oxides is that they act as a control.

[0078] The band gap of metal oxides, typically In-Ga-Zn-O films, is also approximately equal to that of single crystal silicon. It is three times wider and is a cheaper material than SiC, with lower manufacturing costs.

[0079] The band gap of In-Ga-Zn-O is 3.05 eV. The electron energy distribution f(E) in a solid is given by the following formula: It is known to follow the Mi-Dirac statistics.

[0080]

number

[0081] In ordinary semiconductors where the carrier density is not extremely high (not degenerate), the following relationship holds: do.

[0082]

number

[0083] Therefore, the Fermi-Dirac distribution in Equation (1) is approximated by the Boltzmann distribution equation shown in the following equation. Approximated.

[0084]

Number

[0085] (3) Using the equation to calculate the intrinsic carrier density (n i ) of the semiconductor, the following equation is obtained.

[0086]

Number

[0087] Then, the effective density of states (Nc, Nv) of Si and In-Ga-Zn-O and the value of the band gap (Eg) were substituted into Equation (4) to calculate the intrinsic carrier density. The results are shown in Table 1 .

[0088]

Table 1

[0089] It can be seen that In-Ga-Zn-O has an extremely low intrinsic carrier density compared to Si. Also, the carrier density of the oxide semiconductor is less than 1×10 12 cm -3 Below, more preferably below the measurement limit of 1.45×10 10 cm -3 Below is preferred. When 3.05 eV is selected as the bandgap of IGZO, for Si and In-Ga-Zn-O, assuming that the Fermi-Dirac distribution law is approximately correct for the intrinsic carrier concentration, the former is better than the latter about The carrier density can be said to be about 10 17 times larger.

[0090] In addition, a thin film can be formed of the metal oxide by a sputtering method at a heating temperature from room temperature to 450 °C and the maximum process temperature can be 300 °C or higher and 800 °C or lower. When the maximum process temperature is set below the strain point of the glass, it is also possible to form it on a large-area glass substrate. Therefore, for industrialization, it is important that a metal oxide with a wide bandgap can be produced at a maximum process temperature of 300 °C or higher and 800 °C or lower.

[0091] Also, when three-dimensionally integrating a silicon integrated circuit, since the processing temperature of the metal oxide is 300 °C or higher and 800 °C or lower, which is lower than the temperature at which the bonding on the lower side (silicon side) is broken, it is also possible to apply it to a silicon integrated circuit and an integrated circuit formed by forming a metal oxide FET layer above it for three-dimensional integration.

[0092] The metal oxides reported so far have only been amorphous, polycrystalline, or those that obtain single crystals by treatment at a high temperature of about 1500 °C. However, as shown above, after forming a flat non-single crystal of the metal oxide, a non-single crystal thin film having a c-axis orientation can be formed at a relatively low temperature by a method of crystal growth using the flat non-single crystal of the metal oxide as a seed, and further, when a thick non-single crystal can be formed, a wider industrial application can be opened up. In addition, to obtain a high-quality thick non-single crystal, it is preferable that the flatness and smoothness of the substrate are high. This is because even a slight unevenness of the substrate becomes a local deviation of the c-axis, and as crystal growth progresses, it becomes a defect such as a crystal transition because the orientation of the c-axis of adjacent crystals is different.

Advantages of the Invention

[0093] The metal oxide film is formed in two steps, and heat treatment is performed in two steps, so that the material of the base member, regardless of materials such as oxides, nitrides, and metals, a non-single crystal layer with a large film thickness, that is, a non-single crystal layer with a c-axis orientation perpendicular to the film surface, can be obtained on their surfaces (the surface of an insulator or the surface of an oxide, nitride, or metal).

[0094] Note that a transistor using an oxide semiconductor layer having a non-single crystal layer with a c-axis orientation can realize a transistor having a high field-effect mobility. In addition, a transistor with a low off-current can be realized. In addition, a so-called normally-off switching element can be realized, and a semiconductor device with low power consumption can be provided.

[0095] In addition, a transistor using an oxide semiconductor layer having a non-single crystal layer with a c-axis orientation can suppress the change amount of the threshold voltage of the transistor before and after the BT test, and realize high reliability. Also, a transistor using an oxide semiconductor layer having a non-single crystal layer with a c-axis orientation can reduce the change amount of the threshold voltage of the transistor even before and after the BT test in which light is continuously irradiated on the transistor, and a transistor having stable electrical characteristics can be fabricated.

[0096] As the conditions for the first heat treatment capable of forming a thin non-single crystal layer on the surface of the first oxide semiconductor layer, and as the conditions for not allowing crystal growth until reaching the surface of the base member, a second oxide semiconductor layer is formed thereon, and the second oxide semiconductor layer can be made non-single crystal using the thin non-single crystal layer as a seed. The temperature of the temperature condition of the first heat treatment can be lowered, or the heating time can be shortened. ​​​​​​​​​​Therefore, it is suitable for the manufacturing process formed on a large-area substrate. Also, if the first heat treatment temperature and the second heating temperature are 600 °C or lower, the shrinkage amount of the glass can also be suppressed. Therefore it is possible to provide a highly productive manufacturing process that can be obtained at low cost.

[0097] Also, the crystal-oriented lower interface of the first oxide crystal member is intentionally separated from the surface of the base member and provided, and when a device is manufactured, the influence due to interface scattering with the base member can be reduced. By using the crystal layer separated from the gate insulating layer as the channel formation region, a buried channel transistor can be realized.

Brief Description of the Drawings

[0098]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

[0099] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0100] (Embodiment 1) In this embodiment, an example of a manufacturing example of a transistor is shown using FIGS. 1, 2, and 3.

[0101] First, after forming a conductive film on a substrate 400 which is a substrate having an insulating surface, a gate electrode layer 401 is provided by a photolithography process using a photomask.

[0102] Examples of the substrate 400 include a semiconductor substrate, a sapphire substrate, a quartz substrate, a ceramic substrate, etc. Among them, it is preferable to use a glass substrate that can be mass-produced. The glass substrate used as the substrate 400 is preferably one having a strain point of 730 ° C or higher when the temperature of the subsequent heat treatment is high. Also, for the substrate 400, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. ​ It is. By including more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate 2 containing more BaO than B 3 O.

[0103] Also, an insulating layer serving as an underlayer may be provided between the substrate 400 and the gate electrode layer 401. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 400 and can be formed by a laminated structure of one or more layers selected from silicon nitride, silicon oxide, oxynitride silicon, or silicon oxynitride.

[0104] As the gate electrode layer 401, a metal conductive layer can be used. As the material of the metal conductive layer, an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy containing the above-described elements as components, or an alloy combining the above-described elements is preferably used. For example, a three-layer laminated structure in which an aluminum layer is laminated on a titanium layer and a titanium layer is laminated on the aluminum layer, or a three-layer laminated structure in which an aluminum layer is laminated on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferably used. Of course, the metal conductive layer may be a single layer, or a two-layer structure, or a laminated structure of four or more layers. When heat treatment is performed later, it is preferable to select a material that can withstand the heat treatment temperature as the gate electrode layer 401.

[0105] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 can be formed by using a plasma CVD method, a sputtering method, or the like, as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, a silicon oxynitride layer, or a silicon nitride oxide layer. ​​​​​​​​​​ For example, a silicon nitride film and a silicon oxide film are laminated. The film thickness of the gate insulating layer 402 is 50 nm or more and 200 nm or less.

[0106] In this embodiment, the gate insulating layer 402 is formed by a high-density plasma device. Here, the high-density plasma device refers to a device that can achieve a plasma density of 1×10 11 / cm 3 or more. For example, microwave power of 3 kW to 6 kW is applied to generate plasma for forming an insulating film.

[0107] Monosilane gas (SiH 4 ) and nitrous oxide (N 2 O) and a rare gas are introduced into the chamber, and high-density plasma is generated under a pressure of 10 Pa to 30 Pa to form an insulating film on a substrate having a surface of glass or the like. Then, the supply of monosilane gas is stopped, and nitrous oxide (N O) and a rare gas are introduced without exposure to the atmosphere to perform plasma treatment on the surface of the insulating film. It is also possible to perform plasma treatment on the surface of the insulating film by introducing at least nitrous oxide (N 2 O) and a rare gas. The plasma treatment performed on the surface of the insulating film by introducing at least nitrous oxide (N 2 O) and a rare gas is performed after the formation of the insulating film. The insulating film obtained through the above process sequence is an insulating film with a thin film thickness, for example, less than 100 nm, and can ensure reliability.

[0108] When forming the gate insulating layer 402, the flow rate ratio of monosilane gas (SiH 4 ) and nitrous oxide (N 2 O) is in the range of 1:10 to 1:200. Also, as the rare gas introduced into the chamber, helium, argon, krypton, xenon, etc. are used. Although it is possible, it is preferable to use argon, which is inexpensive among others.

[0109] In addition, the insulating film obtained by the high-density plasma device can form a film with a constant thickness. It has excellent step coverage. Also, the insulating film obtained by the high-density plasma device can precisely control the thickness of a thin film.

[0110] The insulating film that has gone through the above process sequence is significantly different from the insulating film obtained by a conventional parallel plate type PCVD device. When comparing the etching rates using the same etchant, it is 10% or more, or 20% or more slower than the insulating film obtained by the parallel plate type PCVD device. The insulating film obtained by the high-density plasma device can be said to be a dense film.

[0111] In this embodiment, a silicon oxynitride film with a film thickness of 100 nm (also called SiOxNy, where x > y > 0) formed using a high-density plasma device is used as the gate insulating layer 402.

[0112] Next, a first oxide semiconductor layer with a thickness of 2 nm or more and 15 nm or less is formed on the gate insulating layer 402. Also, the first oxide semiconductor layer can be formed by sputtering in an atmosphere of a noble gas (typically argon), an oxygen atmosphere, or an atmosphere of a mixture of a noble gas (typically argon) and oxygen.

[0113] Also, it is preferable to remove moisture and the like in the sputtering device before, during, or after forming the oxide semiconductor film. To remove moisture in the sputtering device, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, titanium ​​​​​​​​​​It is preferable to use a sublimation pump. Further, as the exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber of the sputtering apparatus exhausted using a cryopump, for example, contains hydrogen atoms, compounds containing hydrogen atoms such as water (H O), etc. Therefore, since compounds and the like containing such are exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced. As the first oxide semiconductor layer, an In-Sn-Ga-Zn-O-based film which is a quaternary metal oxide, an In-Ga-Zn-O-based film, an In-Sn-Zn-O-based film, 2 an In-Al-Zn-O-based film, a Sn-Ga-Zn-O-based film, an Al-Ga-Zn-O-based film, an Sn-Al-Zn-O-based film, or an In-Zn-O-based film, a Sn-Zn- O-based film, an Al-Zn-O-based film, a Zn-Mg-O-based film, a Sn-Mg-O-based film, an In-Mg- O-based film, or an In-O-based film, a Sn-O-based film, a Zn-O-based film, etc., which are single-element metal oxides, can be used as the oxide semiconductor film.

[0114] Further, as the first oxide semiconductor layer, a thin film represented by InMO (ZnO) (m>0 and m is not a natural number) can also be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. In the present embodiment, an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In O :Ga

[0115] O 3 (ZnO) m (m>0, and m is not a natural number) can also be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. In the present embodiment, an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In O

[0116] In the present embodiment, an oxide semiconductor target (In-Ga-Zn-O-based oxide semiconductor target (In target for In-Ga-Zn-O-based oxide semiconductor (In 2 O 3 :Ga 2 O3 ZnO = 1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, and the DC power supply was 0.5 The first step was performed under an atmosphere of oxygen only, argon only, or argon and oxygen with a thickness of 10 nm. An oxide semiconductor layer is formed. In 2 O 3 :Ga 2 O 3 A target having a composition ratio of ZnO=1:1:1 [molar ratio], or In 2 O 3 :Ga 2 O 3 A target with a composition ratio of ZnO=1:1:4 [molar ratio] was used. In this embodiment, the crystallization is intentionally performed by performing a heat treatment later. It is preferable to use an oxide semiconductor target which is prone to crystallization.

[0117] The relative density of the oxide semiconductor in the oxide semiconductor target is 80% or more, preferably It is preferable that the relative density is 95% or more, and more preferably 99.9% or more. By using the get, the impurity concentration in the oxide semiconductor film to be formed can be reduced, and Therefore, a transistor having excellent thermal properties and high reliability can be obtained.

[0118] In addition, before the first oxide semiconductor layer was formed, the inner wall of the sputtering apparatus, the surface of the target, and the It is advisable to perform a preheat treatment to remove moisture or hydrogen from the target material. The deposition process involves heating the deposition chamber to 200°C to 600°C under reduced pressure. One method is to repeatedly introduce and exhaust nitrogen or inert gas while heating. If so, after cooling the substrate or the sputtering apparatus, the oxide semiconductor film is formed without exposing it to the atmosphere. In this case, it is preferable to use a coolant for the target other than water, such as grease. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform the process while heating.

[0119] Next, a first heat treatment of the first oxide semiconductor layer is performed to crystallize at least a part thereof. The temperature of the first heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, the heating time is 1 minute or longer and 24 hours or shorter. By the first heat treatment, a first oxide semiconductor layer 403 having a non-single crystal layer at least on the surface is formed (see Fig. 2(A)). The non-single crystal layer formed on the surface grows in crystal from the surface toward the inside, and is a flat non-single crystal having an average thickness of 2nm or more and 10nm or less. Also, the non-single crystal layer formed on the surface has a c-axis orientation in the direction perpendicular to the surface. In this embodiment, an example is shown in which most of the first oxide semiconductor layer becomes polycrystalline except in the vicinity of the gate insulating layer interface by the first heat treatment.

[0120] In the first heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, the purity of nitrogen, oxygen, or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1ppm or lower, preferably 0.1ppm or lower). Also, the first heat treatment may be performed in ultra-dry air with H₂O of 20ppm or lower. Also, during the temperature rise of the first heat treatment, 2 ​ The inside of the furnace may be set to a nitrogen atmosphere and switched to an oxygen atmosphere during cooling, and dehydration or dehydrogenation may be performed in the nitrogen atmosphere, and then the atmosphere may be switched to an oxygen atmosphere to supply oxygen to the inside of the first oxide semiconductor layer to make it an i-type. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, the atmosphere is switched to an oxygen atmosphere, so that oxygen can be supplied to the inside of the first oxide semiconductor layer to make it an i-type. By switching the atmosphere to an oxygen atmosphere after dehydration or dehydrogenation is performed in a nitrogen atmosphere, oxygen can be supplied to the inside of the first oxide semiconductor layer to make it an i-type.

[0121] Note that the heat treatment apparatus used for the first heat treatment is not particularly limited, and it may be equipped with an apparatus for heating the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace, a GRTA (Gas Rapid Thermal Anneal) apparatus, an L RTA (Lamp Rapid Thermal Anneal) apparatus such as an RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. For example, an electric furnace, a GRTA (Gas Rapid Thermal Anneal) apparatus, an L RTA (Lamp Rapid Thermal Anneal) apparatus such as an RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. RTA (Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas.

[0122] Next, a second oxide semiconductor layer 404 having a film thickness larger than that of the first oxide semiconductor layer 403 is formed on at least the surface of the first oxide semiconductor layer 403 having a non-single crystal layer (see FIG. 2 (B)). Note that the film thickness of the second oxide semiconductor layer 404 may be determined by the implementer to be an optimal film thickness depending on the device to be manufactured. For example, when manufacturing a bottom gate type transistor, the total film thickness of the first oxide semiconductor layer 403 and the second oxide semiconductor layer 404 is set to 10 nm or more and 200 nm or less. The second oxide semiconductor layer is made of a noble gas (typically argon nm or more and 200 nm or less. The second oxide semiconductor layer is made of a noble gas (typically argon nm or more and 200 nm or less. The second oxide semiconductor layer is made of a noble gas (typically argon nm or more and 200 nm or less. The second oxide semiconductor layer is made of a noble gas (typically argon in an argon atmosphere, an oxygen atmosphere, or an atmosphere of a noble gas (typically argon) and oxygen It can be formed by a sputtering method.

[0123] As the second oxide semiconductor layer 404, an In-Sn-Ga-Zn -O-based film, an In-Ga-Zn-O-based film which is a ternary metal oxide, an In-Sn-Zn-O -based film, an In-Al-Zn-O-based film, a Sn-Ga-Zn-O-based film, a Sn-Al-Zn-O-based film, an In-Zn-O-based film which is a binary metal oxide, a Sn- Zn-O-based film, an Al-Zn-O-based film, a Zn-Mg-O-based film, a Sn-Mg-O-based film, an In- Mg-O-based film, an In-O-based film which is a single-element metal oxide, a Sn-O-based film, a Zn-O-based film, etc. Any oxide semiconductor film can be used.

[0124] In addition, the first oxide semiconductor layer and the second oxide semiconductor layer 404 may be made of a material containing the same components or may have the same crystal structure and a close lattice constant (mismatch of 1% or less). When using a material containing the same components, in the subsequent crystallization, it becomes easier to perform crystal growth using the non-single crystal layer of the first oxide semiconductor layer as a seed. Also, when it is a material containing the same components the interfacial physical properties such as adhesion and electrical properties are also good.

[0125] Next, a second heat treatment is performed to perform crystal growth using the non-single crystal layer of the first oxide semiconductor layer as a seed. The temperature of the second heat treatment is 450°C or higher and 850°C or lower, preferably 550°C or higher and 750°C or lower. Also, the heating time is 1 minute or longer and 24 hours or shorter. The second oxide semiconductor layer is crystallized by the second heat treatment. Thus, the oxide semiconductor laminate 430 is obtained. ​​​It is possible (see Fig. 2(C)). Note that the vicinity of the interface between the oxide semiconductor layer 430 and the gate insulating layer 402 is not crystallized. In this case, an amorphous layer in contact with the gate insulating layer, and a crystalline layer in contact therewith (here, the stack of the non-single crystal of the first oxide semiconductor layer and the non-single crystal of the second oxide semiconductor layer is regarded as one layer) form a two-layer structure.

[0126] When the heating temperature of the second heat treatment is 550°C or higher, in the case where the second oxide semiconductor layer 404 is thick, an amorphous layer may be formed between the crystal layer growing downward from the surface and the crystal layer growing upward with the first oxide semiconductor layer as a seed. In this case, an amorphous layer in contact with the gate insulating layer, a crystal layer thereon, an amorphous layer thereon, and a crystal layer thereon form a four-layer structure. Here, too, the stack of the non-single crystal of the first oxide semiconductor layer and the non-single crystal of the second oxide semiconductor layer is regarded as one layer and is called a four-layer structure.

[0127] Also, depending on the material of the second oxide semiconductor layer 404, when the heating temperature of the second heat treatment is less than 500°C, crystal growth from the surface does not proceed, and a crystal layer that grows upward with the first oxide semiconductor layer as a seed may be formed. In this case, an amorphous layer in contact with the gate insulating layer, a crystal layer thereon, and an amorphous layer thereon form a three-layer structure. Here, too, the stack of the non-single crystal of the first oxide semiconductor layer and the non-single crystal of the second oxide semiconductor layer is regarded as one layer and is called a three-layer structure. As described above, various laminated structures can be obtained depending on the material and film thickness of the second oxide semiconductor layer 404 and the heating conditions of the second heat treatment. Therefore, it is important for the implementer to appropriately adjust the material and film thickness of the second oxide semiconductor layer 404 and the heating conditions of the second heat treatment according to the desired laminated structure. ​​​​​​​​​​​​

[0128] Note that, among the oxide semiconductor layers 430, the region overlapping with the unevenness of the gate insulating layer has grain boundaries and becomes polycrystalline. Also, among the oxide semiconductor layers 430, the region that becomes the channel formation region has at least a flat surface and is a non-single crystal in which the first oxide semiconductor layer and the second oxide semiconductor layer have the same c-axis orientation. Further, in the channel formation region of the oxide semiconductor layers 430, the a-axis and b-axis of the polycrystal are also misaligned. In FIGS. 2(A), 2(B), and 2(C), the state near the interface with the non-crystallized gate insulating layer 402 is not shown, but in order to clearly explain the vicinity of the interface with the gate insulating layer, FIGS. 1(A), 1(B), and 1(C) are shown using enlarged schematic diagrams. FIG. 2(A) corresponds to FIG. 1(A), and the base member 520 corresponds to the gate insulating layer 402. Also, FIG. 2(B) corresponds to FIG. 1(B) and is a cross-sectional view immediately after the formation of the second oxide member 522. Further, FIG. 2(C) corresponds to FIG. 1(C) and is a cross-sectional view after the second heat treatment. Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, among the oxide semiconductor layers 430, the region overlapping with the unevenness of the gate insulating layer has grain boundaries and becomes polycrystalline. Also, among the oxide semiconductor layers 430, the region that becomes the channel formation region has at least a flat surface and is a non-single crystal in which the first oxide semiconductor layer and the second oxide semiconductor layer have the same c-axis orientation. Further, in the channel formation region of the oxide semiconductor layers 430, the a-axis and b-axis of the polycrystal are also misaligned. Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace

[0129] In FIGS. 2(A), 2(B), and 2(C), the state near the interface with the non-crystallized gate insulating layer 402 is not shown, but in order to clearly explain the vicinity of the interface with the gate insulating layer, FIGS. 1(A), 1(B), and 1(C) are shown using enlarged schematic diagrams. FIG. 2(A) corresponds to FIG. 1(A), and the base member 520 corresponds to the gate insulating layer 402. Also, FIG. 2(B) corresponds to FIG. 1(B) and is a cross-sectional view immediately after the formation of the second oxide member 522. Further, FIG. 2(C) corresponds to FIG. 1(C) and is a cross-sectional view after the second heat treatment. Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, among the oxide semiconductor layers 430, the region overlapping with the unevenness of the gate insulating layer has grain boundaries and becomes polycrystalline. Also, among the oxide semiconductor layers 430, the region that becomes the channel formation region has at least a flat surface and is a non-single crystal in which the first oxide semiconductor layer and the second oxide semiconductor layer have the same c-axis orientation. Further, in the channel formation region of the oxide semiconductor layers 430, the a-axis and b-axis of the polycrystal are also misaligned. (A) corresponds to FIG. 1(A), and the base member 520 corresponds to the gate insulating layer 402. Also, FIG. 2(B) corresponds to FIG. 1(B) and is a cross-sectional view immediately after the formation of the second oxide member 522. Also, FIG. 2(C) corresponds to FIG. 1(C) and is a cross-sectional view after the second heat treatment. Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace

[0130] Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace 2 Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace Note that, also in the second heat treatment, it is preferable that nitrogen, oxygen, or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, it is preferable that the purity of the nitrogen, oxygen, or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). Also, the second heat treatment may be performed in ultra-dry air with H2O of 20 ppm or less. Also, when raising the temperature of the second heat treatment, the inside of the furnace is set to a nitrogen atmosphere, and when cooling, the furnace The atmosphere inside may be switched to an oxygen atmosphere.

[0131] Note that the heat treatment apparatus used for the second heat treatment is not particularly limited, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation such as a resistance heating element. For example an electric furnace or an RTA apparatus such as a GRTA apparatus or an LRTA apparatus can be used.

[0132] Next, the oxide semiconductor stack 43 composed of the first oxide semiconductor layer and the second oxide semiconductor layer 0 is processed into an island-shaped oxide semiconductor stack 431 by a photolithography process (see Fig. 2(D ).). Also, a resist mask for forming the island-shaped oxide semiconductor stack 431 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0133] Next, after forming a metal conductive film on the gate insulating layer 402 and the island-shaped oxide semiconductor stack 431 by a sputtering method or the like, a resist mask is formed by a photolithography process, and selective etching is performed to form a metal electrode layer.

[0134] Subsequently, as the material of the metal conductive film that will become the source electrode and the drain electrode (including wiring formed in the same layer), a metal material such as Al, Cu, Cr, Ta, Ti, Mo, W, or an alloy material containing the metal material as a component is used. Also, a refractory metal layer such as Cr, Ta, Ti, Mo, W may be laminated on one or both of the lower side and the upper side of a metal layer such as Al or Cu to form a structure. Also, an Al material added with an element that prevents the generation of hillocks and whiskers generated in the Al film such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. is used. It becomes possible to improve heat resistance by its presence.

[0135] For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers. For example, as the metal conductive film, a three-layer laminated structure in which an aluminum layer is formed on a titanium layer and a titanium layer is laminated on the aluminum layer, or an aluminum layer is formed on a molybdenum layer and a molybdenum layer is laminated on the aluminum layer is preferable. Further, as the metal conductive film, a two-layer laminated structure in which an aluminum layer and a tungsten layer are laminated, a two-layer laminated structure in which a copper layer and a tungsten layer are laminated, or a two-layer laminated structure in which an aluminum layer and a molybdenum layer are laminated can also be used. Of course, the metal conductive film may be a single layer or a laminated structure of four or more layers.

[0136] Further, as the material of the metal conductive film that becomes the source electrode and the drain electrode (including wiring formed in the same layer), it may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In Further, as the material of the metal conductive film that becomes the source electrode and the drain electrode (including wiring formed in the same layer), it may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In Further, as the material of the metal conductive film that becomes the source electrode and the drain electrode (including wiring formed in the same layer), it may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide alloy (In Further, as the material of the metal conductive film that becomes the source electrode and the drain electrode (including wiring formed in the same layer), it may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 ―SnO 2 ), tin oxide (SnO Further, as the material of the metal conductive film that becomes the source electrode and the drain electrode (including wiring formed in the same layer), it may be formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 ―ZnO), indium zinc oxide alloy (In ―ZnO), or a material obtained by adding silicon or silicon oxide to the above metal oxide material can be used.

[0137] Next, the resist mask is removed, a resist mask is formed by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b. Next, the resist mask is removed, a resist mask is formed by a photolithography process, and selective etching is performed to form the source electrode layer 405a and the drain electrode layer 405b. After formation, the resist mask is removed (see Fig. 2(E)). Note that this photolithography In the roughing process, only a part of the island-shaped oxide semiconductor layer 431 may be etched to form an oxide semiconductor layer having a groove (concave portion).

[0138] Also, as shown in Fig. 2(E), it is also one of the features that the gate electrode layer 401 has a region overlapping with the source electrode layer 405a (or the drain electrode layer 405b). The end of the source electrode layer 405a and the step of the gate insulating layer 402, that is, in the cross-sectional view, the region between the flat surface of the gate insulating layer and the changing point to the tapered surface (here, the L OV region shown in Fig. 2(E)). The L OV region of the oxide semiconductor layer 432 is important to prevent carriers from flowing into the grain boundaries generated by the unevenness at the end of the gate electrode layer.

[0139] Also, on the side surface of the oxide semiconductor layer 432, the non-single crystal layer in contact with the source electrode layer 405a or the drain electrode layer 405b may be in an amorphous state.

[0140] Also, the resist mask for forming the source electrode layer 405a and the drain electrode layer 405b may be formed by an inkjet method. Forming the resist mask by an inkjet method eliminates the use of a photomask, thus reducing the manufacturing cost. For reducing the number of photomasks and processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-tone mask which is an exposure mask having multiple light intensities

[0141] transmitted through it. formed by a multi-tone mask. The resist mask formed using the multi-tone mask The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0142] Next, an oxide insulating layer 407 serving as a protective insulating film in contact with part of the oxide semiconductor layer is formed. .

[0143] The oxide insulating layer 407 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The layer 407 can be formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the layer 407 . In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the oxide insulating layer 407 by a sputtering method. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower. The temperature is set to 100°C in this embodiment. The deposition of silicon oxide film by sputtering method is performed using rare gas (typically a In an atmosphere of rare gas (typically argon), oxygen, or a mixture of rare gas (typically argon) and oxygen The target may be a silicon oxide target or a silicon target. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. Silicon oxide can be formed by sputtering in air. The oxide insulating layer 407 formed in contact with the - Impurities such as It uses an inorganic insulating film that does not contain any substances and blocks the intrusion of these substances from the outside. Use a silicon carbide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, etc. Furthermore, a protective insulating layer such as a silicon nitride film or an aluminum nitride film may be formed on the oxide insulating layer 407.

[0144] Also, before forming the oxide insulating layer 407, it is advisable to perform a preheating treatment to remove moisture or hydrogen in the inner wall of the sputtering apparatus, on the target surface, or in the target material. After the preheating treatment, the substrate or the sputtering apparatus is cooled and then the oxide insulating layer is formed without exposing it to the atmosphere. In this case, the target coolant should preferably be grease or the like instead of water. Although a certain effect can be obtained by repeatedly introducing and exhausting nitrogen without heating, it is even better to perform it while heating.

[0145] Also, after forming the oxide insulating layer 407, a structure in which a silicon nitride film is laminated by sputtering may be formed without exposing it to the atmosphere.

[0146] Also, a contact hole reaching the gate electrode layer 401 is formed in the oxide insulating layer 407 and the gate insulating layer 402, and a connection electrode that is electrically connected to the gate electrode layer 401 and applies a gate potential may be formed on the oxide insulating layer 407. Also, after forming the gate insulating layer 402, a contact hole reaching the gate electrode layer 401 is formed, and a connection electrode made of the same material as the source electrode layer or the drain electrode layer is formed thereon. An oxide insulating layer 407 is formed on the connection electrode, and after forming a contact hole reaching the connection electrode in the oxide insulating layer 407, an electrode that is electrically connected to the connection electrode and applies a gate potential may be formed on the oxide insulating layer 407.

[0147] The transistor 470 is formed in the above process (see Fig. 3(B)). Also, Fig. 3(A) shows an example of the top view of the transistor 470. Note that Fig. 3(B) is a cross-sectional view corresponding to the cross-section cut along the dashed line C 1-C2 in Fig. 3(A).

[0148] The transistor 470 has an oxide member whose upper surface of the gate electrode layer in the channel formation region is flat and is c-axis oriented perpendicular to the flat surface and, another feature is that the source electrode layer or the drain electrode layer overlaps up to the unevenness caused by the end of the gate electrode layer . The oxide member (oxide semiconductor layer 432 in this embodiment) becomes polycrystalline with grain boundaries in the region where the concave portion hits when there are unevenness on the substrate side . Therefore, by forming the Lov region shown in Fig. 3(B), carriers can be prevented from flowing through the grain boundaries generated by the unevenness at the end of the gate electrode layer . Therefore, in the transistor 470, the source electrode layer or the drain electrode layer is provided up to above the flat portion of the gate electrode and overlaps (overlaps) with the gate electrode layer . . . .

[0149] The height difference on the surface of the gate insulating layer overlapping with the channel formation region of the transistor 470 has a flat surface of 1 nm or less, preferably 0.2 nm or less . The channel formation region where carriers flow is non-single crystal .

[0150] Since the transistor 470 shown in Fig. 3(B) is intentionally provided with the crystal layer separated from the gate insulating layer , the channel formation region is not formed at the interface with the gate insulating layer, but is formed in the crystal layer separated from the gate insulating layer, and the influence of interface scattering between the gate insulating layer and the oxide member is reduced .

[0151] Crystallization is performed by the first heat treatment and the second heat treatment to oxidize hydrogen, which is an n-type impurity, remove it from the oxide semiconductor, and highly purify it so that it contains as few impurities as possible other than the main component of the oxide semiconductor, thereby making it intrinsic (i-type) or an intrinsic type. That is, instead of adding impurities to make it i-type, by removing impurities such as hydrogen and water as much as possible, a highly purified i-type (intrinsic semiconductor) or approaching it is achieved. By highly purifying the oxide semiconductor layer, the threshold voltage value of the transistor can be made positive, and a so-called normally-off transistor 470 can be realized. Moreover, it goes without saying that the structure of the transistor 470 shown in FIG. 3(B) is not particularly limited. A bottom gate type transistor is sufficient. For example, in order to protect the etching damage during the formation of the source electrode layer and the drain electrode layer in FIG. 2(E), a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used. Also, an electrode layer that can function as a back gate may be provided on the oxide insulating layer 407. The potential of the back gate can be a fixed potential, for example, 0V or the ground potential, and can be appropriately determined by the implementer. Also, by providing gate electrodes above and below the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, a normally-off transistor 470 can be realized.

[0152] Moreover, it is needless to say that the structure of the transistor 470 shown in FIG. 3(B) is not particularly limited. A bottom gate type transistor is sufficient. For example, in order to protect the etching damage during the formation of the source electrode layer and the drain electrode layer in FIG. 2(E), a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used. Moreover, it is needless to say that the structure of the transistor 470 shown in FIG. 3(B) is not particularly limited. A bottom gate type transistor is sufficient. For example, in order to protect the etching damage during the formation of the source electrode layer and the drain electrode layer in FIG. 2(E), a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used. and drain electrode layer, a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used. and drain electrode layer, a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used. and drain electrode layer, a channel stop type transistor provided with an oxide insulating layer overlapping the channel formation region as a channel stopper may also be used.

[0153] Moreover, an electrode layer that can function as a back gate may be provided on the oxide insulating layer 407. The potential of the back gate can be a fixed potential, for example, 0V or the ground potential, and can be appropriately determined by the implementer. Also, by providing gate electrodes above and below the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, Moreover, an electrode layer that can function as a back gate may be provided on the oxide insulating layer 407. The potential of the back gate can be a fixed potential, for example, 0V or the ground potential, and can be appropriately determined by the implementer. Also, by providing gate electrodes above and below the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be reduced. That is, by providing gate electrodes above and below the oxide semiconductor layer, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, the reliability can be improved. Also, by controlling the gate voltage applied to the back gate, By this, the threshold voltage can be controlled. Also, with the threshold voltage being positive, it can function as an enhancement-type transistor. Also, with the threshold voltage being negative, it can function as a depletion-type transistor. For example, by combining an enhancement-type transistor and a depletion-type transistor, an inverter circuit (hereinafter referred to as an EDMOS circuit) can be configured and used in a drive circuit. The drive circuit has at least a logic circuit section and a switch section or a buffer section. The logic circuit section has a circuit configuration including the above EDMOS circuit. Also, the operating principle of a bottom-gate type transistor using an oxide semiconductor will be described below. FIG. 7 shows a longitudinal sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating film (GI) on a gate electrode (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. Also, a back gate (GE2) overlapping with the channel formation region of the oxide semiconductor layer (OS) is provided on an oxide insulating layer covering the source electrode (S) and the drain electrode (D). FIG. 8 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 7. FIG. 8(A) shows the case where the voltage between the source and the drain is at an equipotential (VD = 0V), and FIG. 8(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. FIG. 9 shows an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 7.

[0154] Also, the operating principle of a bottom-gate type transistor using an oxide semiconductor will be described below. Explain.

[0155] FIG. 7 shows a longitudinal sectional view of a transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating film (GI) on a gate electrode (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. Also, a back gate (GE2) overlapping with the channel formation region of the oxide semiconductor layer (OS) is provided on an oxide insulating layer covering the source electrode (S) and the drain electrode (D). On the gate electrode (GE1), an oxide semiconductor layer (OS) is provided via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Also, on the oxide insulating layer covering the source electrode (S) and the drain electrode (D), there is a back gate (GE2) overlapping with the channel formation region of the oxide semiconductor layer (OS). FIG. 8 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 7. FIG. 8(A) shows the case where the voltage between the source and the drain is at an equipotential (VD = 0V), and FIG. 8(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. It has a back gate (GE2) overlapping with the channel formation region of the oxide semiconductor layer (OS).

[0156] FIG. 8 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. 7. FIG. 8(A) shows the case where the voltage between the source and the drain is at an equipotential (VD = 0V), and FIG. 8(B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source. (A) shows the case where the voltage between the source and the drain is set to an equipotential (VD = 0V), and FIG. 8( B) shows the case where a positive potential (VD>0) is applied to the drain with respect to the source.

[0157] FIG. 9 shows an energy band diagram (schematic diagram) in the B-B' cross section in FIG. 7. Shows the state when the gate voltage is 0V. Fig. 9(A) shows a state where a positive voltage ( VG>0) is applied to the gate electrode (GE1), and carriers (electrons) flow between the source electrode and the drain electrode, indicating an on state. Also, Fig. 9(B) shows a state where a negative voltage (VG<0) is applied to the gate electrode (GE1), indicating an off state (minority carriers do not flow). (VG<0) is applied, and it shows the case of an off state (minority carriers do not flow). Shown.

[0158] When the thickness of the oxide semiconductor is about 50 nm and the oxide semiconductor is highly purified, the donor concentration is 1×10 18 / cm 3 or less, the depletion layer spreads over the entire oxide semiconductor. That is, it can be regarded as a completely depleted state.

[0159] Fig. 10 shows the relationship between the vacuum level, the work function of the metal (φ M ), and the electron affinity (χ) of the oxide semiconductor. Shown.

[0160] At room temperature, the electrons in the metal are degenerate, and the Fermi level is located within the conduction band. On the other hand , conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (E F ) is away from the intrinsic Fermi level (E ) located at the center of the band gap and is located closer to the conduction band i . It is known that a part of hydrogen in the oxide semiconductor is one of the factors that act as a donor and causes n-type doping. Known.

[0161] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor and highly purifies it so that it contains as few impurities as possible other than the main components of the oxide semiconductor to make it more intrinsic (i-type) or attempt to make it intrinsic. That is, impurities are added or not. ​Rather than being typified, it is highly purified by removing impurities such as hydrogen and water as much as possible. It is characterized by being of the i-type (intrinsic semiconductor) or approaching it. By doing so, the Fermi level (E F ) can be made to the same level as the intrinsic Fermi level (E i ).

[0162] The oxide semiconductor has a band gap (Eg) of 3.05 eV to 3.15 eV. When the band gap (Eg) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor

[0163] interface, a Schottky-type barrier is not formed for electrons. M That is, when the work function of the metal (φ ) and the electron affinity (χ) of the oxide semiconductor are equal,

[0164] when the two are in contact, an energy band diagram (schematic diagram) as shown in Fig. 8(A) is shown. In Fig. 8(B), the black circles (●) indicate electrons. When a positive potential is applied to the drain, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. In this case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage. When a positive drain voltage is applied, the height of the barrier in Fig. 8(A) without voltage application, that is, half of the band

[0165] gap (Eg), is smaller than the height of the barrier (h). At this time, as shown in Fig. 9(A), the electrons are in the gate insulating film and the highly purified oxide semiconductor.It moves to the lowest energy-stable part on the oxide semiconductor side at the interface with

[0166] Also, in Fig. 9(B), when a negative potential (reverse bias) is applied to the gate electrode (GE1), since the number of minority carriers, holes, is substantially zero, the current approaches an infinitely small value.

[0167] By highly purifying the oxide semiconductor so that it contains as few impurities as possible other than the main component, making it intrinsic (i-type) or substantially intrinsic, the interface characteristics with the gate insulating film become apparent, so it is necessary to consider them separately from the bulk characteristics. Therefore, the gate insulating film needs to be able to form a good interface with the oxide semiconductor. For example, an insulating film formed by CVD using high-density plasma generated at a power frequency in the VHF band to microwave band, or an insulating film formed by sputtering is preferably used.

[0168] By highly purifying the oxide semiconductor while making the interface between the oxide semiconductor and the gate insulating film good, even for an element with a channel width W of 1×10 4 μm and a channel length of 3 μm, the off-current is 10 -13 A or less, and the subthreshold swing value (S value) is 0.1 V / dec. (gate insulating film thickness 100 nm), and such characteristics are highly expected.

[0169] Thus, by highly purifying the oxide semiconductor so that it contains as few impurities as possible other than the main component, a non-single crystal can be formed and the operation of the transistor can be made good.

[0170] (Embodiment 2) ​​Embodiment 1 shows the case where an oxide semiconductor material containing the same components is used for the first oxide member and the second oxide member. However, in this embodiment, the case where an oxide semiconductor material having different components is used is shown.

[0171] Similar to Embodiment 1, by the first heat treatment, even if crystal growth occurs from the surface, the tip of the first oxide crystal member 521b does not reach the interface with the base member 520, and an amorphous region 521a remains (see Fig. 11(A)). In Fig. 11(A), the same parts as in Fig. 1(A) are denoted by the same reference numerals for explanation.

[0172] Next, Fig. 11(B) is a cross-sectional view immediately after forming the second oxide member 532 on the first oxide crystal member 521b. The second oxide member 532 is made of a material different from that of the first oxide crystal member 521 b.

[0173] Then, after forming the second oxide member 532, a second heat treatment is performed. By the second heat treatment, crystal growth is performed as shown in Fig. 11(C). As shown in Fig. 11(C), using the non-single crystal layer of the first oxide member 521b as a seed, crystal growth occurs upward toward the surface of the second oxide member, and the second oxide crystal member 533b is formed. Since an oxide semiconductor material having a different component from that of the first oxide crystal member 521b is used as the second oxide member 532, as shown in Fig. 11 (C), a boundary between the first oxide crystal member 521b and the second oxide crystal member 533b is formed. Also, by the second heat treatment, most of the first oxide semiconductor layer is made into a crystal region except in the vicinity of the gate insulating layer interface. (C), a boundary between the first oxide crystal member 521b and the second oxide crystal member 533b is formed. Also, by the second heat treatment, most of the first oxide semiconductor layer is made into a crystal region except in the vicinity of the gate insulating layer interface.

[0174] The structure of Fig. 11(C) is a region 533c that remains in an amorphous state in contact with the base member 520, A three-layer structure can be said to be formed by stacking a first oxide crystal member 533a on it and then a second oxide crystal member 533b on the first oxide crystal member 533a in this order.

[0175] Also, when the second oxide crystal member to be grown and the first oxide crystal member serving as the base are the same, it is called homoepitaxy (homo-crystal growth). When the second oxide crystal member to be grown is different from the first oxide crystal member serving as the base, it is called heteroepitaxy (hetero-crystal growth ). In this embodiment, either of them is possible depending on the selection of each material.

[0176] Also, the conditions for the first heat treatment and the second heat treatment are within the range of the conditions described in Embodiment 1. Note that the implementer may appropriately select conditions such that an intentionally amorphous region 533c remains in contact with the surface of the base member 520.

[0177] In addition, this embodiment can be freely combined with Embodiment 1.

[0178] (Embodiment 3) In this embodiment, a transistor including a laminated oxide material having a crystal layer in which a plurality of crystals are c-axis oriented is manufactured, and the transistor is used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Also, the transistor can be integrally formed on the same substrate as the pixel portion for a part or the whole of the driving circuit to form a system-on-panel.

[0179] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element can be caused by current or voltage. ​The element whose luminance is controlled is included in that category. Specifically, it includes inorganic EL (Electr o Luminescence), organic EL, and the like. Also, display media such as electronic ink, whose contrast changes due to an electrical action, can also be applied.

[0180] Also, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Further, the display device relates to an element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device. The element substrate is provided with means for supplying current to the display element for each of a plurality of pixels. The element substrate may specifically be in a state where only the pixel electrode of the display element is formed, or after forming a conductive layer to be formed into the pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0181] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC (Flexible pr inted circuit), a TAB (Tape Automated Bon ding) tape, or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the end of the TAB tape or the TCP, or a module in which an IC (integrated circ uit) is directly mounted on the display element by the COG (Chip On Glass) method are all included in the display device.

[0182] In this embodiment, an example of a liquid crystal display device is shown as one form of the semiconductor device of the ​Next, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 12. FIG. 12(A) is a top view of a panel in which transistors 4010, 4011, and a liquid crystal element 4013, which include a laminated oxide material having a c-axis oriented crystal layer formed on a first substrate 4001 as a semiconductor layer, are sealed with a sealing material 4005 between the first substrate 4001 and a second substrate 4006. FIG. 12(B) corresponds to a cross-sectional view taken along M-N in FIGS. 12(A1)(A2).

[0183] The sealing material 4005 is provided so as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Further, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 12(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 12(A2) is an example in which the signal line driving circuit 4003 is mounted by the TAB method.

[0184]

[0185] Also, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 ​​​​​​​​​​​​​, having a plurality of transistors, in Fig. 12(B), the transistors 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are exemplified . Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011 .

[0186] The transistors 4010 and 4011 can be applied with transistors including a c-axis oriented crystal layer shown in Embodiment 1. In this embodiment, the transistors 4010 and 4011 are n-channel transistors. In this embodiment, the transistors 4010 and 4011 are n-channel transistors.

[0187] On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer 4040 may be the same as or different from the gate electrode layer of the transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state.

[0188] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030, the counter electrode Layer 4031 is provided with insulating layers 4032 and 4033 that each function as an alignment film, and sandwiches the liquid crystal layer 4008 via the insulating layers 4032 and 4033.

[0189] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, , an FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0190] Also, 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 403 1 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. Also, using a common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 4005.

[0191] Also, a liquid crystal exhibiting a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric liquid crystal phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, improving the temperature range In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0192] In addition, if a liquid crystal that exhibits a blue phase is used, rubbing treatment of the alignment film is not required. This prevents electrostatic damage caused by the soldering process, and prevents the LCD display from being damaged during the manufacturing process. This reduces the number of defects and damages to the device, thereby improving the productivity of liquid crystal display devices. In particular, a transistor including an oxide semiconductor layer can be easily damaged by static electricity. The electrical characteristics of the transistor may vary significantly and deviate from the design range. A liquid crystal display device having a transistor using a blue phase liquid crystal material is provided. is more effective.

[0193] Note that the liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

[0194] In the liquid crystal display device shown in this embodiment mode, a polarizing plate is provided on the outer side (the viewing side) of the substrate. In this example, a colored layer and an electrode layer for use in a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding layer that functions as a light-shielding matrix may be provided.

[0195] In this embodiment, in order to reduce the surface unevenness of the transistor and To improve reliability, the transistor is covered with an insulating layer ( insulating layers 4020 and 4021) that functions as a protective layer and a planarizing insulating layer. The protective layer is for preventing the intrusion of contaminating impurities such as floating organic substances, metal substances, and water vapor in the atmosphere, and a dense film is preferable. The protective layer may be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, or an aluminum nitride oxide layer using a sputtering method. In this embodiment, an example of forming the protective layer by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective layer. Here, a silicon oxide layer is formed as the first layer of the insulating layer 402 0 using a sputtering method. When a silicon oxide layer is used as the protective layer,

[0196] it is effective in preventing hillock formation of the aluminum layer used as the source electrode layer and the drain electrode layer.

[0197] Also, an insulating layer is formed as the second layer of the protective layer. Here, a silicon nitride layer is formed as the second layer of the insulating layer 4020 using a sputtering method. When a silicon nitride layer is used as the protective layer, it is possible to suppress ions such as sodium from entering the semiconductor region and changing the electrical characteristics of the TFT.

[0198] Also, an insulating layer 4021 is formed as the planarizing insulating layer. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) , siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. This is possible. By laminating a plurality of insulating layers formed of these materials, the insulating layer 4021 may be formed.

[0199] Note that the siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group in it.

[0200] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method , spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 4021 using a material liquid, during the baking process, annealing of the semiconductor layer (300 °C to 400 °C) may be performed simultaneously. By combining the baking process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device .

[0201] The pixel electrode layer 4030 and the counter electrode layer 4031 can use a light-transmissive conductive material such as indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

[0202] ​Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less. As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. The various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018. In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011. The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019.

[0203] In FIG. 12, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned. As the conductive polymer, so-called π-electron conjugated conductive polymers can be used.

[0204] Further, the various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018. In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011.

[0205] In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010, 4011 The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019.

[0206] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive layer 4019. In this embodiment, the connection terminal electrode 4015 is formed from the same conductive layer as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed from the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4010, 4011

[0207] In FIG. 12, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit In FIG. 12, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present embodiment is not limited to this configuration. The scanning line driving circuit It may be separately formed and implemented, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and implemented.

[0208] Also, if necessary, a color filter is provided corresponding to each pixel. Also, a polarizing plate and a diffusion plate are provided outside the first substrate 40 01 and the second substrate 4006. Also, the light source of the backlight is composed of a cold cathode tube or an LED to form a liquid crystal display module.

[0209] The liquid crystal display module includes a TN (Twisted Nematic) mode, an IPS (I n-Plane-Switching) mode, an FFS (Fringe Field S witching) mode, an MVA (Multi-domain Vertical A lignment) mode, a PVA (Patterned Vertical Alig nment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated B irefringence) mode, an FLC (Ferroelectric Liqui d Crystal) mode, an AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0210] Through the above steps, a highly reliable liquid crystal display device can be manufactured.

[0211] Also, by using the manufacturing method of the laminated oxide material having the c-axis oriented crystal layer shown in Embodiment 1 to manufacture the transistors of the driving circuit of the liquid crystal display device, the normally-off state of the transistors in the driving circuit unit can be realized, and power saving can be achieved.

[0212] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0213] (Embodiment 4) The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of a semiconductor device This will be described with reference to FIG. 13. FIG. 13 shows a c-axis oriented crystal formed on a first substrate. A transistor and a light-emitting element including a laminated oxide material having a crystal layer are formed between a second substrate and the transistor and the light-emitting element. FIG. 13(B) is a plan view of the panel sealed with a sealing material, and FIG. 13(A) is a plan view of the panel sealed with a sealing material. This corresponds to the cross-sectional view in I.

[0214] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0215] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. In FIG. 13(B), the transistor 4510 included in the pixel portion 4502 and the signal line driving transistor 4509 included in the circuit 4503a are illustrated.

[0216] The transistors 4509 and 4510 can be applied with highly reliable transistors including a c-axis oriented crystal layer shown in Embodiment 1. In this embodiment the transistors 4509 and 4510 are n-channel transistors.

[0217] A conductive layer 4540 is provided at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the driving circuit on the insulating layer 4544. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Further, the potential of the conductive layer 4540 may be the same as or different from the gate electrode layer of the transistor 4509, and it can also function as a second gate electrode layer. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state.

[0218] An insulating layer 4541 is formed in contact with the semiconductor layer including the channel formation region as a protective insulating layer for the transistor 4509. The insulating layer 4541 may be formed by the same material and method as the oxide insulating layer 407 shown in Embodiment 1. Further, it is configured to be covered with an insulating layer 4544 that functions as a planarization insulating layer to reduce the surface unevenness of the transistor. Here, as the insulating layer 4541, a silicon oxide layer is formed by a sputtering method.

[0219] ​​​​​​​​​​​The insulating layer 4544 may be formed by the same materials and methods as the insulating layer 4021 shown in Embodiment 3. Here, acrylic is used as the insulating layer 4544. Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0220] Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. Moreover, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is a pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 has a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0221] The partition wall 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening so as to be an inclined surface having a continuous curvature. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening so as to be an inclined surface having a continuous curvature.

[0222] The electroluminescent layer 4512 may be configured as a single layer or a plurality of layers may be stacked. Either is acceptable.

[0223] A protective layer may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer, or the like can be formed. A protective layer may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer, or the like can be formed. A protective layer may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon oxynitride layer, a DLC layer, or the like can be formed.

[0224] Moreover, various signals and potentials applied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b, or the pixel portion 4502 are transmitted through the FPCs 4518a and 4518. Moreover, various signals and potentials applied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b, or the pixel portion 4502 are transmitted through the FPCs 4518a and 4518. It is supplied from b.

[0225] The connection terminal electrode 4515 is formed of the same conductive layer as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the same conductive layer as the source electrode layer and the drain electrode layer of the transistors 4509 and 4510.

[0226] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive layer 4519.

[0227] The substrate located in the light extraction direction from the light-emitting element 4511 must be light-transmissive. In that case, a light-transmissive material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0228] As the filler 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler.

[0229] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0230] The signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b may be implemented by a driving circuit formed of single-crystalline semiconductor or polycrystalline semiconductor on a separately prepared substrate. Further, only the signal line driving circuit, or a part thereof, or the scanning line driving circuit or a part thereof may be separately formed and implemented, and is not limited to the configuration of FIG. 13.

[0231] By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured.

[0232] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is.

[0233] (Embodiment 5) An example of electronic paper is shown as one form of the semiconductor device.

[0234] The transistor including the laminated oxide material having the c-axis oriented crystal layer obtained by the method shown in Embodiment 1 may be used for an electronic paper that drives electronic ink using an element electrically connected to a switching element. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as the same readability as paper, lower power consumption compared to other display devices, and the ability to be thin and lightweight. The electrophoretic display may have various forms, but a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed.

[0235] Although various forms of the electrophoretic display can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. A plurality of them are dispersed, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. The particles in the capsule are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. It is as described above. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0236] In this way, the electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0237] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using color filters or particles having dyes.

[0238] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by a transistor including a laminated oxide material having a c-axis oriented crystal layer of Embodiment 1 can be used.

[0239] Note that the first particle and the second particle in the microcapsule may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0240] FIG. 14 shows an active matrix type electronic paper as an example of a semiconductor device. ​​​​​​​​​​​As the transistor 581 used in the device, it can be fabricated in the same manner as the transistor shown in Embodiment 1, and is a highly reliable transistor including a laminated oxide material having a c-axis oriented crystal layer.

[0241] The electronic paper in Fig. 14 is an example of a display device using the twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer used as display elements, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0242] The transistor 581 is a transistor having a bottom gate structure and is covered with an insulating layer 583 in contact with the oxide semiconductor layer. The source electrode layer or drain electrode layer of the transistor 581 is in contact with the first electrode layer 587 through openings formed in the insulating layers 583, 584, and 585 and is electrically connected. Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b, and spherical particles 589 are provided between a pair of substrates 580 and 596, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see Fig. 14).

[0243] Also, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the transistor 581. Using a common connection portion, the second electrode layer 588 and the common potential line can be electrically connected through conductive particles arranged between a pair of substrates.

[0244] Alternatively, it is also possible to use an electrophoretic element instead of the element using a twist ball. Microcapsules with a diameter of about 1 0 μm to 200 μm are used, which encapsulate a transparent liquid, positively charged white fine particles, and negatively charged black fine particles. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, enabling the display of white or black. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since an electrophoretic display element has a higher reflectance than a liquid crystal display element, it does not require a backlight, has low power consumption, and enables the recognition of the display section even in a dim place. Also, even when no power is supplied to the display section, it is possible to hold the once-displayed image. Therefore, even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is separated from a radio wave transmission source, the displayed image can be saved.

[0245] Through the above steps, a highly reliable electronic paper can be fabricated.

[0246] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0247] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include, for example, a television device (also referred to as a TV or a television receiver), a monitor for computers, a digital camera, a digital video camera La, digital photo frame, mobile phone (also referred to as mobile phone, mobile phone device), portable Examples include game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines and so on.

[0248] In this embodiment, an example of an electronic device equipped with the display device obtained in any one of Embodiments 3 to 5 will be described with reference to FIG. 15. FIG. 15(A) is a notebook personal computer manufactured by mounting at least the display device as a component, and is composed of a main body 3001, a housing 3002, a display unit 3003, a keyboard

[0249] 3004, etc. Note that the notebook personal computer has the liquid crystal display device shown in Embodiment 3. FIG. 15(B) is a portable information terminal ( PDA) manufactured by mounting at least the display device as a component. The main body 3021 is provided with a display unit 3023, an external interface 3025, and operation buttons 3024, etc. There is also a stylus 302

[0250] 2 as an accessory for operation. Note that the portable information terminal has the light-emitting display device shown in Embodiment 4. FIG. 15(C) is an electronic book manufactured by mounting the electronic paper shown in Embodiment 5 as a component. FIG. 15(C) shows an example of an electronic book. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed around the shaft portion 2711. With such a configuration, it is possible to perform operations similar to those of a paper book. Note that the portable information terminal has the light-emitting display device shown in Embodiment 4.

[0251] FIG. 15(C) is an electronic book manufactured by mounting the electronic paper shown in Embodiment 5 as a component. FIG. 15(C) shows an example of an electronic book. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed around the shaft portion 2711. With such a configuration, it is possible to perform operations similar to those of a paper book. and so on. By such a configuration, it becomes possible to perform operations similar to those of a paper book. and so on.

[0252] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 15C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 15C).

[0253] FIG. 15C shows an example in which an operating unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. A keyboard and a pointing device may be provided on the rear of the housing. On the front or side of the device, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB Equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to function as an electronic dictionary. It is also possible to use the following.

[0254] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0255] FIG. 15(D) shows a mobile phone manufactured by mounting at least a display device as a component. The device is made up of two housings, a housing 2800 and a housing 2801. The housing 2801 has a front It includes a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, etc. Also , the housing 2800 is equipped with a solar cell 2810 for charging the portable information terminal, an external memory slot 2811, etc. Also, the antenna is built inside the housing 2801 .

[0256] Also, the display panel 2802 is equipped with a touch panel, and a plurality of operation keys 2805 shown by dotted lines are displayed as an image in Fig. 15(D). Note that a booster circuit for boosting the voltage output by the solar cell 2810 to the voltage required for each circuit is also implemented.

[0257] The display direction of the display panel 2802 changes appropriately according to the usage form. Also, since the camera lens 2807 is provided on the same plane as the display panel 2802, a video phone is possible . The speaker 2803 and the microphone 2804 are not limited to voice calls, and video phone , recording, playback, etc. are possible. Furthermore, the housing 2800 and the housing 2801 can be slid and changed from the unfolded state as shown in Fig. 15(D) to an overlapping state, enabling miniaturization suitable for portability.

[0258] The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable , enabling charging and data communication with a personal computer, etc. Also, by inserting a recording medium into the external memory slot 2811, it can support storing and transferring a larger amount of data .

[0259] Also, in addition to the above functions, it is equipped with an infrared communication function, a TV reception function, etc. It is also acceptable.

[0260] FIG. 15(E) shows a digital camera fabricated by mounting at least a display device as a component. It includes a main body 3051, a display unit (A) 3057, an eyepiece unit 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056, etc.

[0261] This embodiment can be freely combined with any one of Embodiments 1 to 5.

Example

[0262] In this example, an experiment of laminating oxide members with different target compositions was conducted, and cross-sectional observation was performed. It was carried out.

[0263] For the sample, a silicon oxynitride film (underlayer film) with a film thickness of 30 nm was formed on a glass substrate by the PCVD method, and then an In-Ga-Zn-O film was formed with a setting of 5 nm, and the first heat treatment was performed. After that, an In-Ga-Zn-O film was formed with a setting of 30 nm, and the second heat treatment was performed.

[0264] In Sample 1, the film formation conditions for the 5-nm In-Ga-Zn-O film were as follows: In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] of a metal oxide target was used, the pressure was 0.6 Pa, a DC power supply of 5 kW, in a mixed atmosphere of oxygen and argon (oxygen flow rate 50 sccm, argon flow rate 50 sccm), the substrate temperature was 200 °C, and the film formation rate was 13.4 nm / min. Also, the first heat treatment was carried out at 650 °C for 6 minutes in a nitrogen atmosphere. Also, the conditions for forming the 30-nm In-Ga-Zn-O film formed after the first heat treatment were as follows: In O 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [molar ratio], a metal oxide target was used, at a pressure of 0.6P a, a DC power supply of 0.5 kW, in an oxygen atmosphere (oxygen flow rate 20 sccm), with the substrate temperature at room temperature, and the film was formed at a deposition rate of 13.4 nm / min. Also, the second heat treatment was carried out at 650 °C for 6 minutes in a nitrogen atmosphere

[0265] When the cross-section of sample 1 thus obtained was observed, it was confirmed that crystallization occurred from the surface of the underlayer film to 3.5 nm to 5 .2 nm, and further, it was confirmed that the lower In-Ga-Zn-O film was crystallized from the surface to 1.2 to 1.5 nm. Also, the region from 6 nm to 34 nm from the surface of the underlayer film was in an amorphous state

[0266] Note that the vicinity of the interface between the In-Ga-Zn-O film and the underlayer film was not crystallized and was confirmed to be in an amorphous state

[0267] Also, as a comparative example, the cross-section of sample 2 without the second heat treatment was observed. It was confirmed that crystallization occurred from the surface of the lower In-Ga-Zn-O film to 0.5 to 1.5 nm In sample 2, a 5 nm In-Ga-Zn-O film was formed under the same film formation conditions as the 5 n m In-Ga-Zn-O film of sample 1. The film formation conditions for the 30 nm In-Ga-Zn- O film were as follows: using a metal oxide target with In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio], at a pressure of 0.6 Pa, a DC power supply of 5 kW, in a mixed atmosphere of oxygen and argon (oxygen flow rate 50 sccm, argon flow rate 50 sccm), with the substrate temperature at 200 °C and the film was formed at a deposition rate of 13.4 nm / min ​​​​​​​

[0268] Also, under the same sample preparation conditions as in Sample 2, and further under a nitrogen atmosphere, heat treatment was performed at 650°C for 6 minutes for the second When cross-sectional observation of Sample 3, which had undergone the heat treatment, was carried out, it was confirmed that crystallization had progressed with orientation from near the base film to the surface of the upper In-Ga-Zn-O film. The thickness of the crystallized film was 28 nm to 30 nm. However, also in this Sample 3, it was confirmed that the vicinity of the interface between the In-Ga-Zn-O film and the base film was not crystallized and was in an amorphous state.

[0269] Also, as Sample 4, after forming a silicon oxynitride film (base film) with a thickness of 30 nm on a glass substrate by the PCVD method, an In-Ga-Zn-O film was formed with a setting of 3 nm, and after the first heat treatment, an In-Ga-Zn-O film was formed with a setting of 30 nm, and the second heat treatment was performed. The film formation conditions for both the 3 nm and 30 nm In-Ga-Zn-O films were such that for both, an In O :Ga 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] metal oxide target was used , under a pressure of 0.6 Pa, a DC power supply of 5 kW, in a mixed atmosphere of oxygen and argon (oxygen flow rate 50 sccm, argon flow rate 50 sccm), a substrate temperature of 200°C, and a film formation rate of 13.4 nm / min.

[0270] Also, in Sample 4, both the first heat treatment and the second heat treatment were carried out at 670°C for 6 minutes under a nitrogen atmosphere.

[0271] When cross-sectional observation of Sample 4 thus obtained was carried out, the In-Ga-Zn-O film and the base ​​​​It was confirmed that the interface of the film was also crystallized. Furthermore, in the upper In-Ga-Zn-O film, it was confirmed that crystallization occurred partially along the orientation of the underlying film side. Also, from the surface of the lower In-Ga-Zn-O film, crystallization has occurred and the orientation can be confirmed.

[0272] Thus, since the region where crystallization occurs also differs depending on the composition of the oxide semiconductor film, the film thickness of the oxide semiconductor film, the film formation conditions of the oxide semiconductor film , and the heat treatment conditions after forming the oxide semiconductor film, it is preferable for the implementer to appropriately adjust the manufacturing conditions of the device.

Explanation of symbols

[0273] 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 First oxide semiconductor layer 404 Second oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Oxide insulating layer 430 Oxide semiconductor laminate 431 Oxide semiconductor laminate 432 Oxide semiconductor laminate 470 Transistor 501 Oxide member 520 Underlying member 521a Amorphous region 521b Oxide crystal member 522 Oxide member 523a Oxide crystal member 523b Oxide crystal member 523c Region remaining in amorphous state 532 Oxide member 533b Oxide crystal member 580 Substrate 581 Transistor 583 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particle 590a Black region 590b White region 594 Cavity 595 Filling material 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 2800 Housing 2801 Housing 2802 Display panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing device 2807 Camera lens 2808 External connection terminal 2810 Solar cell 2811 External memory slot 3001 Main body 3002 Housing 3003 Display unit 3004 Keyboard 3021 Main body 3022 Stylus 3023 Display unit 3024 Operation button 3025 External interface 3051 Main body 3053 Eyepiece 3054 Operation switch 3055 Display unit (B) 3056 Battery 3057 Display unit (A) 4001 Substrate 4002 Pixel portion 4003 Signal line drive circuit 4004 Scanning line drive circuit Sealing material 4005 Second substrate 4006 Liquid crystal layer 4008 Transistor 4010 Transistor 4011 Liquid crystal element 4013 Connection terminal electrode 4015 Terminal electrode 4016 FPC 4018 Anisotropic conductive layer 4019 Insulating layer 4020 Insulating layer 4021 Pixel electrode layer 4030 Counter electrode layer 4031 Insulating layer 4032 Conductive layer 4040 First substrate 4501 Pixel portion 4502 Signal line drive circuit 4503a, 4503b Scan line drive circuit 4504a, 4504b Sealing material 4505 Second substrate 4506 Filling material 4507 Transistor 4509 Transistor 4510 Light emitting element 4511 Electroluminescent layer 4512 Electrode layer 4513 Connection terminal electrode 4515 Terminal electrode 4516 Electrode layer 4517 FPC 4518a, 4518b Anisotropic conductive layer 4519 Partition wall 4520 Conductive layer 4540 Insulating layer 4541 Insulating layer 4544

Claims

1. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; the second layer contains more Zn than In; an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; a first crystalline region of the first region is non-single crystalline; a second crystalline region of the second region is non-single crystalline; A semiconductor device, wherein the third crystal region of the third region is non-single crystal.

2. A first conductive layer; and an insulating film having a region on the first conductive layer; an oxide semiconductor film on the insulating film; a second conductive layer having a region over the oxide semiconductor film; and a third conductive layer having a region over the oxide semiconductor film, the first conductive layer has a region that functions as a gate electrode of a transistor; the insulating film has a region that functions as a gate insulating film of the transistor, the oxide semiconductor film includes a channel formation region of the transistor, the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the transistor, the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the transistor, the oxide semiconductor film includes a first layer and a second layer having a region on the first layer, the first layer comprises In, Ga, and Zn; the second layer comprises In, Ga, and Zn; the second layer contains more Zn than In; an interface between the first layer and the second layer is provided away from a surface of the insulating film, the second layer has a first region overlapping an upper surface of the first conductive layer, a second region not overlapping the first conductive layer, and a third region between the first region and the second region in a plan view; a surface of the third region is not parallel to a surface of the first region; a first crystalline region of the first region is non-single crystalline; a second crystalline region of the second region is non-single crystalline; A semiconductor device, wherein the third crystal region of the third region is non-single crystal.

3. In claim 1 or 2, A semiconductor device, wherein the surface of the first region has a region having a height difference of 1 nm or less in an area of ​​1 μm square measured by AFM.

4. In any one of claims 1 to 3, The insulating film is a laminate of a first silicon oxide layer and a first silicon nitride layer.

5. In any one of claims 1 to 4, a second silicon oxide layer over the oxide semiconductor film; a second silicon nitride layer on the second silicon oxide layer;

6. In any one of claims 1 to 5, a planarization insulating layer having a region on the oxide semiconductor film; a pixel electrode on the planarization insulating layer; The pixel electrode is electrically connected to the transistor.

7. In any one of claims 1 to 5, a planarization insulating layer having a region on the oxide semiconductor film; and a light-emitting element on the planarization insulating layer.

8. In any one of claims 1 to 7, a fifth conductive layer having a region over the oxide semiconductor film; the fifth conductive layer has a region that functions as a second gate electrode of the transistor.

9. In any one of claims 1 to 8, the first conductive layer has a region that functions as a scan line; The region functioning as the scanning line extends in a first direction, A semiconductor device, wherein a channel length direction of the transistor is the first direction.

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