Semiconductor heat treatment material

Abstract

To provide a semiconductor heat treatment material that can improve thermal uniformity.SOLUTION: A semiconductor heat treatment material 10 holds a wafer W and is placed inside a semiconductor heat treatment device for use. The semiconductor heat treatment material 10 is, for example, ring-shaped and has a frame 11 and a wafer holding portion 12 formed inside the frame 11 for loading the wafer W. The upper surface of the wafer holding portion 12 is a wafer loading surface 12A for loading the wafer W. The wafer loading surface 12A is configured to have an inclination angle θ of 11 degrees or more and 20 degrees or less with respect to a horizontal plane when the semiconductor heat treatment material 10 is placed inside the semiconductor heat treatment device. The wafer loading surface 12A is provided with 4 to 16 grooves 12B spaced apart in the circumferential direction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a ring-shaped semiconductor heat treatment member that is disposed inside a semiconductor heat treatment apparatus and holds a wafer.

Background Art

[0002] In the semiconductor manufacturing process, an RTP (Rapid Thermal Process) apparatus has come to be used as a technique for heat-treating a wafer using a semiconductor heat treatment apparatus. The RTP apparatus uses a heating method using lamp heating, and can rapidly heat a wafer to 1000 ° C or higher in several tens of seconds, and can form an oxide film with good in-plane uniformity by controlling the lamp. In the processing chamber of the RTP apparatus, for example, a wafer W is held using a semiconductor heat treatment member 100 made of a ring-shaped silicon carbide as shown in FIG. 6, and heat treatment is performed. This is because silicon carbide has high heat resistance and thermal conductivity, so that the wafer can be uniformly heated and is not easily damaged. Further, the wafer loading surface 101 for loading the wafer W is formed so as to be substantially parallel to the surface of the wafer W when the wafer W is loaded, for example.

[0003] However, for example, a 12-inch wafer W is heavy, and when held at the inner edge of the wafer loading surface 101 of the semiconductor heat treatment member 100, it is greatly curved. Therefore, the wafer W comes into contact with the semiconductor heat treatment member 100 with a large force, and scratches are easily formed on the bottom surface of the wafer W. When scratches occur, slip is likely to occur in the defects in the crystal structure of the wafer W, so it is not preferable for scratches to occur. Therefore, for example, Patent Document 1 describes a semiconductor processing member in which an inclination of about 1 degree to about 10 degrees is provided on the wafer loading surface so that the edge portion of the wafer comes into contact with the wafer loading surface in order to make it difficult for scratches to occur on the wafer.

Prior Art Documents

Patent Documents

[0004] Patent Document 1 Japanese Patent Laid-Open No. 10-173032 Summary of the Invention Problems to be Solved by the Invention

[0005] However, in the semiconductor heat treatment member described in Patent Document 1, although the generation of scratches can be suppressed, there is a problem that the in-plane uniformity of the oxide film is insufficient. In a semiconductor heat treatment apparatus such as an RTP apparatus, heat is transferred from the wafer loading surface to the wafer when the wafer loading surface of the semiconductor heat treatment member comes into contact with the wafer. Therefore, in order to make the formation of the oxide film uniform, it is required to enhance the heat uniformity within the wafer surface. In order to enhance the heat uniformity within the wafer surface, it is required to reduce the contact area between the wafer loading surface and the wafer.

[0006] The present invention has been made based on such problems, and an object thereof is to provide a semiconductor heat treatment member capable of enhancing heat uniformity. Means for Solving the Problems

[0007] The semiconductor heat treatment member of the present invention is a ring-shaped member that is disposed inside a semiconductor heat treatment apparatus and holds a wafer. It has a wafer loading surface for loading the wafer. When the wafer loading surface is disposed inside the semiconductor heat treatment apparatus, it has an inclination angle of 11 degrees or more and 20 degrees or less with respect to the horizontal plane. On the wafer loading surface, 4 or more and 16 or less grooves are provided at intervals in the circumferential direction. Effects of the Invention

[0008] According to the semiconductor heat treatment member of the present invention, when it is disposed in a semiconductor heat treatment apparatus, the wafer loading surface has an inclination angle of 11 degrees or more and 20 degrees or less with respect to the horizontal plane, and 4 or more and 16 or less grooves are provided at intervals in the circumferential direction on the wafer loading surface. Therefore, the contact area between the wafer loading surface and the wafer can be reduced. Thus, the heat uniformity of the wafer can be enhanced, and the variation in the oxide film thickness can be reduced.

[0009] In particular, for each groove, if the depth is set to be 0.05 mm or more and 0.10 mm or less, and the width is set to be 5 mm or more and 10 mm or less, a higher effect can be obtained.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 shows the overall configuration of a semiconductor heat treatment member 10 according to an embodiment of the present invention. FIGS. 2 and 3 show cross-sectional configurations along the line I-I shown in FIG. 1. FIG. 4 shows a cross-sectional configuration along the line II-II shown in FIG. 1. FIG. 5 shows the configuration of a semiconductor heat treatment apparatus 20 for heat-treating a wafer W using the semiconductor heat treatment member 10. The semiconductor heat treatment member 10 holds the wafer W and is disposed and used inside the semiconductor heat treatment apparatus 20. The semiconductor heat treatment member 10 can be suitably used, for example, as an RTP apparatus as the semiconductor heat treatment apparatus 20. In the present embodiment, an RTP apparatus is taken as an example of the semiconductor heat treatment apparatus 20, and the case of performing a film formation process of an oxide film on the surface of the wafer W will be described.

[0013] The semiconductor heat treatment member 10 is, for example, ring-shaped and has a ring-shaped frame portion 11 and a wafer holding portion 12 formed inside the frame portion 11 for loading the wafer W. The semiconductor heat treatment member 10 is preferably constituted by, for example, a member in which an oxide film is formed on the surface of a base material made of silicon carbide. By providing the oxide film, stress is applied in the direction of the base material, and even if the thickness of the base material is reduced, damage due to thermal stress can be suppressed. The base material is preferably constituted by a silicon carbide sintered body or a free-standing film silicon carbide. The free-standing film silicon carbide is, for example, a silicon carbide film formed on a base member made of graphite or the like and then the base member is burned off.

[0014] The film thickness of the oxide film is preferably, for example, 0.5 μm or more and 3 μm or less, and more preferably 0.8 μm or more and 1.2 μm or less. If the film thickness of the oxide film is less than 0.5 μm, when the base material is formed thinly, the resistance to mechanical load and load due to thermal cycle becomes low. On the other hand, if the film thickness of the oxide film is more than 3 μm, the thermal conductivity decreases, and there is a risk of unevenness in the heat treatment result. There is also a risk that the oxide film peels off and causes wafer contamination by particles.

[0015] The wafer holding portion 12 is provided, for example, below the inside of the frame portion 11, and a step is provided between the frame portion 11 and the wafer holding portion 12. The inner diameter of the frame portion 11 is not particularly limited as long as the wafer W can be fitted therein, and can be set to any size according to the outer diameter of the wafer W to be heat-treated. On the upper surface of the frame portion 11, for example, when the semiconductor heat treatment member 10 is disposed inside the semiconductor heat treatment apparatus 20, it is preferable that a flat surface 11A that is horizontal is formed.

[0016] The inner diameter of the wafer holding part 12 is not particularly limited as long as the wafer W can be loaded, and can be set to any size according to the outer diameter of the wafer W to be heat-treated. The thickness of the wafer holding part 12 (the combined thickness of the base material and the oxide film) is preferably 1 mm or less, and more preferably 0.5 mm or less. This is because by making the wafer holding part 12 thinner, the heat capacity of the base material becomes smaller, and the heat responsiveness can be improved. Also, the thickness of the wafer holding part 12 is preferably 0.20 mm or more to ensure strength.

[0017] The upper surface of the wafer holding part 12 is a wafer loading surface 12A for loading the wafer W. The wafer loading surface 12A is inclined, for example, such that the inner side is lower than the outer side, and when the semiconductor heat treatment member 10 is disposed inside the semiconductor heat treatment apparatus 20, it is configured to have an inclination angle θ of 11 degrees or more and 20 degrees or less with respect to the horizontal plane H. That is, the wafer loading surface 12A is preferably configured to have an inclination angle θ of 11 degrees or more and 20 degrees or less with respect to the flat part 11A of the frame part 11, for example. This is because the contact area between the wafer W and the wafer loading surface 12A can be reduced, and the heat uniformity of the wafer W can be enhanced.

[0018] Also, by inclining the wafer loading surface 12A as described above, when the wafer W is loaded on the wafer loading surface 12A, the edge portion of the wafer W can be made to substantially contact the wafer loading surface 12A. Therefore, even if the wafer W is curved, it is possible to suppress the bottom surface of the wafer W from contacting the wafer loading surface 12A and scratching the bottom surface of the wafer W. The inclination angle θ of the wafer loading surface 12A is preferably larger than the angle of the edge portion of the wafer W, for example.

[0019] On the wafer mounting surface 12A, it is preferable that 4 or more and 16 or less grooves 12B are provided at intervals in the circumferential direction. This is because the contact area between the wafer W and the wafer mounting surface 12A can be made smaller. The depth of each groove 12B is preferably, for example, 0.05 mm or more and 0.10 mm or less, and the width (circumferential width) of each groove 12B is preferably, for example, 5 mm or more and 10 mm or less. This is because a higher effect can be obtained while ensuring strength. Each groove 12B is preferably formed along the radial direction, for example, and is preferably arranged at equal intervals in the circumferential direction. In addition, each groove 12B may be formed entirely along the radial direction of the wafer mounting surface 12A as shown in FIG. 2, for example, or may be formed in a partial region where the wafer W contacts as shown in FIG. 3.

[0020] The semiconductor heat treatment member 10 can be manufactured, for example, as follows. First, a base material made of silicon carbide is produced. Specifically, for example, silicon carbide is formed into a predetermined ring-shaped molded body, and this molded body is sintered. Also, for example, a silicon carbide film is formed on the surface of a base member made of graphite or the like by CVD method, and then the base member is burned away and removed. Next, for example, the surface of the base material is ground and polished with a diamond grindstone. Subsequently, an oxide film is formed on the surface of the base material by applying heat at 1000°C or more and 1300°C or less in an oxidizing atmosphere to perform an oxidation treatment. Thereby, the semiconductor heat treatment member 10 is obtained.

[0021] The semiconductor heat treatment member 10 is used in the semiconductor heat treatment apparatus 20, for example, as follows. This semiconductor heat treatment apparatus 20 is an RTP apparatus, and includes, for example, a chamber (reaction tube) 23 having an atmosphere gas inlet 21 and an atmosphere gas outlet 22, a plurality of lamps 24 spaced apart and arranged above the chamber 23, and a substrate support portion 25 that supports the wafer W inside the chamber 23. Although not shown, it also includes a rotating means for rotating the wafer W at a predetermined speed around its central axis.

[0022] The substrate support unit 25 includes a semiconductor heat treatment member 10 and a stage 25A that supports the semiconductor heat treatment member 10. The semiconductor heat treatment member 10 is arranged such that, for example, the flat surface 11A of the frame portion 11 is horizontal and the wafer mounting surface 12A has an inclination angle θ of 11 degrees or more and 20 degrees or less with respect to the horizontal plane. The chamber 23 is made of, for example, quartz. The lamp 24 is made of, for example, a halogen lamp. The stage 25A is made of, for example, quartz. This semiconductor heat treatment apparatus 20 can uniformly heat and process the entire wafer W at a temperature gradient of, for example, 10°C / second to 300°C / second during heating or cooling.

[0023] In this semiconductor heat treatment apparatus 20, the heat treatment of the wafer W is performed as follows. First, the wafer W is loaded and fixed on the semiconductor heat treatment member 10. At this time, it is preferable to load the wafer W such that the upper surface of the wafer W is substantially parallel to the flat surface 11A of the frame portion 11. The wafer W is in contact with the wafer mounting surface 12A substantially at the edge portion. Next, the semiconductor heat treatment member 10 on which the wafer W is loaded is placed above the stage 25A inside the chamber 23.

[0024] Subsequently, a process gas is introduced into the chamber 23 through the atmosphere gas inlet 21 and the internal gas is exhausted from the atmosphere gas outlet 22 to form a predetermined air flow above the wafer W. Next, the lamps 24 arranged in an equidistant manner are individually controlled by feedback from the surface temperature of the wafer W to rapidly heat (for example, to about 1,000°C in several tens of seconds) while controlling the surface temperature of the wafer W, thereby performing a heat treatment on the wafer W. As a result, a desired oxide film is formed on the surface of the wafer W.

[0025] Thus, according to this embodiment, when arranged in the semiconductor heat treatment apparatus 20, the wafer mounting surface 12A has an inclination angle of 11 degrees or more and 20 degrees or less with respect to the horizontal plane, and 4 or more and 16 or less grooves 12B are provided at intervals in the circumferential direction on the wafer mounting surface 12A. Therefore, the contact area between the wafer mounting surface 12A and the wafer W can be reduced. Thus, the heat uniformity of the wafer W can be enhanced and the variation in the oxide film thickness can be reduced.

[0026] In particular, for each groove 12B, if the depth is set to be 0.05 mm or more and 0.10 mm or less, and the width is set to be 5 mm or more and 10 mm or less, a higher effect can be obtained.

Example

[0027] As Examples 1 to 4 and Comparative Examples 1 to 4, semiconductor heat treatment members 10 as shown in FIGS. 1, 2, and 4 were produced. In each example and each comparative example, the inclination angle θ of the wafer mounting surface 12A and the number of grooves 12B were changed, and the others were the same. The inclination angle θ of the wafer mounting surface 12A was 11 degrees in Example 1, 20 degrees in Example 2, 11 degrees in Example 3, 20 degrees in Example 4, 8 degrees in Comparative Example 1, 25 degrees in Comparative Example 2, 11 degrees in Comparative Example 3, and 20 degrees in Comparative Example 4. The number of grooves 12B was 4 in Example 1, 4 in Example 2, 16 in Example 3, 16 in Example 4, 4 in Comparative Example 1, 4 in Comparative Example 2, 3 in Comparative Example 3, and 3 in Comparative Example 4. In each example and each comparative example, the grooves 12B were provided at equal intervals in the circumferential direction, the width of the grooves 12B was 10 mm, and the depth of the grooves was 0.05 mm.

[0028] Also, in each example and each comparative example, the semiconductor heat treatment member 10 was produced by producing a base material made of silicon carbide, and then applying heat to the base material at 1000 ° C or more and 1300 ° C or less in an oxidizing atmosphere for oxidation treatment to form an oxide film with a thickness of 1.0 μm on the surface of the base material.

[0029] The wafer W was held on each produced semiconductor heat treatment member 10 of each example and each comparative example, and heat treatment was performed by a semiconductor heat treatment apparatus 20 as shown in FIG. 5 to form an oxide film on the surface of the wafer W, and the in-plane uniformity of the wafer oxide film and the occurrence status of scratches were examined. The heat treatment conditions of the wafer W were 1000 degrees or more and 1150 degrees or less in a dry oxidation atmosphere for 60 seconds or more and 300 seconds or less.

[0030] The in-plane uniformity of the wafer oxide film was evaluated by non-contact measurement of the wafer surface at 4 million arbitrary points at equal intervals using a reflection spectroscopic film thickness measuring machine. Regarding the evaluation of the in-plane uniformity of the wafer oxide film, a case where the variation of the oxide film in the plane of the wafer W was within 0.1 μm was regarded as good, and a case where it exceeded 0.1 μm was regarded as bad. Also, regarding the occurrence situation of scratches, the surface of the wafer W was measured in the Normal mode of a laser particle counter. Regarding the evaluation of the occurrence situation of scratches, a case where the scratch size was less than 36 nm was regarded as good, and a case where the scratch size exceeded 36 nm was regarded as bad. Table 1 shows the conditions and results of each example and each comparative example. In Table 1, regarding the in-plane uniformity of the wafer oxide film and the occurrence situation of scratches, "○" was used for good cases and "×" was used for bad cases.

[0031]

Table 1

[0032] As shown in Table 1, in Comparative Example 1 where the inclination angle θ of the wafer mounting surface 12A was 8 degrees and the number of grooves 12B was 4, the in-plane variation of the wafer oxide film was larger than 0.1 μm, and scratches occurred on the bottom surface of the wafer W in contact with the edge of the groove 12B. In Comparative Example 2 where the inclination angle θ of the wafer mounting surface 12A was 25 degrees and the number of grooves 12B was 4, it became difficult to stably place the wafer W on the wafer mounting surface 12A, and it became difficult to keep the wafer W and the lamp 24 parallel, so the in-plane variation of the wafer oxide film was larger than 0.1 μm. Also, in Comparative Example 3 where the number of grooves 12B was 3 and Comparative Example 4, the parallelism between the wafer W and the lamp 24 deteriorated, and the in-plane variation of the wafer oxide film was larger than 0.1 μm.

[0033] On the other hand, according to Examples 1 to 4 in which the inclination angle θ of the wafer mounting surface 12A is set to 11 degrees to 20 degrees and the number of grooves 12B is set to 4 to 16, the in-plane variation of the wafer oxide film was as small as within 0.1 μm, and the scratch size was also smaller than 36 nm. That is, it was found that it is preferable to set the inclination angle θ of the wafer mounting surface 12A to 11 degrees or more and 20 degrees or less, and to provide 4 or more and 16 or less grooves 12B on the wafer mounting surface 12A at intervals in the circumferential direction.

[0034] As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments and can be variously modified. For example, in the above embodiments, the manufacturing method has been specifically described, but it is not limited thereto.

Explanation of Reference Numerals

[0035] 10... semiconductor heat treatment member, 11... frame portion, 11A... flat surface, 12... wafer holding portion, 12A... wafer mounting surface, 12B... groove, 20... semiconductor heat treatment apparatus, 21... atmosphere gas inlet, 22... atmosphere gas outlet, 23... chamber, 24... lamp, 25... substrate support portion, 25A... stage, W... wafer

Claims

1. A ring-shaped semiconductor heat treatment member disposed inside a semiconductor heat treatment apparatus for holding a wafer, having a wafer loading surface for loading the wafer, wherein the wafer loading surface has an inclination angle of 11 degrees or more and 20 degrees or less with respect to a horizontal plane when disposed inside the semiconductor heat treatment apparatus, and the wafer loading surface is provided with four or more and sixteen or less grooves spaced apart in the circumferential direction. A semiconductor heat treatment member characterized by the above.

2. The semiconductor heat treatment member according to claim 1, wherein each of the grooves has a depth of 0.05 mm or more and 0.10 mm or less and a width of 5 mm or more and 10 mm or less.

3. The semiconductor heat treatment member according to claim 1, which is constituted by a substrate made of silicon carbide having an oxide film formed on its surface.

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