Gate driver circuit, motor driver device using the same, and electronic apparatus

Abstract

To provide a gate driver circuit capable of operating at a duty cycle of 100%.SOLUTION: A logic circuit 210 generates a high-side control signal HCTRL and a low-side control signal LCTRL, so as to turn on a high-side transistor MH and turn off a low-side transistor ML when a control signal SCTRL is in a first state φ1, and turn off the high-side transistor MH and turn on the low-side transistor ML when the control signal SCTRL is in a second state. A charging circuit 280 includes a charge pump circuit 282 capable of controlling on and off, and configured to charge a boot strap line 202 when the charge pump circuit 282 is turned on. The logic circuit 210 turns on the charge pump circuit 282 when the control signal SCTRL is in the first state φ1 for a predetermined first determination time τ1.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a gate driver circuit.

Background Art

[0002] In motor driver circuits, DC / DC converters, power conversion devices, etc., half-bridge circuits, H-bridge circuits, three-phase bridge circuits (hereinafter collectively referred to as bridge circuits) using power transistors are frequently used.

[0003] When the high-side transistor of the bridge circuit is composed of an N-type transistor, that is, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or an NPN-type bipolar transistor, a bootstrap circuit is used.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] A gate driver circuit using a bootstrap circuit cannot keep the high-side transistor turned on for a long time and cannot fix the bridge circuit in a high-output state. This means that an operation with a 100% duty cycle is impossible.

[0006] The present disclosure has been made in view of such problems, and an exemplary object of one of its aspects is to provide a gate driver circuit operable at a 100% duty cycle.

[0007] One aspect of the present disclosure relates to a gate driver circuit that drives a switching circuit including an N-type high-side transistor and an N-type low-side transistor in response to a control signal. The gate driver circuit includes a bootstrap line, a switching line to be connected to the source of the high-side transistor, and a logic circuit that generates a high-side control signal and a low-side control signal such that when the control signal is in a first state, the high-side transistor is turned on and the low-side transistor is turned off, and when the control signal is in a second state, the high-side transistor is turned off and the low-side transistor is turned on. The gate driver circuit also includes a high-side driver that controls the gate voltage of the high-side transistor in response to the high-side control signal, with the upper power supply node connected to the bootstrap line and the lower power supply node connected to the switching line, a low-side driver that controls the gate voltage of the low-side transistor in response to the low-side control signal, and a charge pump circuit whose on / off state can be controlled. The charge pump circuit is configured to charge the bootstrap line when it is turned on. The logic circuit turns on the charge pump circuit when the control signal is in the first state for a predetermined first determination time.

[0008] In addition, combinations of the above components arbitrarily, and those obtained by mutually replacing the components and expressions of the present disclosure between methods, apparatuses, systems, etc. are also effective as aspects of the present invention.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0010] [Detailed Description] (Overview of the Embodiment) An overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description below and is intended to provide a basic understanding of the embodiments by simplifying some concepts of one or more embodiments. It does not limit the scope of the invention or the disclosure. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed in this specification.

[0011] This overview is not an exhaustive overview of all possible embodiments and is not intended to identify important elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present, in a simplified form, some concepts of one or more embodiments as a prelude to the more detailed description presented later.

[0012] The gate driver circuit according to one embodiment drives a switching circuit including an N-type high-side transistor and an N-type low-side transistor in response to a control signal. The gate driver circuit includes a bootstrap line, a switching line to be connected to the source of the high-side transistor, and a logic circuit that generates a high-side control signal and a low-side control signal such that when the control signal is in the first state, the high-side transistor is turned on and the low-side transistor is turned off, and when the control signal is in the second state, the high-side transistor is turned off and the low-side transistor is turned on. The gate driver circuit also includes a high-side driver that controls the gate voltage of the high-side transistor in response to the high-side control signal, with the upper power supply node connected to the bootstrap line and the lower power supply node connected to the switching line, a low-side driver that controls the gate voltage of the low-side transistor in response to the low-side control signal, and a charge pump circuit whose on and off states are controllable. The charge pump circuit is configured to charge the bootstrap line when it is turned on. The logic circuit turns on the charge pump circuit when the control signal is in the first state over a predetermined first determination time.

[0013] According to this configuration, by operating the charge pump circuit intermittently instead of constantly, it is possible to reduce power consumption while obtaining an output with a 100% duty cycle.

[0014] In one embodiment, the first determination time may be longer than the period of the pulse width modulation of the control signal.

[0015] In one embodiment, the high-side driver may include a current source and a current mirror circuit that folds back the current generated by the current source and supplies it to the gate of the high-side transistor. When the charge pump circuit is on, the amount of current of the current source may be smaller than when it is off.

[0016] In one embodiment, the current amount of the current source when the charge pump circuit is on may be smaller than the current supply capacity of the charge pump circuit.

[0017] In one embodiment, the logic circuit may turn off the charge pump circuit when the control signal changes from the first state to the second state.

[0018] In one embodiment, when the control signal is in the third state, the logic circuit generates a high-side control signal and a low-side control signal so that the high-side transistor is off and the low-side transistor is off, and the logic circuit may turn on the charge pump circuit when the control signal is in the third state for a predetermined second determination time.

[0019] In one embodiment, the logic circuit may turn off the charge pump circuit when the control signal changes from the first state to the third state.

[0020] In one embodiment, the logic circuit may turn on the charge pump circuit when the control signal changes from the third state to the first state or the second state.

[0021] In one embodiment, the logic circuit may turn on the charge pump circuit when the control signal is in the second state for a predetermined third determination time.

[0022] In one embodiment, the logic circuit may turn on the charge pump circuit when the control signal changes from the second state to the first state.

[0023] In one embodiment, the gate driver circuit may be integrally integrated on a single semiconductor substrate. "Integral integration" includes cases where all of the circuit components are formed on the semiconductor substrate, or cases where the main components of the circuit are integrally integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced, and the characteristics of the circuit elements can be kept uniform.

[0024] The mode driving circuit according to one embodiment includes a bridge circuit including a high-side transistor and a low-side transistor, and any one of the above-described gate driver circuits that drives the high-side transistor and the low-side transistor.

[0025] An electronic device according to one embodiment may include a motor and the above-described motor driving device that drives the motor.

[0026] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and repeated descriptions will be omitted as appropriate. Also, the embodiments are illustrative and not restrictive of the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0027] In this specification, the phrase "member A is in a state of being connected to member B" includes not only cases where member A and member B are physically directly connected, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0028] Similarly, the phrase "member C is provided between member A and member B" includes not only the case where member A and member C or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0029] FIG. 1 is a circuit diagram of a switching circuit 100 according to an embodiment. The switching circuit 100 includes a bridge circuit 110 and a gate driver circuit 200. Here, only the configuration of one phase of the switching circuit 100 is shown, but the switching circuit 100 may be three-phase or an H-bridge circuit.

[0030] The bridge circuit 110 includes an upper arm 112 provided between a power line (input line) 102 and an output terminal (output line) 104, and a lower arm 114 provided between the output line 104 and a ground line 106. The upper arm 112 includes an N-type high-side transistor MH. The lower arm 114 includes an N-type low-side transistor ML. Depending on the application, a shunt resistor for current detection may be inserted between the low-side transistor ML and the ground line 106.

[0031] The gate driver circuit 200 controls the high-side transistor MH and the low-side transistor ML of the bridge circuit 110 based on the control signal S CTRL The control signal S CTRL can take three states φ1 to φ3.

[0032] The first state φ1 is a high-output state (V OUT = V IN ) indicating that the high-side transistor MH is on and the low-side transistor ML is off.

[0033] The second state φ2 is a low-output state (V OUT = 0V) indicating that the high-side transistor MH is off and the low-side transistor ML is on.

[0034] The third state φ3 is a high-impedance state (V OUT =HiZ) indicating that the high-side transistor MH is off and the low-side transistor ML is off.

[0035] The gate driver circuit 200 includes a logic circuit 210, a timer circuit 212, a high-side driver 220, a low-side driver 260, a charging circuit 280, and a rectifying element 286, and is a functional IC integrated on one semiconductor substrate.

[0036] The high-side gate pin HG of the gate driver circuit 200 is connected to the gate of the high-side transistor MH, and the low-side gate pin LG is connected to the gate of the low-side transistor ML. The ground pin GND is connected to the source of the low-side transistor ML. The switching pin SW is connected to the output line 104. A bootstrap capacitor C BST is externally connected between the bootstrap pin BST and the switching pin SW.

[0037] The bootstrap line 202 is connected to the bootstrap pin BST, the switching line 204 is connected to the switching pin SW, and the ground line 206 is connected to the GND pin. A constant voltage V REG is applied to the bootstrap line 202 via the rectifying element 286. The rectifying element 286 and the bootstrap capacitor C BST form a bootstrap circuit, and using the switching operation of the bridge circuit 110, a bootstrap voltage V OUT that is higher than the voltage (switching voltage) V BST of the switching line 204 by a predetermined voltage ΔV is generated on the bootstrap line 202. When the forward voltage of the rectifying element 286 is Vf, ΔV = V REG - Vf.

[0038] The logic circuit 210 receives a control signal S CTRLWhen it is in the first state φ1, the high-side transistor MH is turned on and the low-side transistor ML is turned off, and the control signal S CTRL When it is in the second state φ2, the control signal S is configured such that the high-side transistor MH is turned off and the low-side transistor ML is turned on CTRL When it is in the third state φ3, the high-side control signal HCTRL and the low-side control signal LCTRL are generated such that the high-side transistor MH is turned off and the low-side transistor ML is turned off.

[0039] The high-side driver 220 controls the gate voltage V of the high-side transistor MH according to the high-side control signal HCTRL HG The upper power supply node 221 of the high-side driver 220 is connected to the bootstrap line 202, and the bootstrap voltage V BST is supplied. The lower power supply node 222 is connected to the switching line 204, and the switching voltage V OUT is supplied. The high-side driver 220 generates the gate voltage V BST , V OUT that takes two voltage levels V HG at the high-side gate pin HG.

[0040] The low-side driver 260 controls the gate voltage V of the low-side transistor ML according to the low-side control signal LCTRL LG The power supply voltage V DD is supplied to the upper power supply node 261 of the low-side driver 260, and the ground voltage is supplied to the lower power supply node 262 of the low-side driver 260.

[0041] The charging circuit 280 includes a charge pump circuit 282 whose on / off state can be controlled. The charging circuit 280 is configured to charge the bootstrap line 202 when the charge pump circuit 282 is on (enabled). The charge pump circuit 282, also called a trickle charge pump, is integrated into the gate driver circuit 200. The power consumption of the charge pump circuit 282 is on the order of 1 mA or less, for example, about 100 μA. The charge pump circuit 282 generates a voltage V IN higher than the input voltage V CP .

[0042] The on / off state of the charge pump circuit 282 is controlled by the logic circuit 210. The charge pump circuit 282 has an enable terminal EN and turns on when the enable signal CP_EN generated by the logic circuit 210 is asserted (e.g., high) and turns off when the enable signal CP_EN is negated (e.g., low).

[0043] The charging circuit 280 may further include a current source 284 that keeps the charging current constant.

[0044] When the control signal S 1 is in the first state φ1, that is, when it indicates a high output V CTRL =V OUT =V IN , the logic circuit 210 asserts the enable signal CP_EN to turn on the charge pump circuit 282 over a predetermined first determination time τ

[0045] . The logic circuit 210 uses the timer circuit 212 to generate the enable signal CP_EN. 1 As long as it is not the case, the first determination time τ CTRL can be set longer than the period of the pulse width modulation (PWM) of the control signal S 1It may be determined between two times and five times the PWM period. For example, when the PWM period is 50 μs (that is, the PWM frequency is 20 kHz), the first determination time τ 1 can be determined between 100 μs and 250 μs, and may be 200 μs.

[0046] Control signal S CTRL When changes from the first state φ1 to the second state φ2 or the third state φ3, the logic circuit 210 turns off the charge pump circuit 282.

[0047] Also, the logic circuit 210, for a predetermined second determination time τ 2 while the control signal S CTRL is in the third state φ3, that is, when indicating the high impedance state V OUT = HiZ, turns on the charge pump circuit 282. The second determination time τ 2 may be equal to the first determination time τ 1 .

[0048] Control signal S CTRL When changes from the third state φ3 to the first state φ1 or the second state φ2, the logic circuit 210 turns off the charge pump circuit 282.

[0049] The above is the configuration of the switching circuit 100.

[0050] FIG. 2 is a time chart for explaining the operation of the switching circuit 100 of FIG. 1. Before time t 1 , the control signal S CTRL alternately repeats the first state φ1 and the second state φ2, and the output signal V OUT of the switching circuit 100 alternately repeats the high output state V IN and the low output state 0V. The enable signal CP_EN is negative (low), the charge pump circuit is stopped, and the bootstrap voltage V BST is maintained at a voltage level higher by a predetermined voltage width ΔV than the switching voltage V OUT by the bootstrap circuit.

[0051] At time t 1 the control signal S CTRL is fixed to the first state φ1. When the switching of the switching circuit 100 stops, the bootstrap capacitor C BST cannot be charged by the bootstrap circuit, so the bootstrap voltage V BST decreases with time.

[0052] At time t 1 after the elapse of the first determination time τ 1 at time t 2 the logic circuit 210 asserts the enable signal CP_EN. As a result, the charge pump circuit 282 starts operating, and the bootstrap capacitor CBST is charged by the charging circuit 280, and the bootstrap voltage V BST rises. Thereby, the high-side driver 220 can continue to maintain the on state of the high-side transistor MH.

[0053] At time t 3 the control signal S CTRL transitions to the second state φ2. Then the logic circuit 210 negates the enable signal CP_EN and stops the charge pump circuit 282.

[0054] FIG. 3 is a time chart for explaining another operation of the switching circuit 100 of FIG. 1. Before time t 1 the control signal S CTRL alternately repeats the first state φ1 and the second state φ2, and the output signal V OUT of the switching circuit 100 alternately repeats the high output state V IN and the low output state 0V. The enable signal CP_EN is negated (low), the charge pump circuit is stopped, and the bootstrap voltage V BST is maintained by the bootstrap circuit at a voltage level higher by a predetermined voltage width ΔV than the switching voltage V OUT .

[0055] At time t1 to the control signal S CTRL is fixed to the third state φ3, and the high-side transistor MH and the low-side transistor ML are turned off, resulting in a high-impedance state. The switching voltage V OUT takes a voltage level corresponding to the direction of the load current I OUT . Specifically, when the load current I OUT flows into the bridge circuit 110 (sink mode), V OUT = V IN + Vf, and when the load current I OUT flows out of the bridge circuit 110 (source mode), V OUT = -Vf.

[0056] When the switching of the switching circuit 100 stops in the high-impedance state, the bootstrap capacitor C BST cannot be charged by the bootstrap circuit, so the bootstrap voltage V BST decreases with time.

[0057] At time t 1 after the elapse of the second determination time τ 2 , at time t 2 , the logic circuit 210 asserts the enable signal CP_EN. As a result, the charge pump circuit 282 starts operating, and the bootstrap capacitor CBST is charged by the charging circuit 280, and the bootstrap voltage V BST rises. Thereby, the high-side driver 220 can continue to maintain the on state of the high-side transistor MH.

[0058] At time t 3 , the control signal S CTRL transitions to the first state φ1. Then the logic circuit 210 negates the enable signal CP_EN and stops the charge pump circuit 282. At this time, the bootstrap voltage V BST is a voltage V IN higher than the input voltage V CPSince it is maintained, the high-side transistor MH can be surely turned on and transitioned to the high output state.

[0059] The above is the operation of the switching circuit 100. Next, its advantages will be described.

[0060] Regarding FIG. 2, when the high output state continues, the bootstrap circuit stops operating. When this state continues for the first determination time τ 1 By operating the charge pump circuit 282 on the condition that it has continued, the high-side transistor MH can be maintained in the on state during the high output state, and the bootstrap capacitor C BST can be charged.

[0061] Regarding FIG. 3, when the current sink continues in the high impedance state, the switching voltage V OUT sticks to the input voltage V IN +Vf, so the bootstrap circuit stops operating. Therefore, by operating the charge pump circuit 282 on the condition that the high impedance state has continued for the second determination time τ2, the bootstrap capacitor C BST can be charged. As a result, after the high impedance state, it can surely transition to the high output state.

[0062] FIG. 4 is a state transition diagram of the switching circuit 100 of FIG. 1. The switching circuit 100 transitions through five states S1 to S5.

[0063] State S1: High output V OUT =V IN Charge pump circuit = off CP_EN = L

[0064] State S2: High output V OUT =V IN Charge pump circuit = on CP_EN = H

[0065] State S3: Low output V OUT = 0V Charge pump circuit = OFF, CP_EN = L

[0066] State S4: High impedance V OUT = HiZ Charge pump circuit = OFF, CP_EN = L

[0067] State S5: Low output V OUT = HiZ Charge pump circuit = ON, CP_EN = H

[0068] The logic circuit 210 can be implemented as a state machine that transitions between five states φ1 to φ5.

[0069] The conditions for each transition are as follows.

[0070] The transition T1 from state S1 to S2 occurs when S CTRL = φ1 has persisted for the first determination time τ 1 and this is the condition.

[0071] The transition T2 from state S1 to S3 occurs when S CTRL = φ2.

[0072] The transition T3 from state S1 to S4 occurs when S CTRL = φ3.

[0073] The transition T4 from state S2 to S3 occurs when S CTRL = φ2.

[0074] The transition T5 from state S2 to S4 occurs when S CTRL = φ3.

[0075] The transition T6 from state S3 to S1 occurs when S CTRLOccurs on the condition that φ1 = φ1.

[0076] The transition T7 from state S3 to S4 occurs when S CTRL Occurs on the condition that φ3 = φ3.

[0077] The transition T8 from state S4 to S5 occurs when S CTRL φ3 has persisted for the second determination time τ 2 Occurs on this condition.

[0078] The transition T9 from state S4 to S1 occurs when S CTRL Occurs on the condition that φ1 = φ1.

[0079] The transition T10 from state S4 to S3 occurs when S CTRL Occurs on the condition that φ2 = φ2.

[0080] The transition T11 from state S5 to S1 occurs when S CTRL Occurs on the condition that φ1 = φ1.

[0081] The transition T12 from state S5 to S3 occurs when S CTRL Occurs on the condition that φ2 = φ2.

[0082] (Modified Example) Figure 5 is a state transition diagram of the switching circuit 100 according to the modified example of FIG. 1. In this modified example, state S6 is added.

[0083] State S6: Low output V OUT = 0V Charge pump circuit = ON CP_EN = L

[0084] The transition T13 from state S3 to S6 occurs when S CTRL φ2 has persisted for the third determination time τ 3 Occurs on this condition.

[0085] The transition T14 from state S6 to S1 occurs when S CTRLIt occurs on the condition that φ1 is satisfied.

[0086] The transition T15 from state S6 to S4 occurs when S CTRL It occurs on the condition that φ3 is satisfied.

[0087] The transition T11 from state S5 to S1 occurs when S CTRL It occurs on the condition that φ1 is satisfied.

[0088] The transition T12 from state S5 to S3 occurs when S CTRL It occurs on the condition that φ2 is satisfied.

[0089] In the low output state (V OUT = 0V), it is possible to charge the bootstrap capacitor C without operating the charge pump circuit. However, state φ6 may be added and the charge pump circuit 282 may be operated. BST It is possible to charge the bootstrap capacitor C without operating the charge pump circuit, but state φ6 may be added and the charge pump circuit 282 may be operated.

[0090] The present disclosure is understood as the block diagram and circuit diagram of FIG. 1, or extends to various devices and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and embodiments will be described not to narrow the scope of the present disclosure, but to assist in understanding the essence and operation of the present disclosure and the present invention and to clarify them.

[0091] FIG. 6 is a circuit diagram of a gate driver circuit 200 according to an embodiment. FIG. 6 shows a high-side driver 220 and a low-side driver 260.

[0092] The high-side driver 220 and the low-side driver 260 are of the constant-current drive type. The high-side driver 220 includes a variable current source CS11, a first current mirror circuit CM11, a second current mirror circuit CM12, switches SW11 and SW12, an on-fixed transistor M11, and an off-fixed transistor M12. The variable current source CS11, the switches SW11 and SW12, and the transistors M11 and M12 are controlled by a high-side control signal HCTRL (not shown) generated by the logic circuit 210.

[0093] The variable current source CS11 generates a reference current I 0 . The amount of the reference current I 0 can be appropriately switched during the turn-on sequence of the high-side transistor MH. The variable current source CS11 includes current sources CS31, CS32, CS33, and switches SW31 and SW32. The amount of the reference current I 0 changes according to the on / off combination of the switches SW31 and SW32. Note that the number of current sources and the number of switches may be designed according to the number of switching steps of the reference current I 0 .

[0094] The first current mirror circuit CM11 amplifies and folds back the reference current I 0 to generate a turn-on current I ON . The high-side driver 220 sources the turn-on current I ON to the high-side gate pin HG via the switch SW11. The switch SW11 turns on when S CTRL = φ1. Due to the turn-on current I ON , the gate voltage V HG of the high-side transistor MH rises, and the high-side transistor MH turns on.

[0095] After the high-side transistor MH turns on, the on-fixed transistor M11 becomes fully on, and the gate voltage of the high-side transistor MH is fixed at a high level (bootstrap voltage V BST ).

[0096] The first current mirror circuit CM11 folds back the reference current I 0 and generates the current I 1 . The second current mirror circuit CM12 amplifies and folds back the current I 1 to generate the turn-off current I OFF . The high-side driver 220 sinks the turn-off current I OFF from the high-side gate pin LG via the switch SW12. The switch SW12 turns on when S CTRL = φ2. Due to the turn-off current I OFF , the gate voltage V HG of the high-side transistor MH decreases, and the high-side transistor MH turns off.

[0097] After the low-side transistor MH turns off, the off-fixed transistor M12 turns fully on, and the gate voltage of the high-side transistor MH is fixed at the low level (switching voltage V OUT ).

[0098] The current source CS31 of the variable current source CS11 generates a current corresponding to the minimum current amount I 0 of the reference current I generated by the variable current source CS11. This minimum current amount I 0(MIN) is determined to be smaller than the current supply capacity of the charge pump circuit 282. For example, when the current supply capacity of the charge pump circuit 282 is 100 μA, the minimum current amount I 0(MIN) is preferably 10 μA or less, for example, 1 μA. 0(MIN)

[0099] In the states S2 and S5 where the charge pump circuit 282 is on, the logic circuit 210 turns off the switches SW31 and SW32 and operates the variable current source CS11 at the minimum current amount I 0(MIN) . Thereby, the power consumption of the circuit can be significantly reduced.

[0100] The low-side driver 260 is configured in the same manner as the high-side driver 220. Specifically, it includes a variable current source CS21, a first current mirror circuit CM21, a second current mirror circuit CM22, switches SW21 and SW22, an on-fixed transistor M21, and an off-fixed transistor M22. The variable current sources CS21, the switches SW21 and SW22, and the transistors M21 and M22 are controlled by a low-side / high-side control signal LCTRL (not shown) generated by the logic circuit 210.

[0101] The logic circuit 210 turns off the switches SW41 and SW42 and operates the variable current source CS21 at the minimum current amount I OUT even in a state S6 where the low-output state (V 0(MIN) = 0V) charge pump circuit 282 is on. This can significantly reduce the power consumption of the circuit.

[0102] The high-side driver 220 and the low-side driver 260 may be of a constant-voltage drive type.

[0103] FIG. 7 is a circuit diagram of a charge pump circuit 282 according to an embodiment. The charge pump circuit 282 includes inverters INV1 and INV2, flying capacitors Cf1 and Cf2, an output capacitor C OUT , and switches SW51 to SW54. Since the charge pump circuit 282 is integrated into the gate driver circuit 200, the capacitors are on the order of several pF. When the clock frequency is several MHz, for example, 8 MHz, the current supply capacity of the charge pump circuit 282 is about 100 μA. In this example, one end of the output capacitor C OUT is connected to the input of the charge pump circuit 282 and the input voltage V IN is supplied, but not limited thereto, one end of the output capacitor C OUT may be grounded.

[0104] (Application) Subsequently, the application of the switching circuit 100 will be described. The switching circuit 100 can be suitably used for a drive circuit of a motor.

[0105] FIG. 8 is a circuit diagram of a motor drive device 300 including a switching circuit 100 according to an embodiment. The motor drive device 300 drives a three-phase motor 302 as a load and controls its rotational state.

[0106] The motor drive device 300 includes a bridge circuit 110 and a gate driver circuit 200. The bridge circuit 110 is a three-phase inverter and has legs for the U-phase, V-phase, and W-phase, and each phase leg has an upper arm and a lower arm.

[0107] The gate driver circuit 200 includes a logic circuit 210 and high-side drivers 220U to 220W and low-side drivers 260U to 260W. The logic circuit 210 generates control signals indicating the states of the six arms constituting the bridge circuit 110 based on the state of the three-phase motor 302 as a load.

[0108] The high-side drivers 220U to 220W are configured with the architecture of the high-side driver 220 described above. Also, the low-side drivers 260U to 260W are configured with the architecture of the low-side driver 260 described above.

[0109] Here, a three-phase motor is taken as an example, but a single-phase motor may also be used. In this case, the bridge circuit 110 becomes an H-bridge circuit.

[0110] Subsequently, the applications of the motor drive device 300 will be described. The motor drive device 300 can be used for controlling the spindle motor of a hard disk and for controlling the lens drive motor of an imaging device. Alternatively, it can be used for driving the head drive motor of a printer or the paper feed motor. Alternatively, the motor drive device 300 can be used for driving motors in electric vehicles or hybrid vehicles.

[0111] The embodiments are illustrative, and it is understood by those skilled in the art that various modifications are possible for each of the constituent elements and combinations of the processing processes, and such modifications are also within the scope of the present disclosure or the present invention. Hereinafter, such modifications will be described.

[0112] The use of the switching circuit 100 is not limited to the motor drive device 300. For example, the switching circuit 100 can be suitably used for a switching regulator (DC / DC converter), various power conversion devices (inverter and converter), an inverter for lighting a discharge lamp, a digital audio amplifier, and the like. Therefore, the switching circuit 100 can be used for consumer devices including electronic devices and household appliances, automobiles and in-vehicle parts, industrial vehicles and industrial machines.

[0113] Some switching regulators, inverters, and converters do not have a period during which a high-impedance state persists for a long time. In the switching circuit used for such an application, the state S5 may be omitted.

[0114] The embodiments described using specific terms merely show the principles and applications of the present invention, and many modifications and arrangement changes are recognized in the embodiments without departing from the idea of the present invention defined in the claims.

[0115] (Supplementary Note) The following techniques are disclosed in this specification.

[0116] (Item 1) A gate driver circuit that drives a switching circuit including an N-type high-side transistor and an N-type low-side transistor in response to a control signal, a bootstrap line, a switching line to be connected to the source of the high-side transistor, When the control signal is in the first state, the high-side transistor is turned on and the low-side transistor is turned off. When the control signal is in the second state, the high-side transistor is turned off and the low-side transistor is turned on. A logic circuit that generates a high-side control signal and a low-side control signal is provided. A high-side driver that controls the gate voltage of the high-side transistor according to the high-side control signal, with the upper power supply node connected to the bootstrap line and the lower power supply node connected to the switching line. A low-side driver that controls the gate voltage of the low-side transistor according to the low-side control signal. A charge circuit including a charge pump circuit whose on and off can be controlled, and configured to charge the bootstrap line when the charge pump circuit is on. Comprising The logic circuit is a gate driver circuit that turns on the charge pump circuit when the control signal is in the first state over a predetermined first determination time.

[0117] (Item 2) The gate driver circuit according to item 1, wherein the first determination time is longer than the period of the pulse width modulation of the control signal.

[0118] (Item 3) The high-side driver includes a current source and a current mirror circuit that folds back the current generated by the current source and supplies it to the gate of the high-side transistor. The gate driver circuit according to item 1 or 2, wherein the amount of current of the current source is smaller when the charge pump circuit is on than when it is off.

[0119] (Item 4) The gate driver circuit according to item 3, wherein the amount of current of the current source when the charge pump circuit is on is smaller than the current supply capacity of the charge pump circuit.

[0120] (Item 5) The gate driver circuit according to any one of items 1 to 4, wherein the logic circuit turns off the charge pump circuit when the control signal changes from the first state to the second state.

[0121] (Item 6) The logic circuit generates the high-side control signal and the low-side control signal so that when the control signal is in the third state, the high-side transistor is off and the low-side transistor is off. The gate driver circuit according to any one of items 1 to 5, wherein the logic circuit turns on the charge pump circuit when the control signal is in the third state for a predetermined second determination time.

[0122] (Item 7) The gate driver circuit according to item 6, wherein the logic circuit turns off the charge pump circuit when the control signal changes from the first state to the third state.

[0123] (Item 8) The gate driver circuit according to item 7, wherein the logic circuit turns on the charge pump circuit when the control signal changes from the third state to the first state or the second state.

[0124] (Item 9) The gate driver circuit according to any one of items 1 to 8, wherein the logic circuit turns on the charge pump circuit when the control signal is in the second state for a predetermined third determination time.

[0125] (Item 10) The gate driver circuit according to item 9, wherein the logic circuit turns on the charge pump circuit when the control signal changes from the second state to the first state.

[0126] (Item 11) The gate driver circuit according to any one of items 1 to 10, which is integrally integrated on a single semiconductor substrate.

[0127] (Item 12) A bridge circuit including a high-side transistor and a low-side transistor, and the gate driver circuit according to any one of Items 1 to 11 for driving the high-side transistor and the low-side transistor, A motor drive device comprising the same.

[0128] (Item 13) A motor, and the motor drive device according to Item 12 for driving the motor, An electronic device comprising the same.

Explanation of Signs

[0129] 100 Switching circuit 102 Power supply line 104 Output line 106 Ground line 110 Bridge circuit 112 Upper arm 114 Lower arm MH High-side transistor ML Low-side transistor 200 Gate driver circuit 202 Bootstrap line 204 Switching line 206 Ground line 280 Charging circuit 282 Charge pump circuit 284 Current source 286 Rectifying element 210 Logic circuit 212 Timer circuit 220 High-side driver 260 Low-side driver 300 Motor drive device 302 Three-phase motor CS11 Variable current source CM11 First current mirror circuit CM12 Second Current Mirror Circuit SW11, SW12 Switches M11 On-Fixed Transistor M12 Off-Fixed Transistor CS21 Variable Current Source CM21 First Current Mirror Circuit CM22 Second Current Mirror Circuit SW21, SW22 Switches M21 On-Fixed Transistor M22 Off-Fixed Transistor

Claims

1. A gate driver circuit for driving a switching circuit including an N-type high-side transistor and an N-type low-side transistor in response to a control signal, a bootstrap line, a switching line to be connected to the source of the high-side transistor, a logic circuit that generates a high-side control signal and a low-side control signal such that when the control signal is in a first state, the high-side transistor is turned on and the low-side transistor is turned off, and when the control signal is in a second state, the high-side transistor is turned off and the low-side transistor is turned on, a high-side driver that controls the gate voltage of the high-side transistor in response to the high-side control signal, with an upper power supply node connected to the bootstrap line and a lower power supply node connected to the switching line, a low-side driver that controls the gate voltage of the low-side transistor in response to the low-side control signal, a charge circuit including a charge pump circuit whose on and off can be controlled, and configured to charge the bootstrap line when the charge pump circuit is on, comprising The logic circuit turns on the charge pump circuit when the control signal is in the first state over a predetermined first determination time. The gate driver circuit.

2. The gate driver circuit according to claim 1, wherein the first determination time is longer than the period of pulse width modulation of the control signal.

3. The high-side driver includes a current source and a current mirror circuit that folds back the current generated by the current source and supplies it to the gate of the high-side transistor. The gate driver circuit according to claim 1 or 2, wherein the amount of current of the current source is smaller when the charge pump circuit is on than when it is off.

4. The gate driver circuit according to claim 3, wherein the amount of current of the current source when the charge pump circuit is on is smaller than the current supply capacity of the charge pump circuit.

5. The gate driver circuit according to claim 1 or 2, wherein the logic circuit turns off the charge pump circuit when the control signal changes from the first state to the second state.

6. When the control signal is in the third state, the logic circuit generates the high-side control signal and the low-side control signal so that the high-side transistor is turned off and the low-side transistor is turned off. The gate driver circuit according to claim 1 or 2, wherein the logic circuit turns on the charge pump circuit when the control signal is in the third state for a predetermined second determination time.

7. The gate driver circuit according to claim 6, wherein the logic circuit turns off the charge pump circuit when the control signal changes from the first state to the third state.

8. The gate driver circuit according to claim 7, wherein the logic circuit turns on the charge pump circuit when the control signal changes from the third state to the first state or the second state.

9. The gate driver circuit according to claim 1 or 2, wherein the logic circuit turns on the charge pump circuit when the control signal is in the second state for a predetermined third determination time.

10. The gate driver circuit according to claim 9, wherein the logic circuit turns on the charge pump circuit when the control signal changes from the second state to the first state.

11. The gate driver circuit according to claim 1 or 2, which is integrally integrated on a single semiconductor substrate.

12. A bridge circuit including a high-side transistor and a low-side transistor; The gate driver circuit according to claim 1 or 2, which drives the high-side transistor and the low-side transistor; A motor drive device comprising:

13. A motor; The motor drive device according to claim 12, which drives the motor; An electronic device comprising:

Images