Enhancement of interruption lost event in multi-level interruption system

Abstract

To provide a system for, a method of, and a circuit for detecting lost interruption events in a reduced instruction set computer-V (RISC-V) architecture.SOLUTION: A multi-level interruption architecture has an advanced platform level interruption controller (APLIC) and an incoming message signal interruption (MSI) controller (IMSIC) integrated in the APLIC. The APLIC includes a plurality of vectors respectively connected to external interruption inputs. Each of the vectors is mapped to an interruption priority and has a vector interruption lost (IL) bit. The IMSIC receives the MSI from the APLIC and maintains an interruption file including a set of interruption lost (IL) bits indexed by interruption priority.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of priority of U.S. Provisional Patent Application No. 63 / 601,994, filed on November 22, 2023, entitled "Enhanced Interrupt Lost Events in Multilevel Interrupt Systems", the content of which is hereby incorporated by reference in its entirety into this specification.

[0002] This disclosure generally relates to the field of processors and central processing units (CPUs), and more particularly to the interrupt architecture of a processing system.

Background Art

[0003] Modern processors may include a multilevel interrupt system, in which multiple sources may provide wired interrupts and / or message - signal interrupts, different interrupts may have different priorities, and may target different hardware threads.

[0004] Some examples of circuits, devices, and / or methods are described below by way of example only. In this context, the accompanying drawings are referenced.

Brief Description of the Drawings

[0005]

Figure 1

Figure 2

Figure 3

Figure 4

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[0006] The present disclosure is described with reference to the accompanying drawings. Similar components in the various drawings may be represented by similar reference numerals. The drawings are not drawn to scale and are provided merely to illustrate the disclosure. Some aspects of the disclosure are described hereinafter with reference to example applications for illustration. Numerous specific details, relationships, and methods are described to understand the disclosure. Since some acts may occur in a different order and / or in parallel with other acts or events, the present disclosure is not limited by the illustrated order of acts or events. Further, not all illustrated acts or events are required to implement the methodology in accordance with the selected aspects of the present disclosure.

[0007] FIG. 1 is a block diagram of an interrupt architecture for a reduced instruction set-V (RISC-V) system. The architecture of FIG. 1 is configured to handle external interrupts for a plurality of hardware threads (hart) as well as other interrupt targets. The architecture of FIG. 1 includes several interrupt sources, namely, an advanced platform-level interrupt controller (APLIC) 110 and two peripheral component interconnect express (PCIe) devices 105. The interrupt sources are coupled via a bus network 108 to two incoming message signaled interrupt controllers (IMSIC) 120 for two respective harts 150 (e.g., processor cores or CPUs).

[0008] The APLIC 110 receives wired external interrupts. Each external interrupt received by the APLIC 110 has an associated interrupt target, which includes a specific hart (and, in some examples, a specific privilege level of the hart) and an associated interrupt priority. The APLIC 110 converts the wired external interrupts into message signaled interrupts (MSI) 130, and the MSI 130 conveys interrupt information (e.g., interrupt priority and interrupt target) regarding the received interrupts.

[0009] The PCIe device 105 also generates an MSI 130 that conveys information regarding interrupts generated by the PCIe device.

[0010] The bus network 108 sends each MSI to the appropriate IMSIC 120 for the hart of the interrupt target indicated by the MSI. The IMSIC 120 maintains interrupt information for each interrupt target. In the illustrated example, the interrupt information is stored as a bit array within one or more interrupt files 125. The interrupt files 125 are maintained for each privilege level of the hart. In FIG. 1, the machine-level interrupt file is maintained for machine-level privilege, and the supervisor-level interrupt file is maintained for supervisor-level privilege. In other examples, the interrupt files may similarly be maintained for different virtual machines / guest IDs. In each interrupt file, the interrupt pending (IP) and interrupt enable (IE) bit arrays contain bits for each interrupt priority, and these bits are specified by the interrupt priority. Thus, an “interrupt target” may be considered to be a particular IP bit within a particular bit array of a particular interrupt file maintained by the IMSIC 120 for that particular hart 150.

[0011] Referring next to FIG. 2, the aspects of the interrupt architecture of FIG. 1 are shown in more detail. APLIC110 defines interrupt identification for core-external interrupts (wired interrupts or software interrupts). The APLIC110 interrupt identification is related to a physical interrupt line or a software interrupt structure. APLIC110 includes per-interrupt control registers 112(1 - 1023) that store bit vectors, with each vector corresponding to a unique interrupt identification. Each control register maps an interrupt received on a particular line to a hart-ID and privilege level within the hart, where the privilege level can be M-mode (machine mode), S- / HS-mode (supervisor or hypervisor supervisor mode), or VSx (guest ID - virtual machine x supervisor mode). Each control register 112 constructs the received interrupt with a priority (external interrupt identification number: EIID) and provides means for setting, storing, and clearing interrupt pending information (e.g., IP bits) and interrupt enable information (e.g., IE bits) for the interrupt, as well as means for defining the event status for each incoming interrupt line.

[0012] APLIC110 arbitrates pending interrupts for each granularity of the hart's privilege level and signals the information of the winning interrupt as MSI130 to the local IMSIC120 of the target hart. MSI130 indicates an interrupt target including the set HART ID, privilege level, and interrupt priority (EIID). When signaling MSI130 for an arbitrated pending interrupt, APLIC clears the interrupt pending (IP) information in the control register for each APLIC interrupt identification. Note that in a system that signals MSI to the IMSIC module, there can be multiple APLICs.

[0013] Each hart150 is coupled to a dedicated IMSIC120. The IMISC120 provides (e.g., maintains and stores) interrupt files 127, one file for each supported privilege level (M, S / HS), and one file for each supported guest ID (virtual machine). Each interrupt file 127 has a configurable number of priorities associated with the hart's interrupt vector table 157. For each privilege level and perhaps for each virtual machine (guest) as well, the IMSIC120 provides an interrupt file 127, and the interrupt file 127 includes one interrupt pending (IP) bit for each priority level and one interrupt enable (IE) bit for each priority level.

[0014] In APLIC110, while an interrupt for a given privilege / priority is pending, it can happen that the APLIC receives one or more new interrupts through its respective interrupt input signals and / or through software writes that set the interrupt pending bits of vectors already stored in the control registers. In other words, the APLIC110 can receive a (new) interrupt for a given target before it has the opportunity to signal the previous interrupt for that given target. Further, while a particular interrupt priority within the IMSIC120 is pending, the IMSIC120 can receive a further MSI specifying the same interrupt priority again. These subsequent interrupts cannot be captured in an existing system and are called lost interrupts or lost interrupt events. In some safety - related contexts such as automotive applications, it can be important to detect the situation when one or more interrupts are lost at either the APLIC or IMSIC level.

[0015] A system, method, and architecture are provided herein to support the detection and enhancement of lost interrupt events to notify a processing core of the lost interrupt events. In one example, APLIC and IMSIC interrupt identification are extended to have a lost interrupt detection mechanism and a lost interrupt information structure. The lost interrupt information is signaled from APLIC to IMSIC along with each MSI (including information regarding priority, target core, target privilege level, extended with lost information). The IMSIC enhances the lost interrupt information signaled by the MSI, but can also detect an interrupt lost event regarding the priority level. Next, the IMSIC may make the lost interrupt information available to each core.

[0016] Figure 3 is a block diagram of a general interrupt architecture that supports the propagation of the occurrence of lost interrupts to hardware threads. In one example, the interrupt architecture is a modified RISC-V advanced interrupt architecture. However, the disclosed solution may be applied to any processing environment.

[0017] The architecture includes hardware components disposed in hart350, interrupt source 310, and message controller 320 for the hart. Hart350 includes an interrupt vector table 357 mapped to a plurality of interrupt targets. Each interrupt target is associated with a predetermined priority for the hart. In some examples, the hart includes interrupt targets for each privilege and / or for each virtual machine. Setting an interrupt target or its associated value within interrupt vector table 357 may cause the hart to take some action (potentially different actions for different interrupt targets) in response to an interrupt. In some situations, if multiple interrupts occur relatively quickly and continuously for the same interrupt target (e.g., individual signaling by interrupt messages is close enough that lost interrupts occur), the response to the interrupt may be prioritized higher than if a single interrupt occurred. Alternatively, different responses may be taken by the hart when a lost interrupt is detected.

[0018] Interrupt source 310 (e.g., APLIC of FIG. 1) is configured to receive respective external interrupt signals representing respective interrupt events. Each interrupt event is associated with a corresponding interrupt target. The interrupt source transmits an interrupt message (e.g., MSI) based on the received interrupt signal. Each MSI includes information regarding the interrupt target of that interrupt event for the interrupt event.

[0019] The interrupt source may include a source-level lost interrupt detection circuit 315 that performs a function of detecting lost interrupts. In one example, to detect a lost interrupt event, the source-level lost interrupt detection circuit 315 detects that an interrupt signal for a second interrupt event for a given interrupt target is received before the interrupt source 310 transmits an interrupt message for a first interrupt event for the given interrupt target. For example, the source-level lost interrupt detection circuit 315 may detect a lost interrupt event when receiving an interrupt for an interrupt target whose interrupt pending (IP) bit in its vector is already set. In response, the source-level lost interrupt detection circuit 315 stores an indication that the interrupt is lost for the given interrupt target (e.g., by setting the vector interrupt lost (IL) bit in the vector for interrupt identification). The interrupt source 310 encodes the lost interrupt event information in the pending interrupt message (e.g., in the arbitration queue) that conveys information about the first received interrupt. The interrupt source may be further configured to clear an indication that the interrupt is lost (e.g., the vector IL bit) in response to transmitting an interrupt message indicating a lost interrupt.

[0020] The message controller 320 (e.g., the IMSIC of FIG. 1) receives an interrupt message from the interrupt source 310 and is configured to store interrupt information for the interrupt target based on the received message. The message controller 320 includes a controller-level lost interrupt detection circuit 323 that determines that an interrupt event for the interrupt target is lost (e.g., based on one or more of the received interrupt messages). In response, the message controller 320 provides an indication of one or more lost interrupt events to the target hart 350 of the affected interrupt target.

[0021] The controller-level lost interrupt detection circuit 323 detects a lost interrupt and stores information reflecting the lost interrupt as interrupt information. The controller-level lost interrupt detection circuit 323 may be configured to detect that an interrupt has been lost in response to receiving an interrupt message indicating a lost interrupt for a predetermined target, or when the interrupt information 327 indicates that an interrupt is already pending for a predetermined target, in response to receiving an interrupt message for the predetermined target. A different interrupt target having the same or greater privilege as the predetermined interrupt target, in response to receiving an indication of one or more lost interrupt events, the message controller 320 may be configured to reset the lost interrupt information 327 for the interrupt target. Alternatively or additionally, the lost interrupt information for the interrupt target may be set or reset by software.

[0022] The message controller 320 may be configured to signal an indication of one or more lost interrupt events on a per-interrupt priority basis (based on each interrupt priority) or on a per-interrupt target basis. Thus, the MSI controller enhances information regarding lost interrupt events from multiple sources and provides the information to the hart, so that the hart may respond and take countermeasures.

[0023] FIG. 4 is a modification of the architectures of FIGS. 1 and 2 and is a block diagram of an example RISC-V interrupt architecture that provides for the detection, enhancement, and indication of lost interrupt events. The architecture of FIG. 4 is a specific example of the architecture of FIG. 3, and the illustrated aspects of the architecture may be implemented by the general architecture of FIG. 3.

[0024] In the illustrated architecture, the APLIC control register 412 is modified to store a vector interrupt lost (IL) bit for each interrupt identification. The APLIC 410 is modified to set and (optionally) reset the vector IL bit. The MSI message 430 includes one or more bits that encode the status of the vector IL bit 418. The IMSIC 420 is modified to add an array 428 that includes one interrupt lost (IL) bit for each interrupt priority or for each group of interrupt priorities.

[0025] Figure 4 shows an example vector format for interrupt identification stored by the control register 412. The bits that encode source information, target identification, and interrupt priority (EIID) are set by the architecture configuration. The IE bit and the IP bit are set by received external interrupts. When a new interrupt event is detected for interrupt identification and the IP bit for that interrupt identification is already set, the APLIC 410 (e.g., the source-level lost interrupt detection circuit of FIG. 3) sets the vector IL bit. When the interrupt identification is arbitrated, its current vector IL bit status is signaled as part of the modified MSI message 430. When the interrupt lost situation is detected in parallel with the MSI signaling / interrupt pending clear, the vector IL information may be set and signaled by the next interrupt through the MSI. When the vector IL information is signaled through the MSI message 430, the vector IL information may be cleared by software or by the APLIC 410. The APLIC 410 may detect lost interrupt events at different granularities (e.g., for each interrupt or for each group of interrupts).

[0026] The enhanced MSI 430 indicates, for an interrupt, the target hart ID, privilege level, priority (IIED), and an indication of the vector IL bit status of the signaled interrupt identification.

[0027] The IMSIC interrupt file 427 is modified to add one interrupt lost (IL) bit for each interrupt privilege level or for each group of interrupt privilege levels. For example, the additional bit array 428 may be included within the interrupt file and store n IL bits indexed by n interrupt priorities. The IE bits and IP bits are set by the MSIS 430, while the IL bits are set by the IMSIC 420 (e.g., the controller-level lost interrupt detection circuit of FIG. 3). For example, if an MSI for interrupt identification is received by the IMSIC 420 and the associated priority IP bit for the interrupt identification is already set, the IMSIC 420 sets the IL bit for the priority. The IMSIC 420 may set the IL bit associated with a given priority in response to receiving an MSI indicating that the vector IL bit is set for interrupt identification having the given priority. The IL information may be cleared by software and / or the IMSIC 420.

[0028] The IL information may be provided to the interrupt target through the standard IMSIC register interface and cleared together with the IP bits. The IL information may be provided directly to the respective privilege level / priority interrupt vector table 457 of the target hart 450.

[0029] The granularity at which lost interrupt information is detected, enhanced, and reported may be on a per priority / privilege level basis, per priority / virtual machine level basis, per privilege level basis, per hart basis, etc. The lost interrupt information may be detected, enhanced, and reported at different granularities.

[0030] FIG. 5 is a flowchart outlining an example method 500 for signaling lost interrupt information to a computing core (e.g., hart). Method 500 may be performed, for example, by interrupt source 310 of FIG. 3 or APLIC 110 of FIGS. 1 and 2 or APLIC 410 of FIG. 4. The method includes, at 510, receiving a plurality of external interrupt signals, each associated with an interrupt priority. Each external interrupt signal may be associated with a preset interrupt identifier that includes a priority for the signaled interrupt (EIID), an interrupt source identification, and a target hart / privilege level identification. At 520, based on the received interrupt signals, it is determined that an interrupt signal for a given interrupt priority has been lost. In some examples, a lost interrupt signal is detected when an interrupt signal is received for a given interrupt identifier before the previous interrupt signal for the given interrupt identifier has been notified to the computing core.

[0031] In some examples, the method includes providing a plurality of respective vectors connected to each external interrupt input that receives an external interrupt signal. Each vector is associated with a target computing core and includes an indication of an interrupt priority, a vector interrupt pending (IP) bit, and a vector interrupt lost (IL) bit. In these examples, while the vector IP bit is set, when an interrupt is received by the corresponding external interrupt input, the method includes setting the vector IL bit.

[0032] Method 500 includes, at 530, providing an indication to the computing core that an interrupt signal for a given interrupt priority has been lost. In some examples, this operation is performed by selecting a vector based on arbitration rules and transmitting a message signal interrupt (MSI) to an incoming MSI controller (IMSIC) connected to the target computing core of the selected vector. The MSI includes an indication of the status of the vector IL bit of the selected vector and the interrupt priority of the selected vector.

[0033] FIG. 6 is a flow diagram outlining an example method 600 of signaling lost interrupt information to a computing core (e.g., hart). Method 600 may be performed, for example, by the message controller 320 of FIG. 3 or the IMSIC 120 of FIGS. 1 and 2 or the IMSIC 420 of FIG. 4. The method includes, at 610, receiving an interrupt message that includes an indication of one of a plurality of interrupt priorities. The interrupt message may be, respectively, the MSI 130 of FIGS. 1 and 2 or the MSI 430 of FIG. 4. The MSI may include an interrupt lost (IL) bit set to indicate that interrupt signals of the same priority were lost.

[0034] The method includes, at 620, determining, based on the interrupt message, that an interrupt for a given interrupt priority was lost. In some examples, the method includes receiving an MSI that includes an indication of the interrupt priority and an indication that an interrupt signal for the interrupt priority was lost, and in response to the MSI message, setting an IL bit mapped to the interrupt priority in an interrupt file. The method may also include setting an IL bit mapped to the interrupt priority in the interrupt file in response to receiving an MSI that includes an indication of the interrupt priority while an IP bit for the interrupt priority in the interrupt file is already set. The method may include resetting an IL bit mapped to a given interrupt priority in the interrupt file in response to resetting an IP bit mapped to the given interrupt priority in the interrupt file.

[0035] Method 600 includes, at 630, providing to the compute core, for each interrupt priority, respective lost interrupt information indicating whether an interrupt has been lost. In some examples, the method includes providing IL information by maintaining one or more interrupt files mapped to respective interrupt targets. In some examples, the status of one or more IL bits may be combined or summarized on a per-priority or per-privilege level basis to generate lost interrupt information (provided to the compute core). The interrupt lost information may be provided to the compute core through a standard IMSIC register interface including the IL bits within each interrupt file. In some examples, rather than each interrupt file including IL bits, the IMSIC may maintain a set of IL bits having each IL bit associated with a group of priorities and / or privileges. In some examples, the lost interrupt information may be provided directly to the affected privilege level of the compute core.

[0036] In this specification and the appended claims, when describing method steps or functions, the term "determine" as used with reference to some entity (e.g., parameter, variable, etc.) should be interpreted broadly. For example, "determine" should be interpreted to include, for example, receiving and parsing a communication encoding an entity or value of an entity. "Determine" should be interpreted to include accessing and reading from a memory (e.g., lookup table, register, device memory, remote memory, etc.) storing a value for an entity or entity. "Determine" should be interpreted to include calculating or deriving a value of an entity or entity based on another quantity or entity. "Determine" should be interpreted to include any method of estimating or identifying a value of an entity or entity.

[0037] As used herein, when referring to and using any entity or value of an entity, the term "identifying" should be broadly construed to include any method of determining the entity or value of the entity. For example, the term "identifying" should be construed to include, for example, receiving and analyzing a communication that encodes the entity or value of the entity. The term "identifying" should be construed to include accessing and reading a memory (such as a device queue, lookup table, register, device memory, remote memory, etc.) that stores the value for the entity or entity.

[0038] As used herein, when referring to and using several entities (such as parameters or settings) or values of entities, the term "indicating" should be broadly construed to include any method of explicitly or implicitly communicating the entity or value of the entity. For example, bits in a transmission message may be used to explicitly encode the indicated value, or may encode an index or other indicator mapped to the value indicated by a conventional configuration. The absence of a field in a message may implicitly indicate the value of an entity based on a conventional configuration.

[0039] From the above description, it can be seen that the disclosed interrupt architecture detects interrupt lost events at a functional interrupt level (e.g., APLIC), strengthens them at a privilege level / priority level (e.g., IMSIC), extends them with additional (interrupt lost) event detection at the priority level, and then provides a mechanism that enables each processor core or hart to use the information in its respective privileged mode.

[0040] While the invention is illustrated and described with respect to one or more embodiments, alternatives and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, circuitry, systems, etc.), even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the invention illustrated herein, the terms used to describe such components (including references to "means") are intended to correspond to any component or structure that performs the specified function of the described component (e.g., functionally equivalent), unless otherwise specified.

[0041] An example can include a subject, e.g., a method, a means for performing a method act or block, and at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to detect and respond to lost interrupt events according to the embodiments and examples described herein.

[0042] Example 1 is a reduced instruction set computer-V (RISC-V) architecture including an advanced platform level interrupt controller (APLIC) and an incoming message signal interrupt (MSI) controller (IMSIC) coupled to the APLIC, where the APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, each vector is mapped to an interrupt priority, each vector includes a vector interrupt lost (IL) bit, and the IMSIC is configured to receive an MSI from the APLIC and maintain an interrupt file including a set of interrupt lost (IL) bits indexed by interrupt priority.

[0043] Example 2 includes the subject matter of Example 1, includes or omits optional elements, and in response to receiving a message signal interrupt (MSI) including an indication of a predetermined interrupt priority and an indication that the vector IL bit of the corresponding vector is set, or while the interrupt pending (IP) bit for the predetermined interrupt priority in the interrupt file is set, in response to receiving an MSI including an indication of a predetermined interrupt priority, the IMSIC is configured to set the IL bit mapped to the predetermined interrupt priority of the interrupt file.

[0044] Example 3 includes the subject matter of Example 1, includes or omits optional elements, and in response to resetting the IP bit mapped to a predetermined interrupt priority in the interrupt file, the IMSIC is configured to reset the IL bit mapped to the predetermined interrupt priority in the interrupt file.

[0045] Example 4 includes the subject matter of Example 1, includes or omits optional elements, and APLIC is configured to set the vector IL bit of a vector and, in response, transmit an MSI to the IMSIC when an interrupt is received by a corresponding external interrupt input while the IP bit of the vector is set, and the MSI includes the status of the vector IL bit of the vector and an indication of the interrupt priority of the vector.

[0046] Example 5 includes the subject matter of Example 1, includes or omits optional elements, each vector is mapped to a respective interrupt target and the respective interrupt priority of the respective interrupt target, and the IMSIC maintains an interrupt file for each interrupt target.

[0047] Example 6 includes the subject matter of Example 5, includes or omits optional elements, and the interrupt target includes a target hardware thread (hart), the target hart and the privilege level of the target hart, or the target hart and the virtual machine ID of the target hart.

[0048] Example 7 includes the subject matter of Example 1, includes or omits optional elements, and in response to receiving a new interrupt for a given interrupt vector while the interrupt pending (IP) bit for the given interrupt vector is set, APLIC is configured to set the IL bit mapped to the given interrupt vector.

[0049] Example 8 includes the subject matter of Example 1, includes or omits optional elements, and in response to resetting the interrupt pending (IP) bit mapped to a given interrupt vector when the corresponding interrupt is signaled as MSI, APLIC is configured to reset the IL bit mapped to the given interrupt vector.

[0050] Example 9 is an interrupt architecture that includes hardware components disposed in one or more hardware threads (harts), an interrupt source, and an MSI controller, where the interrupt source is configured to receive respective external interrupt signals representing respective interrupt events, each interrupt event has a corresponding interrupt target, each interrupt target is a target hart of one or more harts and corresponds to an interrupt priority, the interrupt source is configured to transmit a plurality of message signal interrupts (MSIs) based on the received interrupt signals, the MSI includes information regarding the interrupt target of the interrupt event for the interrupt event, the MSI controller receives a plurality of MSIs from one or more interrupt sources, stores interrupt information for the interrupt target based on the received plurality of MSIs, determines that an interrupt event for the interrupt target has been lost, and in response, is configured to provide the lost interrupt information to the target hart of the interrupt target, and the lost interrupt information includes an indication of one or more lost interrupt events.

[0051] Example 10 includes the subject matter of Example 9 and includes or omits optional elements, and the interrupt target includes interrupt priorities at a privileged level in the target hart or includes virtual machine interrupt priorities in the target hart.

[0052] Example 11 includes the subject matter of Example 9 and includes or omits optional elements, and one of the plurality of MSIs indicating an interrupt event for a predetermined interrupt target includes an indication that an interrupt signal for the next interrupt event for the predetermined interrupt target was received before transmission of the MSI.

[0053] Example 12 includes the subject matter of Example 11 and includes or omits optional elements, and the MSI controller is further configured to store interrupt information for each interrupt target based on the received plurality of MSIs, the interrupt information indicating whether an interrupt was lost, and the MSI controller is further configured to provide the lost interrupt information to the target hart associated with the interrupt target for which the interrupt was lost.

[0054] Example 13 includes the subject matter of Example 9 and includes or omits optional elements, and when the interrupt information for a predetermined interrupt target indicates that an interrupt is pending, in response to receiving an MSI indicating an interrupt event for the predetermined interrupt target or in response to receiving an MSI indicating that an interrupt event for the predetermined interrupt target was lost, the MSI controller sets the interrupt information for the predetermined interrupt target and is configured to indicate that the interrupt was lost.

[0055] Example 14 includes the subject matter of Example 9, includes or omits optional elements, and the interrupt source converts each wired interrupt into a respective MSI, and before transmitting the MSI for the first interrupt event for a given interrupt target, detects that an interrupt signal for a second interrupt event for the given interrupt target is received, and in response, stores an indication that an interrupt has been lost for the given interrupt target, and is further configured to encode the lost interrupt information in the first MSI for the first interrupt event.

[0056] Example 15 includes the subject matter of Example 14, includes or omits optional elements, and in response to transmitting the first MSI, the interrupt source is further configured to clear the indication that an interrupt has been lost.

[0057] Example 16 includes the subject matter of Example 9, includes or omits optional elements, and the MSI controller is configured to signal an indication of one or more lost interrupt events on a per interrupt priority basis.

[0058] Example 17 includes the subject matter of Example 9, includes or omits optional elements, and the MSI controller is configured to signal an indication of one or more lost interrupt events on a per interrupt target basis.

[0059] Example 18 includes the subject matter of Example 9, includes or omits optional elements, and in response to an interrupt target having the same or greater privilege as the interrupt target receiving an indication of one or more lost interrupt events, the MSI controller is configured to reset the lost interrupt information for the interrupt target.

[0060] Example 19 is a method. The method includes receiving an interrupt message including an indication of one of a plurality of interrupt priorities; determining, based on the interrupt message, that an interrupt for a predetermined interrupt priority has been lost; and providing, to a computing core, respective lost interrupt information for each interrupt priority, where the lost interrupt information indicates whether an interrupt has been lost.

[0061] Example 20 includes the subject matter of Example 19 and includes or omits optional elements. The method further includes, in response to receiving an MSI including an indication of an interrupt priority and an indication that a vector IL bit in an interrupt source vector for the interrupt priority is set, setting an IL bit mapped to the interrupt priority in an interrupt file.

[0062] Example 21 includes the subject matter of Example 19 and includes or omits optional elements. The method further includes, in response to receiving an MSI including an indication of an interrupt priority while an IP bit for the interrupt priority in an interrupt file is set, setting an IL bit mapped to the interrupt priority in the interrupt file.

[0063] Example 22 includes the subject matter of Example 21 and includes or omits optional elements. The method further includes, in response to resetting an IP bit mapped to a predetermined interrupt priority in an interrupt file, resetting an IL bit mapped to the predetermined interrupt priority in the interrupt file.

[0064] Example 23 is a method. The method includes receiving a plurality of external interrupt signals, each associated with an interrupt priority; determining, based on the received interrupt signals, that an interrupt signal for a predetermined interrupt priority has been lost; and providing, to a computing core, an indication that an interrupt signal for a predetermined interrupt priority has been lost.

[0065] Example 24 includes the subject matter of Example 23 and includes or omits optional elements, and the method comprises the step of providing a plurality of respective vectors each connected to a respective external interrupt input that receives an external interrupt signal, each vector being associated with a target computing core, and further, each vector including an indication of interrupt priority, vector interrupt pending (IP) bits, and vector interrupt lost (IL) bits; and the step of setting the vector IL bit of the vector when an interrupt is received by a corresponding external interrupt input while the vector IP bit of the vector is set.

[0066] Example 25 includes the subject matter of Example 24 and includes or omits optional elements, and the method further comprises the step of selecting a vector based on arbitration rules and the step of transmitting a message signal interrupt (MSI) to an incoming MSI controller (IMSIC) connected to the target computing core of the selected vector, the MSI including an indication of the status of the vector IL bit of the selected vector and the interrupt priority of the selected vector.

[0067] The various illustrated logics, logic blocks, modules, circuitry, and circuits described in connection with the aspects disclosed herein can be implemented or executed by a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic circuit, discrete gates or transistor logic, discrete hardware components, or any combination of these designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine.

[0068] In the present disclosure, like reference numerals are used throughout to refer to like elements, and the illustrated structures and devices are not necessarily drawn to scale. As used herein, terms such as "module," "component," "system," "circuit," "circuitry," "element," "slice," etc. are intended to relate to computer-related entities, hardware, software (e.g., at runtime), and / or firmware. For example, a circuit or like term can be a computer having a processor, a process operating on the processor, a controller, an object, an executable program, a storage device, and / or a processing device. By way of example, an application operating on a server and the server can also be a circuit. One or more circuits can be present within a process, a circuit can be localized to one computer, and / or can be distributed between two or more computers. In this specification, a set of elements or other set of circuits can be described, and the term "set" can be interpreted as "one or more."

[0069] As another example, a circuit or like term can be a device having a particular function provided by mechanical components operated by an electrical or electronic circuit, and the electrical or electronic circuit can be operable by a software application or firmware application executed by one or more processors. One or more processors can be present inside or outside the device and can execute at least a portion of the software or firmware application. As yet another example, a circuit can be a device that provides a particular function through electronic components without mechanical components, and the electronic components can include one or more processors that execute software and / or firmware that at least partially provides the functionality of the electronic components, such as field gates, logical components, hardware encoded logic, register transfer logic.

[0070] The use of exemplary terms is intended to present concepts in a specific way. The terms used in this specification are for the purpose of describing only specific examples and are not intended to limit the examples. In this specification, unless the context clearly indicates otherwise, singular articles are intended to include the plural as well. The terms "comprising," "comprises," "including," and / or "includes," when used in this specification, identify the stated features, integers, steps, operations, elements, and / or components, and it should be further understood that they do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "or" as used in this specification includes all options of the elements related to the term "or." For example, A or B should be construed to include only A, only B, as well as both A and B. Further, the phrase "one or more" followed by A, B, or C should be construed to include A, B, C, AB, AC, BC, and ABC.

Claims

1. 1. A Reduced Instruction Set Computer-V (RISC-V) architecture comprising: an advanced platform level interrupt controller (APLIC); and an incoming message signal interrupt (MSI) controller (IMSIC) coupled to the APLIC, the APLIC comprises a plurality of respective vectors connected to respective external interrupt inputs, each vector being mapped to an interrupt priority level, each vector comprising a vector interrupt lost (IL) bit; the IMSIC is configured to receive MSI from the APLIC and to maintain an interrupt file containing a set of interrupt lost (IL) bits indexed by interrupt priority; RISC-V architecture.

2. in response to receiving a message signaled interrupt (MSI) containing an indication of a predetermined interrupt priority of the interrupt file and an indication that the vector IL bit of the corresponding vector is set; or in response to receiving an MSI including an indication of the predetermined interrupt priority while an interrupt pending (IP) bit for the predetermined interrupt priority in the interrupt file is set; the IMSIC is configured to set an IL bit that is mapped to the predetermined interrupt priority level; 2. The RISC-V architecture of claim 1.

3. in response to resetting an IP bit mapped to a predetermined interrupt priority in the interrupt file, the IMSIC is configured to reset an IL bit mapped to the predetermined interrupt priority in the interrupt file.

2. The RISC-V architecture of claim 1.

4. The APLIC is setting the vector IL bit of the vector when an interrupt is received by a corresponding external interrupt input while the IP bit of the vector is set; in response, configured to transmit an MSI to the IMSIC, the MSI including a status of the vector IL bit of the vector and an indication of the interrupt priority of the vector; 2. The RISC-V architecture of claim 1.

5. the respective vectors are each mapped to a respective interrupt target and a respective interrupt priority of the respective interrupt target; The IMSIC maintains an interrupt file for each interrupt target.

2. The RISC-V architecture of claim 1.

6. The interrupt target is target hardware threads (hart); A target HART and the privilege level of the target HART, or A target heart and a virtual machine ID of the target heart are provided.

6. The RISC-V architecture of claim 5.

7. in response to receiving a new interrupt for a given interrupt vector while an interrupt pending (IP) bit for the given interrupt vector is set, the APLIC is configured to set an IL bit mapped to the given interrupt vector; 2. The RISC-V architecture of claim 1.

8. in response to resetting an interrupt pending (IP) bit mapped to a given interrupt vector when a corresponding interrupt is signaled as an MSI, the APLIC is configured to reset an IL bit mapped to the given interrupt vector; 2. The RISC-V architecture of claim 1.

9. Hardware components arranged into one or more hardware threads (harts); An interrupt source; An MSI controller; An interrupt architecture comprising: the interrupt sources are configured to receive respective external interrupt signals representing respective interrupt events, each interrupt event having a corresponding interrupt target, each interrupt target corresponding to an interrupt priority at a target of the one or more interrupts; The interrupt source is configured to send a plurality of message signal interrupts (MSIs) based on the received interrupt signal, the MSIs including, for an interrupt event, information regarding the interrupt target of the interrupt event; The MSI controller includes: receiving a plurality of MSIs from the interrupt sources; storing interrupt information for an interrupt target based on the received plurality of MSIs; determining that an interrupt event for the interrupt target has been lost, in response, configured to provide lost interrupt information to a target hart of the interrupt target, the lost interrupt information comprising an indication of one or more lost interrupt events. Interrupt architecture.

10. The interrupt target has an interrupt priority at a privilege level in the target heart or has an interrupt priority of a virtual machine in the target heart. The interrupt architecture of claim 9.

11. one MSI of the plurality of MSIs indicating an interrupt event for a given interrupt target includes an indication that an interrupt signal for a next interrupt event for the given interrupt target was received prior to transmission of the MSI; The interrupt architecture of claim 9.

12. The MSI controller is further configured to store interrupt information for each interrupt target based on the received plurality of MSIs, the interrupt information indicating whether an interrupt has been lost; The MSI controller is further configured to provide the lost interrupt information to a target hart associated with the interrupt target for which the interrupt was lost. The interrupt architecture of claim 11.

13. when the interrupt information for a given interrupt target indicates that an interrupt is pending, in response to receiving an MSI indicating an interrupt event for the given interrupt target, or in response to receiving an MSI indicating that an interrupt event for the given interrupt target has been lost, the MSI controller is configured to set the interrupt information for the given interrupt target to indicate that an interrupt has been lost. The interrupt architecture of claim 9.

14. The interrupt source is Convert each wired interrupt to its own MSI, detecting that an interrupt signal for a second interrupt event for a given interrupt target is received prior to transmitting an MSI for a first interrupt event for the given interrupt target; in response, storing an indication that an interrupt was lost for said given interrupt target; and further configured to encode the lost interrupt information in a first MSI for the first interrupt event. The interrupt architecture of claim 9.

15. In response to transmitting the first MSI, the interrupt source is further configured to clear the indication that an interrupt was lost. The interrupt architecture of claim 14.

16. the MSI controller is configured to signal the indication of one or more missed interrupt events on a per interrupt priority basis. The interrupt architecture of claim 9.

17. the MSI controller is configured to signal the indication of one or more missed interrupt events on a per interrupt target basis. The interrupt architecture of claim 9.

18. in response to an interrupt target having the same or greater privilege as the interrupt target receiving the indication of the one or more missed interrupt events, the MSI controller is configured to reset the missed interrupt information for the interrupt target. The interrupt architecture of claim 9.

19. 1. A method, comprising: receiving an interrupt message including an indication of one of a plurality of interrupt priorities; determining, based on the interrupt message, that an interrupt for a given interrupt priority has been lost; providing each missed interrupt information for each interrupt priority to a compute core; the lost interrupt information indicating whether an interrupt was lost or not. method.

20. The method further includes, in response to receiving an MSI including an indication of the interrupt priority and an indication that a vector IL bit in an interrupt source vector for the interrupt priority is set, setting an IL bit mapped to the interrupt priority in an interrupt file.

20. The method of claim 19.

21. The method further includes the step of setting an IL bit mapped to the interrupt priority in an interrupt file in response to receiving an MSI including an indication of the interrupt priority while an IP bit for the interrupt priority in the interrupt file is set.

20. The method of claim 19.

22. The method further includes the step of resetting an IL bit mapped to a predetermined interrupt priority in the interrupt file in response to resetting an IP bit mapped to the predetermined interrupt priority in the interrupt file.

22. The method of claim 21.

23. receiving a plurality of external interrupt signals, each of which is associated with an interrupt priority level; determining, based on the received interrupt signal, that an interrupt signal for a given interrupt priority has been lost; providing an indication to a compute core that the interrupt signal for the given interrupt priority has been lost; The method includes:

24. The method comprises: providing a plurality of respective vectors connected to respective external interrupt inputs for receiving said external interrupt signals, each vector being associated with a target computing core, each vector further comprising an indication of an interrupt priority, a vector interrupt pending (IP) bit, and a vector interrupt lost (IL) bit; setting the vector IL bit of the vector when an interrupt is received by a corresponding external interrupt input while the vector IP bit of the vector is set; Further comprising:

24. The method of claim 23.

25. The method comprises: selecting a vector based on an arbitration rule; sending a message signal interrupt (MSI) to an incoming MSI controller (IMSIC) connected to the target computing core of the selected vector; Further comprising: the MSI includes a status of the vector IL bit of the selected vector and an indication of the interrupt priority of the selected vector; 25. The method of claim 24.

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