Full die and partial die tape outs from common design

Abstract

To provide a chip design method and a set of integrated circuits that are taped out from a common design database.SOLUTION: The chip design method comprises: defining the area of a full instance of the integrated circuit; defining one or more cut lines to identify portions to be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized compared to the effort to tape out the full instance.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The embodiments described herein relate to integrated circuits, and more particularly, to integrated circuits designed for full and partial tape-outs.

Background Art

[0002] Integrated circuits include various digital logic circuits and / or analog circuits integrated on a single semiconductor substrate or “chip”. There are a wide variety of integrated circuits, ranging from fixed-function hardware to system-on-chips (SOCs) that include various other components that form highly integrated chips that can be central to microprocessors, processors, integrated memory controllers, and systems.

[0003] A given integrated circuit can be designed for use in various systems (e.g., “general-purpose” components). A given integrated circuit can include a set of components that enable it to be used in various systems, but a particular system may not require all of the components, or all of the functions and / or performance of all of the components. The extra components / functions are effectively wasted, resulting in unrecoverable costs and power consumption (at least leakage power) within the system. In the case of portable systems that operate at least sometimes on a limited power supply (e.g., a battery), inefficient use of power, as opposed to the essentially unlimited supply of a wall outlet, leads to inefficient use of the limited supply and, further, unacceptably short times between charges required by the limited supply.

[0004] Therefore, matching integrated circuit functionality to the requirements of a given system is important for manufacturing high-quality products. However, custom integrated circuit designs for many different systems also have costs in terms of the design and verification effort for each integrated circuit.

Brief Description of the Drawings

[0005] The following detailed description refers to the accompanying drawings briefly described below.

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[0020] Although there may be room for various modifications and alternative forms in the embodiments described in this disclosure, specific embodiments are shown in the drawings by way of example and are described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the embodiments to the specific forms disclosed, but rather the intention is to cover all modifications, equivalents, and alternative forms included within the spirit and scope of the appended claims. The headings used in this specification are for the purpose of organization only and are not intended to limit the scope of the description.

Embodiments for Carrying Out the Invention

[0021] In one embodiment, a method and design for an integrated circuit support two or more tape-outs of different implementation forms of the integrated circuit and its final manufacture based on a common design database. The design can support the overall instance in which all circuit components included in the design are included in the manufactured chip, and one or more partial instances including a subset of the circuit components in the manufactured chip. The partial instance can be manufactured on a smaller die, but the circuit components, as well as their physical layout and wiring with the partial instance, can be the same as the corresponding area within the overall instance. That is, the partial instance can be created by removing a part of the area of the overall instance and the components thereon from the design database to create the partial instance. Executing design, verification, synthesis, timing analysis, design rule checking, electrical analysis, etc. can be shared across the overall instance and partial instances. Further, in one embodiment, integrated circuit chips suitable for various different products such as computing requirements, form factors, cost structures, power supply limitations, etc. can be supported from the same design process. In one embodiment, the overall instance of an SOC can be connected to other overall instances or even different SOCs to build a larger system. In one embodiment, the partial instance can similarly be connected to the overall instance, other partial instances, and / or other SOCs to build a larger system. In one embodiment, a partial instance of a given SOC can include a partial instance of a given circuit component.

[0022] For example, an overall instance may include a specific number of computing units (e.g., a central processing unit (CPU) processor, a graphics processing unit (GPU), a coprocessor attached to the CPU processor, a digital signal processor, an image signal processor, or other special processors). A partial instance may include fewer computing units. The overall instance includes a specific amount of memory capacity via a plurality of memory controllers, and the partial instance may include fewer memory controllers that support a smaller memory capacity. In one embodiment, the number of memory channels may be reduced, thereby reducing the bandwidth. That is, the reduction of the memory controller / memory channel may support a smaller memory and / or a smaller memory bandwidth. The overall instance may include a specific number of input / output (I / O) devices and / or interfaces (also referred to as peripheral devices / interfaces or simply peripherals). The partial instance may have fewer I / O devices / interfaces.

[0023] In one embodiment, the partial instance may further include a stub region. The stub region can provide an end for an input signal to a circuit component included in the partial instance, and the source of those input signals within the overall instance is a circuit component within the removed region, and thus the input signal is unconnected in the absence of the stub. The output signal to a circuit component within the region removed from the circuit component can reach at least the edge of the stub and may be unconnected. In one embodiment, the stub region may include metallization for connecting the input signal to a power (digital 1) or ground (digital 0) wire (e.g., a power and ground grid) as needed to provide proper functionality of the circuit component in the partial instance. For example, a power manager block within the partial instance can receive an input from the removed circuit component, and the input can be connected to the power or ground grid to indicate that the removed circuit component is powered off, idle, etc., such that the power manager block does not wait for a response from the removed circuit component when changing the power state. In one embodiment, the stub region may include only metallization (wiring). That is, the stub region can exclude active circuit configurations (e.g., transistors formed on a semiconductor substrate). The metallization layer (or metal layer) is formed above the surface region of the semiconductor substrate to provide wire interconnects between active circuit elements (or to provide digital 1 / 0 values within the stub region). By managing the partial instance design in this way, the amount of verification of the partial instance can be minimized with respect to the effort in the overall instance. For example, additional timing verification may not be necessary, and additional physical design verification can be minimal.

[0024] FIG. 1 is a block diagram showing an embodiment of an overall instance of an integrated circuit and several partial instances. The overall instance of the integrated circuit is indicated by bracket 12 (“Chip 1”), and the partial instances of the integrated circuit are indicated by brackets 14 and 16 (“Chip 2” and “Chip 3”). Chip 1, which is the overall instance, includes a plurality of circuit components 10A - 10D. The physical positions of the circuit components 10A - 10D on the surface of the semiconductor substrate chip or die (reference number 18) of the overall instance are indicated by the arrangement of the circuit components 10A - 10D. FIG. 1 is a simplified representation, and there may be more circuit components, and the physical arrangement may be different from the arrangement shown in FIG. 1. The various interconnections between the circuit components 10A - 10D are used for communication between the components and are not shown in FIG. 1. The interconnections, as well as the interconnections within the circuit components 10A - 10D themselves, may be implemented in a metallization layer above the surface of the semiconductor substrate.

[0025] Each partial instance corresponds to the “shearing lines” 20A - 20B in FIG. 1. The shearing lines divide these circuit components 10A - 10D included in the overall instance into circuit components 10A - 10D included in various partial instances. Thus, for example, Chip 2 is defined by shearing line 20A and includes circuit components 10A - 10C but does not include circuit component 10D. Similarly, Chip 3 is defined by shearing line 20B and includes circuit components 10A - 10B but does not include circuit components 10C - 10D. The shearing lines may be defined in a design database or may be part of the design process, but may not be explicitly shown in the design database.

[0026] Generally, a design database may include a plurality of computer files that store descriptions of circuit components 10A - 10D and their interconnects. The design database may include, for example, a register transfer level (RTL) description of a circuit expressed in a hardware description language (HDL) such as Verilog, VHDL, etc. The design database may include a circuit description from a circuit editor tool for a circuit that is directly implemented rather than synthesized using a library of standard cells from an RTL description. The design database may include a netlist resulting from synthesis that describes standard cell instances and their interconnects. The design database includes a physical layout description of circuit components and their interconnects, and may include a tape - out description file that describes the integrated circuit in terms of geometric shapes and layers used to create masks for an integrated circuit manufacturing process. The tape - out description file may be expressed in a Graphic Design System (GDSII) format, an Open Artwork System Interchange Standard (OASIS) format, etc. Any of the above combinations may be included in the design database.

[0027] Shearing lines 20A - 20B divide the area of chip 18 into sub - areas within which a subset of circuit components 10A - 10D are instantiated. For example, shearing line 20B divides the area of chip 18 into a first sub - area (above line 20B as oriented in FIG. 1) and a second sub - area (below line 20B). Shearing line 20A further divides the second sub - area into third and fourth sub - areas, and the third sub - area is adjacent to or abuts the first sub - area. The combination of the first sub - area and the second sub - area represents the overall instance. The first sub - area alone (along with the stub area) represents the smallest partial instance (chip 3). The first sub - area and the third sub - area represent another partial instance (chip 2) of this embodiment.

[0028] The physical locations of circuit components within a given sub-region, as well as the interconnects within and between circuit components, may not change between the overall instance and the partial instance. Thus, if the circuit components within the overall instance meet the timing requirements, physical design requirements, and electrical requirements for the normal manufacture and use of the overall instance, the same requirements should generally also be met by the partial instance. The physical design and electrical requirements within the stub region may need to be verified, and as discussed below, certain physical design requirements such as corner exclusion zones or controlled collapse chip connect (C4) bump exclusion zones may apply to the sub-region. However, in one embodiment, once the overall instance has been verified and is ready for tape-out, the tape-out of the partial instance can be advanced with minimal effort.

[0029] Figures 2 to 4 show partial instances and an overall instance of the embodiment shown in FIG. 1. FIG. 4 is the overall instance and thus includes circuit components 10A to 10D. FIGS. 2 and 3 correspond to chip 3 and chip 2 respectively. Thus, the partial instance of FIG. 2 includes circuit components 10A to 10B from the first sub-region and the stub region 22 (stub 1). The partial instance of FIG. 3 includes circuit components 10A to 10B from the first sub-region, circuit component 10C from the second sub-region, and the stub region 24 (stub 2). In another embodiment, the partial instance can be formed by removing, for example, component circuit 10C in the portion between the shear lines 20A to 20B and joining the remaining sub-regions, for example, component circuits 10A to 10B and component circuit 10D. If three or more shear lines are defined, even more variations can be supported by removing one or more sub-regions between each pair of shear lines. Such embodiments can be implemented by implementing a stub region (which may be smaller than the removed sub-region) between the shear lines, or by ensuring that when the sub-region is removed and the remaining sub-regions are moved together, the wires on both sides of the removed sub-region match and are correctly connected. In yet another embodiment where multiple shear lines are used, one or more shear lines can be orthogonal to the other shear lines to remove sub-regions in two or more directions. In various embodiments, any combination of orthogonal shear lines and removal / joining of intermediate portions can be implemented.

[0030] A circuit component can be any group of circuits arranged to implement a particular component of an IC, such as a CPU or GPU, a cluster of processors or GPUs, a memory controller, a communication structure or a part thereof, a peripheral device or a peripheral interface circuit, etc. A given circuit component can have a hierarchical structure. For example, a processor cluster circuit component can have multiple instances of processors, which can be copies of the same processor design arranged multiple times within the area occupied by the cluster.

[0031] According to this description, the method may include defining, in a design database corresponding to an integrated circuit design, an area occupied by the integrated circuit design when manufactured on a semiconductor substrate. For example, the area may be the area of an overall instance as shown in FIGS. 1 and 4. The method may further include defining a scissor line (which may be one of a plurality of scissor lines). The scissor line can divide the area into a first sub-area and a second sub-area, and the combination of the first sub-area and the second sub-area represents the overall instance. The first sub-area and the stub area represent partial instances of an integrated circuit that include fewer circuit components than the overall instance. In the design database, the physical locations of a plurality of circuit components included in both the overall instance and the partial instance of the integrated circuit are defined within the first sub-area. The relative positions of the plurality of circuit components within the first sub-area and the interconnects of the plurality of circuit components within the first sub-area may not change in the overall instance and the partial instance. The physical locations of another plurality of circuit components that are included in the overall instance but excluded from the partial instance are defined within the second sub-area. The stub area is also defined in the design database. The stub area may include the ends of wires that would otherwise cross the scissor line between the first sub-area and the second sub-area. The stub area may ensure the correct operation of the plurality of circuit components within the first sub-area in the absence of the second sub-area in the partial instance. A first data set regarding the overall instance may be created using the first sub-area and the second sub-area, and the first data set defines the overall instance for the manufacture of the overall instance. A second data set regarding the partial instance may also be created using the first sub-area and the stub area. The second data set defines the partial instance for the manufacture of the partial instance. In one embodiment, the method may further include defining a second scissor line within the second sub-area to divide the second sub-area into a third sub-area and a fourth sub-area. The third sub-area may be adjacent to the first sub-area, and the third sub-area and the first sub-area may represent a second partial instance of the integrated circuit.This method may further include creating a third data set for a second partial instance using a first sub-region, a third sub-region, and a second stub region. The third data set defines the second partial instance for the manufacture of the second partial instance.

[0032] As described above, the stub region can exclude circuit configurations. For example, the stub region can exclude active circuit configurations such as transistors or other circuits formed on a semiconductor substrate. The stub region can also exclude circuits (e.g., explicit resistors, inductors, or capacitors) that can be similarly formed in a metallization layer. The metallization layer has parasitic characteristics (e.g., resistance, inductance, and capacitance), but circuits that are explicitly defined are not allowed. The stub region can include only wiring in one or more metallization layers above the surface region of the semiconductor substrate.

[0033] Another method may include, for example, receiving a first data set and a second data set in a semiconductor manufacturing facility or "foundry". The method may further include manufacturing a first plurality of overall instances of an integrated circuit based on the first data set and manufacturing a second plurality of partial instances of the integrated circuit based on the second data set.

[0034] An integrated circuit implementing a partial instance according to the present disclosure can include a plurality of circuit components physically disposed on a surface of a semiconductor substrate forming the integrated circuit, and a plurality of wire terminations along a single edge of the surface (e.g., a stub region). The plurality of wire terminations can be electrically connected to a plurality of supply wires of the integrated circuit to provide a fixed digital logic level on a wire that is an input to one or more of the plurality of circuit components. The power supply wires can be part of a power supply grid (e.g., a power and / or ground grid) within a metallization layer of the integrated circuit. The power and ground grid can also be referred to as the power and ground grid. The input wire terminated by the wire termination is oriented to intersect the single edge and lacks a circuit configured to drive the wire within the integrated circuit (e.g., the wire is driven in the overall instance by a circuit component in a second sub-region that does not exist in the partial instance). The region along the single edge including the plurality of wire terminations also excludes active circuit elements. For example, the region along the single edge can include only wiring in one or more metallization layers above the surface region of the semiconductor substrate.

[0035] The methods described herein can affect various areas throughout the design process for an integrated circuit. For example, floorplanning is an element of the design process in which various circuit components are assigned to areas on a semiconductor substrate. During floorplanning, taking into account the presence of sub-instances and the location of scribe lines, it can be ensured that the circuit components included in all instances are included within a first sub-region and other circuit components are included within a second sub-region (or third and fourth sub-regions, etc.). Further, the shape of the sub-regions can be carefully designed to provide for efficient use of the area in both the overall instances and the sub-instances. The main buses or other interconnects that can provide communication between circuit components throughout the overall instance can be designed to correctly manage the communication in the various instances (e.g., in a sub-instance, the bus can be terminated in a stub region or can be unconnected in the stub region, such that communication should not be sent in the direction of the stub region). Floorplanning can also take into account the tape-out requirements for both the overall instances and the sub-instances (e.g., various exclusion zones as discussed in more detail below). Further, floorplanning can attempt to minimize the number of wires crossing scribe lines in order to simplify the verification that the sub-instances are operating correctly.

[0036] In one embodiment, the considerations at the floorplanning stage can include the specification of certain critical connections that can be affected by shearing in the sub-instances. Clock interconnects and analog interconnects can be examples. Often, a clock interconnect (or “clock tree”) is designed such that the distance and electrical load from a clock generator or clock source to a clock termination is approximately the same, or “balanced,” at various state elements within a circuit component. State elements can include, for example, flip-flops (“flops”), registers, latches, memory arrays, and other clocked storage devices.

[0037] To maintain balance among various instances of integrated circuit design, individual clock trees may be defined between local clock sources within each sub-region and state elements within that sub-region. For example, FIG. 5 is a block diagram showing an overall instance of an integrated circuit (chip 18) and one embodiment of shear lines 20A - 20B that divide the sub-regions of the overall instance for shearing into partial instances. Local clock source(s) 30A - 30C are illustrated, each driving an individual clock tree indicated by lines within each sub-region. The clock tree may not cross the shear lines 20A - 20B. That is, the clock tree within a given sub-region may stay within that sub-region.

[0038] A clock source can be any circuit configured to generate a clock signal for a circuit configuration connected to the clock tree. For example, the clock source may be a phase - locked loop (PLL), a delay - locked loop (DLL), a clock - dividing circuit, etc. The clock source can be connected to a clock input of an integrated circuit to which an external clock signal is provided, and the clock source can multiply or divide the frequency while locking the phase or clock edge to the external signal.

[0039] Accordingly, the method may further include defining one or more first clock trees in the first sub-region to distribute clocks within the first sub-region, and defining one or more second clock trees in the second sub-region to distribute clocks within the second sub-region. The one or more first clock trees may be electrically isolated from the one or more second clock trees in the overall instance. The clock trees may be physically independent as shown in FIG. 5 (e.g., connected to different local clock sources). The clock trees may not need to cross a scribe line into another sub-region. In the manufacturing method, the first data set may further include one or more first clock trees for distributing clocks within the first sub-region and one or more second clock trees for distributing clocks within the second sub-region, and in the overall instance, the one or more first clock trees may be electrically isolated from the one or more second clock trees.

[0040] In one embodiment, the integrated circuit may include one or more clock trees for distributing clocks within a first sub-region of a first region and one or more second clock trees for distributing clocks within a second sub-region. The one or more first clock trees may be electrically isolated from the one or more second clock trees.

[0041] FIG. 6 is a block diagram showing an embodiment of the overall die 18 divided by the shear lines 20A-20B and the provision of local analog pads 32A-32C within each sub-region defined by the shear lines 20A-20B. The analog pads 32A-32C can provide connection points for analog inputs to the chip. Analog signals often have special requirements such as shielding from digital noise that can affect the accuracy and functionality of the analog signal. These signals are continuous value signals as opposed to digital signals that only mean digital values and do not mean transitions between them. By ensuring that the analog requirements are met within each sub-region, the design of the entire integrated circuit can be simplified. In one embodiment, if there is no use of analog signals within a given sub-region, that sub-region can exclude the analog pads and signal routing.

[0042] Accordingly, the method may further include defining one or more first analog inputs within the first sub-region and defining one or more second analog inputs within the second sub-region. The one or more first analog inputs may remain within the first sub-region, and the one or more second analog inputs may remain within the second sub-region. That is, analog signals on or derived from the inputs may be transmitted on wires that do not cross the shear lines 20A-20B. In the manufacturing method, the first data set can further include one or more first analog inputs in the first sub-region, the one or more first analog inputs remaining within the first sub-region, the first data set further including one or more second analog inputs in the second sub-region, and the one or more second analog inputs remaining within the second sub-region.

[0043] According to the present disclosure, an integrated circuit may include a first plurality of circuit components physically disposed within a first region of the surface of a semiconductor substrate forming the integrated circuit, and a second plurality of circuit components physically disposed within a second region of the surface of the semiconductor substrate forming the integrated circuit. One or more first analog inputs may be provided within the first region, and the one or more first analog inputs are separated from the first plurality of circuit components. One or more second analog inputs are provided within the second region, and the one or more second analog inputs are separated from the second plurality of circuit components.

[0044] Another feature of the integrated circuit that may be considered is a design for testability (DFT) strategy. DFT generally includes ports or a plurality of ports, and on the ports, a DFT interface such as an interface compatible with the Joint Test Access Group (JTAG) specification is defined. DFT can include defining a scan chain of state elements to scan in and scan out states in the design, and the scan chain can be defined to stay within a given sub-region, for example. To minimize cross-talk communication as much as possible, separate DFT ports can be provided within each sub-region. If cross-talk communication is required, such signals can be terminated (input to the sub-region) and left unconnected in a stub region (output of the sub-region), similar to other signals. In one embodiment, the scan network and other DFT networks may be designed as a hierarchical ring, whereby portions within removed circuit components can be disconnected from the DFT network without further affecting the remaining network.

[0045] In one embodiment, some circuit components may be instantiated multiple times within the overall instance. One or more of the instances may be in a sub-region not included in one or more of the partial instances. These circuit components are designed to meet all requirements (timing, physical, electrical) at each position of the instance and thus may be overdesigned for some other positions (e.g., the circuit components may be designed to account for worst-case clock skew etc. across those positions). Further, the partial instances may have different packaging solutions that may require additional design to handle differences within the package (e.g., different IR voltage drops).

[0046] In one embodiment, the foundry may require the fabrication of certain “non-logic” cells on the semiconductor substrate. These cells are not part of the integrated circuit itself but may be used by the foundry to adjust the manufacturing process. The cells required by the foundry may have strict rules and may depend on the die size and thus it may be necessary to plan the placement so that these cells in the floorplan of the overall instance are also properly placed in the partial instance(s).

[0047] FIG. 7 shows an embodiment of various types of exclusion regions (or exclusion zones), which is another consideration in integrated circuit design. On the left side of FIG. 7, the overall instance (chip 1) of the overall die 18 is shown together with the partial instance on the right side, with chip 3 on the upper side (the position within the overall instance is above the shear line 20B indicated by the dotted line 34) and chip 2 on the lower side (the position within the overall instance is above the shear line 20A indicated by the chain line 36). For each instance, the corners of the chip have exclusion zones where circuit construction is not permitted (or must follow much stricter design rules than other parts of the semiconductor substrate surface). Since the mechanical stress on the corners of the semiconductor die can be greater than that at other positions of the chip, corner exclusion zones may be defined. The corner exclusion zones are shown by the shaded regions indicated by reference numeral 38 in FIG. 7.

[0048] Thus, the overall instance has "corner" exclusion zones along the sides of the chip not only at the corner exclusion zones at each of the four corners, but also at the corners of the sub-regions adjacent to the shear lines 20A - 20B, and these shear lines terminate at the corners of the chips of the partial instances. The additional corner exclusion zones may be the same size as the corner exclusion zones of the overall instance, or may be different if the size of the corner exclusion zones increases or decreases according to the size of the entire die.

[0049] Thus, the method may further include defining a plurality of exclusion zones at each corner of the semiconductor substrate, and the circuit components are excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The method may further include defining additional exclusion zones at the corners of the first sub-region adjacent to the shear line, whereby the partial instance includes exclusion zones at each corner of the semiconductor substrate on which the partial instance is formed. The first data set in the manufacturing method may include a plurality of exclusion zones at each corner of the semiconductor substrate, the circuit components are excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, and the first data set may include additional exclusion zones at the corners of the first sub-region adjacent to the second sub-region, whereby the partial instance includes exclusion zones at each corner of the semiconductor substrate on which the partial instance is formed.

[0050] Furthermore, an integrated circuit (e.g., including an overall instance) may include a first plurality of circuit components physically disposed within a first region on the surface of a semiconductor substrate forming the integrated circuit, a plurality of exclusion zones at respective corners of the semiconductor substrate, where the circuit components are excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, and another plurality of exclusion zones separating from respective corners along a pair of nominally parallel edges of the semiconductor substrate, where the circuit components are excluded from the another plurality of exclusion zones and the another plurality of exclusion zones are substantially the same size as the plurality of exclusion zones.

[0051] FIG. 7 also shows the allowable positions of C4 bumps in the overall and partial instances of the integrated circuit, and those positions are shown as the double-hatched region of reference numeral 40 in FIG. 7. Regions outside the region indicated by the double-hatched region 40 may not be the allowable positions of C4 bumps (e.g., exclusion zones for C4 bumps), or more stringent rules may be defined for placing C4 bumps in those regions. Thus, there are allowable position / exclusion zones at each edge of each instance. That is, C4 exclusion zones may exist around the entire die 18 and on both sides of the scribe lines 20A - 20B. Thus, the method may further include defining a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region, and controlled collapse chip connection (C4) connections are excluded from the second exclusion zone. In the manufacturing method, the first data set may further include a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region, and controlled collapse chip connection (C4) connections are excluded from the second exclusion zone. In one embodiment, the integrated circuit may include a second exclusion zone along a line between the plurality of exclusion zones, and controlled collapse chip connection (C4) connections are excluded from the second exclusion zone.

[0052] FIG. 8 is a block diagram showing in more detail one embodiment of the circuit components 10B and the stub region 22 of the embodiment of the chip 3 shown in FIG. 2. Similar connections to the circuit components 10A may also be provided, and the stub region 24 of FIG. 3 may be similar to the circuit components 10A-10C. The stub region 22 is provided for the input provided by the removed circuit components that are part of the overall instance but not part of the partial instance, as indicated by the dotted line from the end to the edge of the stub region 22 in FIG. 8, for the V of the circuit component 10B DD terminals 50 (where the input is coupled upward or to binary 1), and V SS or ground terminal 52 (where the input is coupled downward or to binary 0), etc. The selection of binary 1 or binary 0 for a given terminal may depend on the logical effect of the input within the circuit component 10B. Generally, the terminal can be selected as any value that advances the receiving circuit without further input from the removed circuit components that supply the input in the overall instance (e.g., as the output of the removed circuit parts). The terminal provides a known value when there is no driving circuit for the signal. The output of the circuit component 10B connected to the removed circuit components may reach the stub region (e.g., reference numerals 54 and 56), but may be unconnected (e.g., not connectable to the receiving circuit). In the overall instance or a relatively large partial instance, the output wires 54 and 56 may extend to circuit components that do not exist in the partial instance (shown by the dotted line in FIG. 8).

[0053] Thus, the input terminated in the stub region can be a wire that extends into the stub region and is oriented to cross the edge of the integrated circuit where the stub region is located. The input lacks a circuit configured to drive the wire within the integrated circuit (e.g., the wire is driven in the overall instance by circuit components that do not exist in the partial instance).

[0054] In other cases, it may be desirable to replace the local input for the input from the removed circuit component. For example, a loopback circuit used for testing, or a ring interconnect structure, can locally complete the loopback / ring in a partial instance. To support such instances, the receiving circuit component (e.g., circuit component 10B) may include logic circuitry for selecting between a local signal and an input from the removed component. For example, in FIG. 8, circuit component 10B may include a plurality of multiplexers (muxes) 58 and 60. Each mux 58 or 60 may be coupled to an input wire that is normally supplied from a circuit component that does not exist in the partial instance. The input wire may reach the stub region 22 but may be unconnected. Alternatively, the input wire may be terminated with a binary 1 or zero as needed. Such termination of the input can prevent the input from floating and the floating input from causing wasteful current draw between power and ground for a significant period of time. The mux selection wire may also be provided from the stub region 22 and can end with a binary 0 (V SS ) or binary 1 (V DD ) and can cause the mux to select the local wire. If the source circuit component of the input wire exists (e.g., in the overall instance or a relatively large partial instance), the mux selection wire may be provided from the source circuit component (dotted line in FIG. 8). In such a case, the mux selection wire can be a dynamic signal that can select between the local input and the input from the source circuit component if desired during operation, or can be coupled to the opposite binary value compared to the mux selection wire within the stub region 22.

[0055] Thus, in one embodiment of the method, the overall instance may include a plurality of other circuit components within the second sub-region, and these circuit components may include a plurality of outputs that are a plurality of inputs to the plurality of circuit components within the first sub-region. The plurality of circuit components may include a plurality of multiplexer circuits having corresponding inputs among the plurality of inputs as inputs. The method may include representing, in the stub region, a plurality of selection signals for the plurality of multiplexer circuits. The plurality of selection signals may be binary values that select inputs of the plurality of multiplexer circuits, different from the mux inputs to which the plurality of inputs are connected, and may be terminated within the stub region. In one embodiment, the plurality of selection signals may be terminated within the second sub-region with different binary values.

[0056] In one embodiment, the integrated circuit may include a plurality of circuit components physically disposed on the surface of a semiconductor substrate forming the integrated circuit. The plurality of circuit components includes a plurality of multiplexer circuits, and a given multiplexer circuit of the plurality of multiplexer circuits has a first input wire, a second input wire, and a selection control wire. The integrated circuit may further include a region along a single edge of the surface, which is the power supply for the selection control wire, the second input wire reaches a single edge of the surface and is unconnected, and the selection control wire is electrically connected to the supply wire of the integrated circuit. The voltage on the supply wire in use corresponds to a digital logic level that causes the plurality of multiplexer circuits to select the first input wire as the output of the plurality of multiplexer circuits.

[0057] Next, refer to FIG. 9, which is a block diagram of one embodiment of a pair of integrated circuits 76 and 78 that may be an overall instance of chip 18. In one embodiment, break lines 20A-20B are shown with respect to integrated circuit 76, and specific additional details of integrated circuit 76 are shown. In particular, integrated circuit 76 can include a plurality of network switches 70A-70H that can be part of a communication network within integrated circuit 76. The communication network can be an example of a circuit component and can be configured to provide communication between other circuit components (e.g., processors, memory controllers, peripherals, etc.).

[0058] The network switches 70A - 70H can be interconnected using any form such as a ring, mesh, star, etc. When a given communication message or packet is received by the network switches 70A - 70H, the network switches 70A - 70H can determine the output to which the packet should be sent in order to move the packet towards the destination. The direction may depend on which instance of the integrated circuit the network switch is manufactured from. For example, if the whole instance is manufactured, a given network switch such as network switch 70E can transmit the packet either upward or downward as shown in FIG. 9 (or if another circuit component not shown connected to network switch 70E is the target of the packet, network switch 70E can send the packet to that circuit component). However, if a partial instance is formed based on the cut line 20A, network switch 70E cannot send the packet downward because there is no receiving circuit. Similarly, in that scenario, network switch 70F cannot send the packet downward. When a partial instance is formed based on the cut line 20B, network switches 70C and 70D cannot send the packet in the downward direction.

[0059] Therefore, the operations of at least some of the network switches 70A - 70H may be instance - dependent. There may be multiple ways to manage the differences. For example, the input to the switch can specify the instance (output by the stub area or, in the case of the whole instance, by a circuit component within the area below the cut line 20B). In the illustrated embodiment, a routing table or other programmable resource 74 can be included in each network switch 70A - 70H. The routing table 74 can be programmed during initialization based on the instance at a given location (e.g., by boot code or other firmware).

[0060] Similarly, various instances can have different numbers of memory controllers (e.g., circuit components within a removed sub-region can include a memory controller, and additional memory controllers can exist in the remaining sub-regions). The memory address space can be mapped onto the memory controllers, and thus, the mapping can vary based on the number of memory controllers actually present in a given whole or partial instance. The network switches 70A - 70H that carry memory operation packets can be programmable with data that describes the address mapping using programmable resources. Other circuit components that may need to be notified of a properly operating address mapping can similarly have programmable resources.

[0061] In the illustrated embodiment, a pair of integrated circuits 76 and 78 can be configured to communicate with each other and function as if they were a single integrated circuit die. For example, the network switches 70A - 70H on each of the integrated circuits 76 and 78 can communicate via a die - to - die (D2D) interface circuit 72 to form a single communication interconnect across the integrated circuits 76 and 78. Thus, a packet originating from either integrated circuit die can have a destination on the other integrated circuit die and can be sent via the D2D interface circuit 72 to the target in a seamless manner and thus be nearly invisible to the software executed within the system.

[0062] Since a partial instance of an integrated circuit includes less than the whole instance of the circuit configuration, one of the component circuits that can be removed from each of the partial instances is the D2D interface circuit 72. That is, the D2D interface circuit 72 can be instantiated within a sub-region that is removed from each of the partial instances (e.g., below the dashed line 20A in the illustrated embodiment).

[0063] FIG. 10 is a flowchart showing various parts of a design and proof-of-concept / verification method for an integrated circuit that supports whole and partial instances. The design database for the whole instance is shown in the upper center of FIG. 10 (reference number 80). The design databases for the partial instances are shown to the left and right of the whole instance (reference numbers 82 and 84). The design databases 82 and 84 draw out from the design database 80 the contents of the sub-regions forming the integrated circuit and the corresponding stub regions 22 and 24 as shown in FIG. 10, as indicated by the arrows 86 and 88.

[0064] The databases 80, 82, and 84 can be analyzed using static timing analysis (block 90) to verify that the design meets timing requirements, physical verification (block 92) to verify that the design meets various physical design rules, and electrical verification (block 94) to verify that the design meets electrical requirements such as power grid stability and impedance (along with the package used for each design, which can vary between the whole instance and the partial instances). The physical design rules can include features such as the minimum spacing between wirings within a device and / or wiring layer and device size. The physical design rules can also include, as described above, corner exclusion, C4 bump exclusion, etc. Further, in one embodiment, there may be additional "antenna" rules to address for outputs from circuit components that are not connected in the partial instances.

[0065] The results of the various verification steps are considered and triaged (triage ECO blocks 96, 98, and 100) for design changes (design change orders or ECOs) that can be expected to improve the results of subsequent executions of the various verifications. The ECO can be executed in the design database 80 (arrows 102, 104, and 106) regardless of which instance causes the ECO. Thus, the design database 80 can be somewhat overdesigned if the worst-case correction required for the design occurs from one of the partial instances. If changes are made in a sub-region included in the partial instance, after the changes are made to update the partial instance, the design databases 82 and 84 can be extracted from the design database 80.

[0066] Once the various verifications are complete (clean blocks 108, 110, and 112), tape-out is performed on the full instance and the partial instances (blocks 114, 116, and 118), and a data set for each instance is obtained (blocks 120, 122, and 124).

[0067] In various embodiments, there can be additional analysis and design flows, but similarly, any ECO identified by the various design efforts can be implemented in the full instance design database 80 and then extracted into the partial design databases 82 and 84.

[0068] Another area of integrated circuit design methods that can be affected by the overall and partial instance support of integrated circuit design is design verification (DV). DV generally involves testing the integrated circuit design, or a part of it such as a given circuit component, to ensure that the design operates as expected and meets the functional and / or performance requirements of the design. For example, DV can include defining a test bench to stimulate the design and measurement operations against the expected results. The test bench can include, for example, additional HDL code to describe the stimuli. To avoid significant rework and additional resources for executing DV on all instances of the design, a configurable test bench environment that covers each instance can be defined. At the component level, the components can be tested using the reproduction of chip-level differences between instances.

[0069] FIG. 11 is a block diagram showing an embodiment of a test bench configuration for chip-level DV. In this example, the test bench can include a test top level 170 that can include a defined description ($DEFINE) that can be selected to be chip 1 (the overall instance), chip 2 (the partial instance), or chip 3 (the partial instance). That is, for a given simulation, the $DEFINE description can be set to the instance being tested (one of the labeled chips 1, 2, or 3). The test top level 170 can further include a device under test (DUT) 172 (e.g., an integrated circuit of partial and overall instances) and a test bench (TB) 174.

[0070] DUT172 may include portions of integrated circuits included in each instance (e.g., in this embodiment, circuit components 10A - 10B common to each instance). The common portion 176 may be unconditionally included in DUT172 for a given simulation. Depending on the instance being tested in a given simulation, one of three additional portions may be conditionally included. For example, if chip 1 is being tested (and thus the $DEFINE statement describes chip 1), other circuit components 10C - 10D may be included (reference numeral 178). If chip 2 is being tested (and thus the $DEFINE statement describes chip 2), circuit component 10C and stub 24 may be included (reference numeral 180). If chip 3 is being tested (and thus the $DEFINE statement describes chip 3), stub 22 may be included in the worst case (reference numeral 182).

[0071] Test bench 174 may similarly be configurable based on the $DEFINE statement. Test bench 174 may include a common portion 184 corresponding to the common portion 176 (e.g., the stimulus of the common portion 176). The other portions 184, 186, or 188 may be selectively included based on the $DEFINE statements describing chip 1, chip 2, and chip 3, respectively. Stimuli for the corresponding portions 178, 180, and 182 may be included, respectively. That is, the stimulus for the combination of circuit components 10C - 10D may be included in portion 186. The stimulus for the combination of circuit component 10C and stub 24 may be included in portion 188, and the stimulus for stub 22 may be included in portion 190. In one embodiment, since stub 22 may not include any active circuit configuration, portion 190 may be omitted. Alternatively, differences in operation in the common portion 176 may be captured within portion 190.

[0072] Thus, the same overall setup of test top - level 170 enables simulation of any instance of the design with only a change in the $DEFINE statement to select the design.

[0073] FIG. 12 shows an example of a circuit component level test by replication. In this example, chip 1 is shown with a specific input / output (e.g., interface) between circuit component 10C and circuit component 10B. Interfaces between other inputs and outputs of circuit components 10A and 10D are received by circuit component 10B but are not shown in FIG. 12 for simplicity.

[0074] Thus, the test configuration of circuit component 10B can include the DUT's circuit component 10B (reference number 192). The interface between circuit component 10B and circuit component 10C can be modeled via a model of circuit component 10C within test bench 194. The model may be a behavioral model of circuit component 10C. Alternatively, the model can be a bus function model of circuit component 10C that faithfully reproduces the operation of circuit component 10C on the interface but may omit many internal operations. Any model can be used. The test configuration can be replicated to test the placement of chip 3. For example, stub 22 is included to couple various input signals from circuit component 10C to circuit component 10B on the interface upward and downward. The replicated placement includes test bench 196 that instantiates the upward and downward couplings of DUT 192 and stub 22.

[0075] In one embodiment, the design integration (DI) can be similarly modified. The design integration includes the process of connecting various circuit components 10A-10D and can provide any necessary "glue logic" etc. that enables correct communication between the circuit components 10A-10D. When various instances of the integrated circuit are taped out, various configurations can change. For example, the routing of packets through network switches 70A-70H (or a subset of the switches included in a given instance) can be instance-dependent. Accordingly, the programming of the routing table 74 can change based on the instance. Other behaviors of the design such as power management can also change similarly. If the behavior is not sufficiently controlled by the pull-ups and pull-downs within the stubs 22 or 24, fuses can be used to identify the instance and thus the programming of various configuration registers within the routing table 74 or other circuit components 10A-10D. The fuses can be part of the stubs, or can be included in the circuit components 10A-10D, and can be selectively blown for a given instance.

[0076] FIG. 13 is a flowchart showing one embodiment of a method for designing and manufacturing an integrated circuit. For ease of understanding, the blocks are shown in a particular order, but other orders may be used. The individual blocks can be executed in parallel.

[0077] The method may include defining, in a design database corresponding to an integrated circuit design, an area occupied by the integrated circuit design when manufactured on a semiconductor substrate (block 130). The method may further include defining, optionally, a scribe line, or two or more scribe lines. The scribe line(s) can divide the area into a first sub-area and a second sub-area, and the combination of the first sub-area and the second sub-area represents the overall instance of the integrated circuit, and the first sub-area and the stub area represent a partial instance of the integrated circuit that includes fewer circuit components than the overall instance (block 132). The method may further include representing, in the design database, the physical locations of a plurality of circuit components included in both the overall instance and the partial instance of the integrated circuit within the first sub-area (block 134). In one embodiment, the relative positions of the plurality of circuit components within the first sub-area and the interconnects of the plurality of circuit components within the first sub-area do not change in the overall instance and the partial instance. The method may further include representing, in the design database, the physical locations of another plurality of circuit components that are included in the overall instance but excluded from the partial instance of the second sub-area (block 136). The method may further include defining, in the stub area within the design database, the terminations of wires that would otherwise cross the scribe line(s) between the first and second sub-areas, to ensure the correct operation of the plurality of circuit components within the first sub-area in the absence of the second sub-area in the partial instance (block 138). The method may further include creating a first data set regarding the overall instance using the first sub-area and the second sub-area (block 140). The first data set may define the overall instance for manufacturing the overall instance. The method may further include creating a second data set regarding the partial instance using the first sub-area and the stub area, and the second data set defines the partial instance for manufacturing the partial instance (block 142). The method may further include manufacturing the overall and partial instances based on the first and second data sets, respectively (block 144).

[0078] In one embodiment, the stub region may exclude circuit configurations. For example, the stub region may include only wiring in one or more metallization layers above the surface region of the semiconductor substrate. In one embodiment, the other plurality of circuit components in the second sub-region may include a plurality of outputs that are a plurality of inputs to the plurality of circuit components in the first sub-region. The plurality of circuit components may include a plurality of multiplexer circuits having corresponding inputs among the plurality of inputs as inputs. The method may further include representing in the stub region a plurality of selection signals for the plurality of multiplexer circuits. The plurality of selection signals may be binary values that select inputs of the plurality of multiplexer circuits different from the inputs to which the plurality of inputs are connected, and may be terminated within the stub region. The plurality of selection signals may be terminated within the second sub-region with different binary values.

[0079] In one embodiment, the method may further include defining a plurality of exclusion zones at respective corners of the semiconductor substrate. Circuit components may be excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The method may further include defining an additional exclusion zone at a corner of the first sub-region adjacent to the scribe line, whereby the partial instance includes exclusion zones at respective corners of the semiconductor substrate on which the partial instance is formed.

[0080] In one embodiment, the method may further include defining a second exclusion zone along an edge of the first sub-region adjacent to the second sub-region. A controlled collapse chip connection (C4) connection may be excluded from the second exclusion zone. In one embodiment, the method may further include defining one or more first analog inputs within the first sub-region and defining one or more second analog inputs within the second sub-region. The one or more first analog inputs may initially remain within the first sub-region, and the one or more second analog inputs may remain within the second sub-region. In one embodiment, the method may further include defining one or more first clock trees in the first sub-region to distribute clock within the first sub-region and defining one or more second clock trees in the second sub-region to distribute clock within the second sub-region. The one or more first clock trees may be electrically isolated from the one or more second clock trees in the overall instance. In one embodiment, the method may further include defining a second scribe line in the design database for the second sub-region. The second scribe line may divide the second sub-region into a third sub-region and a fourth sub-region, and the third sub-region is adjacent to the first sub-region. The third sub-region and the first sub-region may represent a second partial instance of the integrated circuit. The method may further include creating a third data set for the second partial instance using the first sub-region, the third sub-region, and the second stub region. The third data set may define the second partial instance for the manufacture of the second partial instance.

[0081] FIG. 14 is a flowchart showing one embodiment of a method of manufacturing an integrated circuit. For ease of understanding, the blocks are shown in a particular order, but other orders may be used. The individual blocks may be executed in parallel.

[0082] In one embodiment, the method may include receiving a first dataset regarding an overall instance of an integrated circuit design (block 150). The first dataset may define the overall instance for manufacturing the overall instance. The overall instance may include a first plurality of circuit components physically located in a first sub-region of the region occupied on the semiconductor substrate by the overall instance, and a second plurality of circuit components physically located in a second sub-region of the region occupied on the semiconductor substrate by the overall instance. The method may further include receiving a second dataset regarding a partial instance of the integrated circuit design (block 152). The second dataset may define the partial instance for manufacturing the partial instance. The partial instance may include the first plurality of circuit components within the first sub-region, and the relative positions of the first plurality of circuit components within the first sub-region and the interconnects of the first plurality of circuit components within the first sub-region do not change in the overall instance and the partial instance. The partial instance may further include a stub region adjacent to the first sub-region, and the stub region terminates wires that would otherwise interconnect components within the first and second sub-regions to ensure the correct operation of the first plurality of circuit components within the first sub-region in the absence of the second sub-region in the partial instance. The method may further include manufacturing a first plurality of overall instances of the integrated circuit based on the first dataset (block 154), and manufacturing a second plurality of partial instances of the integrated circuit based on the second dataset (block 156).

[0083] In one embodiment, the stub region excludes circuit configurations. For example, the stub region may include only wiring in one or more metallization layers above the surface region of the semiconductor substrate. In one embodiment, the other plurality of circuit components in the second sub-region include a plurality of outputs that are a plurality of inputs to the first plurality of circuit components in the first sub-region, and the first plurality of circuit components include a plurality of multiplexer circuits each having one of the plurality of inputs as an input. The stub region may further include a plurality of selection signals for the plurality of multiplexer circuits. In one embodiment, the plurality of selection signals are binary values that select inputs of the plurality of multiplexer circuits, different from the inputs to which the plurality of inputs are connected, and are terminated within the stub region. The plurality of selection signals may be terminated within the second sub-region with different binary values in the overall instance.

[0084] In one embodiment, the first data set may include a plurality of exclusion zones at respective corners of a semiconductor substrate. Circuit components may be excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The first data set may further include additional exclusion zones at the corners of the first sub-region adjacent to the second sub-region, whereby the partial instance includes exclusion zones at respective corners of the semiconductor substrate on which the partial instance is formed. In one embodiment, the first data set may further include a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region, and the controlled collapse chip connection (C4) connection is excluded from the second exclusion zone. In one embodiment, the first data set may further include one or more first analog inputs in the first sub-region and one or more second analog inputs in the second sub-region. The one or more first analog inputs remain within the first sub-region and the one or more second analog inputs remain within the second sub-region. In one embodiment, the first data set may further include one or more first clock trees for distributing a clock within the first sub-region and one or more second clock trees for distributing a clock within the second sub-region, and in the overall instance, the one or more first clock trees are electrically isolated from the one or more second clock trees. Computer-readable storage medium

[0085] Next, referring to FIG. 15, a block diagram of one embodiment of a computer-readable storage medium 800 is shown. Generally, a computer-accessible storage medium can include any storage medium that is accessible by a computer at use to provide instructions and / or data to the computer. For example, a computer-accessible storage medium can include magnetic or optical media such as storage media like (fixed or removable) disks, tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray. The storage medium can further include volatile or non-volatile memory media such as RAM (e.g., synchronous DRAM (SDRAM), Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, or flash memory. The storage medium can be physically mounted within the computer to which it provides instructions / data. Alternatively, the storage medium can be connected to the computer. For example, the storage medium can be connected to the computer via a network or wireless link, such as network-attached storage. The storage medium can be connected by a peripheral device interface such as a Universal Serial Bus (USB). Generally, the computer-accessible storage medium 800 can store data in a non-transitory manner, where non-transitory can mean, in this context, not transmitting instructions / data on a signal. For example, non-transitory storage can be volatile (where stored instructions / data can be lost upon power-off) or non-volatile.

[0086] The computer-accessible storage medium 800 of FIG. 15 may store databases 802, 804, and 806 that represent whole instances of integrated circuits and partial instances of integrated circuits. In general, databases 802, 804, and 806 may be databases that are read by a program and used, directly or indirectly, to manufacture hardware that includes the instances. For example, the databases may be behavioral-level descriptions or register-transfer level (RTL) descriptions of hardware functions in a high level design language (HDL) such as Verilog or VHDL. The descriptions can be read by synthesis tools that synthesize the descriptions to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represents the functionality of the hardware that includes the instances. The netlist can then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask can then be used in various semiconductor fabrication steps to generate one or more semiconductor circuits corresponding to the instances. Alternatively, databases 802, 804, and 806 on computer-accessible storage medium 800 may, optionally, be a netlist or a data set (with or without a synthesis library).

[0087] The computer-accessible storage medium 800 stores representations of instances, although other embodiments may, as needed, hold representations of any part of an instance. Computer system

[0088] Next, turning to FIG. 16, a block diagram of one embodiment of system 700 is shown. In the illustrated embodiment, system 700 includes at least one instance of a system-on-chip (SOC) 706 coupled to one or more peripheral devices 704 and an external memory 702. A power management unit (PMU) 708 is presented that supplies a supply voltage to SOC 10 and supplies one or more supply voltages to memory 702 and / or peripheral devices 704. In some embodiments, two or more instances of SOC 706 may be included (and two or more memories 702 may also be included). More specifically, SOC 706 can be any instance of the integrated circuit (e.g., whole or in part) described herein.

[0089] Peripheral device 704 may include any desired circuit configuration depending on the type of system 700. For example, in one embodiment, system 704 can be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 704 can include devices for various types of wireless communication such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. Peripheral device 704 may also include additional storage including a RAM storage device, a solid state storage device, or a disk storage device. Peripheral device 704 may include user interface devices such as a touch display screen or a multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc. In other embodiments, system 700 can be any type of computing system (e.g., a desktop personal computer, a laptop computer, a workstation, a nettop, etc.).

[0090] External memory 702 may include any type of memory. For example, external memory 702 can be a dynamic random access memory (DRAM) such as SRAM, synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, Rambus DRAM, a low-power version of DDR DRAM (e.g., LPDDR, mDDR, etc.). External memory 702 may include one or more memory modules on which memory devices such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. are mounted. Alternatively, external memory 702 may include one or more memory devices mounted on SOC 706 in a chip-on-chip or package-on-package implementation form.

[0091] As shown, system 700 has been shown to be applicable to a wide range of areas. For example, system 700 can be utilized as part of the chips, circuits, components, etc. of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a TV 750 (or a set-top box connected to a TV). Also shown are a smartwatch and a health monitoring device 760. In some embodiments, the smartwatch may include various general computing-related functions. For example, the smartwatch can provide access to email, cellular phone service, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device can monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any health monitoring-related functions. Other wearable devices such as devices worn around the neck, devices implantable in the human body, glasses designed to provide an augmented and / or virtual reality experience, etc. are similarly contemplated.

[0092] System 700 may be further used as part of a cloud-based service(s) 770. For example, the aforementioned device and / or other devices may access computing resources within the cloud (i.e., remotely located hardware and / or software resources). Further, System 700 may be utilized in one or more devices in a home other than those described above. For example, devices within a home can monitor and detect notable conditions. For example, various devices within a home (e.g., a refrigerator, a cooling system, etc.) can monitor the state of the device and issue a warning to the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat can monitor the temperature of a home and automate the adjustment of a heating / cooling system based on the homeowner's response history to various conditions. Also, FIG. 16 shows the application of System 700 to various modes of transportation. For example, System 700 may be used in control systems and / or entertainment systems of aircraft, trains, buses, rental vehicles, passenger cars, ships from private boats to cruise ships, scooters (rental or owned), etc. In various cases, System 700 can be used to provide automatic guidance (e.g., an autonomous vehicle), general system control, and other methods. Many other such embodiments are possible and contemplated. Note that the devices and uses shown in FIG. 16 are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated. ***

[0093] This disclosure includes references to a group of “one embodiment” or “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. A number of possible embodiments, including those specifically disclosed, as well as modifications or alternatives within the spirit or scope of this disclosure are contemplated.

[0094] The present disclosure can discuss potential advantages that can arise from the disclosed embodiments. All implementations of these embodiments will necessarily exhibit some or all of the potential advantages. Whether the advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, invalidates or reduces one or more of the disclosed advantages. Further, sub-optimal design implementation of a particular implementation (e.g., implementation technology or tool) may also invalidate or reduce the disclosed advantages. Even assuming skilled implementation, the realization of the advantages may still depend on other factors such as the environmental circumstances in which the implementation is deployed. For example, the input supplied to a particular implementation may prevent one or more of the problems addressed in the present disclosure from occurring on a particular occasion, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of the present disclosure, it is clearly intended that any potential advantages described herein should not be construed as limitations of the claims that must be met to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to designers having the benefit of the present disclosure. The fact that such advantages are permissively described (e.g., a particular advantage is described as "can occur") is not intended to convey doubt as to whether such advantages can actually be realized, but rather to recognize the technical reality that the realization of such advantages often depends on additional factors.

[0095] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single example is described for a particular feature in the disclosed embodiments, it is not intended to limit the scope of the claims made based on the present disclosure. The disclosed embodiments are intended to be illustrative rather than limiting in the absence of a contrary description in the present disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art who benefit from the present disclosure.

[0096] For example, the features of this application can be combined in any suitable manner. Accordingly, for any such combination of features, new claims can be formulated during the examination procedure of this application (or an application claiming priority to this application). In particular, referring to the appended claims, the features from the dependent claims can be combined, as appropriate, with the features of other dependent claims, including claims that depend on other independent claims. Similarly, the features from each independent claim can be combined as appropriate.

[0097] Accordingly, the appended dependent claims can be drafted such that each depends on a single other claim, but additional dependencies are also contemplated. Any combination of features in dependent claims consistent with the present disclosure is contemplated and can be claimed in this application or another application. In summary, the combinations are not limited to those specifically recited in the appended claims.

[0098] Claims drafted in one format or statutory type (e.g., apparatus) are also intended to support corresponding claims in another format or statutory type (e.g., method), as appropriate. ***

[0099] Since this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, as well as the provisions provided throughout this disclosure, publicly notify that they are used in how to interpret the claims made based on this disclosure.

[0100] References to singular items (i.e., nouns or noun phrases preceded by "a", "an", or "the") are intended to mean "one or more" unless specifically stated otherwise in context. Thus, references to "an item" in the claims do not exclude additional instances of the item without context. "A plurality of" items refers to a set of two or more items.

[0101] The term "may" is used herein in the sense of permission (i.e., having the possibility, being possible), not in the sense of obligation (i.e., not being mandatory).

[0102] The terms "comprising" and "including" and their forms are open-ended and mean "not limited to, but including".

[0103] When the term "or" is used in this disclosure with respect to a list of alternatives, it will generally be understood to be used in an inclusive sense unless specifically stated otherwise in context. Thus, the listing of "x or y" is equivalent to "x or y, or both", and thus includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes it clear that "or" is being used in an exclusive sense.

[0104] The enumeration of 「w, x, y, z, or any combination thereof」, or 「... at least one of w, x, y, and z」 is intended to cover all possibilities including single elements up to the total number of elements in the set. For example, in the case of the set [w, x, y, z], these expressions cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase 「... at least one of w, x, y, and z」 refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in the list of these elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0105] In the present disclosure, various 「labels」 may precede a noun or noun phrase. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., 「the first circuit」, 「the second circuit」, 「a particular circuit」, 「a given circuit」, etc.) refer to different examples of the feature. Further, when applied to a feature, the labels 「first」, 「second」, and 「third」 do not, unless otherwise specified, imply any type of order (e.g., spatial, temporal, logical, etc.).

[0106] As used herein, the phrase "based on" is used to describe one or more factors that affect a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "determine A based on B". This phrase identifies that B is a factor used to determine A or that affects the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0107] The phrases "in response to" and "responsive to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either together with the specified factor or independently of the specified factor. That is, the effect may be in response only to these factors or in response to the specified factors and other unspecified factors. Consider the phrase "perform A in response to B". This phrase identifies that B is a factor that triggers the performance of A or a particular result for A. This phrase does not exclude the possibility that the performance of A may also be in response to some other factor, such as C. This phrase also does not exclude the possibility that performing A may be in response to both B and C. This phrase is intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "responsive to" is synonymous with the phrase "at least partially responsive to". Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to". ***

[0108] Within this disclosure, various physical entities (which may be variously referred to as "units", "circuits", other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This expression of an [entity] "configured" to [perform one or more tasks] is used herein to refer to a structure (i.e., something physical). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be described as being "configured" to perform some task even if the structure is not currently operating. Thus, an entity described or characterized as being "configured" to perform some task refers to something physical such as a device, a circuit, a processor unit, and a memory storing program instructions executable to perform the task. This phrase is not used herein to refer to something intangible.

[0109] In some cases, various units / circuits / components can be described herein as performing a set of tasks or operations. Even if not specifically described, it is understood that those entities are "configured" to perform those tasks / operations.

[0110] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0111] For purposes of a U.S. patent application based on this disclosure, reciting in a claim that a structure is "configured" to perform one or more tasks is not expressly intended to invoke 35 U.S.C. § 112(f) with respect to that claim element. If Applicant desires to invoke 35 U.S.C. § 112(f) during the examination of a U.S. patent application based on this disclosure, that will involve describing the claim element using "means for" performing the function.

[0112] This disclosure may describe various "circuits." These circuits or "circuit configurations" comprise hardware including various types of circuit elements such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memories, embedded dynamic random access memories), programmable logic arrays, etc. The circuits may be custom designed or obtained from standard libraries. In various implementations, the circuit configuration can include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as "units" (e.g., decoder units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units also refer to a circuit or circuit configuration.

[0113] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the foregoing paragraphs. In many cases, the internal arrangement of the hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decoder unit" can be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," which means that the decoder unit is "configured" to perform this function. This functional specification is sufficient to imply to one of ordinary skill in the computer art a set of possible structures for the circuit.

[0114] In various embodiments, as discussed in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to perform. The arrangement of such circuits / units / components relative to each other and the way they interact ultimately generates a microarchitecture specification of the hardware that is either manufactured within an integrated circuit or programmed into an FPGA, forming a physical implementation form of the microarchitecture specification. Thus, the microarchitecture specification is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of those implementation forms belong to a broader structure described by the microarchitecture specification. That is, one skilled in the art presented with the microarchitecture specification provided according to the present disclosure can implement the structure by coding the description of the circuits / units / components into a hardware description language (HDL) such as Verilog or VHDL using ordinary techniques without undue experimentation. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the way used to convert the structure of a circuit, unit, or component to the next level of implementation detail. Such HDL descriptions can take the form of behavioral code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable in contrast to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology, modified for timing, power, and other reasons, and result in a final design database that can be sent to a foundry to generate masks and ultimately manufacture an integrated circuit. Some hardware circuits or parts thereof can also be custom designed with a circuit diagram editor and incorporated into the integrated circuit design along with the synthesized circuits. The integrated circuit can further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements.Some embodiments can implement a plurality of integrated circuits integrally connected to realize a hardware circuit, and / or, in some embodiments, individual elements can be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), or implemented on an FPGA. This separation between the design of this circuit group and the subsequent low-level implementation of these circuits generally results in a scenario where the circuit or logic designer does not specify any particular set of structures for the low-level implementation form, other than an explanation of how the circuit is configured, since this process is performed at different stages of the circuit implementation process.

[0115] The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a number of equivalent structures for that circuit. As described above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. In many cases, the selection made by different design tools or methods for generating these different implementation forms can be arbitrary.

[0116] Furthermore, for a given embodiment, it is common for a single implementation form of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors). Therefore, due to this absolute amount of information, it goes without saying that there is an enormous amount of equivalent possible implementation forms, and it is unrealistic to fully enumerate the low-level structures used to implement a single embodiment. For this reason, the present disclosure uses functional omissions used in the industry to describe the structure of the circuit.

[0117] The description of the subject matter of this application includes, but is not limited to, the following examples. Example of a method: 1. A method comprising: Receiving a first dataset regarding an overall instance of an integrated circuit design, the first dataset defining the overall instance for manufacturing the overall instance, the overall instance including a first plurality of circuit components physically located in a first sub-region of an area occupied by the overall instance on a semiconductor substrate and a second plurality of circuit components physically located in a second sub-region of the area occupied by the overall instance on the semiconductor substrate, Receiving a second dataset regarding a partial instance of an integrated circuit design, the second dataset defining the partial instance for manufacturing the partial instance, the partial instance including the first plurality of circuit components within the first sub-region, the relative positions of the first plurality of circuit components within the first sub-region and the interconnects of the first plurality of circuit components within the first sub-region not changing between the overall instance and the partial instance, the partial instance further including a stub region adjacent to the first sub-region, the stub region including the ends of wires that would otherwise interconnect components within the first and second sub-regions, ensuring the correct operation of the first plurality of circuit components within the first sub-region in the absence of the second sub-region in the partial instance, Manufacturing a first plurality of overall instances of the integrated circuit based on the first dataset, Manufacturing a second plurality of partial instances of the integrated circuit based on the second dataset, a method comprising. 2. The method according to Example 1, wherein the stub region excludes circuit configurations. 3. The method according to Example 2, wherein the stub region includes only wiring in one or more metallization layers above the surface region of the semiconductor substrate. 4. The method according to Example 1, wherein the other plurality of circuit components within the second sub-region include a plurality of outputs that are a plurality of inputs to the first plurality of circuit components within the first sub-region, the first plurality of circuit components including a plurality of multiplexer circuits having each of the plurality of inputs as an input, and the stub region further including a plurality of selection signals for the plurality of multiplexer circuits. 5. The method according to embodiment 4, wherein a plurality of selection signals are binary values that select inputs of a plurality of multiplexer circuits different from an input to which a plurality of inputs are connected, and are terminated within a stub region. 6. The method according to embodiment 5, wherein a plurality of selection signals are binary values different in an overall instance and are terminated within a second sub-region. 7. The first data set includes a plurality of exclusion zones at respective corners of a semiconductor substrate, circuit components are excluded from the plurality of exclusion zones according to mechanical requirements of a manufacturing process used to manufacture an integrated circuit, the first data set includes additional exclusion zones at corners of a first sub-region adjacent to a second sub-region, whereby a partial instance includes exclusion zones at respective corners of a semiconductor substrate on which the partial instance is formed, the method according to embodiment 1. 8. The first data set further includes a second exclusion zone along an edge of a first sub-region adjacent to a second sub-region, and a control collapse chip connection (C4) connection is excluded from the second exclusion zone, the method according to embodiment 1. 9. The first data set further includes one or more first analog inputs for distributing a clock within a first sub-region, the one or more first analog inputs remain within the first sub-region, the first data set further includes one or more second analog inputs for distributing a clock within a second sub-region, and the one or more second analog inputs remain within the second sub-region, the method according to embodiment 1. 10. The first data set further includes one or more first clock trees for distributing a clock within a first sub-region and one or more second clock trees for distributing a clock within a second sub-region, and in an overall instance, the one or more first clock trees are electrically isolated from the one or more second clock trees, the method according to embodiment 1. Example of an integrated circuit: 11. An integrated circuit, A plurality of circuit components physically disposed on a surface of a semiconductor substrate forming an integrated circuit, including a plurality of multiplexer circuits, wherein a given multiplexer circuit of the plurality of multiplexer circuits has a first input wire, a second input wire, and a selection control wire, the plurality of circuit components; A region along a single edge of the surface, wherein the region is a power source for the selection control wire, wherein the second input wire reaches a single edge of the surface and is unconnected, wherein the selection control wire is electrically connected to a supply wire of the integrated circuit, and a voltage on the supply wire in use corresponds to a digital logic level that causes the plurality of multiplexer circuits to select the first input wire as an output of the plurality of multiplexer circuits, the region; An integrated circuit comprising. 12. An integrated circuit, A first plurality of circuit components physically disposed within a first region of a surface of a semiconductor substrate forming the integrated circuit; A plurality of exclusion zones at respective corners of the semiconductor substrate, wherein the circuit components are excluded from the plurality of exclusion zones according to mechanical requirements of a manufacturing process used to manufacture the integrated circuit, the plurality of exclusion zones; Another plurality of exclusion zones separated from respective corners and along a pair of nominally parallel edges of the semiconductor substrate, wherein the circuit components are excluded from the other plurality of exclusion zones and the other plurality of exclusion zones are substantially the same dimensions as the plurality of exclusion zones, the other plurality of exclusion zones; An integrated circuit comprising. 13. The integrated circuit according to embodiment 12, further comprising a second exclusion zone along a line between the plurality of exclusion zones, wherein a controlled collapse chip connection (C4) connection is excluded from the second exclusion zone. 14. One or more first analog inputs within a first sub-region of the first region, remaining within the first sub-region, the one or more first analog inputs; One or more second analog inputs within a second sub-region of a first region adjacent to the first sub-region, the one or more second analog inputs remaining within the second sub-region, and the integrated circuit according to Example 12 further comprising. 15. One or more clock trees for distributing a clock within a first sub-region of the first region, One or more second clock trees for distributing a clock within the second sub-region, and the integrated circuit according to Example 12 further comprising, The integrated circuit according to Example 12, wherein one or more of the first clock trees are electrically isolated from one or more of the second clock trees. 16. An integrated circuit, A first plurality of circuit components physically disposed within a first region of the surface of a semiconductor substrate forming the integrated circuit, A second plurality of circuit components physically disposed within a second region of the surface of a semiconductor substrate forming the integrated circuit, One or more first analog inputs within the first region, the one or more first analog inputs being separated from the first plurality of circuit components, One or more second analog inputs within the second region, the one or more second analog inputs being separated from the second plurality of circuit components, An integrated circuit comprising.

[0118] Many variations and modifications will become apparent to those skilled in the art if the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. 1. A method comprising: defining, in a design database corresponding to an integrated circuit design, an area that will be occupied by the integrated circuit design when manufactured on a semiconductor substrate; defining a shear line dividing the region into a first subregion and a second subregion, the combination of the first subregion and the second subregion representing a full instance of the integrated circuit, and the first subregion and a stub region representing a partial instance of the integrated circuit including fewer circuit components than the full instance; representing in the design database physical locations of a plurality of circuit components included in both the full instance and the partial instance of the integrated circuit within the first sub-region, wherein relative locations of the plurality of circuit components within the first sub-region and interconnects of the plurality of circuit components within the first sub-region do not change between the full instance and the partial instance; representing in the design database the physical locations of a number of other circuit components included in the overall instance but excluded from the partial instance of the second sub-region; defining in the design database in the stub region terminations of wires that would otherwise cross the shear line between the first and second subregions to ensure correct operation of the plurality of circuit components in the first subregion in the absence of the second subregion in the partial instance; creating a first data set for the overall instance using the first sub-region and the second sub-region, the first data set defining the overall instance for manufacturing the overall instance; creating a second data set for the partial instance using the first sub-region and the stub region, the second data set defining the partial instance for manufacturing of the partial instance.

2. The method of claim 1 , wherein the stub region excludes circuitry.

3. The method of claim 2 , wherein the stub region includes only wiring in one or more metallization layers above a surface region of the semiconductor substrate.

4. 2. The method of claim 1 , wherein the other circuit components in the second sub-region include a plurality of outputs that are a plurality of inputs to the circuit components in the first sub-region, the plurality of circuit components including a plurality of multiplexer circuits having respective ones of the plurality of inputs as inputs, the method further comprising: representing a plurality of select signals for the plurality of multiplexer circuits in the stub region.

5. 5. The method of claim 4, wherein the select signals are terminated within the stub region with binary values ​​that select inputs of the multiplexer circuits that are different from the inputs to which the inputs are connected.

6. The method of claim 5 , wherein the plurality of select signals are terminated within the second sub-region at different binary values ​​in the global instance.

7. The method comprises: defining a plurality of exclusion zones at respective corners of the semiconductor substrate, the plurality of exclusion zones from which circuit components are excluded in accordance with mechanical requirements of a manufacturing process used to produce the integrated circuit; 10. The method of claim 1, further comprising: defining additional exclusion zones at corners of the first subregion adjacent the shear line, whereby the partial instance includes an exclusion zone at each corner of the semiconductor substrate on which the partial instance is formed.

8. The method comprises:

2. The method of claim 1, further comprising defining a second exclusion zone along an edge of the first sub-region adjacent to the second sub-region, wherein controlled collapse chip connection (C4) connections are excluded from the second exclusion zone.

9. The method comprises: defining one or more first analog inputs within the first sub-region; defining one or more second analog inputs within the second sub-region; The method of claim 1 , wherein the first one or more analog inputs remain within the first sub-region and the second one or more analog inputs remain within the second sub-region.

10. The method comprises: defining one or more first clock trees in the first sub-region to distribute clocks within the first sub-region; defining one or more second clock trees in the second sub-region to distribute clocks within the second sub-region; 2. The method of claim 1, wherein in the global instance, the one or more first clock trees are electrically isolated from the one or more second clock trees.

11. The method comprises: defining a second shear line in the second subregion to divide the second subregion into a third subregion and a fourth subregion, the third subregion being adjacent to the first subregion, the third subregion and the first subregion representing a second partial instance of the integrated circuit; 2. The method of claim 1, further comprising: creating a third data set for the second part instance using the first sub-region, the third sub-region, and a second stub region, the third data set defining the second part instance for manufacturing the second part instance.

12. The method comprises: defining a test bench environment for the integrated circuit; the test bench environment implicitly includes the plurality of circuit components included in both the entire instance and the partial instance of the integrated circuit; the test bench environment conditionally includes the other plurality of circuit components included in the overall instance but excluded from the partial instance based on the overall instance being tested; the test bench environment conditionally includes the stub region based on the partial instance being tested; the test bench environment unconditionally includes first test stimuli for the plurality of circuit components included in both the entire instance and the partial instance of the integrated circuit; 2. The method of claim 1, wherein the test bench environment includes second test stimuli for the other plurality of circuit components included in the overall instance but excluded from the partial instance based on which the overall instance is being tested.

13. The method comprises: Detecting required changes to the integrated circuit during validation of the integrated circuit design; implementing the required changes in the design database for the entire instance; and The method of claim 1 , further comprising: extracting the design database for the partial instance from the design database for the partial instance.

14. 1. An integrated circuit comprising: a plurality of circuit components physically disposed on a surface of a semiconductor substrate forming the integrated circuit; a plurality of wire terminations along a single edge of said surface, said wire terminations being electrically connected to a plurality of supply wires of said integrated circuit to provide fixed digital logic levels on wires that are inputs to one or more of said plurality of circuit components, said wire terminations being oriented across said single edge and devoid of circuitry configured to drive said wires, such that an area along said single edge including said plurality of wire terminations excludes active circuit elements; 1. An integrated circuit comprising:

15. a plurality of said circuit components including a plurality of multiplexer circuits; a given multiplexer circuit of the plurality of multiplexer circuits has a first input wire, a second input wire, and a selection control wire; the area along the single edge is a source of the select control wire; the second input wire reaches the single edge of the surface and is unconnected; the select control wire is electrically connected to a supply wire of the integrated circuit, a voltage on the supply wire in use corresponding to a digital logic level that causes the plurality of multiplexer circuits to select the first input wire as an output of the plurality of multiplexer circuits; 15. The integrated circuit of claim 14.

16. 15. The integrated circuit of claim 14, wherein the region along the single edge includes only wiring in one or more metallization layers above a surface region of the semiconductor substrate.

17. a first one of the plurality of circuit components being physically disposed within a first sub-region of the surface of the semiconductor substrate; The integrated circuit comprises: a plurality of exclusion zones at respective corners of the semiconductor substrate, the plurality of exclusion zones from which circuit components are excluded in accordance with mechanical requirements of a manufacturing process used to produce the integrated circuit; a plurality of other exclusion zones at the corners of the first sub-region separated from the respective corners and along a pair of nominally parallel edges of the semiconductor substrate, the other plurality of exclusion zones excluding circuit components, the other plurality of exclusion zones being substantially the same dimensions as the other plurality of exclusion zones; 15. The integrated circuit of claim 14 comprising:

18. and a second exclusion zone along a line between the plurality of exclusion zones, the second exclusion zone excluding a controlled collapse chip connection (C4) connection.

20. The integrated circuit of claim 17.

19. one or more first analog inputs in the first sub-region, the one or more first analog inputs remaining within the first sub-region; one or more second analog inputs in a second sub-region adjacent to the first sub-region, the one or more second analog inputs remaining within the second sub-region; The integrated circuit of claim 17 further comprising:

20. one or more first clock trees for distributing a clock within the first sub-domain; one or more second clock trees for distributing a clock within a second sub-region adjacent to the first sub-region; the one or more first clock trees being electrically isolated from the one or more second clock trees; 20. The integrated circuit of claim 17.

21. 1. A method comprising: receiving a first data set relating to an overall instance of an integrated circuit design, the first data set defining the overall instance for manufacturing the overall instance, the overall instance including a first plurality of circuit components physically located in a first sub-area of ​​an area occupied by the overall instance on a semiconductor substrate, and a second plurality of circuit components physically located in a second sub-area of ​​the area occupied by the overall instance on the semiconductor substrate; receiving a second data set for a partial instance of the integrated circuit design, the second data set defining the partial instance for manufacturing the partial instance, the partial instance including the first plurality of circuit components within the first sub-region, a relative position of the first plurality of circuit components within the first sub-region and an interconnect of the first plurality of circuit components within the first sub-region remaining unchanged in the full instance and in the partial instance, the partial instance further including a stub region adjacent to the first sub-region, the stub region including an termination of a wire that would otherwise interconnect components in the first and second sub-regions to ensure correct operation of the first plurality of circuit components in the first sub-region in the absence of the second sub-region in the partial instance; fabricating a first plurality of said entire instances of said integrated circuit based on said first data set; and fabricating a second plurality of the partial instances of the integrated circuit based on the second data set.

22. The method of claim 21 , wherein the stub region excludes circuitry.

23. 23. The method of claim 22, wherein the stub region includes only wiring in one or more metallization layers above a surface region of the semiconductor substrate.

24. 22. The method of claim 21 , wherein other circuit components in the second sub-region include a plurality of outputs that are a plurality of inputs to the first plurality of circuit components in the first sub-region, the first plurality of circuit components including a plurality of multiplexer circuits having respective ones of the plurality of inputs as inputs, and the stub region further includes a plurality of select signals for the plurality of multiplexer circuits.

25. 25. The method of claim 24, wherein the select signals are terminated within the stub region with binary values ​​that select inputs of the multiplexer circuits that are different from the inputs to which the inputs are connected.

26. 26. The method of claim 25, wherein the plurality of select signals are terminated within the second sub-region at different binary values ​​in the global instance.

27. 22. The method of claim 21 , wherein the first data set includes a plurality of exclusion zones at respective corners of the semiconductor substrate, circuit components being excluded from the plurality of exclusion zones according to mechanical requirements of a manufacturing process used to produce the integrated circuit, and the first data set includes additional exclusion zones at corners of the first subregion adjacent to the second subregion, whereby the partial instance includes an exclusion zone at each corner of the semiconductor substrate on which the partial instance is formed.

28. 22. The method of claim 21 , wherein the first data set further includes a second exclusion zone along an edge of the first sub-region adjacent to the second sub-region, the second exclusion zone excluding controlled collapse chip connection (C4) connections.

29. 22. The method of claim 21, wherein the first data set further includes one or more first analog inputs in the first sub-region, the one or more first analog inputs remaining within the first sub-region, and the first data set further includes one or more second analog inputs in the second sub-region, the one or more second analog inputs remaining within the second sub-region.

30. 22. The method of claim 21, wherein the first data set further comprises one or more first clock trees for distributing a clock in the first sub-region and one or more second clock trees for distributing a clock in the second sub-region, and wherein in the global instance, the one or more first clock trees are electrically isolated from the one or more second clock trees.

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