Semiconductor device

Abstract

To provide a semiconductor device suitable for miniaturization with high reliability.SOLUTION: A semiconductor device includes transistors 100 and 130, and a capacitor element 150. The transistor 100 includes a semiconductor layer 101. The semiconductor layer 101 exists over the capacitor element 150. The capacitor element 150 includes a plug 121 functioning as a first electrode electrically connected to the transistor 100.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. Note that, in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a computing device, a memory device, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

[0002]

Background Art

[0003]

[0004]

[0005]

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] One aspect of the present invention is to provide a semiconductor device suitable for miniaturization as one of the problems. Also is to provide a semiconductor device with a reduced circuit area as one of the problems.

[0008] Or, to provide a highly reliable semiconductor device as one of the problems. Or, to impart good electrical characteristics to the semiconductor device as one of the problems. Or, to provide a semiconductor device having a memory element with good holding characteristics as one of the problems. Or, to provide a semiconductor device with a novel configuration as one of the problems. device. Or, to provide a semiconductor device having a memory element with good holding characteristics as one of the problems. Or, to provide a semiconductor device with a novel configuration as one of the problems. device. Or, to provide a semiconductor device with a novel configuration as one of the problems. device as one of the problems.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. problems will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention has a capacitor element and a first transistor, and the first transistor has a first semiconductor layer, the first semiconductor layer is located above the capacitive element, and the capacitive element is the first semiconductor device having a first electrode electrically connected to the transistor. Also, in the above configuration , the capacitive element has a conductive layer of m layers (m is a natural number of 3 or more) and n layers (n is a natural number) of insulating films, the first insulating film is sandwiched between the first conductive layer and the second conductive layer, and the second insulating film is sandwiched between the second conductive layer and the third conductive layer, and it is preferable that the first conductive layer and the third conductive layer are electrically connected .

[0011] Alternatively, one aspect of the present invention includes a capacitive element, a first transistor, and a second transistor , the first transistor has a first semiconductor layer, the capacitive element has an insulating film of n layers (n is a natural number ), and a conductive layer of k layers (k is a natural number of 2 or more), and each of the insulating films of the n layers is sandwiched between at least two conductive layers, the first transistor is located above the second transistor , the first semiconductor layer is located above the capacitive element, and the insulating film of n layers ( n is a natural number) of the capacitive element is located between the first transistor and the second transistor, and the capacitive element is a semiconductor device having a first electrode connected to either the source or the drain of the first transistor .

[0012] Also, in the above configuration, it is preferable that the insulating film of n layers has a function of blocking at least one of hydrogen, water, and oxygen. Also, in the above configuration, the insulating film of n layers preferably contains at least one of silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride.

[0013] In the above configuration, it is preferable that the capacitive element overlaps with the first transistor.

[0014] In the above configuration, the first transistor is provided with a first opening in the first semiconductor layer. It is preferable that the first electrode is in contact with the first opening.

[0015] In the above configuration, the first transistor has a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer are in contact with the first semiconductor layer. An opening is provided in the first semiconductor layer and the first conductive layer that the first transistor has. The first electrode is preferably in contact with the opening provided in the first semiconductor layer and the first conductive layer.

Advantages of the Invention

[0016] According to one aspect of the present invention, a semiconductor device suitable for miniaturization can be provided. In addition, a semiconductor device with a reduced circuit area can be provided.

[0017] In addition, a highly reliable semiconductor device can be provided. In addition, good electrical characteristics can be imparted to the semiconductor device. In addition, a semiconductor device having a memory element with good holding characteristics can be provided. In addition, a semiconductor device with a novel configuration can be provided.

[0018] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be obvious from the description in the specification, drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0019]

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Mode for Carrying Out the Invention

[0020] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and various changes can be made to its form and details without departing from the spirit and scope of the present invention. This will be easily understood by those skilled in the art. Therefore, the present invention is not to be construed as limited to the description of the embodiments

[0021] described below. In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof

[0022] is omitted. Also, when referring to the same function, the hatching pattern may be the same, and there may be cases where no reference numerals are particularly assigned.

[0023] In each drawing described in this specification, the size of each component, the thickness of the layer, or the region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0024] ​Even if a material is described as a "semiconductor," it may be considered an "insulator" if, for example, its electrical conductivity is sufficiently low. In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. In some cases, the distinction cannot be made precisely. Therefore, the term "semiconductor" as used herein means "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." In some cases, this can be rephrased as "body."

[0025] In addition, even if a material is written as a "semiconductor," if the material has a sufficiently high electrical conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and not strictly defined. In some cases, the distinction may not be clear. Therefore, the term "semiconductor" as used herein means "conductor" or "electroconductor". Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor In some cases, this can be rephrased as "body."

[0026] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0027] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. refers to a state. Therefore, it also includes the case where the angle is 85° or more and 95° or less. Also, "substantially perpendicular" refers to a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

[0028] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. is.

[0029] (Embodiment 1) [Configuration example of the stacked structure] Hereinafter, an example of a stacked structure applicable to a semiconductor device according to one aspect of the present invention will be described with reference to FIG. 1. is used.

[0030] The stacked structure shown in FIG. 1(A) has a transistor 100 and a capacitor element 150. The transistor 100 is located above the capacitor element 150. Also, the capacitor element 150 is electrically connected to the transistor 100.

[0031] In addition, the semiconductor layer 101 of the transistor 100 may have a low-resistance region 171a and a low-resistance region 171b. The low-resistance region 171a and the low-resistance region 171b preferably function as a source region or a drain region. Also, the low-resistance region 171a and the low-resistance region 171b may be doped with impurities. By adding impurities, the resistance of the semiconductor layer 101 can be reduced. Examples of the impurities to be added include argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, selected from one or more of them. It is preferably added on top. The low-resistance regions 171a and 171b are, for example, in the semiconductor layer 101, and the above-described impurity element is 5×10 19 atoms / cm 3 or more, preferably or 1×10 20 atoms / cm 3 or more, more preferably 2×10 20 atoms / cm 3 or more, still more preferably 5×10 20 atoms / cm 3 or more, and is a region containing the above.

[0032] Also, the laminated structure shown in FIG. 1(A) may have a transistor 130. Also, it is preferable to have a barrier film 111 between the transistor 100 and the transistor 130. The capacitor element 150 has a conductive layer 151 and a conductive layer 152, and has a structure in which the barrier film 111 is sandwiched between the conductive layer 151 and the conductive layer 152. Here, FIG. 1(B) shows a cross-section taken along the dashed-dotted line A-B shown in FIG. 1(A). Here, the cross-section taken along the dashed-dotted line A-B is, for example, a cross-section approximately perpendicular to the cross-section shown in FIG. 1(A) passing through the dashed-dotted line A-B. Note that there are some portions where reference signs are omitted in FIG. 1(B), but for the portions shown using the same hatching as in FIG. 1(A), for example, reference may be made to FIG. 1(A).

[0033] The transistor 130 is configured to include a first semiconductor material. Also, the transistor 100 is configured to include a second semiconductor material. The first semiconductor material and the second semiconductor material may be the same material, but it is preferable to use different semiconductor materials.

[0034]

[0035] ​​​​​​​Semiconductors that can be used as the first semiconductor material or the second semiconductor material include , for example, semiconductor materials such as silicon, germanium, gallium, and arsenic, silicon and germ nium, gallium, arsenic, aluminum, and other compound semiconductor materials, organic semiconductor materials , or oxide semiconductor materials and the like.

[0036] Here, the case where single-crystal silicon is used as the first semiconductor material and an oxide semiconductor is used as the second semiconductor material will be described.

[0037] The transistor 100 has a semiconductor layer 101 formed of a second semiconductor material, a gate insulating film 1 02, a gate electrode 103, plugs 121 and 122. Further, insulating films 11 2 and 113 are formed so as to cover the transistor 100. The plug 12 1 is in contact with openings provided in the insulating film 113, the insulating film 112, and the semiconductor layer 101, and is connected to the capacitor element 150. That is, the plug 121 is formed so as to penetrate the insulating film 113, the insulating film 112 and the semiconductor layer 101.

[0038] The barrier film 111 is a layer having a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer . Further, the barrier film 111 preferably has low oxygen permeability. Further, the barrier film 111 may have openings or plugs for electrically connecting an electrode or wiring provided above this and an electrode or wiring provided below. For example, as shown in FIG. 1 , it has a plug for electrically connecting the plug 121 and the conductive layer 151. Here, suppressing the diffusion of water and hydrogen means, for example, generally silicon oxide used as an insulating film It indicates that water and hydrogen are difficult to diffuse or have low permeability as compared with, etc. Further, oxygen Low permeability means that the oxygen has low permeability as compared with silicon oxide or the like generally used as an insulating film.

[0039] Similar to the barrier film 111, it is preferable to use a material in which water and hydrogen are difficult to diffuse for the insulating film 112. In particular, it is preferable to use a material in which oxygen is difficult to permeate as the insulating film 112. Note that the insulating film 112 may have a laminated structure of two or more layers. In that case, for example, the insulating film 112 has a two-layer laminated structure, and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used for the lower layer. Further, for the upper layer, it is preferable to use a material in which water and hydrogen are difficult to diffuse, similar to the barrier film 111. Also, the insulating film provided in the lower layer may be configured to supply oxygen from above the semiconductor layer 101 via the gate insulating film 102 as an insulating film in which oxygen is desorbed by heating, similar to the insulating film 114. By covering the semiconductor layer 101 with the insulating film 112 containing a material in which oxygen is difficult to permeate, it is possible to suppress oxygen from being released above the insulating film 112 from the semiconductor layer 101. Further, since the oxygen desorbed from the insulating film 114 can be confined below the insulating film 112, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0040]

[0041] Further, the insulating film 112 in which water and hydrogen are difficult to permeate can suppress the mixing of water and hydrogen, which are impurities for the oxide semiconductor, from the outside, and can suppress fluctuations in the electrical characteristics of the transistor 100. ​​​​​​​​​​This suppresses the generation of the dielectric constant, thereby achieving a highly reliable transistor.

[0042] In addition, below the insulating film 112, there is a layer in which oxygen is desorbed by heating, similar to the insulating film 114. An insulating film is provided, and oxygen is supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102. This may also be configured.

[0043] In addition, the capacitor 150 is preferably formed so as to overlap with the transistor 100. By increasing the overlapping area between the capacitor 150 and the transistor 100, The area of ​​the device can be reduced.

[0044] The semiconductor device shown in FIG. 1 has an insulating film 114 between a transistor 100 and a capacitor element 150. The insulating film 114 preferably contains an oxide. Preferably, the oxide material is a material that separates the oxide from the stoichiometric composition. It is preferable to use an oxide that contains a large amount of oxygen. In the case where the insulating film 114 is used, oxygen released from the insulating film 114 is supplied to the oxide semiconductor. As a result, the electrical characteristics of the second transistor can be improved. Fluctuations can be suppressed and reliability can be improved.

[0045] Here, hydrogen, water, etc. should be reduced as much as possible below the barrier film 111. It is preferable to suppress the desorption of gas. Hydrogen and water are absorbed in the oxide semiconductor. This may cause a change in the electrical characteristics of the lower layer through the barrier film 111. The diffusion of hydrogen and water from the barrier layer to the upper layer can be suppressed by the barrier film 111. Hydrogen and water may diffuse to the upper layer through openings or plugs provided in the film 111. do.

[0046] In order to reduce hydrogen and water contained in each layer located below the barrier film 111, In order to suppress the desorption of gas, the barrier film 111 is formed before the barrier film 111 is formed or the barrier film 111 is introduced thereto. Immediately after forming an opening for forming a conductive layer, etc., the water contained in the layer below the barrier film 111 is removed. It is preferable to carry out a heat treatment to remove oxygen and water or to suppress desorption of gas. The heat resistance of conductive films constituting a semiconductor device and the electrical characteristics of transistors do not deteriorate. The higher the temperature of the heat treatment, the more preferable it is. The temperature is preferably 490°C or higher, more preferably 530°C or higher, but is preferably 650°C or higher. It may be carried out for 1 hour or more under an inert gas atmosphere or a reduced pressure atmosphere, preferably It is preferable to carry out the heat treatment for 5 hours or more, more preferably 10 hours or more. The thickness can be determined by taking into consideration the heat resistance of the wiring or electrode material located below 11. For example, if the material has low heat resistance, the temperature should be 550°C or less, 600°C or less, or 6 The temperature may be 50°C or less, or 800°C or less. It is sufficient to carry out the treatment at least once, but it is more preferable to carry out the treatment multiple times.

[0047] The insulating film provided below the barrier film 111 is analyzed by thermal desorption spectroscopy (TDS analysis). The amount of hydrogen molecules desorbed at a substrate surface temperature of 400°C, as measured by the At 0° C., the amount of hydrogen molecules released is preferably 130% or less, more preferably 110% or less. Alternatively, TDS analysis showed that the amount of desorbed hydrogen molecules at a substrate surface temperature of 450°C was 350 It is preferable that the amount of desorption is 130% or less, and preferably 110% or less, of the amount of desorption at .degree.

[0048] In addition, it is preferable that the water and hydrogen contained in the barrier film 111 itself be reduced. For example, the barrier film 111 may be a TDS-type film. The hydrogen molecule (M / z=2) was analyzed by the deposition in the substrate surface temperature range of 20°C to 600°C. The amount of desorption is 2×10 15 pieces / cm 2 Less than 1 x 10 15 pieces / cm 2 Less than, More than Preferably 5 x 10 14 pieces / cm 2 It is preferable to use a material for the barrier film 111 that has a resistance of less than 1000 MPa. Alternatively, TDS analysis shows that the water vapor deposition rate is 100% in the range of 20℃ to 600℃. The amount of desorption of the molecule (M / z=18) is 1×10 16 pieces / cm 2 Less than 5 x 10 1 5 pieces / cm 2 less than 2×10 12 pieces / cm 2 Barrier film material that is less than 1 It is preferable to use 11.

[0049] In addition, when single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment The process is to terminate the dangling bonds of silicon with hydrogen. The hydrogenation process can also be used to remove the impurities from the transistor 13. Water contained in the gate insulating film of 0 or other insulating films formed below the barrier film 111 Some of the elements are detached and diffuse into the semiconductor layer of the first transistor, forming dangling By terminating the bond, the reliability of the first transistor can be improved.

[0050] Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide m, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate lontium (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST), etc. A so-called h igh-k material-containing insulating film can be used in a single layer or in a laminate. Or these insulators For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide con, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, gallium oxide rium may be added. Or these insulating films may be nitrided to form an oxynitride film. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulating film and used. In particular, aluminum oxide is preferable because of its excellent barrier properties against water and hydrogen.

[0051] In addition to the layer of a material that is difficult to permeate water and hydrogen, the barrier film 111 may be used by laminating layers containing other insulating materials. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing a metal oxide, etc. may be laminated and used.

[0052] Also, it is preferable to use a material that is difficult to permeate oxygen for the barrier film 111. The materials described above are materials that are excellent in barrier properties against hydrogen, water, and also oxygen. By using such materials it is possible to suppress the diffusion of oxygen released when the insulating film 114 is heated to a layer below the barrier film 111. As a result, the oxygen released from the insulating film 114 and the transistor ​This can increase the amount of oxygen that can be supplied to the semiconductor layer of the transistor 100.

[0053] In this way, the concentration of hydrogen and water contained in each layer located below the barrier film 111 is reduced. The barrier film 111 is formed on the surface of the substrate 110 so as to reduce the amount of hydrogen and water emitted, or to suppress the amount of desorbed gas. This prevents hydrogen and water from diffusing into the transistor 100. The hydrogen and water contents in each layer constituting the transistor 100 are extremely low. For example, the insulating film 114, the semiconductor layer 101 of the transistor 100, is the hydrogen concentration in the gate insulating film 102 of 5×10 18 cm -3 Less than 1x, preferably 10 18 cm -3 less than 3×10 17 cm -3 To reduce to less than can be done.

[0054] With the above configuration, both the first transistor and the second transistor have high It is therefore possible to achieve both high reliability and high reliability, thereby achieving a highly reliable semiconductor device.

[0055] The conductive layer 152 may be disposed so as to overlap the channel region of the transistor 100. Examples of this case are shown in Fig. 34(A) and Fig. 34(B). Fig. 34(B) shows the same as Fig. 3 4(A) is a cross section taken along dashed line AB. For example, the gate electrode may have the following function: By supplying a constant potential, the threshold voltage of the transistor 100 can be controlled. Yes, it is possible.

[0056] Further, an example of a stacked structure applicable to the semiconductor device according to one aspect of the present invention is shown in FIGS. 2, 3, 4(A), and 4(B). As shown in FIG. 2, the capacitor element 150 may be formed by stacking three or more conductive layers. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected via the plug 121, the plug 126, and the plug 127, and form one electrode of the capacitor element 150. Also, although not shown, the conductive layer 152, the conductive layer 154a, and the conductive layer 154c are electrically connected to form the other electrode of the capacitor element 150.

[0057] Further, as shown in FIG. 3, conductive layers may be formed on both sides of the plug 126 and the plug 127. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected via the plug 121, the plug 126, and the plug 127, and form one electrode of the capacitor element 150. Also, although not shown, the conductive layer 152, the conductive layer 152b, the conductive layer 154a, the conductive layer 154 b, the conductive layer 154c, and the conductive layer 154d are electrically connected to form the other electrode of the capacitor element 150.

[0058] Also, as shown in FIG. 4(A), the transistor 100 may have a conductive layer 104a and a conductive layer 104b in contact with the semiconductor layer 101. Note that FIG. 4(B) is a cross-section taken along the dashed line A - B shown in FIG. 4(A). The conductive layer 104a and the conductive layer 104b function as a source electrode or a drain electrode. Further, the transistor 100 may have a conductive layer 105. The conductive layer 105 may function as a second gate of the transistor 100. A voltage lower or higher than the source electrode is applied to the conductive layer 105 to ​​​​​​​The threshold voltage may be varied in the positive or negative direction. For example, by varying the threshold voltage of the transistor in the positive direction, it is possible to achieve normally-off even when the gate voltage is 0V, where the transistor is in a non-conductive state (off state). Note that the voltage applied to the conductive layer 105 may be variable or fixed. When making the voltage applied to the conductive layer 105 variable, a circuit for controlling the voltage may be connected to the conductive layer 105 .

[0059] Also, the conductive layer 105 may be connected to the gate electrode 103.

[0060] [Configuration Example] FIG. 5(A) is an example of a circuit diagram of a semiconductor device according to an aspect of the present invention. The semiconductor device shown in FIG. 5(A) includes a transistor 100, a transistor 130, a capacitive element 150, a wiring BL, a wiring WL, and a wiring CL.

[0061] One of the source or drain of the transistor 130 is electrically connected to the wiring BL, and the other is electrically connected to the wiring SL, and the gate is electrically connected to one of the source or drain of the transistor 100 and one electrode of the capacitive element 150. One of the source or drain of the transistor 100 is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL . The other electrode of the capacitive element 150 is electrically connected to the wiring CL. Also, the wiring BG is electrically connected to the second gate of the transistor 100. Note that the gate of the transistor 130 , one of the source or drain of the transistor 100, and the node between one electrode of the capacitive element 150 is called the node FN.

[0062] ​​​The semiconductor device shown in Fig. 5(A) applies a potential corresponding to the potential of the wiring BL to the node FN when the transistor 100 is in the conducting state (on state). Also, it has a function of holding the potential of the node FN when the transistor 100 is in the non-conducting state (off state). That is, the semiconductor device shown in Fig. 5(A) has a function as a memory cell of a memory device. When there are display elements such as liquid crystal elements and organic EL (Electroluminescence) elements electrically connected to the node FN, the semiconductor device in Fig. 5(A) can also function as a pixel of a display device. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Utilizing the change in the conducting state and non-conducting state of the transistor 130 due to the variation of the apparent threshold voltage, the information of the potential held at the node FN is used as data. (A) has a function as a memory cell of a memory device. When there are display elements such as liquid crystal elements and organic EL (Electroluminescence) elements electrically connected to the node FN, the semiconductor device in Fig. 5(A) can also function as a pixel of a display device. The semiconductor device shown in Fig. 5(A) applies a potential corresponding to the potential of the wiring BL to the node FN when the transistor 100 is in the conducting state (on state). Also, it has a function of holding the potential of the node FN when the transistor 100 is in the non-conducting state (off state). That is, the semiconductor device shown in Fig. 5(A) has a function as a memory cell of a memory device. When there are display elements such as liquid crystal elements and organic EL (Electroluminescence) elements electrically connected to the node FN, the semiconductor device in Fig. 5(A) can also function as a pixel of a display device. (A) has a function as a memory cell of a memory device. When there are display elements such as liquid crystal elements and organic EL (Electroluminescence) elements electrically connected to the node FN, the semiconductor device in Fig. 5(A) can also function as a pixel of a display device. (A) has a function as a memory cell of a memory device. When there are display elements such as liquid crystal elements and organic EL (Electroluminescence) elements electrically connected to the node FN, the semiconductor device in Fig. 5(A) can also function as a pixel of a display device.

[0063] The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned. The selection of the conducting state and non-conducting state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. Also, the threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-current as the transistor 100, the potential of the node FN in the non-conducting state can be held over a long period. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. As an example of a transistor with a small off-current, a transistor using an oxide semiconductor can be mentioned.

[0064] Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Utilizing the change in the conducting state and non-conducting state of the transistor 130 due to the variation of the apparent threshold voltage, the information of the potential held at the node FN is used as data. Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Utilizing the change in the conducting state and non-conducting state of the transistor 130 due to the variation of the apparent threshold voltage, the information of the potential held at the node FN is used as data. Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Utilizing the change in the conducting state and non-conducting state of the transistor 130 due to the variation of the apparent threshold voltage, the information of the potential held at the node FN is used as data. Note that a fixed potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Utilizing the change in the conducting state and non-conducting state of the transistor 130 due to the variation of the apparent threshold voltage, the information of the potential held at the node FN is used as data. It can be read out.

[0065] Note that in order to hold the potential held in the node FN at 85°C for 10 years (3.15×10 8 seconds) per 1 fF of capacitance, the off-current value per 1 μm of the channel width of the transistor is preferably less than 4.3 yA (yoctoampere: 1 yA is 10 A). At this time, it is preferable that the fluctuation of the potential of the node FN is within 0.5 V. -24 Or, at 95°C, it is preferable that the off-current is less than 1.5 yA. In the semiconductor device according to one aspect of the present invention, since the hydrogen concentration in the layer below the barrier film is sufficiently reduced, as a result, the transistor using the oxide semiconductor in the upper layer can achieve such an extremely low off-current.

[0066] Also, by increasing the capacitance, the potential can be held at the node FN for a longer time. That is, the holding time can be extended.

[0067] By arranging the semiconductor devices shown in FIG. 5(A) in a matrix, a memory device (memory cell array) can be configured.

[0068] FIGS. 6(A) and (B) show an example of the cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. 5(A). FIG. 6(B) is a cross-section taken along the dashed-dotted line A-B shown in FIG. 6(A).

[0069] The semiconductor devices shown in FIGS. 6(A) and (B) include a transistor 130, a transistor 100 , and a capacitor element 150. The transistor 100 is provided above the transistor 130, and at least one or more barrier films are provided between the transistor 130 and the transistor 100. ​ In addition, the semiconductor device may have a plurality of barrier films. 1 and 2 show an example in which the semiconductor device has barrier films 111a to 111e. 5B shows a top view of the transistor 100. The cross section taken along the dashed line XX′ shown in FIG. is shown as the transistor 100 in FIG. 6A. Also, the dashed line Y-Y′ shown in FIG. A cross section of this is shown as transistor 100 in FIG.

[0070] [First transistor] The transistor 130 is provided on a semiconductor substrate 131 and is made up of a part of the semiconductor substrate 131. A semiconductor layer 132, a gate insulating film 134, a gate electrode 135, and a source region or drain The low resistance layer 133a and the low resistance layer 133b function as an in-region. The illustrated semiconductor device may include a transistor 160. The semiconductor substrate 131 is provided with a capacitor 130 .

[0071] The transistor 130 may be either a p-channel type or an n-channel type, depending on the circuit configuration and An appropriate transistor may be used depending on the driving method.

[0072] The region in which the channel of the semiconductor layer 132 is formed and the region in the vicinity thereof, the source region or the drain region In the low resistance layer 133a and the low resistance layer 133b which become the drain region, a silicon-based semiconductor Preferably, the semiconductor includes a semiconductor such as silicon, and more preferably, the semiconductor includes single crystal silicon. e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), It may be formed of a material having a crystal structure such as GaAlAs (gallium aluminum arsenide). It may also be configured to use silicon having strain therein. Or, by using GaAs, AlGaAs, etc. Transistor 130 may be a HEMT (High Electron Mob ility Transistor).

[0073] Further, transistor 130 may have regions 176 a and 176b, which are LDD (lightly doped drain) regions.

[0074] In addition to the semiconductor material applied to semiconductor layer 132, low resistance layers 133a and 133b contain an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron.

[0075] Gate electrode 135 can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material that contains an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten.

[0076] Here, instead of transistors 130 and 160, transistors 190 and 191 as shown in FIG. 16 may be used. The cross-section shown by the dashed-dotted line A -B in FIG. 16(A) is shown in FIG. 16(B). Transistors 190 and 191 have a convex-shaped semiconductor layer 132 (a part of the semiconductor substrate) in which a channel is formed, and a gate insulating film 134 and a gate electrode 135 are provided along the side surface and the upper surface thereof. Transistors 190 and 191 utilize the convex portion of the semiconductor substrate. ​ It is also called a FIN type transistor. Note that an insulating film that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Here, although the case of forming a convex portion by processing a part of the semiconductor substrate has been shown, an SOI substrate may be processed to form a semiconductor layer having a convex shape. The insulating films 136, 137, and 138 are sequentially laminated and provided so as to cover the transistor 130.

[0077]

[0078] The insulating film 136 functions as a protective film during the activation of the element that imparts conductivity added to the low resistance layer 133a and the low resistance layer 133b in the manufacturing process of the semiconductor device. If the insulating film 136 is not necessary, it may not be provided.

[0079] When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By providing the insulating film 137 containing hydrogen on the transistor 130 and performing a heat treatment, the dangling bonds in the semiconductor layer 132 can be terminated by the hydrogen in the insulating film 137, and the reliability of the transistor 130 can be improved.

[0080] The insulating film 138 functions as a planarization layer that planarizes the step generated by the transistor 130 provided below it. The upper surface of the insulating film 138 may be planarized by a planarization process such as the CMP (Chemical Mechanical Polishing) method in order to improve the flatness of the upper surface.

[0081] In addition, the insulating films 136, 137, and 138 may contain the low resistance layer 133a or the low resistance layer 1 A plug 140 electrically connected to 33b etc., and a plug 139 etc. electrically connected to the gate electrode 135 of the transistor 130 may be embedded.

[0082] 〔Capacitor element〕 A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film may be a single layer or may be multiple layers as shown in FIG. 6. Here, in the example of the semiconductor device shown in FIG. 6(A), it has five-layer barrier films from barrier film 111a to barrier film 111e. When the barrier film is used as the insulating film of the capacitor element, the capacitance can be increased by reducing the film thickness. On the other hand, there is a risk that the barrier property will decrease by thinning. Therefore, by laminating a plurality of thin barrier films, the capacitance can be further increased and the barrier property can be improved, and the characteristics of the transistor 100 and the transistor 130 can be enhanced.

[0083] A conductive layer 151, a conductive layer 152, a conductive layer 153a, a conductive layer 153b, and conductive layers 154a to 154e are provided so as to sandwich the barrier film, forming a capacitor element 150. The plug 121, the plug 126, and the plug 127 are electrically connected. The plug 126 is formed in openings provided in the barrier film 111b, the insulating film 115b, and the barrier film 111c. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected to the conductive layer 104a of the transistor 100 via the plug 127, the plug 126, and the plug 121. The conductive layer 151 is formed so as to be embedded in an opening provided in the insulating film 115a. Similarly, the conductive layer 154a and the conductive layer 154b are formed in the insulating film 115b, and the conductive layer 153a is The conductive layer 154c and the conductive layer 154d are formed in the insulating film 115c, and the conductive layer 1 53b is formed in the insulating film 115e so as to be embedded in the provided openings respectively. .

[0084] Further, FIG. 7 shows a cross section taken along the dashed-dotted line C-D in FIG. 6(A). The conductive layer 154e is electrically connected to the plug 128. Also, the conductive layer 154b and the conductive layer 154d are electrically connected to the plug 128 via the plugs 129a to 129d. The plug 1 28 is connected to the wiring 142 via the plug 141.

[0085] An insulating film 114 is provided to cover the barrier film 111, the conductive layer 152, the conductive layer 154e, etc. .

[0086] Preferably, the upper surface of the insulating film 114 is planarized by the above-described planarization process.

[0087] Preferably, the insulating film 114 uses an oxide material from which a part of oxygen is desorbed by heating. .

[0088] As the oxide material from which oxygen is desorbed by heating, it is preferable to use an oxide containing more oxygen than the oxygen satisfying the stoichiometric composition. As the oxide containing more oxygen than the oxygen satisfying the stoichiometric composition, a part of oxygen is desorbed by heating. The oxide film containing more oxygen than the oxygen satisfying the stoichiometric composition is analyzed by temperature-programmed desorption spectroscopy (TDS: Thermal D esorption Spectroscopy), and the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 3.0×10 20 at oms / cm3 The oxide film is as described above. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower.

[0089] For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide can also be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0090] 〔Second Transistor〕 On top of the insulating film 114, a semiconductor layer 101 of the transistor 100 is provided.

[0091] The transistor 100 has a semiconductor layer 101 in contact with the upper surface of the insulating film 114, conductive layers 104a and 104b, a gate insulating film 102 on the semiconductor layer 101, and a gate electrode 103 overlapping the semiconductor layer 101 via the gate insulating film 102. Also, insulating films 112, 113, and 116 are provided to cover the transistor 100. Further, the transistor 100 may have a conductive layer 105 that functions as a second gate electrode.

[0092] Note that the semiconductor layer 101 may be formed as a single layer, or as shown in the transistor 1 in FIG. 6 ​​​​​​​​​​​​​It is more preferably formed as a stacked structure of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c as shown in 00. The transistor 100 shown in FIG. 6 includes the semiconductor layer 101a , the semiconductor layer 101b in contact with the upper surface of the semiconductor layer 101a, and the conductive layers 104a and 104b that are in contact with the upper surface of the semiconductor layer 101b and are separated in a region overlapping the semiconductor layer 101b. The semiconductor layer 101c is in contact with the upper surface of the semiconductor layer 101b, and a gate insulating film 102 is provided on the semiconductor layer 101c, and a gate electrode 103 that overlaps the semiconductor layer 101b through the gate insulating film 102 and the semiconductor layer 101c. The transistor 100 shown in FIG. 6 also has a conductive layer 105 that functions as a second gate electrode. The conductive layer 105 may be formed simultaneously with the conductive layer 152 that forms a part of the capacitor element 150. The semiconductor layer 101a is provided between the insulating film 114 and the semiconductor layer 101b. Also, the semiconductor layer 101c is provided between the semiconductor layer 101b and the gate insulating film 102. Further, the conductive layers 104a and 104b are in contact with the upper surface of the semiconductor layer 101b and the lower surface of the semiconductor layer 101c.

[0093] An insulating film 112, an insulating film 113, and an insulating film 116 are provided to cover the transistor 100.

[0094] As shown in FIG. 6(A), the side surface of the semiconductor layer 101b is in contact with the conductive layers 104a and 104b. Also, by the electric field of the gate electrode 103, the semiconductor layer 101b can be electrically surrounded (A transistor structure that electrically surrounds a semiconductor by the electric field of a conductor is called a surrounded channel (s-channel) structure. ) Therefore, a channel may be formed in the entire (bulk) semiconductor layer 101b. In an s-channel structure, a large current can flow between the source and drain of a transistor and the on-current during conduction can be increased.

[0095] Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since the transistors can be miniaturized, a semiconductor device having the transistors can be made into a highly integrated and high-density semiconductor device. For example, the transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less , still more preferably 20 nm or less, and the transistor preferably has a channel width of 40 nm or less, more preferably 30 nm or less, still more preferably 20 nm or less.

[0096] Note that the channel length is, for example, in a top view of the transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to be one value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0097] The channel width is, for example, the semiconductor (or when the transistor is in the on state, the inside of the semiconductor) a region where the portion through which current flows) overlaps with the gate electrode, or in a region where a channel is formed refers to the length of the portion where the source and the drain face each other. In one transistor the channel width does not necessarily take the same value in all regions. That is, in one the channel width of a transistor may not be determined to be a single value. Therefore, in this specification the channel width is taken as any one value, the maximum value, the minimum value or the average value in the region where the channel is formed.

[0098] Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width.) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width.) may be different. For example in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor and the influence may become non-negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the top surface of the semiconductor may increase. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . . .

[0099] By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, the shape of the semiconductor . . When the state is not precisely known, it is difficult to accurately measure the effective channel width. .

[0100] Therefore, in this specification, in the top view of the transistor, the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap is defined as the apparent channel width, which may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. The apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap in the top view of the transistor, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. In addition, when simply described as the channel width in this specification, it may refer to the surrounded channel width or the apparent channel width. Or, when simply described as the channel width in this specification, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. In addition, when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. In addition, when calculating the field-effect mobility of the transistor, the current value per channel width, etc., the surrounded channel width may be used for calculation. In that case, the value may be different from the case of calculating using the effective channel width. Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0101] Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0102] Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Note that at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0103] Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is provided on at least a part (or all) of the surface, side surface, top surface, and / or bottom surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). The (section) is in contact with at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Or at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is in contact with at least a part ( or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0104] Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is electrically connected to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is electrically connected to at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0105] Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is arranged in proximity to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is arranged in proximity to at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0106] Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is ​​The (section) is disposed laterally to at least a part (or all) of the surface, side surface, upper surface, and / or lower surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). Or, at least a part (or all ) of the conductive layer 104a (and / or the conductive layer 104b) is at least part (or all) of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0107] Or, at least a part (or all ) of the conductive layer 104a (and / or the conductive layer 104b) is the surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed obliquely above at least a part (or all) of the side surface, upper surface, and / or lower surface. Or, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least part (or all) of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0108] Or, at least a part (or all ) of the conductive layer 104a (and / or the conductive layer 104b) is the surface of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a), It is disposed above at least a part (or all) of the side surface, upper surface, and / or lower surface. Or, at least a part (or all ) of the conductive layer 104a (and / or the conductive layer 104b) is at least part (or all) of the semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a).

[0109] The semiconductor layer 101 is a semiconductor such as a silicon - based semiconductor in the region where a channel is formed. It may include a body. In particular, the semiconductor layer 101 preferably contains a semiconductor having a larger bandgap than silicon. Preferably, the semiconductor layer 101 is configured to include an oxide semiconductor. Using a semiconductor material having a wider bandgap and a lower carrier density than silicon is preferable because it can reduce the current in the off state of the transistor. By using such a material as the semiconductor layer, fluctuations in electrical characteristics can be suppressed, and a highly reliable transistor can be realized. Regarding the preferable form of the oxide semiconductor applicable to the semiconductor layer and its formation method, they will be described in detail in the following embodiments. When substantially intrinsic is mentioned in this specification and the like, the carrier density of the oxide semiconductor layer is less than 1×10 / cm ^2, less than 1×10 / cm

[0110] ^2, or less than 1×10 / cm

[0111] ^2, particularly preferably less than 8×10 / cm

[0112] ^2, more preferably less than 1×10 / cm 17 ^2, even more preferably less than 1×10 3 / cm 15 ^2, and even more preferably less than 1×10 3 / cm 13 ^2, and refers to being 1×10 3 / cm 11 ^2 or more. By highly purifying and making the oxide semiconductor layer intrinsic, stable electrical characteristics can be imparted to the transistor. As the semiconductor layer 101b, for example, a composition of In:Ga:Zn = 1:1:1 or 3:1:2 3 / cm 11 ^2, even more preferably less than 1×10 3 / cm 10 ^2, and even more preferably less than 1×10 3 / cm -9 ^2, and refers to being 1×10 3 / cm ^2 or more. By highly purifying and making the oxide semiconductor layer intrinsic, stable electrical characteristics can be imparted to the transistor. As the semiconductor layer 101b, for example, a composition of In:Ga:Zn = 1:1:1 or 3:1:2 can be used.

[0113] For example, a composition of In:Ga:Zn = 1:1:1 or 3:1:2 When using an In-Ga-Zn-based oxide with an atomic ratio, semiconductor layer 101a or semiconductor layer 10 1c, for example, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:6: 4, 1:6:8, 1:6:10, or an In-Ga-Zn-based oxide with an atomic ratio such as 1:9:6 can be used. Note that the atomic ratios of semiconductor layer 101b, semiconductor layer 101a, and semiconductor layer 101c each include fluctuations of plus or minus 20% of the above atomic ratio as an error. Also, semiconductor layer 101a and semiconductor layer 101c may use materials with the same composition or materials with different compositions. Moreover, when using an In-M-Zn-based oxide for semiconductor layer 101b, the target used to form the semiconductor film that becomes semiconductor layer 101 b has an atomic ratio of the metal elements contained in the target of In:M:Zn = x

[0114] :y :z When this is the case, when x 1 :y 1 :z 1 is such that the value of x 1 / y 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, and z 1 / y 1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less of an atomic ratio of an oxide is preferably used. Note that by setting z 1 / y 1 to 6 or less, the CAAC-OS film described later is more likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, etc. Moreover, when using an In-M-Zn-based oxide for semiconductor layer 101a and semiconductor layer 101c, the target used to form the semiconductor films that become semiconductor layer 101a and semiconductor layer 101c is such that the atomic ratio of the metal elements of the target includes fluctuations of plus or minus 20% of the above atomic ratio as an error. Also, semiconductor layer 101a and semiconductor layer 101c may use materials with the same composition

[0115] or materials with different compositions. When this is the case, the target used to form the semiconductor films that become semiconductor layer 101a and semiconductor layer 101c The atomic ratio of the metal elements contained in the target is In:M:Zn = x 2 :y 2 :z 2 When this is the case, x 2 / y 2 <x 1 / y 1 and z 2 / y 2 has a value of 1 / 3 or more and 6 or less, preferably an oxide having an atomic ratio of 1 or more and 6 or less is preferably used. Note that z 2 / y 2 By setting it to 6 or less, the CAAC-OS film described later is likely to be formed. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1: 3:8, etc. 3:8, etc.

[0116] When forming an oxide semiconductor film by sputtering, a film having an atomic ratio deviated from the atomic ratio of the target may be formed. In particular, zinc may have a smaller atomic ratio in the film than in the atomic ratio of the target. Specifically, it may be 4 0 atomic% or more and about 90 atomic% or less of the atomic ratio of zinc contained in the target. 0 atomic% or more and about 90 atomic% or less of the atomic ratio of zinc contained in the target. 0atomic% or more and about 90atomic% or less of the atomic ratio of zinc contained in the target.

[0117] One of the conductive layer 104a and the conductive layer 104b functions as a source electrode, and the other functions as a drain electrode. One of the conductive layer 104a and the conductive layer 104b functions as a source electrode, and the other functions as a drain electrode.

[0118] The plug 121 is electrically connected to the conductive layer 151 through openings provided in the conductive layer 104a, the semiconductor layer 101a, the semiconductor layer 101b, the semiconductor layer 1 01c, the insulating film 114, and the barrier film 111. Also, the conductive layer 104a is electrically connected to the conductive layer 151 through the plug 121. 01c, the insulating film 114, and the barrier film 111. Also, the conductive layer 104a is electrically connected to the conductive layer 151 through the plug 121. electrically connected to the conductive layer 151 through the plug 121.

[0119] The conductive layers 104a and 104b are made of aluminum, titanium, chromium, nickel, copper , yttrium, zirconium, molybdenum, silver, tantalum, tungsten, or the like of metal or an alloy having this as a main component, which is used in a single-layer structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon, a three-layer structure, a molybdenum film or a molybdenum nitride film and , an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film , and further a molybdenum film or a molybdenum nitride film is formed thereon, such as a three-layer structure. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0120] The gate insulating film 102 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, or a Ga-Zn-based metal oxide, silicon nitride , etc., and may be provided in a laminated or single-layer form.

[0121] Also, as the gate insulating film 102, hafnium silicate (HfSiO x ), hafnium silicate (HfSi O x with nitrogen added y N z ), hafnium aluminate (HfAl ) with nitrogen addedx O y N z ) It is also possible to use high-k materials such as yttrium oxide. It is also acceptable.

[0122] In addition, as the gate insulating film 102, aluminum oxide, magnesium oxide, silicon oxide , silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. oxide insulating films, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride and other nitride insulating films, or films mixed with the above materials can be used to form it.

[0123] In addition, as the gate insulating film 102, similar to the insulating film 114, it is preferable to use an oxide insulating film containing more oxygen than the stoichiometric composition. It is preferable to use an oxide insulating film containing more oxygen than the stoichiometric composition.

[0124] Note that when a specific material is used for the gate insulating film, electrons can be trapped in the gate insulating film under specific conditions to increase the threshold voltage. For example, like a stacked film of silicon oxide and hafnium oxide, a material with many electron trapping levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for a part of the gate insulating film, and at a higher temperature (a temperature higher than the operating temperature or storage temperature of the semiconductor device, or a temperature of 125 °C or higher and 450 °C or lower, typically 1 50 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a state higher than the potential of the source electrode or drain electrode for 1 second or longer, typically 1 minute or longer, so that electrons move from the semiconductor layer towards the gate electrode, and some of them are trapped in the electron trapping levels. tantalum oxide, etc., and at a higher temperature (a temperature higher than the operating temperature or storage temperature of the semiconductor device, or a temperature of 125 °C or higher and 450 °C or lower, typically 1 50 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a state higher than the potential of the source electrode or drain electrode for 1 second or longer, typically 1 minute or longer, so that electrons move from the semiconductor layer towards the gate electrode, and some of them are trapped in the electron trapping levels. 50 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a state higher than the potential of the source electrode or drain electrode for 1 second or longer, typically 1 minute or longer, so that electrons move from the semiconductor layer towards the gate electrode, and some of them are trapped in the electron trapping levels. 50 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a state higher than the potential of the source electrode or drain electrode for 1 second or longer, typically 1 minute or longer, so that electrons move from the semiconductor layer towards the gate electrode, and some of them are trapped in the electron trapping levels. 50 °C or higher and 300 °C or lower), the potential of the gate electrode is maintained at a state higher than the potential of the source electrode or drain electrode for 1 second or longer, typically 1 minute or longer, so that electrons move from the semiconductor layer towards the gate electrode, and some of them are trapped in the electron trapping levels. polar, electrons move, and some of them are trapped in the electron trapping levels.

[0125] In this way, a transistor that has captured the necessary number of electrons at the electron capture level has a threshold voltage The amount of electrons captured is controlled by controlling the voltage of the gate electrode. This allows the threshold voltage to be controlled. The treatment for adding the conductive layer may be performed during the manufacturing process of a transistor.

[0126] For example, forming wiring metal that connects to the source electrode or drain electrode of a transistor After, or after the completion of the pre-process (wafer processing), or after the wafer dicing process It is advisable to carry out the inspection at any stage before shipment from the factory, after packaging, etc. It is preferred that the subsequent exposure to temperatures above 125° C. is not to be allowed for more than 1 hour.

[0127] The gate electrode 103 is made of, for example, aluminum, chromium, copper, tantalum, titanium, or molybdenum. a metal selected from the group consisting of tungsten, tungsten, or an alloy containing the above-mentioned metals, or It can be formed by using an alloy of metals. In addition, impurity elements such as phosphorus may be used. Semiconductors such as polycrystalline silicon doped with silicon, and silicides such as nickel silicide The gate electrode 103 may have a single-layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a silicon layer on an aluminum film, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film, titanium nitride Two-layer structure with tungsten film laminated on the film, tantalum nitride film or tungsten nitride film A two-layer structure with a tungsten film laminated on top of the titanium film and an aluminum film on top of the titanium film. There is a three-layer structure or the like in which layers are stacked and a titanium film is further formed thereon. Also, for aluminum, an alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.

[0128] Also, the gate electrode 103 can be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Further, a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal can also be used.

[0129] Also, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) or the like may be provided between the gate electrode 103 and the gate insulating film 102. Since these films have a work function of 5 eV or more, preferably 5.5 eV or more, and a value larger than the electron affinity of the oxide semiconductor, the threshold voltage of the transistor using the oxide semiconductor can be shifted to a positive value, and a so-called normally-off characteristic switching element can be realized. For example, when using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the semiconductor layer 101, specifically 7 atomic% or more, is used.

[0130] Similar to the barrier film 111, the insulating film 112 can be made of a material through which water and hydrogen hardly diffuse.​​​​​​​​​​​​ This is preferable. In particular, it is preferable to use a material that hardly permeates oxygen as the insulating film 112.

[0131] By covering the semiconductor layer 101 with the insulating film 112 containing a material that hardly permeates oxygen, it is possible to suppress the release of oxygen from the semiconductor layer 101 above the insulating film 112. Furthermore, since the oxygen desorbed from the insulating film 114 can be confined below the insulating film 112, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

[0132] In addition, the insulating film 112 that hardly permeates water or hydrogen can suppress the mixing of water and hydrogen, which are impurities for the oxide semiconductor, from the outside, suppress fluctuations in the electrical characteristics of the transistor 100, and realize a highly reliable transistor.

[0133] Note that an insulating film similar to the insulating film 114, from which oxygen desorbs by heating, may be provided below the insulating film 112, and oxygen may also be supplied from above the semiconductor layer 101 through the gate insulating film 102.

[0134] Also, as shown in FIG. 6(B), in the cross section in the channel width direction of the transistor, by providing the gate electrode 103 facing the upper surface and the side surface of the semiconductor layer 101b, a channel is formed not only near the upper surface but also near the side surface of the semiconductor layer 101b, and the effective channel width is increased, so that the current in the on state (on-current) can be increased. In particular, when the width of the semiconductor layer 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), the region where the channel is formed reaches inside the semiconductor layer 101b. ​​​​​​​​​​​​​Since the size of the gate electrode spreads, its contribution to the on-current increases as the gate electrode becomes finer.

[0135] 17A and 17B illustrate an example of a transistor 100 included in a semiconductor device. The transistor 100 shown in FIG. 17(A) and (B) is the same as the transistor 100 shown in FIG. In comparison, the semiconductor layer 101c is provided in contact with the lower surfaces of the conductive layers 104a and 104b. The main difference is that the dashed line A in FIG. 17(A) is used. -B is a cross section.

[0136] With this configuration, the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 10 Each film that makes up 1c is deposited continuously without being exposed to the air. Therefore, the occurrence of defects at each interface can be reduced.

[0137] The transistor 100 may have a structure shown in FIG. After forming the semiconductor layer 101a and the semiconductor layer 101b, the semiconductor layer 101c is formed. The side surfaces of the semiconductor layer 101a and the semiconductor layer 101b are covered with the semiconductor layer 101c. Alternatively, the transistor 100 may have a structure shown in FIG. 35(A) is that the gate electrode 103, the conductive layer 104a, and the gate The electrode 103 and the conductive layer 104b are overlapped in this structure, whereas in FIG. 35B, the conductive layer 104a and the conductive layer 104b do not overlap with each other. No.

[0138] 6(A), 6(B) and 17(A), 17(B), the semiconductor layer 101b is in contact with the semiconductor layer 101b. Although the configuration in which the conductor layer 101a and the semiconductor layer 101c are provided has been described, it is also possible to adopt a configuration in which one or both of the semiconductor layer 101a and the semiconductor layer 101c are not provided.

[0139] Note that in the configuration shown in FIG. 6(B), the gate insulating film 102 and the end of the semiconductor layer 101c are processed so as to substantially coincide, and the gate electrode 103 is processed so as to be located inside the gate insulating film. An example is shown. However, as in the example of the transistor 100 shown in FIG. 17(C), the gate insulating film 102, the semiconductor layer 101c, and the ends of the gate electrode 103 may be processed so as to substantially coincide. Alternatively, as in the example of the transistor 100 shown in FIG. 17(D), the gate insulating film 102, the semiconductor layer 101c, and the ends of the gate electrode may be processed so as not to coincide with each other.

[0140] The above is the description of the transistor 100.

[0141] The insulating film 116 covering the transistor 100 functions as a planarization layer covering the uneven shape of the lower layer. Further, the insulating film 113 may function as a protective film when forming the insulating film 116. The insulating film 113 may not be provided if it is not necessary.

[0142] Plugs 123, 122, etc. that are electrically connected to the conductive layer 104b are embedded in the insulating film 112, the insulating film 113, and the insulating film 116.

[0143] Wiring 124 and the like that are electrically connected to the plug 123 are provided above the insulating film 116.

[0144] Here, the wiring 124 shown in FIG. 6(A) corresponds to the wiring BL shown in FIG. 5. Similarly, FIG. 6 ​​​​​​​​​​​The wiring 166 shown in (B) corresponds to the wiring BG, and the wiring 142 shown in FIG. 7 corresponds to the wiring CL. Although not shown, the wiring connected to the gate electrode 103 in FIG. 6 corresponds to the wiring WL. Also, the low-resistance layer 133b of the transistor 130 corresponds to the wiring SL. Also, the gate electrode 135 of the transistor 130, the plug 121 that functions as the first electrode of the capacitor element 150, and the node including the conductive layer 104a of the transistor 100 correspond to the node FN shown in FIG. 5(A).

[0145] Also, in FIG. 6, as the insulating film 137 provided on the insulating film 136 containing hydrogen, it is preferable to provide an insulating film 137 containing the same material as the barrier film 111. In this way, by adopting such a configuration, it is possible to effectively suppress the upward diffusion of water and hydrogen remaining in the insulating film 136 containing hydrogen. In this case, before forming the insulating film 137 and after forming the insulating film 137 but before forming the barrier film 111, heat treatment for removing water and hydrogen may be performed a total of two or more times.

[0146] For wirings such as the wiring 124, the wiring 142, and the wiring 166, conductive materials such as metal materials, alloy materials, or metal oxide materials can be used as the material. In particular, it is preferable to use high-melting-point materials such as tungsten and molybdenum that have both heat resistance and conductivity, and in particular, it is preferable to use tungsten.

[0147] Also, conductive layers such as the conductive layer 125, the conductive layer 151, the conductive layer 152, the conductive layer 153a, the conductive layer 153b, the conductive layer 154a to the conductive layer 154e, and plugs such as the plug 121 to the plug 123, the plug 126 to the plug 128, the plug 129a to the plug 129d, the plug 139 to the plug ​ For plugs such as the lug 141, plug 164, and plug 165, a conductive material such as a metal material, alloy material, or metal oxide material can be used as the material. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is particularly preferable to use tungsten. Also, materials such as titanium nitride or titanium may be laminated and used with other materials. For example, by using titanium nitride or titanium, the adhesion to the opening can be improved. Also, conductive layers such as the conductive layer 125, conductive layer 151, conductive layer 152, conductive layer 153a, conductive layer 153b, and conductive layer 154a to conductive layer 154e, and plugs such as the lug 121 to 123, plug 126 to plug 128, plug 129a to plug 129d, plug 139 to plug 141, plug 164, and plug 165 are preferably provided so as to be embedded in the insulating film, and the upper surface of each is preferably flattened. Here, the plug 121 is in contact with the semiconductor layer 101, conductive layer 104a of the transistor 100, and the conductive layer 151. First, by contacting the semiconductor layer 101 and the conductive layer 104a of the transistor 100, it functions as a wiring connected to the source region or drain region of the transistor 100. Also, by contacting the conductive layer 151, it functions as a wiring connected to one electrode of the capacitor element 150. When the plug 121 penetrates the transistor 100 and reaches the conductive layer 151 which is one electrode of the capacitor element 150, one plug can serve as a wiring connecting the electrode of the capacitor element 150 and the source region or drain region of the transistor 100.

[0148]

[0149] Similarly, the plug 122 contacts the semiconductor layer 101, the conductive layer 104b, and the conductive layer 125 of the transistor 100. First, by contacting the semiconductor layer 101 and the conductive layer 10 4b of the transistor 100, it functions as a wiring connected to the source region or the drain region of the transistor 100. Also, by contacting the conductive layer 125, it functions as a wiring connected to the source region or the drain region of the transistor 130. When the plug 122 penetrates the transistor 100 and reaches the conductive layer 125, a single plug can serve as both a wiring connected to the source region or the drain region of the transistor 130 and a wiring connected to the source electrode or the drain electrode of the transistor 100.

[0150] Next, an example of reducing the circuit area using the plugs 121 and 122 will be described with reference to FIG. 30. Also, the configuration shown in FIG. 31 shows an example without using the plugs 121 and 122. For the barrier film 211a, refer to the description of the barrier film 111. Also, for the insulating film 215a, refer to the description of the insulating film 115a. The contact 221 between the conductive layer 104a and the capacitor element 1 50 is formed outside the semiconductor layer 101b, which is a factor increasing the element area. Similarly, the contact 222 between the conductive layer 104b and the conductive layer connected to the source region or the drain region of the transistor 130 is formed outside the semiconductor layer 101b, which is a factor increasing the element area. In the configuration example shown in FIG. 30(A), the plug 121 that penetrates the transistor 100 and is connected to one electrode of the capacitor element 150, and the plug that penetrates the transistor 100 and is connected to the transistor 130

[0151] One electrode of the capacitor element 150 is connected through the plug 121 that penetrates the transistor 100, and the transistor 130 is connected through the plug that penetrates the transistor 100. ​​​​The plug 12 that connects to the conductive layer 251a which is electrically connected to the source electrode or the drain region An example using 2 is shown. The barrier films 211a to 211f refer to the description of the barrier film 111 Refer to it. Also, the insulating films 215a to 215f refer to the description of the insulating film 115a Refer to it. The conductive layer 251 refers to the description of the conductive layer 151. The conductive layer 251a refers to the description of the conductive layer 12 5. Note that Fig. 30(B) is a diagram showing two arrangements of the structure shown in Fig. 30(A) In Fig. 30, an example is shown in which the conductive layers 104a and 104b are not provided However, they may be provided

[0152] In Fig. 31, there are two contacts: the contact 221 between the conductive layer 104a and the capacitor element 150, and the contact 223 between the plug 321 and the conductive layer 104a. In contrast, in Fig. 30, the role of these two contacts can be played by the plug 121 Similarly, in Fig. 31, there are two contacts: the contact 222 between the conductive layer 104b and the conductive layer 251a, and the contact 224 between the plug 322 and the conductive layer 104b. In contrast, in Fig. 30, the role of these two contacts can be played by the plug 122 Thus, by using the plug 121 and the plug 122, the capacitor element 150 can be fabricated with a width similar to that of the transistor 100 in the structure shown in Fig. 30, and the occupied area of the element can be reduced Next, in the cross-sectional view shown in Fig. 30, the top views of the layers 281 to 287 are shown in Fig. 32(A) In the structure shown in Fig. 30, the capacitor element 150 can be fabricated with a width similar to that of the transistor 100, and the occupied area of the element can be reduced

[0153] Next, in the cross-sectional view shown in Fig. 30, the top views of the layers 281 to 287 are shown in Fig. 32(A) Also, in the cross-sectional view shown in Fig. 31, the top views of the layers 291 to 295 are shown in Fig. 32(B ) Each top view shows the minimum structural unit of the memory cell. Using the structure of Fig. 30 It can be seen that by doing so, the area can be reduced to about half compared to FIG. 31.

[0154] Also, as in the cross-section of the semiconductor device shown in FIG. 33, an insulating film 261 for planarization may be provided and plugs 121 and 122 may be formed therefrom.

[0155] The semiconductor device according to one aspect of the present invention has a transistor 130 and a transistor 100 located above the first transistor 130. Therefore, by stacking and providing these, the occupied area of the elements can be reduced. Also, by providing the plugs 121 and 122, the occupied area of the elements can be reduced. Thus, a semiconductor device with a small circuit area and good characteristics can be provided. Further, when one aspect of the present invention is used in a semiconductor device having, for example, a memory, etc., a semiconductor device with a high memory capacity even with a small circuit area and a good holding characteristic can be provided. Furthermore, the barrier film 111 provided between the transistor 130 and the transistor 100 can suppress the diffusion of impurities such as water and hydrogen existing in the lower layer to the transistor 100 side. Moreover, a wiring that functions as a first electrode and a wiring that functions as a second electrode are provided with the barrier film 111 interposed therebetween to form a capacitive element 150. Therefore, the capacitive element 150 can be easily fabricated without separately adding a process for fabricating the capacitive element 150.

[0156] The above is the description of the configuration example.

[0157] [Example of manufacturing method] Hereinafter, an example of the manufacturing method of the semiconductor device shown in the above configuration example will be described with reference to FIGS. 8 to 12​​​​​​​​ This will be described with reference to the cross-sectional view.

[0158] First, a semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide, gallium nitride, etc. can be used. Also, as the semiconductor substrate 131, an SOI substrate may be used. Hereinafter, the case where single crystal silicon is used as the semiconductor substrate 131 will be described.

[0159] Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer can be formed by using the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, the mesa isolation method, etc. OS (Local Oxidation of Silicon) method or STI (Sh allow Trench Isolation) method, mesa isolation method, etc. It may be formed.

[0160] When forming a p-type transistor and an n-type transistor on the same substrate, an n-well or a p-well may be formed in a part of the semiconductor substrate 131. For example, an impurity element such as boron that imparts p-type conductivity is added to the n-type semiconductor substrate 131 to form a p-well, and an n-type transistor and a p-type transistor may be formed on the same substrate.

[0161]

[0161] Subsequently, an insulating film serving as the gate insulating film 134 is formed on the semiconductor substrate 131. For example, the surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Or, after forming silicon oxide by thermal oxidation, the surface of the silicon oxide film is nitrided by performing a nitriding treatment to form a laminated structure of a silicon oxide film and a silicon oxynitride film. Also, by nitriding the surface of the silicon oxide film by performing a nitriding treatment after forming silicon oxide by thermal oxidation, a laminated structure of a silicon oxide film and a silicon oxynitride film may be formed. Also, ​Alternatively, silicon oxide, silicon oxynitride, a high dielectric constant material (also referred to as a high-k material), a certain tantalum oxide, hafnium oxide, hafnium silicate, zirconium oxide, metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide etc. may be used.

[0162] The insulating film may be formed by film deposition using a sputtering method, a CVD (Chemical Vapor Depo sition) method (including a thermal CVD method, a MOCVD (Metal Organic CVD) method a PECVD (Plasma Enhanced CVD) method, etc.), an MBE (Molecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, or a PLD (Pulsed Laser Deposit ion) method, etc.

[0163] Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, etc., or an alloy material or a compound material mainly composed of these metals is preferably used. Also, polycrystalline silicon doped with impurities such as phosphorus can be used. Further, a laminated structure of a metal nitride film and the above metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

[0164] The conductive film is formed by a sputtering method, an evaporation method, a CVD method (a thermal CVD method, a MOCVD method, a PEC ​It can be formed by, for example, the VD method (including the VD method). Also, to reduce damage by plasma, thermal CVD, MOCVD, or ALD is preferable. Subsequently, a resist mask is formed on the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. Then, by removing the resist mask, the gate electrode 135 can be formed.

[0165] Subsequently, a resist mask is formed on the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. Then, by removing the resist mask, the gate electrode 135 can be formed. Subsequently, a resist mask is formed on the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. Then, by removing the resist mask, the gate electrode 135 can be formed. 135 can be formed.

[0166] Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used. Here, the processing method of the film to be processed will be described. When the film to be processed is finely processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Also, a dummy pattern is formed by a photolithography method or the like, sidewalls are formed on the dummy pattern, and then the dummy pattern is removed, and the remaining sidewalls are used as a resist mask to etch the film to be processed. Also, as the etching of the film to be processed, anisotropic dry etching is preferably used to achieve a high aspect ratio. Also, a hard mask made of an inorganic film or a metal film may be used.

[0167] The light used for forming the resist mask can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. The light used for forming the resist mask can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. The light used for forming the resist mask can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, exposure may be performed by immersion exposure technology. Also, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also Also, exposure may be performed by immersion exposure technology. Also, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also , instead of using light for exposure, an electron beam can also be used. Extreme ultraviolet light, X-rays, or Using an electron beam is preferable because extremely fine processing becomes possible. When performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0168] Also, before forming a resist film that serves as a resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed, for example, by spin coating or the like so as to cover the steps of its lower layer and flatten the surface, and the variation in the thickness of the resist mask provided on the upper layer of the organic resin film can be reduced. When performing particularly fine processing, it is preferable to use, as the organic resin film, a material that functions as an antireflection film for the light used for exposure. Examples of such an organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed simultaneously with the removal of the resist mask or after removing the resist mask. After forming the gate electrode 135, a sidewall covering the side surface of the gate electrode 135 may be formed. The sidewall can be formed by depositing an insulating film thicker than the thickness of the gate electrode 135 and then performing anisotropic etching to leave only the insulating film on the side surface portion of the gate electrode 135.

[0169]

[0170] In FIG. 8(A), an example in which the gate insulating film is not etched during the formation of the sidewall is shown, but during the formation of the sidewall, the insulating film that becomes the gate insulating film 134 is also etched simultaneously. This may be done. In this case, a gate insulating film 134 is formed under the gate electrode 135 and the sidewall.

[0171] Subsequently, an element that imparts n-type conductivity such as phosphorus or an element that imparts p-type conductivity such as boron is added to the region of the semiconductor substrate 131 where the gate electrode 135 (and the sidewall) is not provided. A schematic cross-sectional view at this stage corresponds to FIG. 8(A).

[0172] Subsequently, after forming the insulating film 136, a first heat treatment is performed to activate the element that imparts the above-described conductivity.

[0173] The insulating film 136 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc., and may be provided in a laminated or single-layer form. The insulating film 136 can be formed using a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, the coating property can be improved, which is preferable. Also, to reduce damage by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0174] The first heat treatment can be performed, for example, at 400°C or higher and below the strain point of the substrate in an inert gas atmosphere such as a rare gas or nitrogen gas, or in a reduced-pressure atmosphere.

[0175] At this stage, the transistor 130 is formed. Also, the transistor 160 may be formed in the same manner as forming the transistor 130. ​​​​​​​​​​​​​

[0176] Subsequently, an insulating film 137 and an insulating film 138 are formed.

[0177] The insulating film 137, in addition to the materials that can be used for the insulating film 136, is preferably made of silicon oxynitride (SiNOH) containing oxygen and hydrogen, because the amount of hydrogen desorbed by heating can be increased. Further, the insulating film 138, in addition to the materials that can be used for the insulating film 136, is preferably made of silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane, etc. with oxygen or nitrous oxide, etc. When using silicon oxynitride (SiNOH) containing oxygen and hydrogen, it is preferable because the amount of hydrogen desorbed by heating can be increased. In addition, the insulating film 138, in addition to the materials that can be used for the insulating film 136, is preferably made of silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane, etc. with oxygen or nitrous oxide, etc. In addition to the materials that can be used for the insulating film 136, TEOS (Tetra-Ethyl-Ortho-Silicate) or silane, etc. is reacted with oxygen or nitrous oxide, etc. to form silicon oxide with good step coverage. It is preferable to use it.

[0178] The insulating film 137 and the insulating film 138 can be formed, for example, by using a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, when forming the insulating film by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Also, to reduce the damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable. Including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. Subsequently, the upper surface of the insulating film 138 is planarized using a CMP method or the like. Also, a planarizing film may be used as the insulating film 138. In that case, it is not necessarily required to be planarized by a CMP method or the like. For planarizing the upper surface of the insulating film 138, a CMP method or the like can be used. Also, a planarizing film may be used as the insulating film 138. In that case, it is not necessarily required to be planarized by a CMP method or the like. To reduce the damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0179] Subsequently, the upper surface of the insulating film 138 is planarized using a CMP method or the like. Also, a planarizing film may be used as the insulating film 138. In that case, it is not necessarily required to be planarized by a CMP method or the like. When using a planarizing film as the insulating film 138, it is not necessarily required to be planarized by a CMP method or the like. For forming the planarizing film, for example, an atmospheric pressure CVD method or a coating method can be used. Examples of the film that can be formed using the atmospheric pressure CVD method include BPSG (Boron Phosphorus us Silicate Glass), etc. Examples of the film that can be formed using the coating method include HSQ (hydrogen silsesquioxane), etc. us Silicate Glass), etc. Examples of the film that can be formed using the coating method include HSQ (hydrogen silsesquioxane), etc.

[0180] Then, the dangling bonds in the semiconductor layer 132 are desorbed from the insulating film 137 by hydrogen. The second heat treatment is then performed to terminate the layers. By desorbing the water and hydrogen contained in the fuel, the water and hydrogen contents can be reduced.

[0181] The second heat treatment can be carried out under the conditions exemplified in the description of the laminated structure above. For example, The conditions described for the heat treatment in 1 can be used.

[0182] Next, the low resistance layer 133a and the low resistance layer 133b are formed on the insulating film 136, the insulating film 137, and the insulating film 138. An opening is formed that reaches the layer 133b and the gate electrode 135 (see FIG. 8(B)). Thereafter, a conductive film 181 that will become the plug 139 or the like is formed so as to fill the opening (see FIG. 8(C)). After that, the conductive film 181 is subjected to a planarization process so that the upper surface of the insulating film 138 is exposed. As a result, plugs 139 and 140 are formed (see FIG. 8(D)). The formation of 81 can be performed by, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, PEC It can be formed by using a method such as MBE, ALD, or PLD. do.

[0183] Next, the insulating film 115e is formed on the insulating film 138, and an opening is formed. A conductive film is formed so as to fill the gap, and a flat layer is formed on the conductive film so as to expose the upper surface of the insulating film 115e. By carrying out a flattening process, the conductive layer 144 and the conductive layer 153b are formed (FIG. 8(E) 6, the conductive layer 153b functions as an electrode of the capacitor.

[0184] Subsequently, a barrier film 111e is formed, and then an insulating film 115d is formed (see Fig. 9(A)). Subsequently, an opening is formed in the insulating film 115d. Thereafter, a conductive film is formed to fill the opening, and a planarization process is performed on the conductive film so that the upper surface of the insulating film 115e is exposed, thereby forming a conductive layer 154d, a conductive layer 154e, etc. (see Fig. 9(B)). In the example shown in Fig. 6, the conductive layer 154d and the conductive layer 154e function as electrodes of a capacitive element. Thereafter, a barrier film 111d is formed (see Fig. 9(C)).

[0185] Subsequently, openings are formed in the barrier film 111d, the insulating film 115d, and the barrier film 111e. Thereafter, a conductive film that becomes a plug 127 or the like is formed to fill the opening, and a planarization process is performed on the conductive film so that the upper surface of the barrier film 111d is exposed, thereby forming a plug 127 and a plug 145 or the like (see Fig. 9(D)).

[0186] Subsequently, an insulating film 115c is formed (see Fig. 10(A)). Next, an opening is formed in the insulating film 115c. Thereafter, a conductive film is formed to fill the opening, and a planarization process is performed on the conductive film so that the upper surface of the insulating film 115c is exposed, thereby forming a conductive layer 146 and a conductive layer 153a or the like (see Fig. 10(B)). The conductive layer 153a functions as an electrode of a capacitive element.

[0187] Next, after manufacturing the conductive layer 154a, the conductive layer 154b, the plug 126, and the plug 147 using the same method as that shown in Fig. 9, a barrier film 111a is formed, an opening is provided in a region in contact with the conductive layer 143 of the barrier film 111a, and then a conductive film is formed. Thereafter, a resist ​​​​​​​​​​​​Form a mask and remove the unnecessary portions of the conductive film by etching. Then, remove the resist mask, thereby forming the conductive layer 152, the conductive layer 154e, and the conductive layer 105 functioning as the second gate electrode (see Fig. 10(C)).

[0188] Here, in Fig. 9(D), the barrier film 111d has been subjected to a planarization process. As shown in Figs. 9 to 10, the barrier film 111d may be used as it is as the insulating film of the capacitor element. Alternatively, the steps of Figs. 9(D) to 10(C) may be replaced with, for example, the steps of Figs. 13(A) to 14(B) shown below. The barrier film 111d may be removed once and then deposited again. An example thereof is shown in Figs. 13 to 14. For example, when a planarization process is performed by the CMP method or the like, damage or the like may sometimes occur on the surface of the film. In that case, as described below, by removing the damaged film or the surface region of the film and then depositing again the insulating film used for the capacitor element, the capacitance characteristics can be further improved.

[0189] Fig. 13(A) shows a state in which the barrier film 111d and the conductive film such as the plug 12 7 have been subjected to a planarization process as described in Fig. 9(D). Then, as shown in Fig. 13(B), the barrier film 111d is removed by etching or the like. Then, the barrier film 111f is formed. Next, a resist mask is formed, and by performing etching, openings are provided in the barrier film 111f on the plugs such as the plug 127 and the plug 145. Then, the resist mask is removed (see Fig. 13(C)).

[0190] Next, an insulating film 115c is formed. Then, a resist mask is formed and etching is performed to provide an opening in the insulating film 115c. Next, a conductive layer 146, a conductive layer 153a, etc. are formed (see Fig. 14(A)).

[0191] Next, a barrier film 111c is formed, and then an insulating film 115b is formed. Then, a conductive layer 154c, a conductive layer 154d, a barrier film 111f, a plug 127, and a plug 145 are formed. Using the same method as when forming the conductive layer 154a, a conductive layer 154b, a barrier film 111g, a plug 126, and a plug 147 are formed.

[0192] Next, an insulating film 115a is formed. Then, using the same method as when forming the conductive layer 146 and the conductive layer 153a, a conductive layer 125 and a conductive layer 151 are formed. Then, a barrier film 111a is formed. Then, after providing an opening in the barrier film 111a, a conductive film is formed, and a conductive layer 105, a conductive layer 152, and a conductive layer 154e are formed using a resist mask or the like (see Fig. 14(B)). The above is the description of the case where the processes of Figs. 9(D) to 10(C) are replaced with the processes of Figs. 13( A) to 14(B). This is the description of the case where the processes of Figs. 9(D) to 10(C) are replaced with the processes of Figs. 13(A) to 14(B).

[0193] The insulating films 115a to 115e can be formed by the same materials and methods as the insulating film 136 or the like. They can be formed.

[0194] The barrier films 111a to 111g can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, the insulating film can be formed by a CVD method, preferably a plasma C VD method. When forming a film by the VD method, it is preferable because the coating property can be improved. Also, to reduce damage by plasma the thermal CVD method, the MOCVD method, or the ALD method is preferable. The materials that can be used for the barrier film 111a to the barrier film 111g may be referred to the description of the barrier film 111 .

[0195] After forming the insulating film 115e, it is preferable to perform a third heat treatment. By the third heat treatment desorbing water and hydrogen contained in each layer, the content of water and hydrogen can be reduced . Performing the third heat treatment immediately before forming the barrier film 111e and thoroughly removing hydrogen and water contained in the layer below the barrier film 11 1e, and then forming the barrier film 111e can suppress the re-diffusion of water and hydrogen to the layer below the barrier film 111e in the subsequent process.

[0196] The third heat treatment can be performed under the conditions exemplified in the description of the above laminate structure. For example, the conditions described in the first heat treatment etc. can be used. Note that after forming the insulating films 115a to 115d, similar heat treatment may be performed after forming each insulating film.

[0197] At this stage, the capacitive element 150 is formed. The capacitive element 150 includes a conductive layer 152 that functions as part of the first electrode and conductive layers 154a to 154e, and a conductive layer 151, a conductive layer 153a, and a conductive layer 153b that function as part of the second electrode, and is composed of the barrier films 111a to 111e sandwiched therebetween.

[0198] Next, the insulating film 114 is formed. The insulating film 114 can be formed by, for example, sputtering, CVD (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PL D method, etc. can be used for formation. In particular, when the insulating film is formed by CVD method, preferably plasma CVD method, the coating property can be improved, which is preferable. Also in order to reduce the damage caused by plasma, thermal CVD method, MOCVD method or ALD method is preferable .

[0199] In order to make the insulating film 114 contain oxygen in excess, for example, the insulating film 11 4 can be formed in an oxygen atmosphere. Or, oxygen can be introduced into the insulating film 114 after film formation to form a region containing oxygen in excess , and both means can be combined.

[0200] For example, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions ) is introduced into the insulating film 114 after film formation to form a region containing oxygen in excess. As the method of introducing oxygen , ion implantation method, ion doping method, plasma immersion ion implantation method, plasma treatment, etc. can be used.

[0201] For the oxygen introduction treatment, a gas containing oxygen can be used. As the gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Also, in the oxygen introduction treatment, a rare gas can be included in the gas containing oxygen. Or, hydrogen etc. can be included. For example, a mixed gas of carbon dioxide, hydrogen and argon can be used .

[0202] Also, after the insulating film 114 is molded, a planarization treatment such as CMP method can be used to improve the flatness of its upper surface.

[0203] Next, a semiconductor film that will become the semiconductor layer 101a and a semiconductor film that will become the semiconductor layer 101b are sequentially formed into films. It is preferable that the semiconductor films are continuously formed without being exposed to the atmosphere. The semiconductor that will become the semiconductor layer 101a and the semiconductor that will become the semiconductor layer 101b may be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0204] When forming an In-Ga-Zn oxide layer as the semiconductor that will become the semiconductor layer 101a and the semiconductor that will become the semiconductor layer 101b by the MOCVD method, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as the source gas. Note that it is not limited to the above combination of source gases, and triethylindium or the like may be used instead of trimethylindium. Also, triethylgallium or the like may be used instead of trimethylgallium. Further, diethylzinc or the like may be used instead of dimethylzinc.

[0205] After forming the semiconductor film, it is preferable to perform a fourth heat treatment. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Also, the atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after forming the semiconductor film, or may be performed after processing the semiconductor film to form island-shaped semiconductor layers 101a and 101b. By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film, and oxygen deficiencies in the semiconductor film can be reduced. ​​​​​​​​​​​​​

[0206] Thereafter, a resist mask is formed, and unnecessary portions are removed by etching. Thereafter, by removing the resist mask, a stacked structure of the island-shaped semiconductor layer 101a and the island-shaped semiconductor layer 101b can be formed (see Fig. 11(A)). Note that, during the etching of the semiconductor film, a part of the insulating film 114 may be etched, and the insulating film 114 in the region not covered by the semiconductor layer 101a and the semiconductor layer 101 b may be thinned. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 does not disappear due to the etching.

[0207] Thereafter, a conductive film 104 is formed (see Fig. 11(B)). The conductive film 104 can be formed by, for example, sputtering, CVD methods (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. In particular, when the insulating film is formed by CVD, preferably plasma CVD, the coverage can be improved, which is preferable. Also, to reduce damage by plasma, thermal CVD, M OCVD, or ALD is preferable.

[0208] Next, a resist mask is formed, and unnecessary portions of the conductive film 104 are removed by etching. Thereafter, the resist mask is removed, and the conductive layers 104a and 104b are formed. Here, during the etching of the conductive film, a part of the upper portion of the semiconductor layer 101b and the insulating film 114 may be etched, and the portion that does not overlap with the conductive layers 104a and 104b may be thinned. Therefore, it is preferable to form the thickness of the semiconductor film that becomes the semiconductor layer 101b thick in advance in consideration of the etching depth. ​​​​​​

[0209] Next, a gate insulating film 102 and a semiconductor layer 101c are formed, a resist mask is formed, and etching is performed, followed by removing the resist mask. Next, a conductive film to be the gate electrode 103 is formed (see Fig. 12(A)). Then, a resist mask is formed, and the conductive film is processed by etching, and then the resist mask is removed to form the gate electrode 103. The semiconductor that becomes the semiconductor layer 101c may be formed using a sputtering method, a CVD method, an MBE method, or a P LD method, an ALD method, or the like. Note that, when forming an In-Ga-Zn oxide layer as the semiconductor that becomes the semiconductor layer 101c by the MOCVD method, trimethylindium, trimethylgallium, and dimethylzinc may be used as the source gases. Note that the combination of the above source gases is not limited,

[0210] and triethylindium or the like may be used instead of trimethylindium. Also, triethylgallium or the like may be used instead of trimethylgallium. Further, diethylzinc or the like may be used instead of dimethylzinc. At this stage, the transistor 100 is formed. Next, an insulating film 112 is formed. The insulating film 112 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL D method. In particular, when forming the insulating film by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Also, to reduce damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable

[0211]

[0212] Next, an insulating film 112 is formed. The insulating film 112 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL D method. In particular, when forming the insulating film by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Also, to reduce damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable ​​ preferable.

[0213] After forming the insulating film 112, it is preferable to perform a fifth heat treatment. By the heat treatment, oxygen is supplied from the insulating film 114 or the like to the semiconductor layer 101, and oxygen vacancies in the semiconductor layer 101 can be reduced. At this time, the oxygen desorbed from the insulating film 114 is blocked by the barrier film 111 and the insulating film 112 and does not diffuse to the layer below the barrier film 111 and the layer above the insulating film 114, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced. and the insulating film 112 and does not diffuse to the layer below the barrier film 111 and the layer above the insulating film 114, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced. and the insulating film 112 and does not diffuse to the layer below the barrier film 111 and the layer above the insulating film 114, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced. and the insulating film 112 and does not diffuse to the layer below the barrier film 111 and the layer above the insulating film 114, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced. and the insulating film 112 and does not diffuse to the layer below the barrier film 111 and the layer above the insulating film 114, so that the oxygen can be effectively confined. Therefore, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced.

[0214] Further, the insulating film 112 may have a laminated structure of two or more layers. In that case, for example, the insulating film 112 has a two-layer laminated structure, and for the lower layer, silicon oxide, silicon oxynitride, oxynitride silicon, silicon nitride, aluminum oxide, aluminum oxynitride, oxynitride aluminum, aluminum nitride, etc. may be used. For the upper layer, it is preferable to use a material in which water and hydrogen hardly diffuse, similar to the barrier film 111. The insulating film provided in the lower layer may be configured to supply oxygen from above the semiconductor layer 101 through the gate insulating film 102, which is an insulating film from which oxygen desorbs by heating, similar to the insulating film 1 14. 14.

[0215] Subsequently, the insulating film 113 is formed. The insulating film 113 may be formed of, for example, silicon oxide, silicon oxynitride, oxynitride silicon, silicon nitride, aluminum oxide, aluminum oxynitride, oxynitride aluminum, aluminum nitride, etc., and may be provided in a laminated or single-layer form. 。The insulating film 113 can be formed, for example, by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a P ECVD method, etc.), an MBE method, an ALD method, or a PLD method. In particular, when forming a film by a CVD method, preferably a plasma CVD method, the coating property can be made good and thus it is preferable. Also, to reduce damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

[0216] Subsequently, as shown in FIG. 12(B), openings are provided in the insulating film 113, the insulating film 112, the gate insulating film 10 2, the conductive layer 104a, the conductive layer 104b, the semiconductor layer 101b, the semiconductor layer 101a, and the insulating film 114. Next, after forming a conductive film so as to fill the openings, unnecessary portions are removed using a resist mask, and the resist mask is removed to form the plug 121 and the plug 122. Here, the plug 121 is formed so as to penetrate the insulating film 113, the insulating film 112, the gate insulating film 102, the semiconductor layer 101c, the conductive layer 104a, the semiconductor layer 101b, the semiconductor layer 101a , the insulating film 114, and the barrier film 111a, and is connected to the conductive layer 151. Here, the plug 121 and the conductive layer 104a are connected by contacting each other on the side surface of the plug 121. Similarly, the plug 122 is formed so as to penetrate the insulating film 113, the insulating film 112, the gate insulating film 102, the semi conductor layer 101c, the conductive layer 104b, the semiconductor layer 101b, the semiconductor layer 101a, the insulating film 114 and the barrier film 111a, and is connected to the conductive layer 125, and the conductive layer 104b is connected by contacting the side surface of the plug 122.

[0217] Subsequently, the insulating film 116 is formed. The insulating film 116 is, for example, silicon oxide, silicon oxynitride Recon, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, etc. may be used and provided in a laminated or single-layer form. The insulating film 116 can be formed, for example, by using a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a P ECVD method, etc.), an MBE method, an ALD method, or a PLD method. When an organic insulating material such as an organic resin is used as the insulating film 116, it may be formed by a coating method such as a spin coating method. Further, after forming the insulating film 116, it is preferable to perform a planarization treatment on its upper surface. Also, as the insulating film 116, the materials and formation methods shown in the insulating film 13 8 may be used.

[0218] Subsequently, in the same manner as described above, plugs 123 that reach the plug 122 are formed in the insulating film 116.

[0219] Subsequently, a conductive film is formed on the insulating film 116. Then, a resist mask is formed in the same manner as described above, and unnecessary portions of the conductive film are removed by etching. Then, by removing the resist mask , wirings 124, etc. can be formed (see Fig. 12(B)). .

[0220] By the above steps, a semiconductor device according to one aspect of the present invention can be manufactured.

[0221] When forming the semiconductor layer 101a and the semiconductor layer 101b, after forming the conductive film 104 and forming a resist mask, after etching the conductive film 104, the semiconductor layer that becomes the semiconductor layer 101a and the semiconductor layer that becomes the semiconductor layer 101b are formed by etching, and the structure shown in Fig. 1 5(A) may be adopted. Then, the conductive film 104 is processed again to form the conductive layer 104a and​ Form the calling conductive layer 104b, and through the processes shown in FIGS. 12 to 13, the transistor 100 can have a structure as shown in FIG. 15(B).

[0222] Also, as an example of a manufacturing method of a transistor 100 having a structure different from that of the transistor 100 shown in FIG. 15(B), for the transistor 100 described in FIG. 1, an example of its manufacturing method will be briefly explained.

[0223] First, after forming a semiconductor film that will become the semiconductor layer 101 on the insulating film 114, a resist mask or the like is formed, and etching is performed to form the semiconductor layer 101. Next, an insulating film that will become the gate insulating film 102 and a conductive film that will become the gate electrode 103 are formed, a resist mask or the like is formed, and etching is performed to form the gate electrode 103 and the gate insulating film 102.

[0224] Next, the low-resistance region 171a and the low-resistance region 171b are formed. A semiconductor layer with a high carrier density has a low resistance. As a method for increasing the carrier density, for example, addition of impurities or formation of oxygen deficiency can be mentioned. For example, as a method for increasing the carrier density, ion implantation can be used to add elements. Elements that can be used include, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium ium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, german ium, arsenic, yttrium, zirconium, niobium, molybdenum, indium, tin , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and it is preferable to add one or more selected therefrom.

[0225] ​In such a low-resistance region, for example, there is a possibility of trapping unnecessary hydrogen. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region can be reduced, and good transistor characteristics can be obtained.

[0226] Next, the insulating film 112 and the insulating film 113 are formed. Then, the plugs 121 and 122 are formed by the method shown above. Through the above steps, the transistor 100 shown in FIG. 1 can be fabricated.

[0227] (Embodiment 2) In this embodiment, an oxide semiconductor suitable for use in the transistor 100 shown in Embodiment 1 will be described.

[0228] Here, as an example shown in FIG. 6, an example of using a three-layer structure of a semiconductor layer 101a, a semiconductor layer 101b, and a semiconductor layer 101c as the oxide semiconductor is shown. However, the oxide semiconductor that can be used in the transistor 100 may be a single layer. Further, the structure may not have either or both of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c.

[0229] The semiconductor layer 101b is, for example, an oxide semiconductor containing indium. When the semiconductor layer 101b contains indium, for example, the carrier mobility (electron mobility) becomes high. Further, it is preferable that the semiconductor layer 101b contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable as the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, ​​​​​​​​​​Niobium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. are included. However, as the element M, there are cases where a plurality of the aforementioned elements may be combined. There are such cases. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element whose binding energy with oxygen is higher than that of indium. Or, the element M is, for example, an element having a function of increasing the energy gap of an oxide semiconductor. Also, the semiconductor layer 1 01b preferably contains zinc. There are cases where the oxide semiconductor is likely to crystallize when it contains zinc. However, the semiconductor layer 101b is not limited to an indium-containing oxide semiconductor. The semiconductor layer 101b may be, for example, an oxide semiconductor that does not contain indium, such as zinc tin oxide or gallium tin oxide, and contains zinc, gallium, or tin. It may be any oxide semiconductor containing zinc, gallium, or tin.

[0230] However, the semiconductor layer 101b is not limited to an indium-containing oxide semiconductor. The semiconductor layer 101b may be, for example, an oxide semiconductor that does not contain indium, such as zinc tin oxide or gallium tin oxide, and contains zinc, gallium, or tin. It may be any oxide semiconductor that does not contain indium, such as zinc tin oxide or gallium tin oxide, and contains zinc, gallium, or tin. It may be any of them.

[0231] For the semiconductor layer 101b, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0232] For example, the semiconductor layers 101a and 101c are oxide semiconductors composed of one or more elements other than the elements constituting the semiconductor layer 101b. Since the semiconductor layers 101a and 101c are composed of one or more elements other than the elements constituting the semiconductor layer 101b, at the interface between the semiconductor layer 101a and the semiconductor layer 101b, and at the interface between the semiconductor layer 101c and the semiconductor layer 101b, since the semiconductor layers 101a and 101c are composed of one or more elements other than the elements constituting the semiconductor layer 101b, the interface between the semiconductor layer 101a and the semiconductor layer 101b, and At the interface between the semiconductor layer 101b and the semiconductor layer 101c, interface levels are less likely to be formed. .

[0233] The semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c preferably contain at least indium. When the semiconductor layer 101a is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. When the semiconductor layer 101b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, and M is less than 66 atomic%. When the semiconductor layer 101c is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. Note that the semiconductor layer 101c may use the same type of oxide as the semiconductor layer 101a. The semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c preferably contain at least indium. When the semiconductor layer 101a is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. When the semiconductor layer 101b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, and M is less than 66 atomic%. When the semiconductor layer 101c is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. Note that the semiconductor layer 101c may use the same type of oxide as the semiconductor layer 101a. When the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. When the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. When the semiconductor layer 101b is an In-M-Zn oxide, When the sum of In and M is 100 atomic%, preferably In is 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, and M is less than 66 atomic%. When the sum of In and M is 100 atomic%, preferably In is 25 atomic% or more, M is less than 75 atomic%, more preferably In is 34 atomic% or more, and M is less than 66 atomic%. When the semiconductor layer 101c is an In-M-Zn oxide, When the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. When the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 75 atomic% or more. Note that the semiconductor layer 101c may use the same type of oxide as the semiconductor layer 101a. Note that the semiconductor layer 101c may use the same type of oxide as the semiconductor layer 101a.

[0234] The semiconductor layer 101b uses an oxide with a larger electron affinity than the semiconductor layer 101a and the semiconductor layer 101c. For example, as the semiconductor layer 101b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than that of the semiconductor layer 101a and the semiconductor layer 101c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. The semiconductor layer 101b uses an oxide with a larger electron affinity than the semiconductor layer 101a and the semiconductor layer 101c. For example, as the semiconductor layer 101b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than that of the semiconductor layer 101a and the semiconductor layer 101c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. For example, as the semiconductor layer 101b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than that of the semiconductor layer 101a and the semiconductor layer 101c is used. For example, as the semiconductor layer 101b, an oxide with an electron affinity 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than that of the semiconductor layer 101a and the semiconductor layer 101c is used. Note that the electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band.

[0235] Note that indium gallium oxide has a small electron affinity and a high oxygen-blocking property. Therefore, it is preferable that the semiconductor layer 101c contains indium gallium oxide. The gallium atom ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more.

[0236] At this time, when an electric field is applied to the gate electrode, a channel is formed in the semiconductor layer 101b having a large electron affinity among the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c.

[0237] Here, the band structure is shown in FIG. 18(A). In FIG. 18(A), the vacuum level (denoted as vac uum level), the energy (denoted as Ec) at the lower end of the conduction band of each layer, and the energy (denoted as Ev) at the upper end of the valence band are shown.

[0238] Here, there may be a mixed region between the semiconductor layer 101a and the semiconductor layer 101b. Also, there may be a mixed region between the semiconductor layer 101b and the semiconductor layer 101 c. There may be a mixed region between the semiconductor layer 101b and the semiconductor layer 101c. The mixed region has a low interface state density. Therefore, the laminate of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c has an energy that is continuous at the vicinity of each interface (also referred to as a continuous junction) band structure. In FIG. 18(A), the case where the Ec of the semiconductor layer 101a and the second semiconductor layer 101c is the same is shown, but they may be different from each other. For example, the Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101a.

[0239] Note that in FIG. 18(A), the case where the Ec of the semiconductor layer 101a and the second semiconductor layer 101c is the same is shown, but they may be different from each other. For example, the Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101a. For example, the Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101a. For example, the Ec of the semiconductor layer 101c may have a higher energy than that of the semiconductor layer 101a.

[0240] At this time, electrons mainly move in the semiconductor layer 101b, rather than in the semiconductor layer 101a and the semiconductor layer 101c (see Fig. 18(B)). As described above, by reducing the interface level density at the interface between the semiconductor layer 101a and the semiconductor layer 101b and the interface level density at the interface between the semiconductor layer 101b and the semiconductor layer 101c, the movement of electrons in the semiconductor layer 101b is less inhibited, and the on-current of the transistor can be increased. 101b (see Fig. 18(B)). As described above, by reducing the interface level density at the interface between the semiconductor layer 101a and the semiconductor layer 101b and the interface level density at the interface between the semiconductor layer 101b and the semiconductor layer 101c, the movement of electrons in the semiconductor layer 101b is less inhibited, and the on-current of the transistor can be increased. 1a and the semiconductor layer 101b, and the interface level density at the interface between the semiconductor layer 101b and the semiconductor layer 101c, the movement of electrons in the semiconductor layer 101b is less inhibited, and the on-current of the transistor can be increased. 101c, the movement of electrons in the semiconductor layer 101b is less inhibited, and the on-current of the transistor can be increased. Therefore, the on-current of the transistor can be increased. .

[0241] When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used. When the transistor has an s-channel structure, a channel is formed throughout the semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region becomes. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, a semiconductor layer 101b having a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and even more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less may be used.

[0242] In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is preferably smaller. For example, a semiconductor layer 101c having a region with a thickness of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the semiconductor layer 101c contains an element other than oxygen (hydrogen, etc.) that constitutes the adjacent insulator, and diffuses into the semiconductor layer 101b where the channel is formed. In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is preferably smaller. For example, a semiconductor layer 101c having a region with a thickness of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the semiconductor layer 101c contains an element other than oxygen (hydrogen, etc.) that constitutes the adjacent insulator, and diffuses into the semiconductor layer 101b where the channel is formed. In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is preferably smaller. For example, a semiconductor layer 101c having a region with a thickness of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the semiconductor layer 101c contains an element other than oxygen (hydrogen, etc.) that constitutes the adjacent insulator, and diffuses into the semiconductor layer 101b where the channel is formed. In addition, in order to increase the on-current of the transistor, the thickness of the semiconductor layer 101c is preferably smaller. For example, a semiconductor layer 101c having a region with a thickness of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the semiconductor layer 101c contains an element other than oxygen (hydrogen, etc.) that constitutes the adjacent insulator, and diffuses into the semiconductor layer 101b where the channel is formed. It has a function of blocking the intrusion of substances such as silicon. Therefore, the semiconductor layer 10 1c preferably has a certain thickness. For example, a semiconductor layer 101c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more is used. In addition, the semiconductor layer 101c preferably has a property of blocking oxygen in order to suppress the outward diffusion of oxygen released from the insulating film 102 or the like.

[0243] In addition, in order to improve reliability, the semiconductor layer 101a is thick and the semiconductor layer 101c is thin which is preferable. For example, a semiconductor layer 101a having a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more is used. By increasing the thickness of the semiconductor layer 101a, the distance from the interface between the adjacent insulator and the semiconductor layer 101 a to the semiconductor layer 101b where the channel is formed can be increased. However, since the productivity of the semiconductor device may decrease, for example, a semiconductor layer 1 having a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less is used. 01a.

[0244] When the oxide semiconductor film contains a large amount of hydrogen, by combining with the oxide semiconductor, a part of the hydrogen becomes a donor and generates electrons as carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film and purify it to have as little impurities as possible.

[0245] Note that, by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, oxygen may also decrease simultaneously. Therefore, in order to compensate for the oxygen deficiency increased by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, it is preferable to perform a treatment of adding oxygen to the oxide. In this specification and the like, when supplying oxygen to the oxide semiconductor film, it may be described as an oxygen addition treatment, or when making the oxygen contained in the oxide semiconductor film more than the

[0246] stoichiometric composition, it may be described as a peroxygenation treatment. In this way, the oxide semiconductor film can be made into an oxide semiconductor film that is type-I (intrinsic) or substantially type-I (intrinsic) approaching type-I infinitely by removing hydrogen or moisture by the dehydration treatment (dehydrogenation treatment) and compensating for the oxygen deficiency by the oxygen addition treatment. 17 / cm 3 Hereinafter, 1×10 16 / cm 3 or less, 1×10 / cm 15 or less, 1×10 3 / cm 14 or less, 1×10 3 / cm 13 or less, 1×10 3 or less, and particularly preferably less than 8×10 / cm 11 / cm 3 / cm 11 / cm 3 less than 1×10 / cm 10 / cm 3 less than 1×10 -9 / cm 3 / cm or more.

[0247] In this way, a transistor including an oxide semiconductor film of type I or substantially type I can achieve extremely excellent off-current characteristics. For example, when a transistor using an oxide semiconductor film is in the off state, the drain current at room temperature (about 25 °C) is 1 × 10 -18 A or less, preferably 1 × 10 -21 A or less, more preferably 1 × 10 -24 A or less, or 1 × 10 A or less at 85 -15 °C, preferably 1 × 10 -18 A or less, more preferably 1 × 10 -21 A or less. Note that the off state of a transistor means a state where the gate voltage is sufficiently smaller than the threshold voltage in the case of an n-channel type transistor. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold voltage, the transistor is in the off state.

[0248] Hereinafter, the structure of the oxide semiconductor film will be described.

[0249] The oxide semiconductor film can be divided into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. Alternatively, the oxide semiconductor can be divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor. The non-single crystal oxide semiconductor film includes a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, etc. Also, examples of the crystalline oxide semiconductor include a single crystal oxide semiconductor, CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, etc.

[0250] First, the CAAC-OS film will be described. Note that CAAC-OS can also be called an oxide semiconductor having CANC (C -Axis Aligned nanocrystals). This is also possible.

[0251] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts (also referred to as pellets) oriented in the c-axis direction. That is one of the oxide semiconductor films having a plurality of crystal parts (also referred to as pellets) oriented in the c-axis direction.

[0252] When a composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of CAAC-OS is observed by a transmission electron microscope (TEM: Transmission Elec tron Microscope) for the CAAC-OS film, a plurality of pellets can be confirmed. On the other hand, in the high-resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as gray boundaries), cannot be clearly confirmed. Therefore, it can be said that the CAAC-O S film is less likely to cause a decrease in electron mobility due to grain boundaries. That is, it can be said that the CAAC-OS film is less likely to cause a decrease in electron mobility due to grain boundaries.

[0253] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. The metal atoms in each layer have a shape reflecting the concavity and convexity of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film. in each layer have a shape reflecting the concavity and convexity of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film. in each layer have a shape reflecting the concavity and convexity of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and are arranged parallel to the formed surface or the upper surface of the CAAC-OS film.

[0254] On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, no regularity is found in the arrangement of metal atoms between different crystal parts. However, no regularity is found in the arrangement of metal atoms between different crystal parts. However, no regularity is found in the arrangement of metal atoms between different crystal parts.

[0255] Figure 19(a) is a cross-sectional TEM image of the CAAC-OS film. Further, Figure 19(b) is a cross-sectional TEM image obtained by further magnifying Figure 19(a), and the atomic arrangement is emphasized for easy understanding.

[0256] Figure 19(c) is a local Fourier transform image of the region (diameter: about 4 nm) surrounded by a circle between A-O-A' in Figure 19(a). From Figure 19(c), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between A-O and O-A', it is suggested that they are different grains. Further, it can be seen that the angle of the c-axis changes continuously little by little such as 14.3°, 16. 6°, 26.4° between A-O. Similarly, it can be seen that the angle of the c-axis changes continuously little by little such as -18.3°, -17.6°, -15.9° between O-A '.

[0257] When electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also called nano-beam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the upper surface of the CAAC-OS film, spots are observed (see Figure 20(A)).

[0258] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystalline part of the CAAC-OS film has orientation.

[0259] Most of the crystalline parts contained in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm. Therefore, the crystalline parts contained in the CAAC-OS film have a side length of 10 This also includes cases where the size is small enough to fit within a cube of less than 1 nm, less than 5 nm, or less than 3 nm. However, when a plurality of crystal portions included in the CAAC-OS film are connected, it may form one large crystal region. For example, in a planar TEM image, a crystal region of 2500 nm or more, 5 μm 2 or more, or 1000 μm 2 or more may be observed. 2 When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD)

[0260] apparatus, for example, in the out-of-plane method analysis of a CAAC-OS film having InGaZnO 4 crystals, a peak may appear near a diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the InGaZnO crystals, it can be confirmed that the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak 4 is attributed to the (110) plane of the InGaZnO crystals. In the case of a single crystal oxide semiconductor film of InGaZnO if analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane

[0261] are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. When X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO 4 crystals. In the case of a single crystal oxide semiconductor film of InGaZnO 4 if analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed near 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. In contrast, in the case of the CAAC-OS film, no distinct peak appears even when φ scan is performed with 2θ fixed near 56°. When X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the InGaZnO crystals. In the case of a single crystal oxide semiconductor film of InGaZnO

[0262] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above-described cross-sectional TEM observation is a plane parallel to the ab plane of the crystal.

[0263] Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film.

[0264] Also, in the CAAC-OS film, the distribution of the c-axis oriented crystal parts does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the ratio of the c-axis oriented crystal parts in the region near the upper surface may be higher than that in the region near the formed surface. In addition, in the CAAC-OS film with the addition of impurities, the region where the impurities are added is altered, and regions with different ratios of partially c-axis oriented crystal parts may be formed.

[0265] Note that in the out-of-plane 4 analysis of the CAAC-OS film having InGaZnO crystals, in addition to the peak with 2θ near 31°, a peak also appears at 2θ near 36°. ​​​​​​​​​​​may occur. The peak near 36° of 2θ indicates that a part of the CAAC-OS film contains crystals without c-axis orientation. The CAAC-OS film preferably shows a peak near 31° of 2θ and does not show a peak near 36° of 2θ.

[0266] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon, deprive the oxide semiconductor film of oxygen, disrupt the atomic arrangement of the oxide semiconductor film, and reduce the crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), and when contained inside the oxide semiconductor film, they disrupt the atomic arrangement of the oxide semiconductor film and reduce the crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

[0267] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0268] A low impurity concentration and a low defect level density (few oxygen deficiencies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film with high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using the oxide semiconductor film has electrical characteristics (threshold voltage becomes negative) ​​​​​​​​It is also called "marine". It is rare for it to become "high purity genuine" or "substantially high purity". The intrinsic oxide semiconductor film has few carrier traps. Transistors using the film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0269] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0270] Figure 36(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. The observation was performed using, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. This can be done by, etc.

[0271] FIG. 36(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 36(A). From FIG. 36(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0272] As shown in FIG. 36(B), CAAC-OS has a characteristic atomic arrangement. FIG. 36(C) shows the characteristic atomic arrangement indicated by auxiliary lines. FIGS. 36(B) and 36(C) show that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap generated by the inclination between pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc).

[0273] Here, based on the Cs-corrected high-resolution TEM image, the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown, and it has a structure like bricks or blocks stacked (see FIG. 36(D)). The location where the inclination occurs between the pellets observed in FIG. 36(C) corresponds to the region 5161 shown in FIG. 36(D).

[0274] Also, FIG. 37(A) shows the Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. The enlarged Cs-corrected high-resolution TEM images of the regions (1), (2), and (3) in FIG. 37(A) are shown in FIGS. 37(B), 37(C), and FIG 37(D), respectively. From FIGS. 37(B), 37(C), and 37(D), it can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape in the pellets. However

[0275] no regularity is observed in the arrangement of the metal atoms between different pellets.

[0275] Next, CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, CAAC-OS having a crystal of InGaZnO 4 When performing structural analysis by the out-of-plane method on [the sample], as shown in Fig. 38(A), a peak may appear at around a diffraction angle (2θ) of 31°. This peak is attributed to the (009) plane of the InGaZ nO 4 crystal. Thus, it can be confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface.

[0276] In the structural analysis of CAAC-OS by the out-of-plane method, in addition to the peak around 2θ of 31°, a peak may also appear at around 2θ of 36°. The peak around 2θ of 36° indicates that a part of the CAAC-OS contains crystals without c-axis orientation. More preferable CAAC-OS shows a peak at around 2θ of 31° and does not show a peak at around 2θ of 36° in the structural analysis by the out-of-plane method.

[0277] On the other hand, when performing structural analysis by the in-plane method in which X-rays are incident on CAAC-OS from a direction substantially perpendicular to the c-axis, a peak appears at around 2θ of 56°. This peak is attributed to the (110) plane of the In GaZnO crystal. In the case of CAAC-OS, even when the analysis ( 4 φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, as shown in Fig. 38(B), no distinct peak appears. In contrast, for a single-crystalline oxide semiconductor of InGaZnO when the φ scan is performed with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in Fig. 38(C). Therefore, from the structural analysis using XRD, CAAC-OS is 4 It can be confirmed that the orientations of the a-axis and b-axis are irregular.

[0278] Next, CAAC-OS analyzed by electron diffraction will be described. For example, InGaZ nO 4 For CAAC-OS having crystals of, when an electron beam with a probe diameter of 300 nm is incident parallel to the sample surface, a diffraction pattern as shown in Fig. 39(A) (also referred to as a limited-field transmission electron diffraction pattern) may appear. This diffraction pattern includes spots due to the (009) plane of InGaZnO crystals. Therefore, it can also be seen by electron diffraction that 4 the pellets included in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. On the other hand, Fig. 39(B) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicular to the sample surface for the same sample. From Fig. 39 (B), a ring-shaped diffraction pattern is confirmed. Therefore, it can also be seen by electron diffraction that the a-axis and b-axis of the pellets included in CAAC-OS do not have orientation. Note that the first ring in Fig. 39(B) is considered to be due to the (010) plane and the (100) plane, etc. of InGaZnO crystals. Also, the second ring in Fig. 39(B) is considered to be due to the (110) plane, etc. Note that the first ring in Fig. 39(B) is considered to be due to the (010) plane and 4 the (100) plane, etc. of InGaZnO crystals. Also, the second ring in Fig. 39(B) is considered to be due to the (110) plane, etc.

[0279] Next, the polycrystalline oxide semiconductor film will be described.

[0280] In the observation image by TEM, crystal grains can be confirmed for the polycrystalline oxide semiconductor film. The crystal grains included in the poly crystalline oxide semiconductor film are, for example, 2 nm or more and 3 It is often the case that the particle size is less than 00 nm, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less. Also, in the observation image by TEM, crystal grain boundaries may be confirmed in the polycrystalline oxide semiconductor film. There are cases where it can be seen.

[0281] The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientations may be different between the plurality of crystal grains. Also, when performing structural analysis on the polycrystalline oxide semiconductor film using an XRD apparatus, for example, in the out-of-plane method analysis of the polycrystalline oxide semiconductor film having crystals of InGaZnO peaks around 2θ of 31°, peaks around 2θ of 36°, or other peaks may appear. 4 In the analysis of the out-of-plane method of the polycrystalline oxide semiconductor film having crystals of InGaZnO In the analysis by the out-of-plane method of the polycrystalline oxide semiconductor film having crystals of InGaZnO, peaks around 2θ of 31°, peaks around 2θ of 36°, or other peaks may appear. There are cases where peaks around 2θ of 31°, peaks around 2θ of 36°, or other peaks may appear.

[0282] Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the crystal grain boundaries of the polycrystalline oxide semiconductor film. Also, the crystal grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the crystal grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using a polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film. a transistor using a polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film. There are cases where it becomes a transistor with large fluctuations in electrical characteristics and low reliability.

[0283] Next, the microcrystalline oxide semiconductor film will be described.

[0284] In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film. The crystal part contained in the microcrystalline oxide semiconductor film is 1 nm or more and 100 nm or less. It is often the case that the size is less than or 1 nm or more and 10 nm or less. In particular, 1 nm or more and 10 n m or less, or a nanocrystal (nc: nanocryst tal) that is a microcrystal of 1 nm or more and 3 nm or less has an oxide semiconductor film called an nc-OS (nanocrystalline O xide Semiconductor) film. Further, the nc-OS film may not clearly confirm grain boundaries in an observation image by, for example, T EM. Note that the nanocrystal may have the same origin as the pellet in CAAC-OS. Therefore, hereinafter the crystal part of nc-OS may be called a pellet.

[0285] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, the nc-OS film has no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film. Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film in some cases. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part (pellet), no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Further, for the nc-OS film, when electron diffraction (also called limited field of view electron diffraction) using an electron beam with a probe diameter larger than that of the pellet (for example, 50 nm or more) is performed, a diffraction pattern such as a halo pattern is observed. On the other hand, when nano-beam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the pellet is performed on the nc-OS film, spots are observed. Further, when nano beam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the pellet is performed on the nc-OS film, spots are observed. Also, when nano beam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the pellet is performed on the nc-OS film, spots are observed. Also, when nano When performing beam electron diffraction, there are cases where a region with high luminance is observed in a circular (ring-shaped) pattern. Furthermore, there are cases where a plurality of spots are observed within the ring-shaped region (see Fig. 20 (B)).

[0286] Since there is no regularity in the crystal orientation among the pellets (nanocrystals) in this way, nc- OS can also be referred to as an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals ).

[0287] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However, there is no regularity in the crystal orientation among different crystal parts in the nc-OS film. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film.

[0288] Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore, a transistor using the nc-OS film may have a high field-effect mobility. Also, since the nc-OS film has a higher density of defect levels than the CAAC-OS film, there may be more carrier traps. Therefore, a transistor using the nc-OS film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using the CAAC- OS film. However, the nc-OS film can be formed even when it contains relatively many impurities. Since it can be formed, it is easier to form than the CAAC-OS film and can be suitably used depending on the application. There are cases where this is possible. Therefore, a semiconductor device having a transistor using the nc-OS film may be manufactured with high productivity.

[0289] Next, the amorphous oxide semiconductor film will be described.

[0290] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and has no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

[0291] In the observation image by TEM, the crystal part cannot be confirmed in the amorphous oxide semiconductor film.

[0292] When performing structural analysis on the amorphous oxide semiconductor film using an XRD apparatus, no peak indicating a crystal plane is detected in the out-of- plane method. Also, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Also, when nano-beam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed. is observed.

[0293] The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. Also, the amorphous oxide semiconductor film is an oxide semiconductor film having a high density of defect levels.

[0294] An oxide semiconductor film having a high impurity concentration and a high density of defect levels is an oxide semiconductor film having many carrier traps and carrier generation sources.

[0295] Therefore, the amorphous oxide semiconductor film has a higher carrier density than the nc-OS film. This may occur. Therefore, a transistor using an amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Accordingly, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, a transistor using an amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. on electrical characteristics. Thus, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, a transistor using an amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. Since the amorphous oxide semiconductor film has a high density of defect levels, there may be many carrier traps. Therefore, a transistor using an amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. a transistor using an amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film. a transistor using an amorphous oxide semiconductor film has larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film or an nc-OS film.

[0296] Note that the oxide semiconductor film may have a structure that exhibits physical properties between those of an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film. Note that the oxide semiconductor film may have a structure that exhibits physical properties between those of an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film. iconductor) film. iconductor) film.

[0297] Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed. Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed. Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed. Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed. Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed. Voids may be observed in the high-resolution TEM image of the a-like OS film. Also, in the high-resolution TEM image, there are regions where a crystal part can be clearly confirmed and regions where a crystal part cannot be confirmed. The a-like OS film may undergo crystallization and growth of the crystal part due to a small amount of electron irradiation during observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization due to a small amount of electron irradiation during observation by TEM is hardly observed.

[0298] Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO has a layered structure. Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO has a layered structure. 4 Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO has a layered structure. , There are two Ga-Zn-O layers between the In-O layers. InGaZnO 4 The unit cell of the crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers that are stacked in a layered structure in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice plane spacing of the (009) plane (also referred to as the d-value). From crystal structure analysis, the value is determined to be 0.29 n m. Therefore, focusing on the lattice fringes in the high-resolution TEM image, where the distance between the lattice fringes is between 0.28 nm and 0.30 nm, each lattice fringe corresponds to the a-b plane of the In GaZnO crystal. 4 Since it has a relaxation, the a-like OS has an unstable structure. Below, it is shown that the a-like

[0299] OS is an unstable structure compared to the CAAC-OS and nc-OS. To show that the a-like OS is an unstable structure compared to the CAAC-OS and nc-OS, the change in structure due to electron irradiation is shown.

[0300] As samples for electron irradiation, a-like OS (denoted as sample A), nc-OS ( denoted as sample B), and CAAC-OS (denoted as sample C) are prepared. All of the samples are In-Ga-Zn oxides.

[0301] First, high-resolution cross-sectional TEM images of each sample are obtained. From the high-resolution cross-sectional TEM images, it can be seen that each sample has a crystalline part.

[0302] Note that the determination of which part is regarded as one crystalline part can be performed as follows. For example, InGaZnO 4 The unit cell of the crystal is known to have three In-O layers and six Ga-Zn-O layers, for a total of nine layers that are stacked in a layered structure in the c-axis direction. The distance between adjacent layers of them is about the same as the lattice plane spacing of the (009) plane (also referred to as the d value). And from crystal structure analysis, the value is determined to be 0.29 nm. Therefore, the positions where the lattice fringe spacing is between 0.28 nm and 0.30 nm can be regarded as the crystal part of InGaZnO 4 . Note that the lattice fringe corresponds to the a-b plane of the InGaZnO 4 crystal.

[0303] Figure 40 shows an example of investigating the average size of the crystal parts (from 22 to 45 locations) of each sample . However, the length of the above-mentioned lattice fringe is regarded as the size of the crystal part. From Figure 40, it can be seen that the a-like OS shows that the crystal part grows as the cumulative electron irradiation dose increases. Specifically , as shown by (1) in Figure 40, at the initial stage of observation by TEM, the crystal part (also referred to as the initial nucleus) with a size of about 1.2 nm grows to a size of about 2.6 nm when the cumulative irradiation dose is 4.2×10 8 e - / nm 2 . On the other hand, for nc-OS and CAAC-OS, it can be seen that there is no change in the size of the crystal part in the range from the start of electron irradiation to a cumulative electron irradiation dose of 4.2×10 8 e - / nm 2 . Specifically, as shown by (2) and (3) in Figure 40, regardless of the cumulative electron irradiation dose, the sizes of the crystal parts of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm respectively .

[0304] Thus, for a-like OS, crystal part growth may be observed by electron irradiation ​On the other hand, it can be seen that nc-OS and CAAC-OS hardly show crystal growth by electron irradiation. That is, it can be understood that a-like OS has an unstable structure compared to nc-OS and CAAC-OS. Moreover, since a-like OS has looseness, it has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. Also, oxide semiconductor films may have different densities depending on the structure. For example, if the composition of an oxide semiconductor film is known, its structure can be estimated by comparing it with the density of a single crystal of the same composition. For example, the density of an a-like OS film is 78.6% or more and less than 92.3% of the density of a single crystal. Also, for example, the density of an nc-OS film and the density of a CAAC-OS film are 92.3% or more and less than 100% of the density of a single crystal. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0305] Moreover, since a-like OS has looseness, it has a lower density structure compared to nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. Also, the density of nc-OS and the density of CAAC-OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. -OS are 92.3% or more and less than 100% of the density of a single crystal of the same composition. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself. An oxide semiconductor with a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0306] Also, oxide semiconductor films may have different densities depending on the structure. For example, if the composition of an oxide semiconductor film is known, its structure can be estimated by comparing it with the density of a single crystal of the same composition. For example, by comparing with the density of a single crystal of the same composition, the structure of the oxide semiconductor film can be estimated. For example, the density of an a-like OS film is 78.6% or more and less than 92.3% of the density of a single crystal. Also, for example, the density of an nc-OS film and the density of a CAAC-OS film are 92.3% or more and less than 100% of the density of a single crystal. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself. For example, the density of an a-like OS film is 78.6% or more and less than 92.3% of the density of a single crystal. Also, for example, the density of an nc-OS film and the density of a CAAC-OS film are 92.3% or more and less than 100% of the density of a single crystal. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself. Also, for example, the density of an nc-OS film and the density of a CAAC-OS film are 92.3% or more and less than 100% of the density of a single crystal. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself. For example, the density of an nc-OS film and the density of a CAAC-OS film are 92.3% or more and less than 100% of the density of a single crystal. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself. An oxide semiconductor film with a density less than 78% of the density of a single crystal is difficult to form a film itself.

[0307] The above will be described using specific examples. For example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure is 6.357 g / cm³. Therefore, for example, In:Ga:Zn = 1:1: In an oxide semiconductor film satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a single crystal InGaZnO having a rhombohedral crystal structure is 6.357 g / cm³. Therefore, for example, In:Ga:Zn = 1:1: 4 The density of a single crystal InGaZnO having a rhombohedral crystal structure is 6.357 g / cm³. Therefore, for example, In:Ga:Zn = 1:1: 3 1 and the density of the single crystal InGaZnO is 6.357 g / cm³. Therefore, for example, In:Ga:Zn = 1:1: In an oxide semiconductor film satisfying 1 [atomic ratio], the density of the a-like OS film is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Further, for example, in an oxide semiconductor film satisfying In:Ga:Zn = 1:1 :1 [atomic ratio], the density of the nc-OS film and the density of the CAAC -OS film are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0308] Note that there may be no single crystal with the same composition. In that case, by combining single crystals with different compositions at an arbitrary ratio, the density corresponding to a single crystal with a desired composition can be calculated . The density of a single crystal with a desired composition may be calculated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to calculate the density by combining as few types of single crystals as possible . . .

[0309] Next, the single crystal oxide semiconductor film will be described

[0310] The single crystal oxide semiconductor film is an oxide semiconductor film with a low impurity concentration and a low density of defect levels (low oxygen deficiency ). Therefore, the carrier density can be lowered. Accordingly, a transistor using a single crystal oxide semiconductor film is less likely to have normally-on electrical characteristics . Also, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect levels, the number of carrier traps may be reduced . Accordingly, a transistor using a single crystal oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor . .

[0311] Note that an oxide semiconductor film has a higher density when it has fewer defects. Also, an oxide semiconductor film Higher crystallinity results in higher density. Also, the oxide semiconductor film has a low impurity concentration such as hydrogen and higher density. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. Also , the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. Also, the polycrystalline oxide semi conductor film has a higher density than the microcrystalline oxide semiconductor film. Also, the microcrystalline oxide semiconductor film has a higher density than the non crystalline oxide semiconductor film.

[0312] Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C AAC-OS film.

[0313] <Film formation model> Hereinafter, an example of the film formation models of CAAC-OS and nc-OS will be described.

[0314] FIG. 41(A) is a schematic diagram of a film formation chamber in which CAAC-OS is formed by a sputtering method.

[0315] The target 5130 is adhered to the backing plate. A plurality of magnets are arranged at a position facing the target 5130 through the backing plate. A magnetic field is generated by the plurality of magnets. The sputtering method that uses the magnetic field of the magnets to increase the film formation speed is called the magnetron sputtering method.

[0316] The substrate 5120 is arranged to face the target 5130, and the distance d (also referred to as the target-substrate distance (T-S distance).) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. Most of the film formation chamber is filled with a film formation gas (for example, an acid A mixed gas containing nitrogen, argon, or oxygen at a ratio of 5% by volume or more) fills the space, and the pressure is controlled to be 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here , by applying a voltage of a certain level or more to the target 5130, discharge starts and plasma is confirmed . Note that a high-density plasma region is formed by a magnetic field near the target 5130 . In the high-density plasma region, the film-forming gas is ionized to generate ions 5101 . The ions 5101 are, for example, positive ions of oxygen (O + ) or positive ions of argon (A r + ), etc

[0317] . Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains contains a cleavage plane. In FIG. 42(A), as an example, the structure of the crystal of InGaZnO contained in the target 5130 is shown . Note that FIG. 42(A) shows the structure when observing the crystal of InGaZnO in the direction parallel to the b-axis . From FIG. 42(A), it can be seen that in two adjacent Ga-Zn-O layers, oxygen atoms in each layer are arranged at a short distance 4 . And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent Ga-Zn-O layers. As a result, the crystal of InGaZnO has a cleavage plane between two adjacent Ga-Zn-O layers 4 . From FIG. 42(A), it can be seen that in two adjacent Ga-Zn-O layers, oxygen atoms in each layer are arranged at a short distance . And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent Ga-Zn-O layers. As a result, the crystal of InGaZnO has a cleavage plane between two adjacent Ga-Zn-O layers . And since oxygen atoms have a negative charge, a repulsive force is generated between two adjacent Ga-Zn-O layers. As a result, the crystal of InGaZnO has a cleavage plane between two adjacent 4 Ga-Zn-O layers . The ions 5101 generated in the high-density plasma region are accelerated toward the target 5130 by an electric field and eventually collide with the target 5130. At this time, from the cleavage plane, a flat plate shape or a pellet

[0318] . The ions 5101 generated in the high-density plasma region are accelerated toward the target 5130 by an electric field and eventually collide with the target 5130. At this time, from the cleavage plane, a flat plate shape or a pellet is formed Pellets 5100a and 5100b, which are sputter particles in the form of flakes, are detached and ejected. Note that the structures of pellets 5100a and 5100b may be distorted by the impact of ion 5101 collisions. When ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side.

[0319] Pellet 5100a is a sputter particle in the form of a flat plate or pellet having a triangular, for example, equilateral triangular plane. Also, pellet 5100b is a sputter particle in the form of a flat plate or pellet having a hexagonal, for example, regular hexagonal plane. Note that sputter particles in the form of flat plates or pellets such as pellets 5100a and 5100b are collectively referred to as pellet 5100. The shape of the plane of pellet 5100 is not limited to a triangle or a hexagon. For example, it may be a shape in which a plurality of triangles are combined. For example, it may be a quadrilateral (for example, a rhombus) formed by combining two triangles (for example, equilateral triangles). Pellet 5100 is determined in thickness according to the type of film-forming gas and the like. Although the reason will be described later, it is preferable that the thickness of pellet 5100 is uniform. Also, it is more preferable that the sputter particles are in the form of pellets without thickness than in the form of thick dice. For example, pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 above. For example, when ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side. Pellet 5100 is determined in thickness according to the type of film-forming gas and the like. Although the reason will be described later, it is preferable that the thickness of pellet 5100 is uniform. Also, it is more preferable that the sputter particles are in the form of pellets without thickness than in the form of thick dice. For example, pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 above. For example, when ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side.

[0320] Pellet 5100 is determined in thickness according to the type of film-forming gas and the like. Although the reason will be described later, it is preferable that the thickness of pellet 5100 is uniform. Also, it is more preferable that the sputter particles are in the form of pellets without thickness than in the form of thick dice. For example, pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 above. For example, when ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side. Pellet 5100 is determined in thickness according to the type of film-forming gas and the like. Although the reason will be described later, it is preferable that the thickness of pellet 5100 is uniform. Also, it is more preferable that the sputter particles are in the form of pellets without thickness than in the form of thick dice. For example, pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Also, for example, pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably 1.2 nm or more and 2.5 nm or less. Pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 above. For example, when ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side. Pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 above. For example, when ion 5101 collides with target 5130 having In-Ga-Zn oxide, as shown in FIG. 42(B), a Ga-Zn-O layer, In-Ga-Zn oxide layer, and In-Ga-O layer are formed in this order from the substrate side. The pellet 5100 having three layers of an In-O layer and Ga-Zn-O layers peels off. FIG. 42 (C) shows the structure of the peeled pellet 5100 observed from a direction parallel to the c-axis. The pellet 5100 has a sandwich structure having two Ga-Zn-O layers (bread) and an In-O layer (filling), which can also be called a nano-sized sandwich structure.

[0321] When the pellet 5100 passes through the plasma, its side surface may be negatively or positively charged. For example, the oxygen atoms located on the side surface of the pellet 5100 may be negatively charged. Due to the side surfaces having charges of the same polarity, repulsion between the charges occurs, making it possible to maintain a flat plate-like or pellet-like shape. When the CAAC-OS is an In-Ga-Zn oxide, the oxygen atoms bonded to indium atoms may be negatively charged. Or, the oxygen atoms bonded to indium atoms, gallium atoms, or zinc atoms may be negatively charged. Also, when the pellet 5100 passes through the plasma, it may grow by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. in the plasma. The difference in size between (2) and (1) in FIG. 40 mentioned above corresponds to the growth component in the plasma. Here, when the substrate 5120 is at about room temperature, the growth of the pellet 5100 on the substrate 5120 is unlikely to occur, resulting in nc-OS (see FIG. 41(B)). Since film formation can be carried out at about room temperature, nc-OS film formation is possible even when the substrate 5120 has a large area. Note that in order to grow the pellet 5100 in the plasma, it is effective to increase the film formation power in the sputtering method. By increasing the film formation power, the structure of the pellet 5100 can be stabilized. ​​​​​​​​

[0322] As shown in FIGS. 41(A) and 41(B), for example, pellet 5100 flies like a kite in the plasma and floats gently up to the substrate 5120. Since pellet 51 00 is charged, a repulsive force is generated when approaching an area where other pellets 5100 have already been deposited . Here, on the upper surface of the substrate 5120, a magnetic field (also referred to as a horizontal magnetic field) parallel to the upper surface of the substrate 5120 is generated . Also, a potential difference is applied between the substrate 5120 and the target 51 30, so a current flows from the substrate 5120 toward the target 5130 . Therefore, pellet 5100 receives a force (Lorentz force) on the upper surface of the substrate 5120 due to the action of the magnetic field and the current. This can be understood by Fleming's left-hand rule .

[0323] Pellet 5100 has a larger mass compared to a single atom. Therefore, it is important to apply some force externally to move on the upper surface of the substrate 5120. One of such forces may be the force generated by the action of the magnetic field and the current. In order to apply sufficient force to pellet 5100 to move on the upper surface of the substrate 5120, on the upper surface of the substrate 5120, a magnetic field parallel to the upper surface of the substrate 5120 should be 10 G or more, preferably 20 G or more, more preferably 30 G or more, and even more preferably 50 G or more. Alternatively, on the upper surface of the substrate 5120, a region where the magnetic field parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more of the magnetic field perpendicular to the upper surface of the substrate 5120 should be provided .

[0324] ​​​​At this time, the magnet and the substrate 5120 move relative to each other or rotate, so that the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 can receive forces from various directions and move in various directions.

[0325] Also, when the substrate 5120 is heated as shown in Fig. 41(A), the resistance due to friction or the like between the pellet 5100 and the substrate 5120 is in a small state. As a result, the pellet 5100 moves so as to glide on the upper surface of the substrate 5120. The movement of the pellet 5100 occurs with the flat plate surface facing the substrate 5120. After that, when it reaches the side surfaces of other pellets 5100 that have already been deposited, the side surfaces bond to each other. At this time, the oxygen atoms on the side surfaces of the pellet 510 0 desorb. Since the oxygen vacancies in the CAAC-OS may be filled by the desorbed oxygen atoms, CAAC-OS with a low density of defect levels is obtained. Note that the temperature of the upper surface of the substrate 5120 may be, for example, 100°C or higher and less than 500°C, 150°C or higher and less than 450°C, or 170°C or higher and less than 400°C. Therefore, even when the substrate 5120 has a large area, it is possible to form CAAC-OS.

[0326] Also, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, and the strain in the structure caused by the collision of the ions 5101 is relaxed. The pellet 51 00 with the relaxed strain becomes almost a single crystal. Since the pellet 5100 becomes almost a single crystal, even if it is heated after the pellets 5100 are bonded to each other, almost no expansion or contraction of the pellet 5100 itself can occur. Therefore, the grain boundaries do not widen due to the widening of the gaps between the pellets 5100.​​​ It does not form defects such as boundaries or crevasse formation.

[0327] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between the pellets 5100. The CAAC-OS was deformed, such as shrinking, due to heating during film formation, heating after film formation, or bending. Even in cases where the material is not fully deformed, it is possible to relieve local stress or release strain. This structure is suitable for use in flexible semiconductor devices. The resulting arrangement resembles randomly stacked nanocrystals.

[0328] When the target 5130 is sputtered by ions 5101, not only the pellet 5100 but also However, zinc oxide may peel off. Zinc oxide is lighter than pellet 5100, so Therefore, it will reach the upper surface of the substrate 5120 first. A zinc oxide layer 5102 having a thickness of 0.5 nm to 2 nm is formed. A schematic cross-sectional view is shown in Figure 43.

[0329] As shown in FIG. 43(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, it slides on pellet 5105b. In another aspect of 5a, a plurality of particles 5103 detached from the target along with zinc oxide. is crystallized by heating from the substrate 5120 to form the region 5105a1. Note that a plurality of particles 5103 may contain oxygen, zinc, indium, gallium, etc.

[0330] Then, as shown in FIG. 43(B), the region 5105a1 is integrated with the pellet 5105a to become the pellet 5105a2. Also, the pellet 5105c is arranged such that its side surface contacts another side surface of the pellet 5 105b.

[0331] Next, as shown in FIG. 43(C), after the pellet 5105d is further deposited on the pellet 5105a2 and on the pellet 5105b, it moves so as to slide on the pellet 5105a2 and on the pellet 51 05b. Also, it moves further so as to slide on the zinc oxide layer 5102 toward another side surface of the pellet 5105c.

[0332] Then, as shown in FIG. 43(D), the pellet 5105d is arranged such that its side surface contacts the side surface of the pellet 510 5a2. Also, the pellet 5105e is arranged such that its side surface contacts another side surface of the pellet 51 05c. Also, on another side surface of the pellet 5105d, a plurality of particles 5103 peeled off from the target 5130 together with zinc oxide are crystallized by heating from the substrate 5120 to form the region 5105d1.

[0333] As described above, the deposited pellets are arranged so as to contact each other, and growth occurs on the side surfaces of the pellets, whereby CAAC-OS is formed on the substrate 5120. Therefore, CAAC -OS has larger individual pellets than nc-OS. The difference in size between (3 ) and (2) in FIG. 40 described above corresponds to the growth amount after deposition. ​​​

[0334] In addition, since the gaps between the pellets become extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm or more and 200 nm or less, 15 nm or more and 100 nm or less, or 20 nm or more and 50 nm or less when viewed from the top surface. At this time, in the oxide semiconductor used for a fine transistor, the channel formation region may be contained in one large pellet. That is, the region having a single crystal structure can be used as the channel formation region. In addition, as the pellet becomes larger, the region having a single crystal structure may be used as the channel

[0335] formation region, the source region, and the drain region of the transistor. In this way, by forming the channel formation region of the transistor and the

[0336] like in a region having a single crystal structure, the frequency characteristics of the transistor may be improved. Based on the above model, it is considered that the pellets 5100 are deposited on the substrate 5120. Even when the surface to be formed does not have a crystal structure, since the CAAC-OS film can be formed, it can be seen that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not

[0337] require laser crystallization and can form a uniform film even on a large-area It can be seen that the pellets 5100 are arranged along the shape. For example, on the upper surface of the substrate 5120 When it is flat at the atomic level, the pellets 5100 are juxtaposed with the flat plate surface, which is a plane parallel to the a-b plane, facing down If the thickness of the pellets 5100 is uniform, a layer with uniform thickness, flatness, and high crystallinity is formed. Then, by stacking n layers (n is a natural number) of such layers, CAAC-OS can be obtained.

[0338] On the other hand, even when the upper surface of the substrate 5120 has irregularities, CAAC-OS has a structure in which n layers (n is a natural number) of layers where the pellets 510 0 are juxtaposed along the irregularities are stacked. Because the substrate 51 20 has irregularities, there are cases where gaps are likely to occur between the pellets 5100. However, even in this case, intermolecular forces act between the pellets 5100, and they are arranged so that the gaps between the pellets are as small as possible despite the irregularities. Therefore, even with irregularities, CAAC-OS with high crystallinity can be obtained.

[0339] Since CAAC-OS is formed by such a model, it is preferable that the sputter particles are in the form of pellets without thickness. When the sputter particles are in the form of thick dice, the surface facing the substrate 5120 may not be constant, and it may not be possible to make the thickness and crystal orientation uniform.

[0340] According to the film formation model shown above, even on a surface to be formed having an amorphous structure, CAAC-OS having high crystallinity can be obtained.

[0341] When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nano-beam electron diffraction. ​​​​​​

[0342] Figure 20(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. The camera 618 is installed facing the fluorescent plate 632, and it is possible to photograph the pattern that appears on the fluorescent plate 632. The angle formed by the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern photographed by the camera 618. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 618 may be installed in the film chamber 622 in some cases. For example, Figure 20(C) shows a transmission electron diffraction measurement apparatus having an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, a sample chamber 614 below the optical system 612, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. Note that the film chamber 622 may not be provided. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured.

[0343] Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured.

[0344] Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. Figure 20(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in Figure 20(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto a substance 628 disposed in the sample chamber 614 through the optical system 612. The electrons that have passed through the substance 628 enter a fluorescent plate 632 installed inside the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a pattern corresponding to the intensity of the incident electrons appears, and thus a transmission electron diffraction pattern can be measured. , install the camera 618 in the film chamber 622 so as to face the incident direction of the electrons 624 is also possible. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 632 .

[0345] In the sample chamber 614, a holder for fixing the substance 628 as a sample is installed. The holder has a structure that allows electrons passing through the substance 628 to pass through. The holder may, for example have a function of moving the substance 628 in the X-axis, Y-axis, Z-axis, etc. The moving function may have an accuracy of moving, for example, in the range of 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc. These ranges may be set to the optimal range depending on the structure of the substance 628.

[0346] Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measuring apparatus will be described.

[0347] For example, as shown in FIG. 20(D), by changing (scanning) the irradiation position of the electrons 624 which are nano-beams in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 20(A) is observed. Or, if the substance 628 is an nc-OS film, a diffraction pattern as shown in FIG. 20( B) is observed.

[0348] By the way, even if the substance 628 is a CAAC-OS film, a diffraction pattern similar to that of the nc-OS film partially may be observed. Therefore, the quality of the CAAC-OS film is sometimes represented by the ratio of the area where the diffraction pattern of the CAAC-OS film in a certain range is observed (also referred to as the CA AC conversion rate). For example, for a high-quality CAAC-OS film , the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90 % or more, and even more preferably 95% or more. Note that the ratio of the area where a diffraction pattern different from that of the CAAC-OS film is observed is denoted as the non-CAAC conversion rate.

[0349] As an example, for the upper surface of each sample having a CAAC-OS film immediately after film formation (denoted as as-sputtered) or after heat treatment at 450 °C in an oxygen-containing atmosphere , a transmission electron diffraction pattern was obtained while scanning. Here, the diffraction pattern was observed while scanning at a speed of 5 nm / second for 60 seconds, and the observed diffraction pattern was converted into still images every 0.5 seconds to derive the CAAC conversion rate. Note that a nano-beam electron beam with a probe diameter of 1n m was used as the electron beam. The same measurement was performed on 6 samples. And for the calculation of the CA AC conversion rate, the average value of the 6 samples was used. The CAAC conversion rate of each sample is shown in Fig. 21(A). The C

[0350] AAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (non-CAAC conversion rate was 24.3%). Also, the CAAC conversion rate of the CAAC-OS film after heat treatment at 450 °C was 85.3% (non-CAAC conversion rate was 14.7%) . It can be seen that the CAAC conversion rate after heat treatment at 450 °C is higher than that immediately after film formation. That is, it can be seen that by heat treatment at a high temperature (for example, 400 °C or higher), the non-CAAC conversion rate decreases (the CAAC conversion rate increases). Also, in heat treatment below 500 °C ​​​​It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained even with

[0351] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The pattern was a folded pattern. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment could not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the neighboring domains influences the rearrangement of the CAAC domain. .

[0352] 21(B) and 21(C) show the CAAC- 21(B) and 21(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the 50°C heat treatment has a more homogeneous film quality. It can be seen that the film quality of the CAAC-OS film is improved by the heat treatment at a low temperature.

[0353] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0354] The CAAC-OS film can be formed, for example, by the following method.

[0355] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The film is formed by sputtering using the RF sputtering method, D The oxide semiconductor film can be formed by a C sputtering method, an AC sputtering method, or the like. In order to improve the uniformity of the distribution, film composition distribution, or crystallinity distribution, It is more preferable to use DC sputtering or AC sputtering.

[0356] By increasing the substrate temperature during film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the film is formed with the substrate temperature being 100°C or higher and 740°C or lower, preferably 200°C or higher and 500°C or lower. By increasing the substrate temperature during film formation, when sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate. At this time, since the sputtering particles are positively charged, the sputtering ring particles adhere to the substrate while repelling each other, so that the sputtering particles do not accumulate unevenly and a CAAC-OS film with uniform thickness can be formed.

[0357] By reducing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the concentration of impurities in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0358] Further, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30 vol% or higher, preferably 100 vol%.

[0359] Alternatively, the CAAC-OS film is formed by the following method.

[0360] First, a first oxide semiconductor film is formed with a thickness of 1 nm or more and less than 10 nm. The first oxide semiconductor film is formed using a sputtering method. Specifically, the substrate temperature is 100°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower, and the oxygen ratio in the film formation gas is 30 It is formed into a film with a volume percentage of [X]% or more, preferably 100% by volume.

[0361] Next, a heat treatment is performed to convert the first oxide semiconductor film into a highly crystalline first CAAC-OS film The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650 °C or lower. Also, the time of the heat treatment is 1 minute or longer and 24 hours or shorter, preferably 6 minutes or longer and 4 hours or shorter. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after performing the heat treatment in an inert atmosphere, the heat treatment is performed in an oxidizing atmosphere. By the heat treatment in an inert atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies may be generated in the first oxide semiconductor film by the heat treatment in an inert atmosphere. In that case, the oxygen vacancies can be reduced by the heat treatment in an oxidizing atmosphere. Note that the heat treatment may be performed under a reduced pressure of 1000 Pa or lower, 100 Pa or lower, 10 Pa or lower, or 1 Pa or lower. Under reduced pressure, the impurity concentration of the first oxide semiconductor film can be reduced in an even shorter time.

[0362] When the thickness of the first oxide semiconductor film is 1 nm or more and less than 10 nm, it can be more easily crystallized by heat treatment than when the thickness is 1

[0363] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed with a thickness of 10 nm or more and 5 0 nm or less. The second oxide semiconductor film is formed by a sputtering method. Specifically, the substrate temperature is 100°C or higher and 500°C or lower, preferably 150°C or higher and 450 °C or lower, and the oxygen ratio in the film-forming gas is 30% by volume or more, preferably 100% by volume, and it is formed Form a film.

[0364] Next, perform a heat treatment to cause solid-phase growth of the second oxide semiconductor film from the first CAAC-OS film to obtain a second CAAC-OS film with high crystallinity. The temperature of the heat treatment is 350 °C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. Also, the time of the heat treatment is 1 minute or longer and 24 hours or shorter, preferably 6 minutes or longer and 4 hours or shorter. Also, the heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after performing the heat treatment in an inert atmosphere the heat treatment is performed in an oxidizing atmosphere. By the heat treatment in an inert atmosphere, the impurity concentration of the second oxide semiconductor film can be reduced in a short time. On the other hand, oxygen deficiency may be generated in the second oxide semiconductor film by the heat treatment in an inert atmosphere. In that case, the oxygen deficiency can be reduced by the heat treatment in an oxidizing atmosphere. Note that the heat treatment may be performed under a reduced pressure of 1 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be further reduced in a shorter time .

[0365] As described above, a CAAC-OS film having a total thickness of 10 nm or more can be formed.

[0366] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0367] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one aspect of the present invention will be described with reference to the drawings.

[0368] [Example of Circuit Configuration] In the configuration shown in Embodiment 1, various circuits can be configured by varying the connection configurations of transistors, wirings, and electrodes. Hereinafter, examples of circuit configurations that can be realized by using the semiconductor device of one aspect of the present invention will be described.

[0369] 〔CMOS Circuit〕 The circuit diagram shown in FIG. 22(A) shows the configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. In the figure, transistors to which the second semiconductor material is applied are indicated with the symbol "OS".

[0370] 〔Analog Switch〕 The circuit diagram shown in FIG. 22(B) shows a configuration in which the sources and drains of transistor 2100 and transistor 2200 are connected. By adopting such a configuration, it can function as a so-called analog switch.

[0371] 〔Example of Memory Device〕 An example of a semiconductor device (memory device) that can hold stored content even when power is not supplied and has no limit on the number of write operations by using a transistor which is one aspect of the present invention is shown in FIG. 22.

[0372] The semiconductor device shown in FIG. 22(C) has a transistor 3200 using the first semiconductor material, a transistor 3300 using the second semiconductor material, and a capacitor element 3400. As the transistor 3300, the transistors exemplified in the above embodiment can be used.

[0373] In this embodiment, as the transistor 3300, an example is shown in which a transistor having a semiconductor layer with an oxide semiconductor and having a channel formed therein is used. Since the off-current of the transistor 3300 is small, by using this transistor, it is possible to retain the stored content for a long time. That is, it is possible to realize a semiconductor memory device that does not require a refresh operation or requires a very low frequency of refresh operation, and thus the power consumption can be sufficiently reduced.

[0374] In FIG. 22(C), the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. Also, the third wiring 3003 is electrically connected to one of the source electrode or the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. Then, the gate electrode of the transistor 3200 and the other of the source electrode or the drain electrode of the transistor 3300 are electrically connected to one of the electrodes of the capacitor element 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor element 3400.

[0375] In the semiconductor device shown in FIG. 22(C), by taking advantage of the feature that the potential of the gate electrode of the transistor 3200 can be held, information can be written, held, and read out as follows.

[0376] Explanation will be made about the writing and holding of information. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, and the transistor 3300 is turned on. ​​​​​​​​​​​​​​​This causes the potential of the third wiring 3003 to be applied to the gate electrode of the transistor 3200 and to the capacitor element 3400. That is, a predetermined charge is applied to the gate electrode of the transistor 3200 (write). Here, either of two different potential level charges (hereinafter referred to as Low level charge and High level charge) is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is in the off state, and the transistor 3300 is turned off, so that the charge applied to the gate electrode of the transistor 3200 is held (hold). Since the off-current of the transistor 3300 is extremely small, the charge on the gate electrode of the transistor 3200 is held for a long time.

[0377]

[0378] Next, the reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 while a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 takes different potentials according to the amount of charge held on the gate electrode of the transistor 3200. Generally, when the transistor 3200 is an n-channel type, the apparent threshold value V when a High level charge is applied to the gate electrode of the transistor 3200 is lower than the apparent threshold value V when a Low level charge is applied to the gate electrode of the transistor 3200. Here, the apparent threshold voltage means the potential of the fifth wiring 3005 required to turn the transistor 3200 "on state". Therefore, the potential of the fifth wiring 3005 is V th_ H th_L th_H and V th_L ​​​​​​​​​​​between the potential V 0 By setting it like this, the charge applied to the gate electrode of the transistor 3200 can be determined For example, in writing, when a High-level charge is applied, the potential of the fifth wiring 3005 is V 0 (>V th_H ) and then the transistor 3200 will be in the " on state". When a Low-level charge is applied, the potential of the fifth wiring 3005 is V 0 (<V th_L ) and even so, the transistor 3200 remains in the "off state" Therefore, by discriminating the potential of the second wiring 3002, the stored information can be read out.

[0379] Note that when the memory cells are arranged and used in an array, it is necessary to be able to read only the information of the desired memory cell. If the information is not read like this, a potential such that the transistor 3200 becomes in the "off state" regardless of the state of the gate electrode, that is, a potential smaller than V th_ H can be applied to the fifth wiring 3005. Or, a potential such that the transistor 3200 becomes in the "on state" regardless of the state of the gate electrode, that is, a potential larger than V th_L can be applied to the fifth wiring 3005. th_L more larger can be applied to the fifth wiring 3005.

[0380] The semiconductor device shown in Fig. 22(D) mainly differs from Fig. 2 2(C) in that the transistor 3200 is not provided. Also in this case, writing and holding operations of information are possible by the same operation as above .

[0381] Next, the reading of information will be described. When the transistor 3300 becomes in the on state, The third wiring 3003 in a floating state conducts with the capacitor element 3400, and the third wiring 3003 and the capacitor element 3400 redistribute charges. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 depends on the potential of one of the electrodes of the capacitor element 3400 (or the charge stored in the capacitor element 3400) and takes different values.

[0382] For example, if the potential of one of the electrodes of the capacitor element 3400 is V, the capacitance of the capacitor element 3400 is C, and the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge redistribution is VB0, then the potential of the third wiring 3003 after charge redistribution is (CB ×VB0 + C×V) / (CB + C). Therefore, assuming that the potential of one of the electrodes of the capacitor element 3400 takes two states of V1 and V0 (V1 > V0) as the state of the memory cell, it can be seen that the potential of the third wiring 3003 when holding the potential V1 (= (CB×VB0 + C×V1 )) / (CB + C)) is higher than the potential of the third wiring 3003 when holding the potential V0 (= ( CB×VB0 + C×V0) / (CB + C)). And by comparing the potential of the third wiring 3003 with a predetermined potential, information can be read. ) / (CB + C)) is higher than the potential of the third wiring 3003 when holding the potential V0 (= ( CB×VB0 + C×V0) / (CB + C)).

[0383] Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

[0384] In this case, a transistor in which the above first semiconductor material is applied to a drive circuit for driving the memory cell can be used, and a transistor in which the second semiconductor material is applied as the transistor 3300 can be stacked and provided on the drive circuit. In the semiconductor device shown in this embodiment, an off - transistor using an oxide semiconductor in the channel formation region is used, and a transistor in which the second semiconductor material is applied as the transistor 3300 is stacked and provided on the drive circuit.

[0385] In the semiconductor device shown in this embodiment mode, an off - transistor using an oxide semiconductor in the channel formation region ​By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0386] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating film does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single operation, high speed operation can be easily achieved.

[0387] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0388] (Embodiment 4) In this embodiment, an example of a semiconductor device including a transistor according to one embodiment of the present invention will be described. FIG. 29 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Here is one example.

[0389] The semiconductor device shown in FIG. 29 includes a capacitor 660a, a capacitor 660b, and a transistor 661a, transistor 661b, transistor 662a, and transistor 662b and inverter 663a, inverter 663b, wiring BL, wiring BLB, and wiring W L, wiring CL, and wiring GL.

[0390] The semiconductor device shown in FIG. 29 is a memory cell in which inverters 663a and 663b are connected in a ring to form a flip - flop. The node from which the output signal of inverter 663b is output is designated as node VN1, and the node from which the output signal of inverter 663a is output is designated as node VN2. By arranging the memory cells in a matrix, a storage device (memory cell array) can be configured. One of the source and drain of transistor 662a is electrically connected to wiring BL, and the other of the source and drain is electrically connected to node VN1, and the gate is electrically connected to wiring WL. One of the source and drain of transistor 662b is electrically connected to node VN2, and the other of the source and drain is electrically connected to wiring BLB, and the gate is electrically connected to wiring WL.

[0391] One of the source and drain of transistor 661a is electrically connected to node VN1, and the other of the source and drain is electrically connected to one electrode of capacitor element 660a, and the gate is electrically connected to wiring GL. Here, the node between the other of the source and drain of transistor 661a and one electrode of capacitor element 660a is designated as node NVN1. One of the source and drain of transistor 661b is electrically connected to node VN2, and the other of the source and drain is electrically connected to one electrode of capacitor element 660b, and the gate is electrically connected to wiring GL. continues.

[0392] ​​​​​​​​​ Connect. Here, the other of the source and drain of the transistor 661b and the capacitor element 660 Let the node between one electrode of b be the node NVN2.

[0393] The other electrode of the capacitor element 660a is electrically connected to the wiring CL. The other of the capacitor element 660b The other electrode is electrically connected to the wiring CL.

[0394] The selection of the conductive state and non-conductive state of the transistors 662a and 662b can be controlled by the potential applied to the wiring WL. The selection of the conductive state and non-conductive state of the transistors 661a and tra nsistor 661b can be controlled by the potential applied to the wiring GL. to do.

[0395] The writing, holding, and reading of the memory cell shown in FIG. 29 will be described below.

[0396] At the time of writing, first, a potential corresponding to data 0 or data 1 is applied to the wiring BL and the wiring BLB. to apply.

[0397] For example, when data 1 is to be written, the wiring BL is set to the high-level power supply potential (VDD), the wiring BLB is set to the ground potential. Next, a potential (VH) obtained by adding VDD to the threshold voltage of the transistors 662a and transistors 6 62b is applied to the wiring WL.

[0398] Next, by setting the potential of the wiring WL to be less than the threshold voltages of the transistors 662a and 662b, the data 1 written in the flip-flop is held.

[0399] At the time of reading, the wiring BL and the wiring BLB are set to VDD in advance. Next, the wiring WL By applying VH, the wiring BL remains unchanged at VDD, while the wiring BLB discharges through the transistor 662a and the inverter 663a and becomes the ground potential. The potential difference between this wiring BL and the wiring BLB is amplified by a sense amplifier (not shown), and the stored data 1 can be read out.

[0400] When writing data 0, the wiring BL is set to the ground potential and the wiring BLB is set to VDD. Then, VH can be applied to the wiring WL. Next, by setting the potential of the wiring WL to be lower than the threshold voltages of the transistors 662 a and 662b, the written data 0 in the flip - flop is retained. When reading, the wirings BL and BLB are set to VDD in advance, and by applying VH to the wiring WL, the wiring BLB remains unchanged at VDD, while the wiring BL discharges through the transistor 662b and the inverter 663b and becomes the ground potential. The potential difference between this wiring BL and the wiring BLB is amplified by a sense amplifier, and the stored data 0 can be read out. Therefore, the semiconductor device shown in FIG. 29 functions as a so - called SRAM (Static Random

[0401] Access Memory). Since the SRAM uses flip - flops to hold data, a refresh operation is not required. Therefore, the power consumption during data retention can be suppressed. Also, since no capacitive elements are used in the flip - flops, it is suitable for applications that require high - speed operation. In addition, the semiconductor device shown in FIG. 29 is connected from the node VN1 through the transistor 661a. to

[0402] ​It is possible to write data to node NVN1. Similarly, data can be written from node VN2 to node NVN2 via transistor 661b. The written data is retained by setting transistor 661a or transistor 661b to the non-conductive state. For example, even when the supply of the power potential is stopped, the data of node VN1 and node VN2 may be retained. Unlike a conventional SRAM in which data is immediately lost when the supply of the power potential is stopped, the semiconductor device shown in FIG. 29 can retain data even after the supply of the power potential is stopped. Therefore, a semiconductor device with low power consumption can be realized by appropriately turning the power potential on or off. For example, by using the semiconductor device shown in FIG. 29 in the storage area of the CPU, the power consumption of the CPU can also be reduced.

[0403]

[0404] Note that the period during which data is retained in node NVN1 and node NVN2 is found to vary depending on the off-currents of transistor 661a and transistor 661b. Therefore, in order to lengthen the data retention period, transistors with low off-current may be used for transistor 661a and transistor 661b. Or, the capacitances of capacitor element 660a and capacitor element 660b may be increased.

[0405] For example, if the transistor 100 and capacitor element 150 shown in Embodiment 1 are used as transistor 661a and capacitor element 660a, it becomes possible to retain data in node NVN1 over a long period. Similarly, the transistor 100 and capacitor element 150 ​​​​​​​​​​​​​​If transistors 661b and capacitor element 660b are used, data can be retained at node NVN2 for a long period. Therefore, for transistors 661a and 661b, reference may be made to the description of transistor 100. Also, for capacitor elements 660a and 660b, reference may be made to the description of capacitor element 150.

[0406] Also, as described in the above embodiment, by using plug 121 and plug 122 in transistor 100, the occupied area of elements including transistor 100 and capacitor element 150 can be reduced. For transistors 661a, 661 b, capacitor element 660a, and capacitor element 660b shown in FIG. 29, transistor 100 and capacitor element 150 described in the above embodiment can be used. Therefore, the semiconductor device shown in FIG. 29 can be manufactured without significantly increasing the occupied area compared to a conventional SRAM. For the transistors included in transistors 662a, 662b, inverter 663a, and the transistors included in inverter 663b, reference may be made to the description of transistor 130.

[0407] As shown above, it can be seen that the semiconductor device according to one aspect of the present invention has high performance with respect to the occupied area. Also, it can be seen that it is a highly productive semiconductor device.

[0408] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0409] (Embodiment 5) In this embodiment, the R including the transistor or the memory device exemplified in the above embodiment will be described with reference to FIG. 23 for the RF tag.

[0410] The RF tag in this embodiment has a memory circuit inside, stores the necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Due to such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article. Since it has such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article. Since it has such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article. Since it has such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article. Since it has such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article. Since it has such characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading the individual information of the article or the like. Note that extremely high reliability is required for use in these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article.

[0411] The configuration of the RF tag will be described with reference to FIG. 23. FIG. 23 is a block diagram showing a configuration example of the RF tag. The configuration of the RF tag will be described with reference to FIG. 23. FIG. 23 is a block diagram showing a configuration example of the RF tag.

[0412] As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader / writer, etc.). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor showing a rectifying action included in the demodulation circuit 807. By this, a decrease in the rectifying action caused by the reverse current can be suppressed, and saturation of the output of the demodulation circuit can be prevented. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linearity. It is possible. The data transmission format is roughly classified into three types: an electromagnetic coupling method in which a pair of coils are arranged opposite to each other and communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. The RF tag 800 shown in this embodiment can be used in any of these methods. Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 between the antenna 802 connected to the communicator 801. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal by a capacitive element provided in the subsequent stage to generate an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain level to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of the stable power supply voltage. The demodulation circuit 807 is a circuit for demodulating by envelope detection of the input AC signal and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

[0413] Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 between the antenna 802 connected to the communicator 801. Also, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal by a capacitive element provided in the subsequent stage to generate an input potential. The rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal with the antenna 804, for example, half-wave double voltage rectification, and smooths the rectified signal by a capacitive element provided in the subsequent stage to generate an input potential. For example, half-wave double voltage rectification, and smooths the rectified signal by a capacitive element provided in the subsequent stage to generate an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain level to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain level to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large. The limiter circuit is a circuit for controlling so as not to input power exceeding a certain level to the subsequent stage circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

[0414] The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of the stable power supply voltage. The reset signal generation circuit is a circuit for generating a reset signal for the logic circuit 809 using the rise of the stable power supply voltage.

[0415] The demodulation circuit 807 is a circuit for demodulating by envelope detection of the input AC signal and generating a demodulated signal. Also, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804. The modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

[0416] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds the input information, and has a row decoder, a column decoder, a memory area, etc. Also, the ROM 811 is a circuit for storing unique numbers (IDs), etc., and outputting according to the processing.

[0417] Note that each of the above circuits can be appropriately selected or discarded as necessary.

[0418] Here, the memory circuit described in the previous embodiment can be used as the memory circuit 810. Since the memory circuit according to one aspect of the present invention can hold information even when the power is cut off, it can be suitably used for an RF tag. Further, since the memory circuit according to one aspect of the present invention requires significantly less power (voltage) for writing data than conventional non-volatile memories, it is also possible not to cause a difference in the maximum communication distance between the read and write operations of the data. Furthermore, it is possible to suppress the occurrence of malfunction or miswriting due to insufficient power during data writing.

[0419] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory, so it can also be applied to the ROM 811. In that case, it is preferable for the manufacturer to prepare a separate command for writing data to the ROM 811 and prevent t...

Claims

1. A first transistor; A second transistor; and A capacitive element; A first insulating film; A second insulating film; A third insulating film; A first conductive layer; and a second conductive layer; the first insulating film has a region located above a gate electrode of the first transistor, the second insulating film has a region located above the first insulating film, the third insulating film has a region located above the second insulating film, the first conductive layer has a region located above the third insulating film, the first terminal and the second terminal of the capacitance element have a region located above the third insulating film; the first terminal and the second terminal of the capacitive element have regions located below a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; the second conductive layer penetrates a semiconductor in which the second transistor is formed, and is constantly in electrical contact with the first conductive layer.

2. A first transistor; A second transistor; and A capacitive element; A first insulating film; A second insulating film; A third insulating film; A first conductive layer; and A second conductive layer; and a third conductive layer; the first insulating film has a region located above a gate electrode of the first transistor, the second insulating film has a region located above the first insulating film, the third insulating film has a region located above the second insulating film, the first conductive layer has a region located above the third insulating film, the first terminal and the second terminal of the capacitance element have a region located above the third insulating film; the first terminal and the second terminal of the capacitive element have regions located below a channel formation region of the second transistor; a source electrode or a drain electrode of the second transistor is always electrically connected to a first terminal or a second terminal of the capacitance element; the third conductive layer has a region located above a channel formation region of the second transistor, the second conductive layer penetrates a semiconductor in which the second transistor is formed and is always electrically connected to the first conductive layer; The third conductive layer is always electrically connected to the second conductive layer.

3. In claim 1 or 2, A semiconductor device, wherein a channel formation region of the first transistor has single crystal silicon.

4. In any one of claims 1 to 3, the first insulating film includes oxygen and silicon; the second insulating film includes nitrogen and silicon; The third insulating film comprises oxygen and silicon.

5. In any one of claims 1 to 4, The semiconductor device, wherein the third insulating film is a planarizing film.

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