Electronic display using three-dimensional wiring

Abstract

To inhibit luminance unevenness and diminish the number of points which require external voltage application by electrically interconnecting lines which are divided and arranged on a back of a substrate.SOLUTION: On a back of a substrate of an electronic display 1, an adhesive layer-inclusive insulating film 32 is formed at a predetermined point of a power line 14' to cover the predetermined point. A conducting adhesive layer-inclusive metal foil 31 is formed at predetermined points of respective ground lines 13'-1 and 13'-2 and a predetermined point of the adhesive layer-inclusive insulating film 32 to cover the predetermined points. Accordingly, the ground lines 13'-1 and 13'-2 are electrically interconnected owing to the conducting adhesive layer-inclusive metal foil 31. The power line 14' is electrically isolated from the ground lines 13'-1 and 13'-2 owing to the adhesive layer-inclusive insulating film 32.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an electronic display using three-dimensional wiring. [Background technology]

[0002] Conventionally, a tiling display configured by arranging a plurality of panel units has been known (see, for example, Non-Patent Documents 1 and 2). A tiling display has an advantage that it can realize various sizes, shapes, and aspect ratios.

[0003] However, in the case of a typical panel unit, it is necessary to form signal lines and the like on the periphery, and it is difficult to eliminate the bezel provided on the periphery. Therefore, when panel units are arranged in a tiled display, there is a problem that the bezel makes the seams between the panel units stand out.

[0004] To solve this problem, a structure is envisaged in which signal lines etc. are taken out to the back side of the panel unit using three-dimensional wiring that passes through through holes. This structure eliminates the need to form signal lines etc. on the periphery of the panel unit, making it possible to realize a bezel-less panel unit and enabling seamless, unnoticeable tiling.

[0005] As a core technology for realizing such a bezel-less panel unit, a TFT (Thin Film Transistor) (three-dimensional wiring TFT) has been developed that uses an extremely thin polyimide (PI) film substrate and can be driven by three-dimensional wiring passing through holes from the back side of the film substrate (see, for example, non-patent document 3).

[0006] FIG. 8 is a diagram showing an example of a schematic structure of the front surface side of a substrate of an electronic display and an example of the arrangement of each element that constitutes a pixel circuit, showing a structure using three-dimensional wiring formed on a film substrate as viewed from the front surface side of the substrate.

[0007] 8, the electronic display 100 is configured with M×N pixel circuits 99 arranged in an array in the vertical and horizontal directions, where M and N are integers of 2 or more.

[0008] The pixel circuit 99 is configured to include a signal line (front side signal line) 11, a scanning line (front side scanning line) 12, a ground line (front side ground line) 13, a power line (front side power line) 14, a storage capacitor 15, a selection TFT 21, a driving TFT 22, and a light emitting element (such as an LED) 23. The pixel circuit 99 is a circuit for driving the light emitting element 23 using the selection TFT 21 and the driving TFT 22. Note that Fig. 8 shows only components related to the present invention, and components not directly related to the present invention are omitted.

[0009] Specifically, the pixel circuit 99 includes three light-emitting elements 23, and a selection TFT 21, a driving TFT 22, a storage capacitor 15, a signal line 11, etc. are formed corresponding to each of the three light-emitting elements 23. In addition, a scanning line 12, a ground line 13, a power supply line 14, etc. are formed in common to the three light-emitting elements 23.

[0010] Three signal lines 11 in the vertical direction, one scanning line 12 in the horizontal direction, one ground line 13 in the horizontal direction, and one power supply line 14 in the horizontal direction are formed in one pixel circuit 99. In other words, an electronic display 100 having M×N pixel circuits 99 has 3×N signal lines 11 in the vertical direction, M scanning lines 12 in the horizontal direction, M ground lines 13 in the horizontal direction, and M power supply lines 14 in the horizontal direction.

[0011] Fig. 9 is an example of a circuit diagram of the pixel circuit 99 shown in Fig. 8. In this pixel circuit 99, the signal line 11 is connected to the drain electrode D of the selection TFT 21, and the scanning line 12 is connected to the gate electrode G of the selection TFT 21. The ground line 13 is connected to the source electrode S of the drive TFT 22 and one electrode of the storage capacitor 15, and the power line 14 is connected to the anode of the light-emitting element 23.

[0012] Furthermore, the source electrode S of the selection TFT 21, the gate electrode G of the drive TFT 22 and the other electrode of the storage capacitor 15 are connected, and the cathode of the light emitting element 23 and the drain electrode D of the drive TFT 22 are connected.

[0013] Fig. 10 is a schematic diagram showing an example of the cross-sectional structure of a pixel circuit including a TFT that can be driven by three-dimensional wiring. This pixel circuit 99' is intended to explain the main part of the example of the cross-sectional structure of the pixel circuit 99 shown in Fig. 8. Therefore, the TFTs shown by dotted lines in Fig. 10 correspond to the selection TFT 21 and the drive TFT 22 shown in Figs. 8 and 9, but the connections of the electrodes do not accurately reflect the circuit diagram shown in Fig. 9, but are merely shown in outline.

[0014] This pixel circuit 99' has a laminated structure in which an undercoat film 105, an insulating film 104, a protective film 102, etc. are formed on the front side of a film substrate 101, and a planarizing layer 106, etc. are formed on the back side. The film substrate 101 is, for example, a polyimide (PI) substrate, and various resin (plastic) substrates can be used depending on the application, etc.

[0015] In addition, in this pixel circuit 99', a planarizing layer 106 is formed under the film substrate 101, but there are cases where the planarizing layer 106 is not formed.

[0016] In addition, in this pixel circuit 99', a gate electrode 107 is formed above the base film 105, a source electrode 108 and a drain electrode 109 are formed above the insulating film 104 and the semiconductor layer 103, and wirings 110-1, 110-2, and 110-3 are formed below the planarization layer 106.

[0017] Each of the wirings 110-1, 110-2, and 110-3 corresponds to any one of the signal lines (rear-side signal lines) 11'-1 and 11'-2, scanning lines (rear-side scanning lines) 12'-1 and 12'-2, ground lines (rear-side ground lines) 13'-1 and 13'-2, and power lines (rear-side power lines) 14' arranged on the rear side of the substrate, as shown in FIG. 11, which will be described later.

[0018] In addition, this pixel circuit 99' is provided with through holes 111-1 and 111-3 that pass through the insulating film 104, the base film 105, the film substrate 101 and the planarization layer 106, and a through hole 111-2 that passes through the base film 105, the film substrate 101 and the planarization layer 106.

[0019] Within through hole 111-1, three-dimensional wiring 112-1 is formed for electrically connecting drain electrode 109 and wiring 110-1, within through hole 111-2, three-dimensional wiring 112-2 is formed for electrically connecting gate electrode 107 and wiring 110-2, and within through hole 111-3, three-dimensional wiring 112-3 is formed for electrically connecting source electrode 108 and wiring 110-3.

[0020] The through holes 111-1, 111-2, and 111-3 are collectively referred to as the through holes 111, and the three-dimensional wirings 112-1, 112-2, and 112-3 are collectively referred to as the three-dimensional wiring 112.

[0021] 8 to 10, in a pixel circuit 99 constituting an electronic display 100, a selection TFT 21, a driving TFT 22 and a light-emitting element 23 formed on the front side of the substrate need to be driven from the rear side of the substrate using three-dimensional wiring 112 passing through a through hole 111.

[0022] Therefore, it is necessary to form four types of wiring, namely, a signal line 11', a scanning line 12', a ground line 13' and a power line 14', on the rear surface of the substrate of the electronic display 100, and connect them to the signal line 11, the scanning line 12, the ground line 13 and the power line 14 on the front surface of the substrate using three-dimensional wiring 112 passing through through holes 111.

[0023] In other words, in order to drive the selection TFT 21, the driving TFT 22, and the light-emitting element 23 provided in the pixel circuit 99 on the front surface of the substrate of the electronic display 100, the respective wiring for connecting to the signal line 11, etc. on the front surface of the substrate must be formed on the back surface of the substrate.

[0024] However, when four types of wiring, namely, signal line 11', scanning line 12', ground line 13', and power line 14', are formed on the rear surface of the substrate of electronic display 100, overlaps will occur between the respective wirings (e.g., signal line 11' and scanning line 12'). The same applies to signal line 11' and ground line 13', and signal line 11' and power line 14'. If the respective wirings are shorted (electrically connected), accurate signals cannot be sent to the respective pixel circuits 99.

[0025] As a first method to solve this problem, it is possible to multiply the layers (wiring layers) forming the four types of wiring into two or more layers and form an insulating layer between each wiring layer. This can prevent short circuits between the wiring, but it complicates the structure and manufacturing process of the electronic display 100.

[0026] A second method for solving the above problem is to divide and arrange the four types of wiring on the back side of the substrate (see, for example, Non-Patent Document 4 and Patent Application Publication No. 2023-050657, which was made by the same applicant and inventor of this patent application and was unpublished at the time of filing this patent application). This eliminates overlap between the wirings and allows the wiring layer on the back side of the substrate to be formed as a single layer, thereby simplifying the structure and manufacturing process of the electronic display 100. [Prior art documents] [Non-patent literature]

[0027] [Non-Patent Document 1] D. Nakamura et al., SID 2015 DIGEST, pp.1031-1034 (2015) [Non-Patent Document 2] G. Biwa et al., SID 2019 DIGEST, pp.121-124 (2019) [Non-Patent Document 3] H.Tsuji et al., Proceedings of the 28th International Display Workshops (IDW '21), p.143 (2021) [Non-Patent Document 4] H.Tsuji et al., Proceedings of the 29th International Display Workshops (IDW '22), p.1055 (2022) Summary of the Invention [Problem to be solved by the invention]

[0028] However, when the four types of wiring are arranged separately on the back surface of the board, it may be necessary to divide the ground line 13' or the power line 14' into two depending on the wiring arrangement method.

[0029] FIG. 11 is a diagram for explaining an example of the arrangement and cross-sectional structure when the ground line 13' and the like are divided into two on the back surface side of the substrate of the electronic display 100. In FIG.

[0030] The electronic display 100 is 3 cm square, has a resolution of 133 ppi, has 160 x 160 pixels, and has a pixel size of 190 μm square. On the rear surface of the substrate of the electronic display 100, four types of wiring, namely, a signal line 11', a scanning line 12', a ground line 13', and a power line 14', are formed on the same plane, but the ground line 13' is divided into two near the center of the electronic display 100 and arranged as ground lines 13'-1 and 13'-2. Similarly, the signal line 11' and the scanning line 12' are arranged as signal lines 11'-1 and 11'-2 and scanning lines 12'-1 and 12'-2. The same applies to FIG. 1 described later.

[0031] 11, on the rear surface of the substrate of electronic display 100, 3×N signal lines 11'-1 and 11'-2 are formed, which are split into two, corresponding to the 3×N signal lines 11 formed on the front surface of the substrate as shown in Fig. 8. The 3×N signal lines 11'-1 and 11'-2 on the rear surface of the substrate are connected to the 3×N signal lines 11 on the front surface of the substrate via three-dimensional wiring 112 that passes through the corresponding through holes 111.

[0032] Also, on the rear surface side of the substrate, M scanning lines 12'-1 and 12'-2 divided into two are formed corresponding to the M scanning lines 12 formed on the front surface side of the substrate shown in Fig. 8. The M scanning lines 12'-1 and 12'-2 on the rear surface side of the substrate are connected to the M scanning lines 12 on the front surface side of the substrate via three-dimensional wiring 112 passing through the corresponding through holes 111.

[0033] Furthermore, on the rear surface side of the substrate, electrodes of two divided ground lines 13'-1 and 13'-2 are formed corresponding to the M ground lines 13 formed on the front surface side of the substrate shown in Fig. 8. The electrodes of the two ground lines 13'-1 and 13'-2 on the rear surface side of the substrate are connected to the M ground lines 13 on the front surface side of the substrate via three-dimensional wiring 112 passing through the respective through holes 111.

[0034] Also, on the rear surface side of the substrate, an electrode of one power line 14' is formed corresponding to the M power lines 14 formed on the front surface side of the substrate shown in Fig. 8. The electrode of one power line 14' on the rear surface side of the substrate is connected to the M power lines 14 on the front surface side of the substrate via three-dimensional wiring 112 passing through the respective through holes 111.

[0035] In an example of a cross-sectional structure at the dotted line α3-1 shown near the end of the ground line 13'-1 on the left side of Figure 11, the ground line 13'-1 is laminated and formed on the back side of the film substrate 101, as shown on the right side of Figure 11.

[0036] In addition, the cross-sectional structure example shown on the right side of Figure 11 shows the cross-sectional structure example shown in Figure 10 viewed upside down, and corresponds to an example in which no planarization layer 106 is formed below the film substrate 101.

[0037] Similarly, at the location of dotted line α3-2 shown near the end of the ground line 13'-2, the ground line 13'-2 is formed on the back surface of the film substrate 101. Similarly, at the location of dotted line β3 shown near the center of the power supply line 14', the power supply line 14' is formed on the back surface of the film substrate 101.

[0038] 11, when the ground line 13' is divided into two ground lines 13'-1 and 13'-2 on the rear side of the substrate of the electronic display 100, the voltage at the divided portion of the ground lines 13'-1 and 13'-2 becomes discontinuous. This causes a problem of uneven brightness in the light-emitting element 23. The same applies when the power line 14' is divided into two.

[0039] Furthermore, if power line 14' is divided into two, power lines 14'-1 and 14'-2, the same problem occurs in that brightness becomes uneven. Furthermore, there is also the problem that the number of components increases because it is necessary to apply voltage from outside to the two power lines 14'-1 and 14'-2.

[0040] The present invention has been made to solve the above-mentioned problems, and its object is to provide an electronic display that electrically connects wiring that is arranged separately on the back side of a substrate. [Means for solving the problem]

[0041] In order to solve the above problem, the electronic display of claim 1 has a plurality of pixel circuits arranged in a vertical and horizontal array, and drives the TFTs and light-emitting elements of the pixel circuits formed on the front side of the substrate via three-dimensional wiring that passes through holes from signal lines, scanning lines, ground lines, and power lines formed on the rear side of the substrate, wherein one of the ground lines and the power lines is a first wiring and the other is a second wiring, and the second wiring is divided and arranged on the rear side of the substrate, an adhesive layer and an insulating film are formed at predetermined locations of the first wiring so as to cover the predetermined locations, and a conductive adhesive layer and a metal foil are formed at predetermined locations of the second wiring and the insulating film so as to cover these predetermined locations, and all of the divided second wirings are electrically connected by the conductive adhesive layer and the metal foil, and the first wiring and all of the second wirings are electrically insulated by the insulating film.

[0042] The electronic display of claim 2 is characterized in that, in the electronic display of claim 1, the conductive adhesive layer and the metal foil are metal foil having a conductive adhesive layer, the adhesive layer and the insulating film are insulating film having an adhesive layer, all of the second wiring and the insulating film are adhered to the conductive adhesive layer, and the first wiring is adhered to the adhesive layer. Effect of the Invention

[0043] As described above, according to the present invention, wiring that is arranged separately on the rear surface side of the substrate of an electronic display can be electrically connected.

[0044] For example, if a ground line is divided and arranged, by electrically connecting these lines, the voltage at the divided points will not be discontinuous, and as a result, there will be no uneven brightness in the light-emitting elements of the electronic display. The same applies to power lines.

[0045] In addition, for example, by electrically connecting power lines that are arranged in separate parts, there is no need to apply voltage from the outside to multiple points; it is enough to apply it to one point, so the number of components does not increase. [Brief description of the drawings]

[0046] [Figure 1] 1 is a diagram showing an example of the arrangement of wiring etc. on the back side of a substrate in an electronic display according to an embodiment of the present invention. [Diagram 2] (1) is a diagram showing an example of a cross-sectional structure around a first ground line arranged in a divided manner, (2) is a diagram showing an example of a cross-sectional structure around a power line, and (3) is a diagram showing an example of a cross-sectional structure around a second ground line arranged in a divided manner. [Diagram 3] 14(4) is a diagram showing an example of a cross-sectional structure around the first and second ground lines and the power supply line that are arranged separately. FIG. [Figure 4] 1A to 1C are diagrams illustrating an example of a manufacturing process for an electronic display according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a diagram illustrating the continuation of FIG. 4. [Figure 6] FIG. 13 is a diagram showing an example of the arrangement of wiring etc. on the back surface of the substrate in an electronic display in which an insulating film with an adhesive layer is formed on the power line in process P507. [Figure 7] 1A is a diagram showing an example of a cross-sectional structure around first and second ground lines arranged separately, and FIG. 1B is a diagram showing an example of a cross-sectional structure around a power line. [Figure 8] 1A and 1B are diagrams illustrating an example of a schematic structure of the front surface side of a substrate of an electronic display and an example of the arrangement of each element constituting a pixel circuit. [Figure 9] 2 is an example of a circuit diagram of a pixel circuit. [Figure 10] 1 is a schematic diagram showing an example of a cross-sectional structure of a pixel circuit including a TFT that can be driven by three-dimensional wiring. [Figure 11] 1A to 1C are diagrams illustrating examples of arrangement and cross-sectional structure when a ground line, etc. is divided into two on the back surface side of the substrate of an electronic display. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The electronic display of the present invention is characterized in that, on the rear side of the substrate, an adhesive layer and an insulating film are formed so as to cover a part of a first wiring (e.g., a power line) arranged in one region, a conductive adhesive layer and a metal foil are formed so as to cover a part of a second wiring (e.g., a ground line) arranged in a plurality of regions and a part of the insulating film, all the second wirings are electrically connected by the conductive adhesive layer and the metal foil, and the first wirings and all the second wirings are insulated by the insulating film.

[0048] This makes it possible to electrically connect all of the second wirings arranged separately on the rear surface side of the substrate of the electronic display while being insulated from the first wirings.

[0049] [Electronic Display] First, the arrangement and structure of four types of wiring (signal lines, scanning lines, ground lines, and power lines) on the back side of the substrate of the electronic display according to the embodiment of the present invention, the metal foil with a conductive adhesive layer, and the insulating film with an adhesive layer will be described. The structure of the front side of the substrate of the electronic display is as shown in FIG.

[0050] Fig. 1 is a diagram showing an example of the arrangement of wiring etc. on the back side of the substrate of an electronic display according to an embodiment of the present invention. On the back side of the substrate of this electronic display 1, signal lines 11'-1 and 11'-2 divided and arranged in two regions, scanning lines 12'-1 and 12'-2 divided and arranged in two regions, ground lines 13'-1 and 13'-2 divided and arranged in two regions, and a power line 14' arranged in one region are formed, corresponding to the signal line 11, scanning line 12, ground line 13 and power line 14 formed on the front side of the substrate shown in Fig. 8.

[0051] The arrangement of these signal lines 11'-1, 11'-2, scanning lines 12'-1, 12'-2, ground lines 13'-1, 13'-2 and power line 14' is similar to the arrangement of the signal lines 11'-1, 11'-2, etc. formed on the rear side of the substrate of the electronic display 100 shown in Figure 11.

[0052] The area in which these wirings are arranged is one of the areas obtained by dividing the same plane on the back side of the substrate into multiple areas, as shown in Fig. 11, and these wirings do not overlap with each other. In other words, when the electronic display 1 is viewed from the back side of the substrate, the signal lines 11'-1, 11'-2, the scanning lines 12'-1, 12'-2, the ground lines 13'-1, 13'-2, and the power line 14' do not overlap with each other in wirings of different types and wirings of the same type.

[0053] An insulating film 32 with an adhesive layer is formed at a predetermined location near the center of the power line 14' on the rear surface of the substrate of the electronic display 1. Furthermore, metal foil 31 with a conductive adhesive layer is formed at predetermined locations of the ground lines 13'-1 and 13'-2 and at predetermined locations of the insulating film 32 with an adhesive layer so as to cover these predetermined locations (see FIG. 3(4) described later).

[0054] FIG. 2(1) is a diagram showing an example of a cross-sectional structure around a first ground line 13'-1 that is arranged separately, and shows the cross-sectional structure of the portion of dotted line α1-1 in FIG.

[0055] This cross-sectional structure example shows the cross-sectional structure example shown in Fig. 10 viewed upside down, and corresponds to an example in which the planarizing layer 106 is not formed under the film substrate 101. The same applies to Figs. 2(2) and (3), Fig. 3(4), and Figs. 7(1) and (2) described later.

[0056] 2(1), a metal foil 31 with a conductive adhesive layer, which is made of a metal foil 31a and a conductive adhesive layer 31b, is laminated on an upper surface 41 (the upper surface when viewed in the figure) of a ground line 13'-1 on a film substrate 101. An upper surface 41 and one side surface 42 of the ground line 13'-1, and an upper surface 43 of the film substrate 101 are adhered to the conductive adhesive layer 31b.

[0057] FIG. 2(2) is a diagram showing an example of a cross-sectional structure around the power supply line 14', and shows the cross-sectional structure of the portion of dotted line β1 in FIG.

[0058] As shown in FIG. 2(2), on the upper surface 44 of the power line 14′ on the film substrate 101, an insulating film 32 with an adhesive layer, which is composed of an insulating film 32a and an adhesive layer 32b, and a metal foil 31 with a conductive adhesive layer, which is composed of a metal foil 31a and a conductive adhesive layer 31b, are laminated in this order.

[0059] An upper surface 44 and both side surfaces 45, 46 of the power line 14' and an upper surface 47 of the film substrate 101 are adhered to the adhesive layer 32b. In addition, an upper surface 48 of the insulating film 32a constituting the adhesive-layer-attached insulating film 32 is adhered to the conductive adhesive layer 31b.

[0060] FIG. 2(3) is a diagram showing an example of a cross-sectional structure around the second ground line 13'-2 that is arranged separately, and shows the cross-sectional structure of the portion of dotted line α1-2 in FIG.

[0061] 2(3), similarly to FIG. 2(1), a metal foil 31 with a conductive adhesive layer, which is made of a metal foil 31a and a conductive adhesive layer 31b, is laminated on an upper surface 49 of the ground line 13'-2 on the film substrate 101. The upper surface 49 and one side surface 50 of the ground line 13'-2, and an upper surface 51 of the film substrate 101 are adhered to the conductive adhesive layer 31b.

[0062] Here, the metal foil 31 with a conductive adhesive layer shown in Figure 1 and Figures 2 (1), (2) and (3) is a single component, and the insulating film 32 with an adhesive layer shown in Figure 1 and Figure 2 (2) is also a single component.

[0063] FIG. 3(4) is a diagram showing an example of a cross-sectional structure around the first and second ground lines 13'-1 and 13'-2 and the power line 14', which are arranged separately, and shows the cross-sectional structure of the portion of dotted line γ1 in FIG.

[0064] The cross-sectional structure example around the power line 14' shown in Fig. 3(4) has the same structure as the cross-sectional structure example around the power line 14' shown in Fig. 2(2). As shown in Fig. 1, the cross-sectional structure example shown in Fig. 3(4) by dotted line γ1 is obtained by dividing the periphery of the power line 14' in the horizontal direction, and the cross-sectional structure example shown in Fig. 2(2) by dotted line β1 is obtained by dividing the periphery of the power line 14' in the vertical direction.

[0065] 3(4), the insulating film 32 with an adhesive layer, which is made up of an insulating film 32a and an adhesive layer 32b, is formed so as to cover an upper surface 44 of the power line 14' on the film substrate 101. Also, the metal foil 31 with a conductive adhesive layer, which is made up of a metal foil 31a and a conductive adhesive layer 31b, is formed so as to cover the ground lines 13'-1 and 13'-2 on the film substrate 101, and to cover the insulating film 32 with an adhesive layer laminated on the upper surface 44 of the power line 14'.

[0066] The adhesive layer 32b constituting the adhesive-layered insulating film 32 is adhered to the top surface 44 and both side surfaces 52, 53 of the power supply line 14', as well as the top surface 54 of the film substrate 101 on the side of the power supply line 14' between the ground wire 13'-1 and the power supply line 14', and the top surface 55 of the film substrate 101 on the side of the power supply line 14' between the ground wire 13'-2 and the power supply line 14'.

[0067] In addition, the upper surfaces 41, 49 and one side surface 42, 50 of the ground lines 13'-1, 13'-2, the upper surface 48 of the insulating film 32a, the upper surface 43 of the film substrate 101 between the ground line 13'-1 and the power line 14' on the side of the ground line 13'-1, and the upper surface 51 of the film substrate 101 between the ground line 13'-2 and the power line 14' on the side of the ground line 13'-2.

[0068] That is, the ground lines 13'-1 and 13'-2 are electrically connected to each other by the metal foil 31 with a conductive adhesive layer, which is made of the metal foil 31a and the conductive adhesive layer 31b. Also, the ground lines 13'-1 and 13'-2 are electrically insulated from the power line 14' by the insulating film 32 with an adhesive layer, which is made of the insulating film 32a and the adhesive layer 32b (by the insulating film 32a).

[0069] [Method of manufacturing electronic display 1] Next, a method for producing the electronic display 1 according to the embodiment of the present invention will be described. Fig. 4 is a diagram for explaining an example of a process for producing the electronic display 1 according to the embodiment of the present invention, and Fig. 5 is a diagram for explaining the continuation of Fig. 4.

[0070] This example of the manufacturing process shows a method of manufacturing a TFT backplane (three-dimensional wiring TFT-BP) manufactured on a film substrate 101 using three-dimensional wiring 112. For the layers of the electronic display 1, please refer to the cross-sectional structure shown in FIG.

[0071] First, a PI film substrate 101 having a thickness of 8 μm is formed on a first glass substrate (first glass substrate), and a silicon nitride film having a thickness of 50 nm is formed as a base film 105 on the film substrate 101 (on the front side of the film substrate 101) by sputtering (step P401).

[0072] Next, a 200 nm thick metal laminate film made of molybdenum alloy and aluminum is formed by sputtering on the undercoat film 105 (on the front surface side). Then, the gate electrode 107 of the selection TFT 21, the gate electrode 107 of the driving TFT 22, the scanning line 12, the ground line 13, and the power line 14 are formed by a photolithography process (step P402).

[0073] Next, a 200 nm thick insulating film 104 made of a silicon oxide film is formed on (on the front side of) the base film 105, the gate electrode 107 of the selection TFT 21, the gate electrode 107 of the driving TFT 22, the scanning line 12, the ground line 13 and the power line 14 using a sputtering device (step P403).

[0074] Next, a semiconductor layer (active layer) 103 made of In-Sn-Zn-O (ITZO) and having a thickness of 30 nm is formed on the insulating film 104 by a sputtering device, and is patterned by a photolithography process (step P404).

[0075] Next, a heat treatment is performed using a hot plate in the atmosphere at 300° C. for 1 hour (step P405), and vias are formed by dry etching (step P406).

[0076] Next, a 200 nm thick metal laminate film made of molybdenum alloy, nickel and gold is formed by sputtering on the insulating film 104 and the semiconductor layer 103 (on the front surface side). Then, the source electrode 108 and drain electrode 109 of the selection TFT 21, the source electrode 108 and drain electrode 109 of the driving TFT 22, contact electrodes for the light emitting element 23 and the signal line 11 are formed by a photolithography process (step P501).

[0077] Next, the protective film 102 is formed of an organic film that can be applied on the insulating film 104, the semiconductor layer 103, the source electrode 108 and the drain electrode 109 of the selection TFT 21, the source electrode 108 and the drain electrode 109 of the driving TFT 22, and on (the front surface side of) the signal line 11. Then, a heat treatment is performed in the atmosphere at 150° C. for 1 hour (step P502).

[0078] Next, a second glass substrate is attached onto the protective film 102 using an adhesive layer (fix film) (step P503), and then the first glass substrate is peeled off by laser lift-off (step P504).

[0079] After the first glass substrate is peeled off in step P504, the through holes 111 are formed by dry etching (step P505). Note that the through holes 111 may be formed by wet etching, laser drilling, or the like, in addition to dry etching.

[0080] Then, the three-dimensional wiring 112 made of a metal laminate film made of molybdenum alloy and aluminum and the wiring on the rear surface side (signal lines 11'-1, 11'-2, scanning lines 12'-1, 12'-2, ground lines 13'-1, 13'-2, and power line 14') are formed (step P506).

[0081] Next, an insulating film 32a having an adhesive layer 32b (insulating film 32 with an adhesive layer) is formed on a part of the power line 14' on the back side of the substrate so as to cover the part (step P507). The insulating film 32 with an adhesive layer is formed using, for example, a general polyimide tape, and the polyimide tape is attached to a predetermined part of the power line 14' to form a laminated structure.

[0082] FIG. 6 is a diagram showing an example of the layout of wiring etc. on the back surface side of the substrate in the electronic display 1 in which the adhesive-layered insulating film 32 is formed on the power line 14' in process P507.

[0083] As shown in FIG. 1, on the rear surface of the substrate of this electronic display 1, signal lines 11'-1, 11'-2 divided and arranged in two areas, scanning lines 12'-1, 12'-2 divided and arranged in two areas, ground lines 13'-1, 13'-2 divided and arranged in two areas, and a power line 14' arranged in one area are formed without overlapping each other.

[0084] Also, an insulating film 32 with an adhesive layer is formed at a predetermined location near the center of the power line 14' so as to cover the predetermined location.

[0085] Figure 7(1) is a diagram showing an example of the cross-sectional structure around the first and second ground lines 13'-1, 13'-2 which are arranged separately, and shows the cross-sectional structure of the dotted lines α2-1, α2-2 in Figure 6 when the adhesive-layered insulating film 32 is formed on the power line 14' by process P507.

[0086] As shown in FIG. 7(1), ground lines 13'-1 and 13'-2 are laminated on the back surface side of a film substrate 101.

[0087] Figure 7(2) is a diagram showing an example of the cross-sectional structure around the power line 14', and shows the cross-sectional structure of the area of ​​dotted line β2 in Figure 6 when the adhesive-layered insulating film 32 is formed on the power line 14' by process P507.

[0088] As shown in FIG. 7(2), on the upper surface 44 of the power line 14' on the film substrate 101, an insulating film 32 with an adhesive layer, which is made up of an insulating film 32a and an adhesive layer 32b, is laminated.

[0089] More specifically, the adhesive-layered insulating film 32 is formed to cover the upper surface 44 of the power line 14' on the film substrate 101, and the upper surface 44 and both side surfaces 45, 46 of the power line 14', as well as the upper surface 47 of the film substrate 101, are adhered to the adhesive layer 32b.

[0090] Returning to FIG. 5, after forming the insulating film 32 with an adhesive layer in step P507, a metal foil 31a (metal foil 31 with a conductive adhesive layer) having a conductive adhesive layer 31b is formed on a portion of the ground lines 13'-1, 13'-2 on the back side of the substrate and on a portion of the insulating film 32 with an adhesive layer so as to cover these portions (step P508).

[0091] To form the metal foil 31 with a conductive adhesive layer, for example, a copper foil adhesive tape (model number CU7636R) manufactured by Dexerials Corporation is used, and the copper foil adhesive tape is attached to predetermined locations of the ground lines 13'-1, 13'-2 and the insulating film 32 with an adhesive layer to form a laminated structure.

[0092] As a result, the ground wire 13'-1 and the ground wire 13'-2 formed by the division are electrically connected by the metal foil with a conductive adhesive layer 31. In addition, since the insulating film with an adhesive layer 32 is present between the metal foil with a conductive adhesive layer 31 electrically connected to the ground wires 13'-1 and 13'-2 and the power wire 14', the power wire 14' and the ground wires 13'-1 and 13'-2 are electrically insulated by the insulating film 32a.

[0093] Finally, the second glass substrate and the adhesive layer (fix film) are peeled off (step P509).

[0094] In this way, by mounting the light-emitting element 23 on the three-dimensional wiring TFT-BP thus fabricated, the electronic display 1 using the three-dimensional wiring 112 can be fabricated.

[0095] Between steps P504 and P505, a planarization layer 106 may be formed on the back side of the film substrate 101 using an organic film that can be applied by coating (see FIG. 10), and a heat treatment may be performed in the atmosphere at 150° C. for 1 hour.

[0096] As described above, according to the electronic display 1 of the embodiment of the present invention, on the back side of the substrate, an insulating film 32 with an adhesive layer is formed at predetermined locations of the power line 14' so as to cover the predetermined locations, and a metal foil 31 with a conductive adhesive layer is formed at predetermined locations of the ground lines 13'-1, 13'-2 and at predetermined locations of the insulating film 32 with an adhesive layer so as to cover these predetermined locations.

[0097] As a result, the ground lines 13'-1, 13'-2 are electrically connected by the metal foil 31 with a conductive adhesive layer, and the power line 14' and the ground lines 13'-1, 13'-2 are electrically insulated by the insulating film 32 with an adhesive layer.

[0098] 1 shows an example in which the ground line 13' is arranged in two separate areas and the power line 14' is arranged in one area on the back side of the substrate. Alternatively, an electronic display 1 in which the power line 14' is arranged in two separate areas and the ground line 13' is arranged in one area may be used.

[0099] In this case, on the back side of the substrate, an insulating film 32 with an adhesive layer is formed at a predetermined location of the electrode of one ground line 13' so as to cover the predetermined location, and a metal foil 31 with a conductive adhesive layer is formed at predetermined locations of the electrodes of two power lines 14' and at predetermined locations of the insulating film 32 with an adhesive layer so as to cover these predetermined locations.

[0100] As a result, the electrodes of the two power lines 14' are electrically connected by the metal foil 31 with a conductive adhesive layer, and the electrodes of one ground line 13' and the electrodes of the two power lines 14' are electrically insulated by the insulating film 32 with an adhesive layer.

[0101] Therefore, by using the metal foil 31 with a conductive adhesive layer and the insulating film 32 with an adhesive layer, it is possible to electrically connect the ground line 13' or the power line 14' arranged separately on the back side of the substrate of the electronic display 1. This makes it possible to suppress uneven brightness and reduce the number of places where voltage application from the outside is required.

[0102] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept thereof.

[0103] For example, in the electronic display 1 according to an embodiment of the present invention, a metal foil 31 with a conductive adhesive layer (e.g., a copper foil adhesive tape) in which the metal foil 31a and the conductive adhesive layer 31b are integrated is used, but the metal foil 31a and the conductive adhesive layer 31b do not have to be integrated.

[0104] In addition, in the electronic display 1 according to the embodiment of the present invention, an insulating film 32 with an adhesive layer (e.g., a polyimide tape) in which the insulating film 32a and the adhesive layer 32b are integrated is used, but the insulating film 32a and the adhesive layer 32b do not have to be integrated.

[0105] In this case, referring to Figures 2(1) to (3), the electronic display 1 is configured by laminating a conductive adhesive layer 31b member and metal foil 31a on the upper surfaces of the ground lines 13'-1, 13'-2, and by laminating an adhesive layer 32b member, insulating film 32a, a conductive adhesive layer 31b member and insulating film 32a on the upper surface of the power line 14'.

[0106] In the electronic display 1 according to the embodiment of the present invention, the conductive adhesive layer 31b is used as a member provided between the metal foil 31a and the ground lines 13'-1, 13'-2 and between the metal foil 31a and the insulating film 32a. However, the member does not necessarily have to have adhesiveness, and it is sufficient that the member functions as a conductive adhesive layer for bonding the metal foil 31a and the ground lines 13'-1, 13'-2 and bonding the metal foil 31a and the insulating film 32a.

[0107] In the electronic display 1 according to the embodiment of the present invention, the adhesive layer 32b is used as a member provided between the insulating film 32a and the power line 14'. However, the member does not necessarily have to have adhesiveness, and only needs to function as an adhesive layer for adhering the insulating film 32a and the power line 14'. [Explanation of symbols]

[0108] 1,100 Electronic displays 11,11'-1,11'-2 Signal line 12,12'-1,12'-2 scan lines 13,13'-1,13'-2 Ground wire 14,14' power wire 15 Holding capacity 21 Selection TFT 22 Driving TFT 23 Light emitting element 31 Metal foil with conductive adhesive layer 31a Metal foil 31b Conductive adhesive layer 32 Insulating film with adhesive layer 32a Insulating film 32b Adhesive layer 41,43,44,47,48,49,51,54,55 Top surface 42,45,46,50,52,53 Side 99,99' pixel circuit 101 Film substrate 102 Protective film 103 Semiconductor layer 104 Insulating film 105 Base film 106 Planarization layer 107 Gate electrode 108 Source Electrode 109 Drain electrode 110-1, 110-2, 110-3 Wiring 111-1, 111-2, 111-3, 111 Through hole 112-1,112-2,112-3,112 Three-dimensional wiring α1-1, α1-2, α2-1, α2-2, α3-1, α3-2, β1, β2, β3, γ1 dotted line

Claims

1. An electronic display comprising a plurality of pixel circuits arranged in a vertical and horizontal array, the TFTs and light emitting elements of the pixel circuits formed on the front surface of a substrate being driven via three-dimensional wiring that passes through through holes from signal lines, scanning lines, ground lines and power lines formed on the rear surface of the substrate, When one of the ground line and the power supply line is a first line and the other is a second line, and the second line is divided and arranged on the back surface side of the substrate, an adhesive layer and an insulating film are formed on a predetermined portion of the first wiring so as to cover the predetermined portion; a conductive adhesive layer and a metal foil are formed on a predetermined portion of the second wiring and a predetermined portion of the insulating film so as to cover these predetermined portions; An electronic display characterized in that all of the second wirings arranged in a divided manner are electrically connected by the conductive adhesive layer and the metal foil, and the first wirings and all of the second wirings are electrically insulated by the insulating film.

2. 2. The electronic display of claim 1, The conductive adhesive layer and the metal foil are made of a metal foil having a conductive adhesive layer, and the adhesive layer and the insulating film are made of an insulating film having an adhesive layer, an electronic display, characterized in that all of the second wirings and the insulating film are adhered to the conductive adhesive layer, and the first wirings are adhered to the adhesive layer.

Images