Reference voltage circuit

Abstract

To provide a technique for stabilizing a reference voltage while suppressing power consumption in a reference voltage circuit.SOLUTION: A charge correction circuit 133 supplies correction charges, which are set according to the conversion result of the analog signal A0 in a sub-ADC 11, to output terminals of a plus-side reference voltage source 131 and a minus-side reference voltage source 132. The correction charge is set so that fluctuations in the charge supplied to a DAC 12 from the plus-side reference voltage source 131 and the minus-side reference voltage source 132, which occur depending on the combination of capacitors C1 to C8 involved in the processing in the MDAC 12, are suppressed.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a technique for supplying a reference voltage to an AD converter. [Background technology]

[0002] The pipeline type AD conversion circuit and the cyclic type AD conversion circuit (hereinafter, referred to as the main ADC) have multiple stages. Each stage is composed of a sub-ADC and an MDAC. The sub-ADC performs analog-to-digital conversion of an analog input signal. The MDAC adds or subtracts a signal level according to the conversion result from the analog input signal in accordance with the conversion result of the sub-ADC, and generates an analog output signal by amplifying the addition / subtraction result by a set magnification, and inputs the signal to the next stage.

[0003] The MDAC realizes multi-bit DA conversion and addition / subtraction calculations by, for example, selecting which of multiple capacitors to use in the process and by combining whether the capacitors to use in the process are connected to a positive reference voltage or a negative reference voltage. For this reason, the accuracy of the reference voltage has a large impact on the performance of the main ADC.

[0004] The reference voltage circuit that supplies the reference voltage has a buffer circuit at its output stage that is configured using, for example, an operational amplifier or a source follower circuit, so that the reference voltage does not fluctuate due to the charging current for the MDAC capacitor. Note that the buffer circuit that realizes responsiveness according to the operating speed of the MDAC may require power consumption equivalent to that of the amplifier provided at the output stage of the MDAC.

[0005] In response to this, the following Patent Document 1 describes a technology that uses an auxiliary capacitor connected to the output end of a buffer circuit via a switch to make up for the shortfall in charge supply by the buffer circuit, and supplies the charge stored in the auxiliary capacitor when it is necessary to supplement the load current. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6239773 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the conventional technology described in Patent Document 1, the charging voltage of the auxiliary capacitor is determined according to the difference between the output voltage at the previous operation and the reference voltage. Therefore, there was a problem that it was difficult to apply this to a circuit in which the supplied charge fluctuates irregularly for each operation, such as a main ADC using an MDAC.

[0008] In addition, a method for improving characteristics by attaching a large-capacity stabilizing capacitor to the output terminal of the reference voltage circuit is generally known. However, in this case, the stabilizing capacitor needs to have a large capacity of about 1000 to 10000 times that of the capacitor to which the reference voltage is supplied. In addition, the main ADC, which operates at high speed, is realized by an IC chip. If a stabilizing capacitor is attached externally to an IC chip incorporating the main ADC, the speed required by the main ADC cannot be met due to the influence of the wire conductance of the terminals, etc. In addition, it is not practical to incorporate a stabilizing capacitor in the same IC chip as the main ADC, because a very large chip area is required for the stabilizing capacitor.

[0009] The present disclosure provides a technique for stabilizing a reference voltage while suppressing power consumption of a reference voltage circuit. [Means for solving the problem]

[0010] One aspect of the present disclosure is a reference voltage circuit comprising a reference voltage source and a charge correction circuit. The reference voltage source is configured to supply a reference voltage to be applied to an MDAC that changes the charge state of a plurality of capacitors holding an analog input signal according to a conversion result of an ADC that performs analog-to-digital conversion of an analog input signal, adds or subtracts a signal level according to the conversion result from the analog input signal, and generates an analog output signal by amplifying the addition / subtraction result by a set magnification, in order to change the charge state of the capacitors. The charge correction circuit is configured to supply a correction charge, which is set according to the conversion result, to an output terminal of the reference voltage source, so that fluctuations in the charge supplied from the reference voltage source to the MDAC, which occur according to the charge state of the plurality of capacitors, are suppressed.

[0011] According to this configuration, it is possible to stabilize the reference voltage while suppressing the power consumption of the reference voltage circuit. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram showing a configuration of a pipeline converter. [Diagram 2] 4 is a timing diagram of control signals generated by a control circuit. FIG. [Diagram 3] This is a circuit diagram of the first stage that uses a ternary DAC. [Figure 4] 1 is a graph showing the conversion characteristics of a sub-ADC. [Diagram 5] 1 is a table showing the relationship between the input voltage range of a sub ADC and a digital signal and a DA control signal generated by the sub ADC. [Figure 6] 1 shows an equivalent circuit of the first stage during sample and hold. [Figure 7] 4 is a graph showing input / output characteristics of an analog signal in a first stage. [Figure 8] FIG. 2 is a circuit diagram showing a configuration of a charge correction circuit. [Figure 9] 11 is a graph showing the relationship between the charge required by an MDAC, the charge supplied from a correction circuit, and the charge supplied from a reference voltage source. [Figure 10] 13 is a graph showing the relationship between the charge required by the MDAC and the charge supplied from the correction circuit and the charge supplied from the reference voltage source when the granularity of correction is made coarse. [Figure 11] 11 is a graph showing the relationship between the charge required by an MDAC employing a binary DAC, the charge supplied from a correction circuit, and the charge supplied from a reference voltage source. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1. Configuration] First, a pipeline analog-to-digital converter (hereinafter, referred to as pipeline ADC) 1 to which the reference voltage circuit 13 of this embodiment is applied will be described.

[0014] The pipeline ADC 1 shown in FIG. 1 includes a stage circuit 10, a digital demodulation circuit 20, and a control circuit 30. The stage circuit 10 includes M stages ST 1 ~ST M M is an integer equal to or greater than 2. In the following, m=1 to M, and the mth stage is referred to as the mth stage ST m He said.

[0015] First stage ST 1 The analog signal A to be converted is 0 Analog signal A is input. 0 is a differential signal represented by two input signals VIP and VIN.

[0016] 1st Stage ST 1 is the analog signal A 0 Based on n 1 D-bit digital signal 1 and outputs it to the digital demodulation circuit 20. 1 is the analog signal A 0 and the quantized digital signal D 1Analog signal A representing the quantization error between 1 and the second stage ST 2 Output to.

[0017] mth stage ST where m=2~M-1 m is the previous stage m-1 ST m-1 Analog signal A output from m-1 Based on n m D-bit digital signal m and outputs it to the digital demodulation circuit 20. m is the analog signal A m―1 and the quantized digital signal D m Analog signal A representing the quantization error between m Then, the m+1th stage ST m+1 Output to.

[0018] In other words, the first stage ST 1 ~M-1 Stage ST M-1 Each has the same function and converts the input analog signal A m-1 and the analog signal A to be converted to AD in the next stage. m and a function of generating

[0019] The final stage, M stage ST M The first M-1 stage ST M-1 Analog signal A from M-1 Based on n M D-bit digital signal M and outputs it to the digital demodulation circuit 20. That is, the Mth stage ST M is the input analog signal A M-1 It only has the function of AD conversion.

[0020] In addition, each stage ST m The digital signal D generated by m The number of bits in m are the stages ST m In other words, the number of bits for determining the value of the digital signal Dm may have redundancy.

[0021] The digital demodulation circuit 20 includes each stage ST 1 ~ST M A redundant digital signal D is output from 1 ~D M Based on this, a digital signal Dout representing the final AD conversion result is generated and output.

[0022] The control circuit 30 controls each stage ST 1 ~ST M 2, the control signal φ1 is a clock signal, and a high level corresponds to the sample period of the stage circuit 10, and a low level corresponds to the hold period of the stage circuit 10. The control signal φ2 is a signal that is at a high level for a certain period during the hold period.

[0023] [2. 1st Stage] 1st Stage ST 1 The specific circuit configuration of the first stage ST1 is as follows. 0 The digital signal Dout, which is the result of AD conversion, is the digital signal D 1 The quantization error is multiplied by 8 to obtain the second stage ST 2 Analog signal A provided to 1 Generate.

[0024] As shown in Figure 3, the first stage ST 1 The analog-to-digital converter includes a sub-ADC 11, a multiplying digital-to-analog converter (hereinafter, referred to as an MDAC) 12, and a reference voltage circuit . The sub ADC 11 converts the input analog signal A 0 Quantize to n 1 D-bit digital signal 1 and generates a digital signal D according to a control signal φ2 from the control circuit 30. 1 The control circuit 10 outputs DA control signals Z1 to Z8 having values ​​according to the input signals.

[0025] As shown in Figure 4, the sub-ADC 11 receives an analog signal A within the input voltage range -VREF to +VREF. 0 The voltage level of is converted to a 5-bit digital signal D 1 In this embodiment, VREF=1600 mV.

[0026] In the following, the voltage levels of the input voltage range -VREF to +VREF are normalized to -1 to 1 as shown in FIG. 5. 1 In this example, the decimal number -1 is represented as 11111B, and the decimal numbers 0 to 15 are represented as 00000B to 01111B.

[0027] Sub ADC11 is A 0 If the voltage level is in the voltage range -1 to -15 / 16, it outputs D1 = -1; if it is in the voltage range (2n-1) / 16 to (2n+1) / 16 (where n = -7 to 7), it outputs D1 = n+7; if it is in the voltage range 15 / 16 to 1, it outputs D1 = 15.

[0028] Sub ADC11 is D 1 The control circuit 10 outputs three-value DA control signals Z1 to Z8 according to the input signal. For j=1 to 8, the DA control signal Zj is 1 = 7+j~15, 1, D 1 = 0~7-j, the signal is -1, otherwise it is 0.

[0029] In other words, if the number of DA control signals Z1 to Z8 whose value is 1 is n and the number whose value is -1 is m, then D 1 If =-1~6, m=7-D 1 ,n=0, and D 1 If m=n=7, then m=n=0, and D 1 For =8~15, m=0, n=D 1 The result is -7.

[0030] Returning to FIG. 3, the MDAC 12 includes a differential amplifier 121, a first circuit 122, a second circuit 123, and a switch SW1. The differential amplifier 121 amplifies the difference between the output of the first circuit 122 and the output of the second circuit 123 by a predetermined factor to generate an analog signal A 1 Generates an analog signal A 1 is represented by the difference between the output voltage VOP at the non-inverting output terminal of the differential amplifier 121 and the output voltage VON at the inverting output terminal.

[0031] One end of the switch SW1 is connected to the non-inverting output terminal of the differential amplifier 121, and the other end is connected to the inverting output terminal. The switch SW1 is operated by a control signal φ1 from the control circuit 30. The switch SW1 is turned on when the control signal φ1=1 (i.e., during the sample period) and is turned off when the control signal φ1=0 (i.e., during the hold period).

[0032] The first circuit 122 includes capacitors C0 to C8, switch blocks SB1 to SB8, and a switch SW2. The capacitor C0 is connected between the inverting input terminal and the non-inverting output terminal of the differential amplifier 121. For k=1 to 8, one end of the capacitor Ck is connected to the inverting input terminal of the differential amplifier 121, and the other end is connected to the switch block SBk. The capacitances of the capacitors C0 to C8 are all set to the same value.

[0033] One end of the switch SW2 is connected to the inverting input terminal of the differential amplifier 121, and the other end is applied with a common voltage VCM. The switch SW2 is operated by a control signal φ1 from the control circuit 30. The switch SW2 is turned on when the control signal φ1=1, and is turned off when the control signal φ1=0.

[0034] The switch blocks SB1 to SB8 all have the same configuration. As shown in the upper part of FIG. The switch SWk1 is operated by a control signal φ1 from the control circuit 30. When the control signal φ1=1, the switch SWk1 connects one end of the capacitor Ck to the positive input terminal, thereby applying the input signal VIP. When the control signal φ1=0, the switch SWk1 connects to the output terminal of the switch SWk2.

[0035] The switch SWk2 is operated by a DA control signal Zk from the sub-ADC 11. When the DA control signal Zk=1, the switch SWk2 connects one end of the capacitor Ck to a positive power supply line LP leading to a positive reference voltage source 131 via the switch SWk1, thereby applying a positive reference voltage VREFP to the capacitor Ck. When the DA control signal Zk=0, the switch SWk2 connects one end of the capacitor Ck to a common level line LC via the switch SWk1, thereby applying a common voltage VCM to the capacitor Ck. When the DA control signal Zk=-1, the switch SWk2 connects one end of the capacitor Ck to a negative power supply line LN leading to a negative reference voltage source 132 via the switch SWk1, thereby applying a negative reference voltage VREFN to the capacitor Ck. The positive reference voltage VREFP and the negative reference voltage VREFN are set to the magnitudes shown in equations (1) and (2).

[0036]

number

[0037] That is, when the control signal φ1=1 (i.e., during the sample period), the input signal VIP (=VCM+A 0 When the control signal φ1=0 (i.e., during the hold period), one end of the capacitor Ck is applied with one of the positive reference voltage VREFP, the common voltage VCM, and the negative reference voltage VREFN in accordance with the DA control signal Zk.

[0038] The second circuit 123 has a similar configuration to the first circuit 122. However, in the case of the second circuit 123, VIP is replaced with VIN (=VCM-A0 / 2), with VOP replaced by VON, and the inverting input terminal and non-inverting output terminal of the differential amplifier 121 replaced by a non-inverting input terminal and an inverting output terminal, respectively. Also, the switch SWk2 in the second circuit 123 is opposite to the first circuit 122 in that it is connected to the negative power supply line LN when the DA control signal Zk=1, and is connected to the positive power supply line LP when the DA control signal Zk=-1.

[0039] In the MDAC12 configured in this manner, during a sample period when the control signal φ1=1, the switches SW1 and SW2 are on and the switch SWk1 selects the input signal VIP / VIN side, so that the equivalent circuit of the MDAC12 is shown in the left column of Fig. 6. That is, the capacitor C0 is reset (i.e., the charge is discharged), and the capacitors C1 to C8 are charged with a charge according to the voltage level of the analog signal A0.

[0040] During a hold period when the control signal φ1=0, the switches SW1 and SW2 are turned off and the switch SWk1 selects the output of the switch SWk2, so that the equivalent circuit of the MDAC 12 is shown in the right column of FIG.

[0041] That is, in the first circuit 122, a positive reference voltage VREFP is applied to n capacitors Ck via a switch block SBk where the DA control signal Zk=1. Also, in the first circuit 122, a negative reference voltage VREFN is applied to m capacitors Ck via a switch block SBk where the DA control signal Zk=-1. Furthermore, in the first circuit 122, a common voltage VCM is applied to (8-nm) capacitors Ck via a switch block SBk where the DA control signal Zk=0.

[0042] In the second circuit 123, a negative reference voltage VREFN is applied to n capacitors Ck via a switch block SBk where the DA control signal Zk=1. Also, in the second circuit 123, a positive reference voltage VREEFP is applied to m capacitors Ck via a switch block SBk where the DA control signal Zk=-1. Furthermore, in the second circuit 123, a common voltage VCM is applied to (8-nm) capacitors Ck via a switch block SBk where the DA control signal Zk=0.

[0043] When the operation of the MDAC 12 switches from the sample period to the hold period, the charge stored in the capacitors C1 to C8 is redistributed between the capacitors C1 to C8 and the capacitor C0. Basically, the analog signal A sampled in the capacitors C1 to C8 is 0 is the analog signal A amplified by a factor corresponding to the ratio of the total capacitance of C1 to C8 to the capacitance of C0 (i.e., 8 times). 1 will be output as:

[0044] However, D 1 When A = n + 7, the negative reference voltage VREFN is applied to the n capacitors Ck of the first circuit 122 and the positive reference voltage VREFP is applied to the n capacitors Ck of the second circuit 123 by the DA control signals Z1 to Z8. As a result, the analog signal A 1 The level of D is shifted to the negative side by n × VREF. 1 When A = 7-m, the positive reference voltage VREFP is applied to the m capacitors Ck of the first circuit 122 and the positive reference voltage VREFN is applied to the m capacitors Ck of the second circuit 123 by the DA control signals Z1 to Z8. As a result, the analog signal A 2 The level of is shifted to the positive side by m × VREF. 1 In the case of =7, neither the negative reference voltage VREFN nor the positive reference voltage VREFP is applied to the capacitor Ck. As a result, the analog signal A 1 The level of is output without being shifted.

[0045] In other words, analog signal A0 Of these, digital signal D 1 The digital signal D is shifted so that the signal in the voltage range corresponding to 1 The analog signal A is amplified 8 times and converted to 1 As a result, the second stage ST 2 are supplied to.

[0046] As a result, as shown in FIG. 7, the first stage ST 1 Analog signal A at 0 ,A 1 The graph showing the input / output characteristics of the digital signal D has a sawtooth shape that repeats linear changes in the range of -VREF / 2 to VREF / 2. 1 This allows the signal to be identified as being in one of the 17 divided input voltage ranges.

[0047] Incidentally, when switching from the sampling period to the holding period, a transfer of charges occurs between the capacitor Ck to which the positive reference voltage VREFP or the negative reference voltage VREFN is applied and the reference voltage circuit 13.

[0048] Digital signal D 1 =-1 to 6 (that is, m=1 to 8, n=0), the amount of charge movement +ΔQp occurring in the first circuit 122 and the amount of charge movement −ΔQn occurring in the second circuit 123 are expressed by equations (3) and (4).

[0049]

number

[0050] In equations (3) and (4), the first term on the right hand side is the charge stored in the capacitor Ck during the sample period (hereinafter referred to as the sample charge). The second term on the right hand side is the charge stored in the capacitor Ck during the hold period by being connected to the positive reference voltage VREFP or the negative reference voltage VREFN (hereinafter referred to as the hold charge). In other words, the difference between the sample charge and the hold charge is the amount of charge movement +ΔQp, -ΔQn.

[0051] Digital signal D 1 = 8 to 15 (i.e., m = 0, n = 1 to 8), the amount of charge movement occurring in the first circuit 122 is expressed by equation (4) with m replaced by n, and the amount of charge movement occurring in the second circuit 123 is expressed by equation (3) with m replaced by n.

[0052] [3. Reference voltage circuit] Returning to FIG. 3, the reference voltage circuit 13 includes a first stage ST 1 A positive reference voltage VRFFP and a negative reference voltage VREFN are supplied to the MDAC12.

[0053] The reference voltage circuit 13 includes a positive reference voltage source 131 , a negative reference voltage source 132 , and a charge correction circuit 133 . The positive reference voltage source 131 supplies a positive reference voltage VREFP to the positive power supply line LP. The negative reference voltage source 132 supplies a negative reference voltage VREFN to the negative power supply line LN. The positive reference voltage source 131 and the negative reference voltage source 132 each have a buffer circuit at the output stage. The buffer circuit is composed of a source follower circuit that increases the current driving capability, a feedback circuit that keeps the output voltage of the source follower circuit constant, and the like.

[0054] The charge correction circuit 133 is a circuit for supplying the charges necessary for charging and discharging to the capacitors C1 to C8 of the first circuit 122 and the capacitors C1 to C8 of the second circuit 123, which are the destinations of the positive side reference voltage VREFP and the negative side reference voltage VREFN, when switching from the sample period to the hold period.

[0055] As shown in FIG. 8, the charge correction circuit 133 includes a plurality of unit circuits U1 to U8 (eight in this embodiment). For i=1 to 8, the unit circuit Ui has a capacitor C Qi and four switches S i1 ~S i4 The switched capacitor circuit is formed of the above.

[0056] Capacitor C Qi At one end of the switch S i1 and switch S i3 is connected, and the capacitor C Qi At the other end of the switch S i2 and switch S i4 is connected. Capacitor C Qi Switch S i1 It is connected to the positive power line LP via the switch S i2 It is connected to the negative power supply line LN via the capacitor C Qi Switch S i4 It is connected to the negative power supply line that supplies the negative power supply voltage VSS via the capacitor C Q1 ~C Q4 Switch S i3 (where i=1 to 4) is connected to the positive power supply line that supplies the positive power supply voltage VDD through the capacitor C Q5 ~C Q8 Switch S i3 (where i=5 to 8) are connected to a negative power supply line that supplies a negative power supply voltage VSS.

[0057] Switch S i1 and S i2 is operated by the DA control signal Zk, and is turned on when Zk=1 or -1, and turned off when Zk=0. i3 and S i4 is operated by a control signal φ1 from the control circuit 30, and is turned on when φ1=1 and turned off when φ1=0.

[0058] The positive power supply voltage VDD and the negative power supply voltage VSS are set so as to satisfy the relationship of the following equation (5). (VDD-VSS)>(VREFP-VREFN) (5) Capacitor C Q1 ~C Q4 (i.e., for i = 1 to 4) switch S i1 and S i2 is off and switch S i3 and S i4 When switch S is on, it is charged with VDD-VSS. i3 and S i4 is turned off and switch S i1 and S i2 When is switched on, the capacitor C Qi The positive power supply line LP is connected to the individual correction charge +ΔQ i (or -ΔQ i At the same time, an individual correction charge -ΔQ i (or +ΔQ i (pulling in).

[0059] ΔQ i = {(VDD-VSS)-(VREFP-VREFN)} x C Qi (6) Capacitor C Q5 ~C Q8 (i.e., when i=5 to 8) switch S i1 and S i2 is off and switch S i3 and S i4 When the switch S is turned on, the charge is discharged. i3 and S i4 is turned off and switch S i1 and S i2 When is switched on, the capacitor C Qi is the individual correction charge +ΔQ expressed by the following equation (7) from the positive power line LP i (or -ΔQ i At the same time, a correction charge -ΔQ i (or, +ΔQi supply).

[0060] ΔQ i = (VREFP-VREFN) × C Qi (7) Here, the capacitor C Q1 ~C Q8 This section explains how to set the capacity. First, the digital signal D from the sub ADC11 1 For each of the 17 values ​​taken by Q, the transferred charges +ΔQp, −ΔQp calculated from equations (3) and (4) are calculated as the required charge Qnd. The required charge Qnd is represented by the graph shown by the solid line in FIG.

[0061] The digital signal from the sub ADC11 is D 1 = 7 (that is, m = n = 0), during the hold period, the common voltage VCM is applied to all of the capacitors C1 to C8 of the first circuit 122 and the second circuit 123. In this case, no charge transfer occurs between the capacitors C1 to C8 and the reference voltage circuit 13, and therefore the required charge Qnd becomes zero.

[0062] When the digital signal D1 from the sub-ADC 11 is D1=8 to 15 (i.e., m=0, n=1 to 8), the number n of capacitors Ck in which charge transfer occurs between the sub-ADC 11 and the reference voltage circuit 13 increases as the input voltage A0 increases. 1 Within each voltage range where A0 is constant, the amount of charge transfer per capacitor Ck that occurs between the reference voltage circuit 13 decreases as the input voltage A0 increases.

[0063] Therefore, as shown in the graph in Figure 9, D 1 = 8 to 15 (i.e., input voltage A0 = 0 mV to 1600 mV), the required charge Qnd is D 1 As n increases, the waveform increases once and then decreases. Also, within a constant range of n, the required charge Qnd monotonically decreases as the absolute value of the input voltage A0 increases.

[0064] The digital signal from the sub ADC11 is D1 =-1 to 6 (i.e., m=1 to 8, n=0), the number m of capacitors Ck in which charge transfer occurs between the reference voltage circuit 13 and the analog signal A 0 The smaller the digital signal D 1 Within each voltage range where the voltage is constant, the amount of charge transfer per capacitor Ck between the analog signal A and the reference voltage circuit 13 is 0 The smaller is the smaller.

[0065] In other words, the digital signal is D 1 =-1 to 6 (i.e., input voltage A0 = -1600mV to 0mV), the waveform of the graph showing the required charge Qnd is 1 The waveform when =8~15 is analog signal A 0 It has a line-symmetric shape folded back around the line where θ is 0.

[0066] Next, using the graph of the required charge Qnd described above, the correction charge ΔHQk supplied by the reference voltage circuit 13 is set. For k=1 to 8, D 1 = D if -1 to 6 1 The average required charge Qnd in the voltage range of =7-k is 1 If =8~15, D 1 The average required charge Qnd in the voltage range of =k+7 is the correction charge ΔHQ k The correction charge ΔHQ 7 = 0. Therefore, the correction charge ΔHQ k is represented by the dashed line in the graph of FIG.

[0067] Next, the correction charge ΔHQ 1 ~ΔHQ 8 Using this, the capacitor C Q1 ~C Q8 A method for determining the capacity of the capacitor is described. First, in equation (6), set i = 1, and ΔQ 1 ΔHQ 1 Substituting, C Q1 Next, for i = 2 to 4, ΔQ on the left side of equation (6) is calculated.i Substituting equation (8) into C Q2 ~C Q4 Calculate ΔQ on the left side of equation (7) for i = 5 to 8. i Substituting equation (8) into C Q5 ~C Q8 That is, the charge correction circuit 133 calculates the correction charge ΔHQ i For each capacitor C Q1 ~C Qi The system is structured to share and supply the ΔQ i is the capacitor C Qi represents the charge shared by the

[0068]

number

[0069] In this way, by supplying the correction charge ΔHQ from the charge correction circuit 133, the charge (hereinafter, the supplied charge) Qs supplied from the positive side reference voltage source 131 and the negative side reference voltage source 132 to charge the capacitors C1 to C8 of the MDAC12 becomes the difference between the required charge Qnd and the correction charge ΔHQ, and is represented by the dotted line in Figure 9.

[0070] In other words, from FIG. 9, it can be seen that the supplied charge Qs when the charge correction circuit 133 is provided is about 1 / 5 compared to when the plus side reference voltage source 131 and the minus side reference voltage source 132 supply all of the required charge Qnd.

[0071] [4. Circuit configuration after the second stage] Second Stage ST 2 ~M-1 Stage ST M-1 is the first stage ST 1 However, the digital signal D m The number of bits in m is the first stage ST 1 Digital signal D 1 The number of bits in 1 Each stage ST mIn the above, the number of switch blocks SBk and the number of capacitors Ck connected to the switch block SBk are m The number of bits in m It is set according to.

[0072] In addition, stage ST m The more the stage ST m Analog signal A input to m-1 becomes more amplified, and the digital signal D out Analog signal A corresponding to 1 bit of m-1 Accordingly, the margin for noise in the MDAC 12 increases, and the requirements for the accuracy of the positive reference voltage VREFP and the negative reference voltage VREFN are also relaxed. 2 After that, the charge correction circuit 133 may be omitted.

[0073] [5. Terminology] In this embodiment, the analog signal A 0 corresponds to the analog input signal in this disclosure, and analog signal A 1 corresponds to the analog output signal in this disclosure. The sub-ADC 11 corresponds to the ADC in this disclosure.

[0074] [6. Effects] According to the embodiment described above in detail, the following effects are achieved. (6a) The reference voltage circuit 13 supplies a correction charge ΔHQ to the MDAC 12 in accordance with the DA control signals Z1 to Z8 corresponding to the conversion result of the sub-ADC 11. 1 ~ΔHQ 8 Therefore, the positive reference voltage VREFP and the negative reference voltage VREFN supplied to the MDAC 12 by the reference voltage circuit 13 can be stabilized without installing a large-capacity stabilizing capacitor.

[0075] (6b) By providing the charge correction circuit 133, it is not necessary to use a highly responsive circuit that follows the operating speed of the MDAC 12 as a buffer circuit that constitutes the output stage of the positive reference voltage source 131 and the negative reference voltage source 132. As a result, the power consumption of the reference voltage circuit 13 and, ultimately, the pipelined ADC 1 can be reduced.

[0076] (6c) The charge correction circuit 133 uses the DA control signals Z1 to Z8 generated by the sub ADC 11 directly to control the unit circuits U1 to U8 without processing them such as decoding, thereby achieving high-speed control without unnecessary delay.

[0077] 7. Other Embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0078] (7a) In the above embodiment, the digital signal D output by the sub-ADC 11 1 17 values ​​represented by (D 1 = 7 does not require correction, D 1 = 7, so the correction capacitance ΔHQ 1 ~ΔHQ 8 On the other hand, the granularity of the correction can be reduced by applying the same correction capacity to multiple values. For example, as shown in Figure 10, ΔHQ 1 = ΔHQ 2 , ΔHQ 3 = ΔHQ 4 = ΔHQ 5 , ΔHQ 6 = ΔHQ 7 In this case, the circuit scale of the charge correction circuit 133 can be reduced.

[0079] (7b) In the above embodiment, the MDAC12 is a so-called ternary DAC that applies one of the positive reference voltage VREFP, the common voltage VCM, and the negative reference voltage VREFN to the capacitors C1 to C8 in response to the DA control signals Z1 to Z8. However, the MDAC12 is not limited to a ternary DAC, and may be a so-called binary DAC that applies one of the positive reference voltage VREFP and the negative reference voltage VREFN to the capacitors C1 to C8 in response to the DA control signals Z1 to Z8. The relationship between the required charge Qnd, the correction charge ΔHQ, and the supplied charge Qs when a binary DAC is used is shown in FIG. 11. When a binary DAC is used, the circuit configuration of the MDAC12 can be simplified compared to when a ternary DAC is used.

[0080] (7c) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments. [Explanation of symbols]

[0081] 1... Pipeline analog-to-digital converter (pipeline ADC), 10... Stage circuit, 11... Sub ADC, 12... Multiplying digital-to-analog converter (MDAC), 13... Reference voltage circuit, 20... Digital demodulation circuit, 30... Control circuit, 121... Differential amplifier, 122... First circuit, 123... Second circuit, 131... Positive reference voltage source, 132... Negative reference voltage source, 133... Charge correction circuit, C0 to C8, C Q1 ~C Q8 ... Capacitor, LC... Common level line, LN... Negative power line, LP... Positive power line, SB 1 ~SB 8 …Switch block, ST 1 ~STM ...stage, SW1, SW2, SWk1, SWk2, Si1~Si4...switches, U1~U8...unit circuit.

Claims

1. an MDAC that changes the charge states of a plurality of capacitors that hold an analog input signal according to a conversion result of an ADC that performs analog-to-digital conversion of the analog input signal, thereby adding or subtracting a signal level according to the conversion result from the analog input signal, and amplifying the addition / subtraction result by a set magnification to generate an analog output signal; and a reference voltage source configured to supply a reference voltage to be applied to change the charge states of the capacitors to the MDAC; a charge correction circuit configured to supply a correction charge to an output terminal of the reference voltage source, the correction charge being set according to the conversion result so that fluctuations in the charge supplied from the reference voltage source to the MDAC, which fluctuations occur according to the charge states of the plurality of capacitors, to the output terminal of the reference voltage source; A reference voltage circuit comprising:

2. 2. The reference voltage circuit of claim 1, The charge correction circuit includes: A switched capacitor circuit is provided, The switched capacitor circuit is configured to supply the correction charge to the MDAC by charging or discharging the plurality of capacitors while being disconnected from the output terminal of the reference voltage source during a sample period in which the MDAC acquires the analog input signal, and by connecting the capacitor selected according to the conversion result to the output terminal of the reference voltage source during a hold period in which addition, subtraction, and amplification are performed on the analog input signal acquired by the MDAC. Reference voltage circuit.

3. 3. The reference voltage circuit according to claim 2, The charge correction circuit includes: A signal indicating the conversion result output from the ADC is used as a control signal for the switched capacitor circuit. Reference voltage circuit.

Images