Semiconductor device and doherty amplifier circuit

Abstract

To provide a semiconductor device achieving a matching circuit for an N-way Doherty amplifier circuit.SOLUTION: A semiconductor device includes: a package that includes a base and an output lead; a first semiconductor chip 40a that includes a main amplifier into which an input signal is distributed and which outputs an amplified first signal to a first output pad; a second semiconductor chip 40b that includes a first peak amplifier into which the input signal is distributed and which outputs an amplified second signal to a second output pad; a third semiconductor chip 40c that includes a second peak amplifier into which the input signal is distributed and which outputs an amplified third signal to a third output pad; a first impedance converter that has a first end electrically connected to the first output pad and the output lead, and a second end electrically connected to the second output pad and the third output pad; a first matching circuit that matches impedances of the first output pad and the first end with each other; and a second matching circuit that matches impedances of the second output pad and the second end with each other.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a Doherty amplifier circuit. [Background technology]

[0002] An N-way Doherty amplifier circuit (N is 3 or more) using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2). The N-way Doherty amplifier circuit is provided with an impedance converter that electrically connects the output terminal of the main amplifier and the output terminal of a first peak amplifier, and an impedance converter that electrically connects the output terminal of the main amplifier and the output terminal of the first peak amplifier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,022,760 [Patent Document 2] U.S. Pat. No. 10,601,375 Summary of the Invention [Problem to be solved by the invention]

[0004] However, it is difficult to realize a matching circuit that matches the impedance between the main amplifier and the impedance converter, and a matching circuit that matches the impedance between the first peak amplifier and the impedance converter.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to realize a matching circuit for an N-way Doherty amplifier circuit. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a package having a base and an output lead; a first semiconductor chip mounted on the base and comprising a main amplifier that amplifies a first signal obtained by distributing an input signal, and a first output pad that outputs the amplified first signal; a second semiconductor chip mounted on the base and comprising a first peak amplifier that amplifies a second signal obtained by distributing the input signal, and a second output pad that outputs the amplified second signal; a third semiconductor chip mounted on the base and comprising a second peak amplifier that amplifies a third signal obtained by distributing the input signal, and a third output pad that outputs the amplified third signal; a first impedance converter mounted on the base and having a first end electrically connected to the first output pad and the output lead and a second end electrically connected to the second output pad and the third output pad; a first matching circuit mounted on the base and matching an impedance between the first output pad and the first end; and a second matching circuit mounted on the base and matching an impedance between the second output pad and the second end. Effect of the Invention

[0007] According to the present disclosure, a matching circuit for an N-way Doherty amplifier circuit can be realized. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a Doherty amplifier circuit according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing the drain efficiency versus input power of each amplifier in the first embodiment. [Diagram 3] FIG. 3 is a circuit diagram of the Doherty amplifier circuit in accordance with the first embodiment. [Figure 4] FIG. 4 is a circuit diagram of a rear stage of the transistor in the first embodiment. [Diagram 5] FIG. 5 is a plan view of the semiconductor device in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA of FIG. [Figure 7] FIG. 7 is a plan view of a portion of the semiconductor device in the first embodiment. [Figure 8] FIG. 8 is an equivalent circuit diagram of FIG. [Figure 9] FIG. 9 is a plan view of a portion of the semiconductor device in the first comparative example. [Figure 10] FIG. 10 is an equivalent circuit diagram of FIG. [Figure 11] FIG. 11 is a plan view of a portion of the semiconductor device in the second comparative example. [Figure 12] FIG. 12 is an equivalent circuit diagram of FIG. [Figure 13] FIG. 13 is a plan view of a portion of the semiconductor device in Comparative Example 3. As shown in FIG. [Figure 14] FIG. 14 is an equivalent circuit diagram of FIG. [Figure 15] FIG. 15 is a plan view of the circuit board in the first comparative example. [Figure 16] FIG. 16 is a plan view of the circuit board in the first embodiment. [Figure 17] FIG. 17 is a plan view of a semiconductor device illustrating another example of the impedance converter in the first embodiment. [Figure 18] FIG. 18 is a circuit diagram illustrating another example of the impedance converter in the first embodiment. [Figure 19] FIG. 19 is a plan view illustrating another example 1 of the matching circuit in the first embodiment. [Figure 20] FIG. 20 is an equivalent circuit diagram of FIG. [Figure 21] FIG. 21 is a plan view illustrating another example of the matching circuit in the first embodiment. [Figure 22] FIG. 22 is an equivalent circuit diagram of FIG. [Figure 23] FIG. 23 is a plan view illustrating another example 3 of the matching circuit in the first embodiment. [Figure 24] FIG. 24 is an equivalent circuit diagram of FIG. [Diagram 25] FIG. 25 is a plan view illustrating another example 4 of the matching circuit in the first embodiment. [Figure 26]FIG. 26 is an equivalent circuit diagram of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device comprising: a package having a base and an output lead; a first semiconductor chip mounted on the base and including a main amplifier that amplifies a first signal obtained by distributing an input signal and a first output pad that outputs the amplified first signal; a second semiconductor chip mounted on the base and including a first peak amplifier that amplifies a second signal obtained by distributing the input signal and a second output pad that outputs the amplified second signal; a third semiconductor chip mounted on the base and including a second peak amplifier that amplifies a third signal obtained by distributing the input signal and a third output pad that outputs the amplified third signal; a first impedance converter mounted on the base and having a first end electrically connected to the first output pad and the output lead and a second end electrically connected to the second output pad and the third output pad; a first matching circuit mounted on the base and matching impedance between the first output pad and the first end; and a second matching circuit mounted on the base and matching impedance between the second output pad and the second end. This makes it possible to realize a first matching circuit and a second matching circuit for an N-way Doherty amplifier circuit having a low characteristic impedance. (2) In the above (1), a second impedance converter may be mounted on the base, the third end of the second impedance converter being electrically connected to the second end of the first impedance converter and the fourth end being electrically connected to the third output pad, and a third matching circuit that matches the impedance between the third output pad and the fourth end. This makes it possible to realize a third matching circuit and a second matching circuit with low characteristic impedance. (3) In the above (1) or (2), the first end may be electrically connected to the first output pad via a first bonding wire, and the first end may be electrically connected to the output lead via a second bonding wire, thereby allowing the first bonding wire to be used as a part of a first matching circuit. (4) In the above (3), the second end may be electrically connected to the second output pad via a third bonding wire, whereby the third bonding wire can be used as a part of a second matching circuit. (5) In the above (2), the first end may be electrically connected to the first output pad via a first bonding wire, the second end may be electrically connected to the output lead via a second bonding wire, the second end and the third end may be electrically connected to the second output pad via a third bonding wire, and the fourth end may be electrically connected to the third output pad via a fourth bonding wire, thereby allowing the first, third, and fourth bonding wires to be used as parts of the first, second, and third matching circuits. (6) In any one of (1) to (5) above, a line component may be provided that includes a dielectric substrate mounted on the base and a line pattern provided on the dielectric substrate, and the first impedance converter may include the line pattern, thereby enabling the characteristic impedance and electrical length of the first impedance converter to be accurately achieved. (7) In any one of (1) to (5) above, the first impedance converter may include a first capacitor mounted on the base and having a first end electrically connected to the base, a second capacitor mounted on the base and having a first end electrically connected to the base, and a fifth bonding wire electrically connecting a second end of the first capacitor to a second end of the second capacitor, the first impedance converter including the first capacitor, the second capacitor, and the fifth bonding wire. This allows the first impedance converter to be formed. (8) In any one of the above (1) to (7), the first impedance converter may rotate the phase of a center frequency of an operating band by 90° between the first end and the second end, thereby enabling the first impedance converter to convert the impedance on the real axis of a Smith chart into an impedance on the real axis. (9) In the above (8), the first matching circuit may rotate the phase of the center frequency by 90° between a signal source of the main amplifier and the first end, and the second matching circuit may rotate the phase of the center frequency by 90° between a signal source of the first peak amplifier and the second end. This allows an impedance converter including the first and second matching circuits to convert an impedance on the real axis of a Smith chart to an impedance on the real axis. (10) In the above (2) or (5), the first impedance converter may rotate the phase of a center frequency of an operating band by 90° between the first end and the second end, the second impedance converter may rotate the phase of the center frequency of an operating band by 90° between the third end and the fourth end, the first matching circuit may rotate the phase of the center frequency by 90° between a signal source of the main amplifier and the first end, the second matching circuit may rotate the phase of the center frequency by 90° between a signal source of the first peak amplifier and the second end and the third end, and the third matching circuit may rotate the phase of the center frequency by 90° between a signal source of the second peak amplifier and the fourth end. In this way, the impedance converter including the first and second impedance converters and the first and second matching circuits can convert an impedance on the real axis of a Smith chart to an impedance on the real axis. (11) In any one of the above (1) to (10), an input power of the input signal at which the first peak amplifier is turned on may be greater than the input power at which the main amplifier is turned on, and the input power at which the second peak amplifier is turned on may be greater than the input power at which the first peak amplifier is turned on. This makes it possible to realize a Doherty amplifier circuit. (12) In any one of the above (1) to (11), an angle between a direction in which the amplified first signal flows and a direction in which the amplified second signal flows at the first end may be equal to or greater than 70° and equal to or less than 110°. This allows for miniaturization. (13) One embodiment of the present disclosure is a Doherty amplifier circuit including the semiconductor device according to any one of (1) to (12) above and a distributor that distributes the input signal into the first signal, the second signal, and the third signal, thereby realizing a Doherty amplifier circuit.

[0010] [Details of the embodiment of the present disclosure] Specific examples of the semiconductor device and the Doherty amplifier circuit according to the embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] A high-output high-frequency amplifier circuit used in a mobile communication base station will be described as an example of the Doherty amplifier circuit. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. FIG. 1 is a block diagram of the Doherty amplifier circuit according to the first embodiment. In FIG. 1, bias circuits that supply bias voltages to the main amplifier 10a and the peak amplifiers 10b and 10c are not shown.

[0012] As shown in FIG. 1, the Doherty amplifier circuit 100 has three paths 15a to 15c arranged in parallel between a distributor 16 and a combiner 18. A high-frequency signal is input as an input signal Sin to an input terminal Tin. The distributor 16 distributes the input signal Sin input to the input terminal Tin into signals S1 (first signal), S2 (second signal), and S3 (third signal). The distributor 16 is, for example, a Wilkison type distributor. In this way, the Doherty amplifier circuit 100 is a 3-way amplifier circuit. An N-way Doherty amplifier circuit having N paths 15a to 15c (three or more) may also be used.

[0013] The signals S1 to S3 pass through paths 15a to 15c, respectively. The path 15a includes a phase adjuster 23, a matching circuit 12a, a main amplifier 10a, and a matching circuit 14a (first matching circuit). The path 15b includes a phase adjuster 24, a matching circuit 12b (second matching circuit), a peak amplifier 10b, and a matching circuit 14b. The path 15c includes a matching circuit 12c (third matching circuit), a peak amplifier 10c, and a matching circuit 14c.

[0014] Phase adjusters 23 and 24 adjust the phase between paths 15a to 15c. Matching circuits 12a to 12c match the impedance seen from distributor 16 to matching circuits 12a to 12c, respectively, to the impedance seen from matching circuits 12a to 12c to main amplifier 10a, peak amplifier 10b (first peak amplifier), and 10c (second peak amplifier), respectively.

[0015] The main amplifier 10a and the peak amplifiers 10b and 10c amplify the signals S1 to S3, respectively, and output the amplified signals S4 to S6, respectively. The matching circuits 14a to 14c match the impedances seen by the main amplifier 10a and the peak amplifiers 10b and 10c at the matching circuits 14a to 14c, respectively, to the impedances seen by the matching circuits 14a to 14c at the nodes N1 to N3, respectively.

[0016] The combiner 18 includes impedance converters 20 to 22. The impedance converter 20 (first impedance converter) is connected between nodes N1 and N2. The impedance converter 21 (second impedance converter) is connected between nodes N2 and N3. The impedance converter 22 is connected between node N1 and an output terminal Tout. The combiner 18 combines signals S4 to S6, and outputs the combined signal to the output terminal Tout as an output signal Sout.

[0017] The main amplifier 10a and the peak amplifiers 10b and 10c are, for example, field effect transistors (FETs), such as GaN gallium nitride high electron mobility transistors (HEMTs) or LDMOSs (laterally diffused metal oxide semiconductors).

[0018] FIG. 2 is a diagram showing the drain efficiency of each amplifier with respect to the input power in the first embodiment. As shown in FIG. 2, when the input power Pin increases, the main amplifier 10a starts to operate. At power P1 at which the drain efficiency of the main amplifier 10a is maximized, the peak amplifiers 10b and 10c do not operate. When the input power Pin becomes greater than power P1, the peak amplifier 10b starts to operate in addition to the main amplifier 10a. At power P2 at which the drain efficiency of the peak amplifier 10b is maximized, the peak amplifier 10c does not operate. When the input power Pin becomes greater than power P2, the peak amplifier 10c starts to operate in addition to the main amplifier 10a and the peak amplifier 10b. After that, at power P3, the drain efficiency of the peak amplifier 10c becomes maximized. In this way, the input power at which the peak amplifier 10b turns on is greater than the input power at which the main amplifier 10a turns on, and the input power at which the peak amplifier 10c turns on is greater than the input power at which the peak amplifier 10b turns on. The main amplifier 10a is, for example, a class A or class AB amplifier, and the peak amplifiers 10b and 10c are, for example, class C amplifiers.

[0019] The conditions for the Doherty amplifier circuit 100 to operate as shown in FIG. 2 are as follows. Condition 1: At power P1, the output power of the main amplifier 10a is saturated, and the peak amplifiers 10b and 10c are not operating. Condition 2: At power P2, the output power of the main amplifier 10a and the peak amplifier 10b is saturated, and the peak amplifier 10c is not operating. Condition 3: At power P3, the output powers of the main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are saturated. Condition 4: The main amplifier 10a, the peak amplifier 10b, and the peak amplifier 10c are not oversaturated. Condition 5: When the peak amplifiers 10b and 10c are not operating, the impedance seen from the node N1 to the peak amplifiers 10b and 10c is open, and when the peak amplifier 10c is not operating, the impedance seen from the node N2 to the peak amplifier 10c is open.

[0020] [Circuit configuration explanation] A description will be given of a circuit configuration that satisfies the above conditions 1 to 5. Fig. 3 is a circuit diagram of a Doherty amplifier circuit according to Example 1. Matching circuits 12a to 12c are omitted from the illustration.

[0021] As shown in Fig. 3, the main amplifier 10a and the peak amplifiers 10b and 10c are transistors Q1 to Q3. The sources S of the transistors Q1 to Q3 are grounded. Signals S1 to S3 are input to the gates G of the transistors Q1 to Q3, respectively. Signals S4 to S6 are output from the drains D of the transistors Q1 to Q3, respectively. Impedance converters 25a to 25c are connected between the drains D of the transistors Q1 to Q3 and the nodes N1 to N3, respectively.

[0022] FIG. 4 is a circuit diagram of the rear stage of the transistor in the first embodiment. As shown in FIG. 4, the transistors Q1 to Q3 in FIG. 3 do not include the drain-source capacitance Cds, the drain inductance Ld, and the drain resistance Rd. The drain-source capacitance Cds is shunt-connected to the rear stage of the signal source Id, and the drain inductance Ld and the drain resistance Rd are connected in series. The drain resistance Rd is connected to the pad 43 of the semiconductor chips 40a to 40c described later. The matching circuits 14a to 14c are provided between the pad 43 and the nodes N1 to N3, respectively. The impedance converters 25a to 25c in FIG. 3 include the drain-source capacitance Cds, the drain inductance Ld, the drain resistance Rd, and the matching circuits 14a to 14c, respectively.

[0023] When transistors Q1 to Q3 are at saturation power, the load impedance Zopt (called output matching) at which the output power is maximized and the load impedance Zmod (called efficiency matching) at which the efficiency is maximized are located almost on the real axis of the Smith chart. In other words, the reactance components of the load impedances Zopt and Zmod are almost 0. For example, assuming a Doherty amplifier circuit with a center frequency of the operating band of 2 GHz, a maximum output power of each of transistors Q1 to Q3 of 200 W, and a maximum output power of the output signal Sout of 600 W, Zopt is about 2 Ω and Zmod is Zopt x M (M is about 1 to 5).

[0024] The impedance converters 20 to 22 and 25a to 25c delay the phase at the center frequency of the operating band by 90°. This converts the impedance located approximately on the real axis of the Smith chart into an impedance located approximately at a different position on the real axis of the Smith chart. The characteristic impedances of the impedance converters 20 to 22 and 25a to 25c are set by the impedances before and after the conversion. For example, in a 2-way Doherty amplifier, the impedance converters 25b and 20 can delay the phase by 180°. Since there is no node to which the peak amplifier 10c is connected, there is no need to separate the impedance converters 25b and 20. On the other hand, in an N-way Doherty amplifier (N is 3 or more), there is a node N2 between the impedance converters 20 and 25b that electrically connects the peak amplifier 10c. Therefore, the impedance converters 25b and 20 are separated, each of which delays the phase by 90°, and a node N2 is provided between them.

[0025] 3, the impedance converters 25a to 25c convert the impedances Z1a to Z1c seen from the signal sources Id of the transistors Q1 to Q3 to the impedance converters 25a to 25c, respectively, into impedances Z2a to Z2c seen from the impedance converters 25a to 25c to the nodes N1 to N3, respectively. The impedance converter 20 converts the impedance Z3b seen from the node N2 to the impedance Z3a seen from the impedance converter 20 to the node N1. The impedance converter 21 converts the impedance Z2c seen from the node N3 to the impedance Z3c seen from the impedance converter 21 to the node N2. The impedance converter 22 converts the impedance Z4 seen from the node N1 to the load impedance Z0 seen from the impedance converter 22 to the output terminal Tout.

[0026] For example, a case where the saturation power of the main amplifier 10a, the peak amplifiers 10b, and 10c are the same will be described. At power P3, the output power of the main amplifier 10a, the peak amplifiers 10b, and 10c is the maximum power Pmax. In this case, the following is assumed. At power P2, the output power of the main amplifier 10a is Pmax / 2, and the output power of the peak amplifier 10b is Pmax / 4. At power P1, the output power of the main amplifier 10a is Pmax / 3. When the input power Pin is each of powers P1 to P3, the output power of the main amplifier 10a, the peak amplifiers 10b, and 10c can be appropriately set other than the above. It is assumed that the load impedance Z0 is 50Ω, and the impedance Z4 is 16.7Ω. The load impedance Z0 and the impedance Z4 can also be appropriately set. It is assumed that the matching circuits 14a to 14c have the same configuration. The configurations of the matching circuits 14a to 14c can be appropriately set.

[0027] At power P1, the impedance seen from node N1 to impedance converter 20 is almost infinite, so impedance Z2a is 16.7Ω, the same as impedance Z4. Impedance converter 25a converts impedance Z2a of 16.7Ω to impedance Z1a of Zmod. This allows main amplifier 10a to operate with efficient matching.

[0028] In the power P2, the impedance Z4 of 16.7Ω is distributed to the impedance Z2a of 25Ω and the impedance Z3a of 50Ω. The impedance converter 20 converts the impedance Z3a of 50Ω to the impedance Z3b of 12.5Ω. Since the impedance seen from the node N2 to the impedance converter 21 is almost infinite, the impedance Z2b is 12.5Ω, which is the same as the impedance Z3b. In the power P2, the powers of the main amplifier 10a and the peak amplifier 10b are Pmax / 2 and Pmax / 4, respectively. Therefore, in order to output-match the main amplifier 10a and the peak amplifier 10b, the impedances Z1a and Z1b are 2×Zopt and 4×Zopt, respectively. The impedance converter 25a converts the impedance Z2a of 25Ω to the impedance Z1a of 2×Zopt. The impedance converter 25b converts the impedance Z2b of 12.5Ω to the impedance Z1b of 4×Zopt. As a result, the main amplifier 10a and the peak amplifier 10b operate in an output matching state.

[0029] In the power P3, the impedance Z4 of 16.7Ω is distributed to the impedance Z2a of 50Ω and the impedance Z3a of 25Ω. The characteristic impedance of the impedance converter 20 is 25Ω, and the impedance converter 20 converts the impedance Z3a of 25Ω to the impedance Z3b of 25Ω. The impedance Z3b of 25Ω is distributed to the impedance Z2b of 50Ω and the impedance Z2c of 50Ω. The characteristic impedance of the impedance converter 21 is 50Ω, and the impedance converter 21 converts the impedance Z3c of 50Ω to the impedance Z2c of 50Ω. In this way, the impedances Z2a to Z2c are all 50Ω. The impedance converters 25a to 25c convert the impedances Z2a to Z2c of 50Ω so that the impedances Z1a to Z1c are all Zopt. As a result, the main amplifier 10a and the peak amplifiers 10b and 10c operate in output matching.

[0030] As described above, by using the impedance converters 20 to 22 and 25a to 25c, the Doherty amplifier circuit 100 can be operated as shown in Fig. 2. The phase adjusters 23 and 24 align the phases of the signals S4 to S6 at the node N1. The phase adjuster 23 delays the phase of the signal S1 by about 180°, for example. The phase adjuster 24 delays the phase of the signal S2 by about 90°.

[0031] A description will be given of the semiconductor device used in Example 1. In Fig. 1, a main amplifier 10a, peak amplifiers 10b and 10c, matching circuits 12a to 12c and 14a to 14c, and impedance converters 20 and 21 are provided in a semiconductor device 102.

[0032] When the input power Pin is power P1, P2, and P3, in order to achieve a balanced wide band, the characteristic impedance of the impedance converters 25a to 25c is about √(Zopt×Zmod). When Zopt is about 2Ω, the characteristic impedance of the impedance converters 25a to 25c is 2Ω to 4Ω. The remaining part of the impedance converters 25a to 25c excluding the drain-source capacitance Cds in FIG. 4 is realized by the matching circuits 14a to 14c. For example, the matching circuits 14a to 14c are lines with a characteristic impedance of 2Ω to 4Ω and a phase of about 30° to 50°.

[0033] [Description of semiconductor device] A semiconductor device that realizes such matching circuits 14a to 14c will be described. Fig. 5 is a plan view of the semiconductor device in Example 1. Fig. 6 is a cross-sectional view taken along line AA in Fig. 5. Lid 36 is not shown in Fig. 5. The thickness direction of base 31 is defined as Z direction, the direction from lead 34a to lead 35 as X direction, and the direction perpendicular to the X direction and Z direction as Y direction.

[0034] As shown in FIG. 5 and FIG. 6, in the semiconductor device 102 of the first embodiment, the package 30 has at least a base 31 having a conductive upper surface, a frame 32, and a lid 36. The base 31 is a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the base 31. The frame 32 and the lid 36 are dielectric layers made of, for example, resin such as glass epoxy resin or ceramic. The semiconductor chips 40a to 40c, the line component 45, the high dielectric component 50, the line component 60, and the capacitive component 65 are mounted on the base 31. The frame 32 is provided on the base 31 so as to surround the semiconductor chips 40a to 40c, the line component 45, the high dielectric component 50, the line component 60, and the capacitive component 65. The lid 36 is bonded to the upper surface of the frame 32 by an insulating adhesive (not shown) such as resin. The frame 32 and the lid 36 seal the semiconductor chips 40a to 40c in the gap.

[0035] The planar shape of the frame 32 is substantially rectangular. Leads 34a to 34c (input leads) are provided on the negative side in the X direction of the frame 32. A lead 35 (output lead) is provided on the positive side in the X direction of the frame 32. The leads 34a to 34c and 35 are, for example, a metal layer or metal plate of copper or the like. Signals S1 to S3 are input to the leads 34a to 34c, respectively, and an output signal Sout is output from the lead 35.

[0036] Corresponding to path 15a, lead 34a, capacitive component 65, semiconductor chip 40a (first semiconductor chip), line component 45, and high dielectric component 50 are arranged in the X direction. Corresponding to path 15b, lead 34b, capacitive component 65, semiconductor chip 40b (second semiconductor chip), line component 45, and high dielectric component 50 are arranged in the X direction. Corresponding to path 15c, lead 34c, capacitive component 65, semiconductor chip 40c (third semiconductor chip), line component 45, and high dielectric component 50 are arranged in the X direction. Between high dielectric component 50 and frame 32, line component 60 is mounted so as to extend in the Y direction.

[0037] Each of the semiconductor chips 40a to 40c includes a semiconductor substrate 41, pads 42 and 43 provided on the upper surface of the semiconductor substrate 41, and an electrode 44 provided on the lower surface of the semiconductor substrate 41. The pads 42 and 43 and the electrode 44 are a gate electrode, a drain electrode, and a source electrode, respectively, and the pad 42 is an input pad. The pads 43 of the semiconductor chips 40a, 40b, and 40c are a first output pad, a second output pad, and a third output pad, respectively. The semiconductor substrate 41 includes the transistors Q1 to Q3 shown in FIG. 3. When the transistors Q1 to Q3 are GaN HEMTs, the semiconductor substrate 41 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOSs, the semiconductor substrate 41 is, for example, a silicon (Si) substrate. The pads 42 and 43 and the electrode 44 are, for example, metal layers such as gold layers.

[0038] The capacitive component 65 includes a dielectric substrate 66, an electrode 67 provided on an upper surface of the dielectric substrate 66, and an electrode 68 provided on a lower surface of the dielectric substrate 66. The electrodes 67 and 68 sandwiching the dielectric substrate 66 form a capacitor. The dielectric substrate 66 is, for example, an alumina substrate or a barium titanate substrate. The electrodes 67 and 68 are, for example, metal layers such as gold layers.

[0039] The line component 45 includes a dielectric substrate 46, a line pattern 47 provided on the upper surface of the dielectric substrate 46, and an electrode 48 provided on the lower surface of the dielectric substrate 46. The line pattern 47 and the electrode 48 form a transmission line. The dielectric substrate 46 is, for example, an alumina substrate. The line pattern 47 and the electrode 48 are, for example, metal layers such as gold layers.

[0040] The high dielectric component 50 includes a high dielectric substrate 51, an electrode 52 provided on the upper surface of the high dielectric substrate 51, and an electrode 53 provided on the lower surface of the high dielectric substrate 51. The electrodes 52 and 53 sandwiching the high dielectric substrate 51 form a capacitor. The high dielectric substrate 51 has a higher relative dielectric constant than an alumina substrate, such as a barium titanate substrate. The electrodes 52 and 53 are metal layers, such as gold layers.

[0041] The line component 60 includes a dielectric substrate 61, line patterns 62a and 62b provided on the upper surface of the dielectric substrate 61, and an electrode 63 provided on the lower surface of the dielectric substrate 61. The line pattern 62a and the electrode 63 form a transmission line TL01. The line pattern 62b and the electrode 63 form a transmission line TL02. The transmission lines TL01 and TL02 correspond to the impedance converters 20 and 21, respectively. The width of the transmission line TL01 in the X direction is greater than the width of the transmission line TL02 in the X direction. This makes the characteristic impedance of the transmission line TL01 lower than the characteristic impedance of the transmission line TL02. Both ends of the transmission line TL01 in the Y direction correspond to the ends 20a (first end) and 20b (second end) of the impedance converter 20, respectively. Both ends of the transmission line TL02 in the Y direction correspond to the ends 21a (third end) and 21b (fourth end) of the impedance converter 21, respectively. The electrodes 44, 48, 53, 63 and 68 are bonded to the base 31 by a conductive bonding layer 38, such as a brazing material or a metal paste.

[0042] The bonding wire 71 electrically connects the leads 34a to 34c to the electrode 67. The bonding wire 72 electrically connects the electrode 67 to the pad 42. The bonding wire 73 electrically connects the pad 43 to the line pattern 47. The bonding wire 74 electrically connects the line pattern 47 to the electrode 52. The bonding wire 75a electrically connects the electrode 52 of the path 15a to the end 20a of the line pattern 62a. The bonding wire 75b electrically connects the electrode 52 of the path 15b to the end 20b of the line pattern 62a and the end 21a of the line pattern 62b. The bonding wire 75c electrically connects the electrode 52 of the path 15c to the end 21b of the line pattern 62b. The bonding wire 76 electrically connects the end of the line pattern 62a to the lead 35. The bonding wires 71 to 76 are metal wires such as gold wires or aluminum wires.

[0043] The bonding wires 71 and 72 function as inductors, and the capacitive component 65 functions as a capacitor. Thus, the bonding wires 71, 72 and the capacitive component 65 correspond to the matching circuits 12a to 12c of the T-type LCL circuit.

[0044] Next, the matching circuits 14a to 14c are connected, taking the matching circuit 14a as an example. The configurations of the matching circuits 14b and 14c are the same as the matching circuit 14a. FIG. 7 is a plan view of a part of the semiconductor device in the first embodiment. FIG. 8 is an equivalent circuit diagram of FIG. 7. As shown in FIGS. 7 and 8, a drain-source capacitance is electrically connected between the pad 43 and a reference potential such as ground in the semiconductor chip 40a. Since the influence of the drain inductance Ld and the drain resistance Rd in FIG. 4 is small, the influence of the drain inductance Ld and the drain resistance Rd is ignored. An inductor L1 and a transmission line TL1 are connected in series between the pad 43 and the lead 35. The inductor L1 and the transmission line TL1 form a matching circuit 14a. An end 20a of the impedance converter 20 is connected to a node N1 between the transmission line TL1 and the lead 35.

[0045] The inductor L1 corresponds to the bonding wires 73 and 74 and the line component 45. The transmission line TL1 corresponds to the high-dielectric component 50. The drain-source capacitance Cds of the transistor Q1 and the matching circuit 14a form an impedance converter 25a.

[0046] Inductor L1 may be formed only with bonding wire. When forming inductor L1 using bonding wire, the bonding wire is lengthened to increase the inductance of inductor L1. In this case, there is a possibility that the bonding wire will melt if a large current flows through the bonding wire. Therefore, the length of bonding wires 73 and 74 is shortened by providing line component 45.

[0047] 3 is reduced (e.g., from 2Ω to 4Ω), the characteristic impedance of the transmission line TL1 is reduced. For example, the characteristic impedance can be adjusted by adjusting the width of the electrode 52 in the Y direction and the thickness of the high dielectric substrate 51, and the phase can be adjusted by adjusting the width of the electrode 52 in the X direction.

[0048] As described above, it is possible to reduce the characteristic impedance of the matching circuits 14a to 14c. Comparative Examples 1 to 3 will be described as a method for reducing the characteristic impedance of the matching circuits 14a to 14c.

[0049] [Comparative Example 1] Fig. 9 is a plan view of a portion of the semiconductor device in Comparative Example 1. Fig. 10 is an equivalent circuit diagram of Fig. 9. As shown in Fig. 9, in Comparative Example 1, a bonding wire 79 is provided to connect the pad 43 and the lead 35. As shown in Fig. 10, an inductor L0 is connected between the pad 43 and the lead 35. The matching circuit 14a and the impedance converter 20 are provided on a circuit board 39 on which the package 30 is mounted. The inductor L0 corresponds to the bonding wire 79.

[0050] When the matching circuits 14a to 14c are provided on the circuit board 39 on which the semiconductor device 102 is mounted as in the comparative example 1, if a transmission line with a low characteristic impedance is provided on the circuit board, the line width becomes wide. This is because the dielectric substrate of the circuit board 39 has a relatively low dielectric constant and is thick. As an example, the line width becomes about 40 mm. This increases the size of the circuit board. If the characteristic impedance of the matching circuit 14a is increased (for example, 10Ω), the matching circuit 14a becomes narrow-banded. If a wide line is used, the line connecting the matching circuits 14a to 14c and the impedance converter 20 also becomes wide. If a shunt capacitor is used without a line, resonance occurs due to the inductance of the via of the circuit board 39 for shunt connection. The characteristic impedance of the impedance converters 20 and 21 does not need to be as low as the characteristic impedance of the matching circuits 14a to 14c. However, when impedance converters 20 and 21 are provided on circuit board 39, problems such as those described in the following comparative examples 2 and 3 arise.

[0051] [Comparative Example 2] Fig. 11 is a plan view of a portion of a semiconductor device in Comparative Example 2. Fig. 12 is an equivalent circuit diagram of Fig. 11. As shown in Fig. 11, in Comparative Example 2, a capacitive component 55d is mounted on a base 31. A bonding wire 73a that connects a pad 43 and an electrode 56 of the capacitive component 55d, and a bonding wire 79a that connects the pad 43 and a lead 35 are provided.

[0052] As shown in FIG. 12, there is provided a shunt-connected inductor L2 and a capacitor C2 connected in series with the inductor L2. An inductor L0a is provided between the pad 43 and the lead 35. The inductor L2 is an inductor that compensates for the drain-source capacitance Cds. The inductance of the inductor L2 is expressed as 1 / ((2×π×f0) 2×Cds). f0 is the center frequency of the operating band. Capacitor C2 cuts DC. Matching circuit 14a and impedance converter 20 are provided on circuit board 39. Inductors L2 and L0a correspond to bonding wires 73a and 79a, respectively. Capacitor C2 corresponds to capacitive component 55d.

[0053] In Comparative Example 2, inductor L2 is provided to compensate for drain-source capacitance Cds, so impedance converter 25a that rotates the phase by 90° may be provided after pad 43. However, since bonding wire 79a passes over capacitive component 55d, the inductance of inductor L0a becomes larger than the inductance of inductor L0 in Comparative Example 1. If the inductance of inductor L0a is large, it is difficult to design an impedance converter that has a desired characteristic impedance and rotates the phase by 90° using inductor L0a and matching circuit 14a having a capacitor and an inductor, making it difficult to achieve a wide bandwidth.

[0054] [Comparative Example 3] Fig. 13 is a plan view of a portion of the semiconductor device in Comparative Example 3. Fig. 14 is an equivalent circuit diagram of Fig. 13. As shown in Fig. 13, in Comparative Example 3, high dielectric component 50b is mounted on base 31. Bonding wire 79b that connects pad 43 and electrode 52 of high dielectric component 50b, and bonding wire 79c that connects electrode 52 and lead 35 are provided.

[0055] As shown in Fig. 14, an inductor L0b, a transmission line TL0a, and an inductor L0c are connected in series between a pad 43 and a lead 35. The inductor L0b, the transmission line TL0a, and the inductor L0c form a matching circuit 14a. The impedance converter 20 is provided on a circuit board 39. The inductors L0b and L0c correspond to the bonding wires 79b and 79c, respectively. The transmission line TL0a corresponds to the high-dielectric component 50b.

[0056] In Comparative Example 3, matching circuit 14a is provided inside package 30. This allows matching circuit 14a with low characteristic impedance to be realized. However, the parasitic capacitance of lead 35 is large. Therefore, the high-frequency characteristics of lead 35 deviate significantly from an ideal transmission line. This makes it difficult to design an impedance converter that has a desired characteristic impedance and rotates the phase by 90° using matching circuit 14a and lead 35, and makes it difficult to achieve a wide bandwidth.

[0057] As an example, when the center frequency f0 is 2 GHz, the characteristic impedances of the impedance converters 20, 21, and 22 are 3.9Ω, 7.9Ω, and 11.4Ω, respectively. The characteristic impedance of the matching circuits 14a to 14c is 2.63Ω, and the phase rotation angle is 37.2°. An example will be described in which the impedance converters 20, 21, and 22 are provided on a circuit board 39 as in Comparative Example 1.

[0058] FIG. 15 is a plan view of the circuit board in Comparative Example 1. As shown in FIG. 15, packages 30a to 30c are mounted on a circuit board 39. A main amplifier 10a and peak amplifiers 10b and 10c are mounted in the packages 30a to 30c, respectively. Line patterns 58a to 58g are provided on the circuit board 39. The line pattern 58a is a line with a characteristic impedance of 50Ω. The line pattern 58b corresponds to the impedance converter 22. The line patterns 58c and 58d correspond to the impedance converters 20 and 21, respectively. The line patterns 58e to 58g correspond to the matching circuits 14a to 14c, respectively. For example, assuming that the center frequency is 2 GHz and the relative dielectric constant and thickness of the circuit board 39 are 3.5 and 500 μm, respectively, the length of the 1 / 4 wavelength line is about 20 mm. The widths of the line patterns with characteristic impedances of 2.63Ω, 3.9Ω, 7.8Ω, and 11.4Ω are 35 mm, 25 mm, 12 mm, and 7.8 mm, respectively. When these line patterns 58a to 58g are provided on the circuit board 39, the width D1 in the Y direction is about 107 mm. In this way, the circuit board 39 becomes large.

[0059] [Explanation of Example 1] 16 is a plan view of the circuit board in the first embodiment. In the first embodiment, in addition to the main amplifier 10a and the peak amplifiers 10b and 10c, matching circuits 14a to 14c and impedance converters 20 and 21 are mounted in the package 30. Therefore, it is only necessary to provide the line patterns 58a and 58b on the circuit board 39, and it is not necessary to provide the line patterns 58c to 58g. Therefore, the width D2 in the Y direction is the width of the package 30, which is smaller than the width D1 of the first comparative example.

[0060] As described above, according to the first embodiment, as shown in Fig. 5 and Fig. 7, the impedance converter 20 and the matching circuits 14a and 14b are mounted on the base 31. The end 20a of the impedance converter 20 is electrically connected to the pad 43 of the semiconductor chip 40a via the matching circuit 14a, and is also electrically connected to the lead 35. The end 20b of the impedance converter 20 is electrically connected to the semiconductor chip 40b, and is also electrically connected to the pad 43 of the semiconductor chip 40c via the impedance converter 21. The matching circuit 14a matches the impedance between the pad 43 of the semiconductor chip 40a and the end 20a. The matching circuit 14b matches the impedance between the pad 43 of the semiconductor chip 40b and the end 20b.

[0061] In this manner, by mounting the impedance converter 20 and the matching circuits 14a and 14b on the base 31, the matching circuits 14a and 14b with low characteristic impedance can be realized. As a result, the impedance converters 25a and 25b can rotate the phase between the signal source of the transistor Q1 and the node N1 and between the signal source of the transistor Q2 and the node N2 by 90°. Thus, an N-way Doherty amplifier circuit 100 can be realized. Also, the circuit board 39 can be made smaller.

[0062] The impedance converter 21 is mounted on a base 31. An end 21a of the impedance converter 21 is electrically connected to an end 20b of the impedance converter 20, is short-circuited, and has the same potential. An end 21b of the impedance converter 21 is electrically connected to a pad 43 of the semiconductor chip 40c. The matching circuit 14c matches the impedance between the pad 43 of the semiconductor chip 40c and the end 21b.

[0063] In this way, by mounting the impedance converter 21 and the matching circuit 14c on the base 31, it is possible to realize a matching circuit 14c with low characteristic impedance. As a result, the impedance converter 25c can rotate the phase between the signal source of the transistor Q3 and the node N3 by 90°. Therefore, it is possible to realize an N-way Doherty amplifier circuit 100. There may be cases where the impedance converter 21 is not necessary.

[0064] The end 20a of the impedance converter 20 is electrically connected to the pad 43 of the semiconductor chip 40a via bonding wires 73, 74, and 75a (first bonding wires). The end 20a of the impedance converter 20 is electrically connected to the lead 35 via a bonding wire 76 (second bonding wire). This allows the bonding wires 73, 74, and 75a to be used as part of the matching circuit 14a. The bonding wire 76 allows the node N1 to be electrically connected to the outside of the package 30.

[0065] An end 20b of the impedance converter 20 is electrically connected to a pad 43 of the semiconductor chip 40b via bonding wires 73, 74, and 75b (third bonding wires). An end 21b of the impedance converter 21 is electrically connected to a pad 43 of the semiconductor chip 40c via bonding wires 73, 74, and 75c (fourth bonding wires). This allows the bonding wires 73, 74, and 75b to be used as parts of the matching circuit 14b. The bonding wires 73, 74, and 75c to be used as parts of the matching circuit 14c.

[0066] The impedance converter 20 includes a line pattern 62a provided on the line component 60, and the impedance converter 21 includes a line pattern 62b provided on the line component 60. This makes it possible to form the impedance converters 20 and 21 using the transmission lines TL01 and TL02. By using the line patterns 62a and 62b, the characteristic impedance and electrical length of the impedance converters 20 and 21 can be accurately achieved.

[0067] The impedance converter 20 rotates the phase of the center frequency of the operating band by 90° between the terminals 20a and 20b, and the impedance converter 21 rotates the phase of the center frequency f0 of the operating band by 90° between the terminals 21a and 21b. This allows the impedance converters 20 and 21 to convert the impedance on the real axis of the Smith chart to the impedance on the real axis.

[0068] The matching circuit 14a rotates the phase of the center frequency f0 by 90° between the signal source of the main amplifier 10a and the end 20a. The matching circuit 14b rotates the phase of the center frequency f0 by 90° between the signal source of the peak amplifier 10b and the end 20b. The matching circuit 14c rotates the phase of the center frequency f0 by 90° between the signal source of the peak amplifier 10c and the end 20b. As a result, the impedance converters 25a to 25c, each including the matching circuits 14a to 14c, can convert the impedance on the real axis of the Smith chart into the impedance on the real axis.

[0069] As shown in FIG. 5, at the end 20a, the angle θ between the direction 80 in which the signal S4 flows and the direction 81 in which the signal S5 flows is about 90°. This allows the impedance converter 20 to be provided between the semiconductor chips 40a and 40b and the frame body 32, extending in the Y direction, and the package 30 can be made smaller. At the end 20b, the angle between the direction in which the signal S5 flows and the direction in which the signal S6 flows is also about 90°, similar to the angle θ. This allows the impedance converter 21 to be provided between the semiconductor chips 40b and 40c and the frame body 32, extending in the Y direction, and the package 30 can be made smaller. The angle θ does not have to be 90°, and can be, for example, 70° or more and 110° or less, or 80° or more and 100° or less.

[0070] Rotating the phase of the center frequency f0 by 90° does not have to be strictly 90°. For example, the phase to be rotated is 70° or more and 110° or less, or 85° or more and 95° or less. Furthermore, the impedance on the real axis does not have to be strictly on the real axis (i.e., the reactance component is 0). The absolute value of the reactance component of the impedance may be 1.0 times or less than the resistance component, or 0.2 times or less.

[0071] [Another example of impedance converters 20 and 21] Fig. 17 is a plan view of a semiconductor device showing another example of the impedance converter in the first embodiment. As shown in Fig. 17, in a semiconductor device 104, a line component 60a includes electrodes 63a to 63c on a dielectric substrate 61. The electrodes 63a and 63b are electrically connected by a bonding wire 78a. The electrodes 63b and 63c are electrically connected by a bonding wire 78b. The electrode 63a is connected to bonding wires 75a and 76. The electrodes 63b and 63c are connected to bonding wires 75b and 75c, respectively.

[0072] 18 is a circuit diagram showing another example of the impedance converter in the first embodiment. An inductor L01 is connected between nodes N1 and N2, and an inductor L02 is connected between nodes N2 and N3. Capacitors C01, C02, and C03 are shunt-connected to nodes N1 to N3, respectively. The capacitors C01 and C02 and the inductor L01 form an impedance converter 20, and the capacitors C02, C03, and the inductor L02 form an impedance converter 21. The capacitors C01, C02, and C03 correspond to the electrodes 63a to 63c and the base 31, which sandwich the dielectric substrate 61, respectively. The inductors L01 and L02 correspond to the bonding wires 78a and 78b, respectively.

[0073] The target characteristic impedances of the impedance converters 20 and 21 are Z01 and Z02, respectively, the capacitances of the capacitors C01 to C03 are C01 to C03, respectively, and the inductances of the inductors L01 and L02 are L01 and L02, respectively. In this case, the following are set: L01=Z01 / (2×π×f0), L02=Z02 / (2×π×f0), C01=(2×π×f0) / Z01, C02=(2×π×f0) / Z01+(2×π×f0) / Z02, C03=(2×π×f0) / Z02. This allows the characteristic impedances Z01 and Z02 of the impedance converters 20 and 21 to be set to the target values.

[0074] As shown in FIG. 17 and FIG. 18, the impedance converter 20 may include a capacitor C01 (first capacitor), a capacitor C02 (second capacitor), and a bonding wire 78a (fifth bonding wire). The first ends of the capacitors C01 and C02 are electrically connected to the base 31. The bonding wire 78a electrically connects the second end of the capacitor C01 to the second end of the capacitor C02. The impedance converter 21 may include capacitors C02, C03, and a bonding wire 78b. The first ends of the capacitors C02 and C03 are electrically connected to the base 31. The bonding wire 78b electrically connects the second end of the capacitor C02 to the second end of the capacitor C03. This allows the impedance converters 20 and 21 to be formed. Although an example in which the electrodes 63a to 63c are provided on one dielectric substrate 61 has been described, the electrodes 63a to 63c may be provided on different dielectric substrates 61.

[0075] [Another example 1 of matching circuits 14a to 14c] The matching circuit 14a will be described as an example of the matching circuits 14a to 14c, but the matching circuits 14b and 14c can be formed in the same manner. The same applies to other examples 2 to 4 of the matching circuits 14a to 14c described later. FIG. 19 is a plan view showing another example 1 of the matching circuit in the first embodiment. FIG. 20 is an equivalent circuit diagram of FIG. 19. As shown in FIG. 19, in another example 1 of the matching circuit 14a, a capacitive component 55a is mounted on a base 31. A bonding wire 77a electrically connects the pad 43 and the electrode 57 of the capacitive component 55a, and a bonding wire 75a electrically connects the electrode 57 and the end 20a are provided.

[0076] 20, there is provided an inductor L1a that connects the pad 43 and a node N1, and a capacitor C1a that is shunt-connected between the inductor L1a and the node N1. The inductor L1a corresponds to the bonding wire 77a. The capacitor C1a corresponds to the capacitive component 55a.

[0077] The capacitance of the capacitor C1a is set to Cds, and the inductance of the inductor L1a is set to 1 / ((2×π×f0) 2 ×Cds), impedance converter 25a rotates the phase of center frequency f0 by 90°. The characteristic impedance of impedance converter 25a is 1 / (2×π×f0×Cds). In another example 1 of matching circuits 14a to 14c, the characteristic impedance cannot be freely set, but the number of parts mounted on base 31 can be reduced.

[0078] [Another example 2 of matching circuits 14a to 14c] Fig. 21 is a plan view showing another example 2 of the matching circuit in the first embodiment. Fig. 22 is an equivalent circuit diagram of Fig. 21. As shown in Fig. 21, in another example 2 of the matching circuit 14a, capacitive components 55d and 55b are mounted on a base 31. A bonding wire 73a electrically connects the pad 43 and the electrode 57 of the capacitive component 55d, a bonding wire 77b electrically connects the pad 43 and the electrode 57 of the capacitive component 55b, and a bonding wire 75a electrically connects the electrode 57 of the capacitive component 55b and the end 20a are provided.

[0079] As shown in Fig. 22, an inductor L2 is shunt-connected, and a capacitor C2 is connected in series to the inductor L2. An inductor L1b connects the pad 43 and a node N1, and a capacitor C1b is shunt-connected between the inductor L1b and the node N1. The inductors L2 and L1b correspond to the bonding wires 73a and 77b, respectively. The capacitors C2 and C1b correspond to the capacitive components 55d and 55b, respectively.

[0080] The inductance of inductor L2 is 1 / ((2×π×f0) 2×Cds). As a result, inductor L2 does not completely compensate for drain-source capacitance Cds. The uncompensated capacitance component is taken as ΔCds. Capacitor C2 is a DC blocking capacitor, and its capacitance is large enough not to affect inductor L2 at center frequency f0. The inductance of inductor L1b is 1 / ((2×π×f0) 2 ×(Cds-ΔCds)) and the capacitance of capacitor C1b is Cds-ΔCds. As a result, impedance converter 25a rotates the phase of center frequency f0 by 90°. The characteristic impedance of impedance converter 25a is 1 / (2×π×f0×(Cds-ΔCds)). In this way, by selecting the value of ΔCds, the characteristic impedance of impedance converter 25a can be set arbitrarily, compared to alternative example 1.

[0081] Instead of the inductor L2 and the capacitor C2, the capacitor C2 may be provided without providing an inductor. In this case, the capacitance of the capacitor C2 is ΔCds. The inductance of the inductor L1b is 1 / ((2×π×f0) 2 ×(Cds+ΔCds)) and the capacitance of capacitor C1b is Cds+ΔCds. As a result, impedance converter 25a rotates the phase of center frequency f0 by 90°. The characteristic impedance of impedance converter 25a is 1 / (2×π×f0×(Cds+ΔCds)). In this case as well, the characteristic impedance of impedance converter 25a can be set arbitrarily.

[0082] [Another example 3 of matching circuits 14a to 14c] Fig. 23 is a plan view showing another example 3 of the matching circuit in the first embodiment. Fig. 24 is an equivalent circuit diagram of Fig. 23. As shown in Fig. 23, in another example 3 of the matching circuit 14a, a capacitive component 55d and a high dielectric component 50a are mounted on a base 31. A bonding wire 73a electrically connects the pad 43 and the electrode 57 of the capacitive component 55d, a bonding wire 77c electrically connects the pad 43 and the electrode 52 of the high dielectric component 50a, and a bonding wire 75a electrically connects the electrode 52 of the high dielectric component 50a and the end 20a are provided.

[0083] As shown in Fig. 24, an inductor L2 is shunt-connected, and a capacitor C2 is connected in series to the inductor L2. An inductor L1c and a transmission line TL1a are connected in series between a pad 43 and a node N1. The inductors L2 and L1c correspond to the bonding wires 73a and 77c, respectively. The capacitor C2 corresponds to the capacitive component 55d. The transmission line TL1a corresponds to the high-dielectric component 50a.

[0084] The inductance of inductor L2 is 1 / ((2×π×f0) 2 ×Cds). As a result, the inductor L2 compensates for the drain-source capacitance Cds. The phase of the center frequency f0 can be rotated by 90° using the inductor L1c and the transmission line TL1a. The characteristic impedance and the phase to be rotated of the transmission line TL1a can be set in the same way as for the high dielectric component 50 in Figs. 7 and 8. Since the drain-source capacitance Cds is compensated for in this way, the phase to be rotated by the transmission line TL1a only needs to be set to about 90°, which makes it easier to design the high dielectric component 50a.

[0085] [Another Example 4 of Matching Circuits 14a to 14c] Fig. 25 is a plan view showing another example 4 of the matching circuit in the first embodiment. Fig. 26 is an equivalent circuit diagram of Fig. 25. As shown in Fig. 25, in another example 4 of the matching circuit 14a, a capacitive component 55d and a capacitive component 55c are mounted on a base 31. A bonding wire 73a electrically connects the pad 43 and the electrode 57 of the capacitive component 55d, a bonding wire 77d electrically connects the pad 43 and the electrode 52 of the capacitive component 55c, and a bonding wire 75a electrically connects the electrode 52 of the capacitive component 55c and the end 20a are provided.

[0086] As shown in Fig. 26, the inductor L2 is shunt-connected, and the capacitor C2 is connected in series to the inductor L2. The inductors L1d and L3 are connected in series between the pad 43 and the node N1. The capacitor C1c is shunt-connected to the node between the inductors L1d and L3. The inductors L2, L1d, and L3 correspond to the bonding wires 73a, 77d, and 75a, respectively. The capacitors C2 and C1c correspond to the capacitive components 55d and 55c, respectively.

[0087] The inductance of inductor L2 is 1 / ((2×π×f0) 2 ×Cds). As a result, the inductor L2 compensates for the drain-source capacitance Cds. The phase of the center frequency f0 can be rotated by 90° using inductors L1d, L3 and capacitor C1c. For example, when the characteristic impedance of the impedance converter 25a is Z0, the inductances of inductors L1d and L3 are set to Z0 / (2×π×f0), and the capacitance of capacitor C1c is set to 1 / (2×π×f0×Z0). Since the drain-source capacitance Cds is compensated for in this way, the design of inductors L1d, L3 and capacitor C1c becomes easier.

[0088] In the first embodiment, the semiconductor substrates 41 of the semiconductor chips 40a to 40c are separate from each other. However, at least two of the semiconductor substrates 41 of the semiconductor chips 40a to 40c may be provided as a common integrated substrate.

[0089] Although a 3-way Doherty amplifier circuit has been described as an example, in the case of an N-way Doherty amplifier circuit, N semiconductor chips 40a to 40c, N matching circuits 14a to 14c, and N-1 impedance converters 20 and 21 may be provided.

[0090] Although the saturation power of the main amplifier 10a and the peak amplifiers 10b and 10c has been described as being the same, the saturation power of the main amplifier 10a and the peak amplifiers 10b and 10c may be different from each other. For example, the saturation power of the peak amplifiers 10b and 10c may be twice that of the main amplifier 10a.

[0091] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0092] 10a main amplifier 10b, 10c Peak amplifier 12a, 12b, 12c, 14a, 14b, 14c matching circuit Routes 15a, 15b, and 15c 16 Distributor 18 Synthesizer 20, 21, 25a, 25b, 25c Impedance converter 20a, 20b, 21a, 21b ends 23, 24 Phase adjuster 30 Packages 31 Base 32 Frame 34a, 34b, 34c, 35 Lead 36 Lid 39 Circuit Board 40a, 40b, 40c Semiconductor chip 41 Semiconductor Substrate 42, 43 Pad 44, 48, 52, 53, 56, 57, 63, 63a, 63b, 63c, 67, 68 electrode 45, 60 Track parts 46 Dielectric Substrate 47, 58a, 58b, 58c, 58d, 58e, 58f, 58g, 62a, 62b track patterns 50, 50a, 50b High dielectric components 51 High dielectric substrate 55a, 55b, 55c, 55d, 65 Capacitive components 71, 72, 73, 73a, 74, 75a, 75b, 75c, 76, 77a, 77c, 77d, 78a, 78b, 79, 79a, 79b, 79c Bonding wire 80, 81 direction 100 Doherty amplifier circuit 102, 104 Semiconductor device

Claims

1. a package having a base and an output lead; a first semiconductor chip mounted on the base, the first semiconductor chip including a main amplifier for amplifying a first signal obtained by distributing an input signal, and a first output pad for outputting the amplified first signal; a second semiconductor chip mounted on the base, the second semiconductor chip including a first peak amplifier that amplifies a second signal obtained by dividing the input signal, and a second output pad that outputs the amplified second signal; a third semiconductor chip mounted on the base, the third semiconductor chip including a second peak amplifier that amplifies a third signal obtained by dividing the input signal, and a third output pad that outputs the amplified third signal; a first impedance converter mounted on the base, the first end being electrically connected to the first output pad and the output lead and the second end being electrically connected to the second output pad and the third output pad; a first matching circuit mounted on the base and configured to match impedance between the first output pad and the first end; a second matching circuit mounted on the base and configured to match an impedance between the second output pad and the second end; A semiconductor device comprising:

2. a second impedance transformer mounted on the base, the second impedance transformer having a third end electrically connected to the second end of the first impedance transformer and a fourth end electrically connected to the third output pad; a third matching circuit that matches an impedance between the third output pad and the fourth end; The semiconductor device according to claim 1 .

3. the first end is electrically connected to the first output pad via a first bonding wire; 3. The semiconductor device according to claim 1, wherein the first end is electrically connected to the output lead via a second bonding wire.

4. The semiconductor device according to claim 3 , wherein the second end is electrically connected to the second output pad via a third bonding wire.

5. the first end is electrically connected to the first output pad via a first bonding wire; the second end is electrically connected to the output lead via a second bonding wire; the second end and the third end are electrically connected to the second output pad via a third bonding wire; The semiconductor device according to claim 2 , wherein the fourth end is electrically connected to the third output pad via a fourth bonding wire.

6. a line component including a dielectric substrate mounted on the base and a line pattern provided on the dielectric substrate, The semiconductor device according to claim 1 , wherein the first impedance converter includes the line pattern.

7. a first capacitor mounted on the base and having a first end electrically connected to the base; a second capacitor mounted on the base and having a first end electrically connected to the base; a fifth bonding wire electrically connecting a second end of the first capacitor and a second end of the second capacitor; Equipped with 3. The semiconductor device according to claim 1, wherein the first impedance converter includes the first capacitor, the second capacitor, and the fifth bonding wire.

8. 3. The semiconductor device according to claim 1, wherein the first impedance converter rotates a phase of a center frequency of an operating band by 90 degrees between the first end and the second end.

9. the first matching circuit rotates the phase of the center frequency by 90° between a signal source of the main amplifier and the first end; The semiconductor device according to claim 8 , wherein the second matching circuit rotates a phase of the center frequency by 90° between a signal source of the first peak amplifier and the second end.

10. The first impedance converter rotates a phase of a center frequency of an operating band by 90° between the first end and the second end, the second impedance converter rotates a phase of a center frequency of an operating band by 90° between the third end and the fourth end; the first matching circuit rotates the phase of the center frequency by 90° between a signal source of the main amplifier and the first end; the second matching circuit rotates a phase of the center frequency by 90° between a signal source of the first peak amplifier and the second end and between the signal source of the first peak amplifier and the third end; 6. The semiconductor device according to claim 2, wherein the third matching circuit rotates a phase of the center frequency by 90 degrees between a signal source of the second peak amplifier and the fourth terminal.

11. an input power of the input signal at which the first peak amplifier is turned on is greater than the input power at which the main amplifier is turned on; 3 . The semiconductor device according to claim 1 , wherein the input power at which the second peak amplifier is turned on is greater than the input power at which the first peak amplifier is turned on.

12. 3. The semiconductor device according to claim 1, wherein an angle between a direction in which the amplified first signal flows and a direction in which the amplified second signal flows at the first end is greater than or equal to 70° and less than or equal to 110°.

13. A semiconductor device according to claim 1 or 2, a distributor that distributes the input signal into the first signal, the second signal, and the third signal; A Doherty amplifier circuit comprising:

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