Ad conversion circuit

Abstract

To provide an AD conversion circuit with low distortion.SOLUTION: An AD conversion circuit (101) includes: a delta-sigma converter (1) that converts an analog input voltage into one bit digital output data; a reference voltage source (2) that outputs a reference voltage for determining a full scale of AD conversion; a detection circuit (3) that includes at least one of a first detection circuit (31) that detects from the one bit digital output data that the analog input voltage is lower than a first voltage value and a second detection circuit (32) that detects from the one bit digital output data that the analog input voltage is higher than a second voltage value, the second voltage value being higher than the first voltage value; and a correction circuit (4) that corrects the reference voltage based on detection results of the detection circuit and outputs the corrected reference voltage. The delta-sigma converter performs delta-sigma conversion based on an output of the correction circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an AD conversion circuit. [Background technology]

[0002] In recent years, AD conversion circuits have been used in a variety of applications.

[0003] As an example of the related art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-134696 A

[0005] [overview] A ΔΣ AD conversion circuit is used when high resolution is required, and high accuracy (low distortion) is also required for the distortion characteristics.

[0006] However, as the resolution increases, slight nonlinearity in the circuit affects the distortion characteristics, making it difficult to achieve low distortion.

[0007] The AD conversion circuit according to the present disclosure includes a ΔΣ converter configured to convert an analog input voltage into 1-bit digital output data, a reference voltage source configured to output a reference voltage for determining a full scale of AD conversion, a detection circuit including at least one of a first detection circuit configured to detect from the 1-bit digital output data that the analog input voltage is lower than a first voltage value and a second detection circuit configured to detect from the 1-bit digital output data that the analog input voltage is higher than a second voltage value and to set the second voltage value higher than the first voltage value, and a correction circuit configured to correct the reference voltage based on a detection result of the detection circuit and output the corrected reference voltage. The ΔΣ converter is configured to perform ΔΣ conversion based on an output of the correction circuit. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration of an AD conversion circuit according to the first embodiment. [Diagram 2] FIG. 2 is a timing chart showing an example of waveforms of an analog input voltage and a corrected reference voltage. [Diagram 3] FIG. 3 is a diagram showing an example of the relationship between the analog input voltage and the digital output data when the reference voltage is not corrected. [Figure 4] FIG. 4 is a timing chart showing example waveforms of an analog input voltage, a voltage corresponding to 1-bit digital output data when the reference voltage is not corrected, and a voltage obtained by smoothing the corrected reference voltage. [Diagram 5] FIG. 5 is a diagram illustrating an example of the configuration of a ΔΣ converter. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of the detection circuit. [Figure 7] FIG. 7 is a diagram illustrating an example of a configuration of a correction circuit. [Figure 8] FIG. 8 is a diagram showing a configuration of an AD conversion circuit according to the second embodiment.

[0009] [Detailed Description] First Embodiment 1 is a diagram showing a configuration of an AD conversion circuit 101 according to a first embodiment (hereinafter referred to as "AD conversion circuit 101"). The AD conversion circuit 101 includes a ΔΣ converter 1, a reference voltage source 2, a detection circuit 3, a correction circuit 4, and a non-volatile memory 5.

[0010] The ΔΣ converter 1 converts an analog input voltage AIN into 1-bit digital output data DOUT. The ΔΣ converter 1 performs ΔΣ conversion based on a reference voltage VREF2 output from a correction circuit 4.

[0011] The reference voltage source 2 outputs a reference voltage VREF1 to determine the full scale of AD conversion.

[0012] The detection circuit 3 includes a first detection circuit 31 and a second detection circuit 32. The first detection circuit 31 detects from the 1-bit digital output data DOUT that the analog input voltage AIN is lower than a first voltage value V1. The second detection circuit 32 detects from the 1-bit digital output data DOUT that the analog input voltage AIN is higher than a second voltage value V2. Note that the second voltage value V2 is higher than the first voltage value V1.

[0013] The correction circuit 4 corrects the reference voltage VREF1, which is a DC voltage, based on the detection result of the detection circuit 3, and outputs a reference voltage VREF2, which is the corrected reference voltage. When the correction amount C1 in the correction circuit 4 is zero, the reference voltage VREF2 has the same voltage waveform as the reference voltage VREF1, and when the correction amount C1 in the correction circuit 4 is not zero, the reference voltage VREF2 has a voltage waveform different from that of the reference voltage VREF1.

[0014] The nonvolatile memory 5 nonvolatilely stores the first voltage value V1, the second voltage value V2, and the correction amount C1 in the correction circuit 4. The first voltage value V1 read from the nonvolatile memory 5 is used in the first detection circuit 31. The second voltage value V2 read from the nonvolatile memory 5 is used in the second detection circuit 32. The correction circuit 4 corrects the reference voltage VREF1 by the correction amount C1 in the correction circuit 4 read from the nonvolatile memory 5. The correction amount C1 may be set to the same value when the analog input voltage AIN is lower than the first voltage value V1 and to be set to different values ​​when the analog input voltage AIN is higher than the second voltage value V2.

[0015] 2 is a timing chart showing an example of waveforms of the analog input voltage AIN and the reference voltage VREF2 (reference voltage after correction). In the example shown in FIG. 2, the correction amount C1 is set differently when the analog input voltage AIN is lower than the first voltage value V1 and when the analog input voltage AIN is higher than the second voltage value V2. In the example shown in FIG. 2, the correction amount C1 when the analog input voltage AIN is lower than the first voltage value V1 is the correction amount C1D, and the correction amount C1 when the analog input voltage AIN is higher than the second voltage value V2 is the correction amount C1U. In the example shown in FIG. 2, when the analog input voltage AIN is equal to or higher than the first voltage value V1 and equal to or lower than the second voltage value V2, the correction amount C1 in the correction circuit 4 becomes zero, and the reference voltage VREF2 has the same voltage waveform as the reference voltage VREF1. On the other hand, when the analog input voltage AIN is lower than the first voltage value V1, the correction amount C1 in the correction circuit 4 is not zero, and the reference voltage VREF2 has a voltage waveform different from that of the reference voltage VREF1, more specifically, a waveform of a compression wave (first compression wave) that alternates between the value REF1 of the reference voltage VREF1 and a value REF2D (=REF1-C1D) different from the value REF1. The larger the difference between the analog input voltage AIN and the first voltage value V1, the more the time (frequency) that the first compression wave has the value REF2D increases. Also, when the analog input voltage AIN is higher than the second voltage value V2, the correction amount C1 in the correction circuit 4 is not zero, and the reference voltage VREF2 has a voltage waveform different from that of the reference voltage VREF1, more specifically, a waveform of a compression wave (second compression wave) that alternates between the value REF1 of the reference voltage VREF1 and a value REF2U (=REF1-C1U) different from the value REF1. The larger the difference between the analog input voltage AIN and the second voltage value V2, the more time (frequency) the second compression wave has the value REF2U. Note that the voltage VREF20 in Fig. 2 is a voltage obtained when the reference voltage VREF2 is smoothed by an LPF (Low Pass Filter). In the example shown in Fig. 2, the values ​​REF2D and REF2U different from the value REF1 are smaller than the value REF1, but the values ​​REF2D and REF2U different from the value REF1 may be larger than the value REF1.

[0016] FIG. 3 is a diagram showing an example of the relationship between the analog input voltage AIN and the digital output MDOUT when the reference voltage VREF1 is not corrected. The digital output shown in FIG. 3 is the digital output MDOUT when the 1-bit serial output data DOUT is multi-bited by an appropriate decimation filter. In the example shown in FIG. 3, when the analog input voltage AIN is lower than the first voltage value V1 and when the analog input voltage AIN is higher than the second voltage value V2, the linearity between the analog input voltage AIN and the digital output MDOUT decreases. FIG. 4 is a timing chart showing an example of the waveforms of the analog input voltage AIN, the voltage DOUT0 corresponding to the 1-bit digital output data DOUT when the reference voltage VREF1 is not corrected, and the voltage VREF20 obtained by smoothing the reference voltage VREF2 (the reference voltage after correction). The example shown in FIG. 4 corresponds to the example shown in FIG. 3. The voltage DOUT0 is obtained by amplifying the distortion component to make the distortion easier to understand.

[0017] In the examples shown in FIG. 3 and FIG. 4, when the analog input voltage AIN is lower than the first voltage value V1 and when the analog input voltage AIN is higher than the second voltage value V2, the sensitivity of the AD conversion is decreased and the distortion is increased. Therefore, the distortion can be reduced by increasing the sensitivity of the AD conversion by lowering the reference voltage VREF2 (reference voltage after correction). If the sensitivity of the AD conversion is increased when the analog input voltage AIN is lower than the first voltage value V1, the reference voltage VREF2 (reference voltage after correction) can be increased to decrease the sensitivity of the AD conversion. If the sensitivity of the AD conversion is increased when the analog input voltage AIN is higher than the second voltage value V2, the reference voltage VREF2 (reference voltage after correction) can be increased to decrease the sensitivity of the AD conversion. In other words, the AD conversion circuit 101 can apply an inverse characteristic to the generated distortion by correcting the reference voltage VREF1 to the reference voltage VREF2 as described above, and the distortion can be reduced by the inverse characteristic.

[0018] When the analog input voltage AIN is higher than the second voltage value V2, it is desirable to set the correction amount C1 in the correction circuit 4 so that the reference voltage VREF2 (corrected reference voltage) becomes lower as the difference between the analog input voltage AIN and the second voltage value V2 increases. This makes it possible to further reduce distortion. The correction amount C1 may change continuously according to the difference between the analog input voltage AIN and the second voltage value V2, or may change discretely according to the difference between the analog input voltage AIN and the second voltage value V2.

[0019] The waveform example of the reference voltage VREF2 (reference voltage after correction) shown in Fig. 2 corresponds to the examples shown in Fig. 3 and Fig. 4. The relationship between the analog input voltage AIN and the 1-bit digital output data DOUT when the reference voltage VREF1 is not corrected may be found by measurement or simulation for each type of AD conversion circuit 101, and the first voltage value V1, the second voltage value V2, and the correction amount C1 in the correction circuit 4 may be set based on the found relationship and written to the non-volatile memory 5. The type of the non-volatile memory 5 is not particularly limited. For example, a flash memory, a ROM (Read Only Memory), etc. may be used as the non-volatile memory 5.

[0020] Fig. 5 is a diagram showing an example configuration of the ΔΣ converter 1. The ΔΣ converter 1 of the example configuration shown in Fig. 5 includes a subtractor 11, an integrator 12, a quantizer 13, and a 1-bit D / A converter 14. The 1-bit digital output data DOUT is the duty ratio of the bit stream output from the quantizer 13, and represents the ratio (AIN / VREF2) of the analog input voltage AIN to the reference voltage VREF2.

[0021] 6 is a diagram showing an example of the configuration of the detection circuit 3. The detection circuit 3 of the example configuration shown in FIG.

[0022] The delay devices 301-303 and the NOR gate 304 constitute a first detection circuit. The NOR gate 304 outputs a first detection signal DET1 which is a NOR of the outputs of the delay devices 301-303. The first detection circuit constituted by the delay devices 301-303 and the NOR gate 304 detects that the analog input voltage AIN is lower than a first voltage value V1 when the 1-bit digital output data DOUT is 0 an arbitrary number of times (three times in this example) in succession. The first detection circuit constituted by the delay devices 301-303 and the NOR gate 304 sets the first detection signal DET1 to a high level when it detects that the analog input voltage AIN is lower than the first voltage value V1, and sets the first detection signal DET1 to a low level when it does not detect that the analog input voltage AIN is lower than the first voltage value V1.

[0023] The delay devices 301-303 and the AND gate 305 constitute a second detection circuit. The AND gate 305 outputs a second detection signal DET2 which is the logical product of the outputs of the delay devices 301-303. The second detection circuit constituted by the delay devices 301-303 and the AND gate 305 detects that the analog input voltage AIN is higher than a second voltage value V2 when the 1-bit digital output data DOUT is 1 an arbitrary number of times (three times in this example) in succession. The second detection circuit constituted by the delay devices 301-303 and the AND gate 305 sets the second detection signal DET2 to a high level when it detects that the analog input voltage AIN is higher than the second voltage value V2, and sets the second detection signal DET2 to a low level when it does not detect that the analog input voltage AIN is higher than the second voltage value V2.

[0024] 6, the number (the number of taps) of the multiple delay elements electrically connected to the NOR gate 304 is variable according to the first voltage value V1. Similarly, the number (the number of taps) of the multiple delay elements electrically connected to the AND gate 305 is variable according to the second voltage value V2.

[0025] FIG. 7 is a diagram showing an example of a configuration of a correction circuit. The correction circuit 4 of the configuration example shown in FIG. 7 includes an operational amplifier OP1, a resistor R1 with a fixed resistance value, a resistor R2 with a fixed resistance value, and a variable resistor R3 with a variable resistance value. The operational amplifier OP1 generates and outputs a reference voltage VREF2 according to the difference between a reference voltage VRE1 and a divided voltage of the reference voltage VRE2. A voltage divider circuit formed by the resistors R1, R2, and the variable resistor R3 divides the reference voltage VRE2. Therefore, the value of the reference voltage VRE2 varies according to the resistance value of the variable resistor R3. The resistance value of the variable resistor R3 becomes a default value when both the first detection signal DET1 and the second detection signal DET2 are at a low level, and becomes a value different from the default value when either one of the first detection signal DET1 and the second detection signal DET2 is at a high level.

[0026] <Second embodiment> 8 is a diagram showing a configuration of an AD conversion circuit 102 according to a second embodiment (hereinafter referred to as "AD conversion circuit 102"). The AD conversion circuit 102 has a configuration in which a temperature sensor 6, a power supply voltage detection circuit 7, a clock frequency detection circuit 8, and an adjustment circuit 9 are added to the AD conversion circuit 101. Note that the temperature sensor 6, the power supply voltage detection circuit 7, and the clock frequency detection circuit 8 may be provided outside the AD conversion circuit 102.

[0027] The temperature sensor 6 detects the temperature around the temperature sensor 6 and outputs the detection result.

[0028] The power supply voltage detection circuit 7 is a monitor circuit that monitors the power supply voltage, detects the value of the power supply voltage, and outputs the detection result. The power supply voltage monitored by the power supply voltage detection circuit 7 is the power supply voltage supplied to the ΔΣ converter 1. The ΔΣ converter 1 is driven by the supplied power supply voltage.

[0029] The clock frequency detection circuit 8 is a monitor circuit that monitors the frequency of the clock signal (clock frequency), detects the clock frequency, and outputs the detection result. The clock frequency monitored by the clock frequency detection circuit 8 is the frequency of the clock signal supplied to the ΔΣ converter 1. The ΔΣ converter 1 operates based on the supplied clock signal.

[0030] The correction circuit 4 and the adjustment circuit 9 are circuits that adjust the correction amount C1 in the correction circuit 4 in accordance with the output of the temperature sensor 6, the output of the power supply voltage detection circuit 7, and the output of the clock frequency detection circuit 8, and correct the reference voltage VREF1 with the adjusted correction amount C1.

[0031] The adjustment circuit 9 adjusts the correction amount C1 in the correction circuit 4, which is read from the nonvolatile memory 5, according to the output of the temperature sensor 6, the output of the power supply voltage detection circuit 7, and the clock frequency detection circuit 8, and outputs the adjusted correction amount C1 to the correction circuit 4. The correction circuit 4 corrects the reference voltage VREF1 with the adjusted correction amount C1 to generate the reference voltage VREF2.

[0032] The relationship between the output of the temperature sensor 6, the output of the power supply voltage detection circuit 7, and the output of the clock frequency detection circuit 8 and the adjustment contents in the adjustment circuit 9 can be found, for example, by measurement or simulation for each type of AD conversion circuit 101, and the found relationship can be written in the non-volatile memory 5 in the form of table data, a formula, or the like.

[0033] <Other> The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The technical scope of the present disclosure is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0034] For example, in the first and second embodiments described above, the detection circuit 3 is configured to include both the first detection circuit 31 and the second detection circuit 32, but the detection circuit 3 may be configured to include only one of the first detection circuit 31 and the second detection circuit 32.

[0035] For example, in the second embodiment described above, the correction amount C1 in the correction circuit 4 was adjusted in accordance with the output of the temperature sensor 6, the output of the power supply voltage detection circuit 7, and the output of the clock frequency detection circuit 8, but the correction amount C1 in the correction circuit 4 may be adjusted in accordance with any one or any two of the output of the temperature sensor 6, the output of the power supply voltage detection circuit 7, and the output of the clock frequency detection circuit 8.

[0036] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0037] The AD conversion circuit (101, 102) of the present disclosure comprises a ΔΣ converter (1) configured to convert an analog input voltage into 1-bit digital output data, a reference voltage source (2) configured to output a reference voltage for determining the full scale of the AD conversion, a detection circuit (3) including at least one of a first detection circuit (31) configured to detect from the 1-bit digital output data that the analog input voltage is lower than a first voltage value, and a second detection circuit (32) configured to detect from the 1-bit digital output data that the analog input voltage is higher than a second voltage value and so that the second voltage value is higher than the first voltage value, and a correction circuit (4, 9) configured to correct the reference voltage based on the detection result of the detection circuit and output the corrected reference voltage, and the ΔΣ converter is configured to perform ΔΣ conversion based on the output of the correction circuit (first configuration).

[0038] According to the AD conversion circuit of the first configuration, it is possible to reduce the generated distortion by applying an inverse characteristic to the generated distortion.

[0039] In the AD conversion circuit of the first configuration described above, the detection circuit may be configured (second configuration) to include at least the first detection circuit and to have a non-volatile memory (5) configured to non-volatilely store the first voltage value and the correction amount in the correction circuit.

[0040] In the AD conversion circuit of the first configuration described above, the detection circuit may be configured (third configuration) to include at least the second detection circuit and to have a non-volatile memory (5) configured to non-volatilely store the second voltage value and the correction amount in the correction circuit.

[0041] In the AD conversion circuit of any of the first to third configurations, the detection circuit may include at least the first detection circuit, and the first detection circuit may be configured to detect that the analog input voltage is lower than the first voltage value when the 1-bit digital output data is 0 an arbitrary number of times in succession (fourth configuration).

[0042] In the AD conversion circuit of any of the above first to fourth configurations, the detection circuit may include at least the second detection circuit, and the second detection circuit may be configured to detect that the analog input voltage is higher than the second voltage value when the 1-bit digital output data is 1 an arbitrary number of times in succession (fifth configuration).

[0043] In the AD conversion circuit of any of the first to fifth configurations, the correction circuit may be configured to adjust the amount of correction in response to the output of a temperature sensor (6) (sixth configuration).

[0044] In the AD conversion circuit of any of the first to sixth configurations above, the ΔΣ converter may be driven by a power supply voltage, and the correction circuit may be configured to adjust the amount of correction depending on the output of a first monitor circuit (7) configured to monitor the power supply voltage (seventh configuration).

[0045] In the AD conversion circuit of any of the above first to seventh configurations, the ΔΣ converter may operate based on a clock signal, and the correction circuit may be configured to adjust the amount of correction in accordance with the output of a second monitor circuit (8) configured to monitor the frequency of the clock signal (8th configuration). [Explanation of symbols]

[0046] 1 Delta-Sigma Converter 2 Reference Voltage Source 3. Detection circuit 4. Compensation circuit 5 Non-volatile memory 6 Temperature Sensor 7 Power supply voltage detection circuit 8 Clock Frequency Detection Circuit 9 Adjustment circuit 11 Subtractor 12 Integrator 13 Quantizer 14 1-bit D / A converter 31 First detection circuit 32 Second detection circuit 101 AD conversion circuit according to the first embodiment 102 AD conversion circuit according to the second embodiment 301, 302, 303 Delay 304 NOR Gate 305 AND Gate OP1 Operational Amplifier R1, R2 resistance R3 variable resistor

Claims

1. A ΔΣ converter configured to convert an analog input voltage into 1-bit digital output data; A reference voltage source configured to output a reference voltage for determining a full scale of AD conversion; a detection circuit including at least one of a first detection circuit configured to detect from the 1-bit digital output data that the analog input voltage is lower than a first voltage value, and a second detection circuit configured to detect from the 1-bit digital output data that the analog input voltage is higher than a second voltage value, the second voltage value being higher than the first voltage value; a correction circuit configured to correct the reference voltage based on a detection result of the detection circuit and output the corrected reference voltage; Equipped with The ΔΣ converter is configured to perform ΔΣ conversion based on the output of the correction circuit.

2. the detection circuit includes at least the first detection circuit, 2. The AD conversion circuit according to claim 1, further comprising a non-volatile memory configured to store the first voltage value and the correction amount in the correction circuit in a non-volatile manner.

3. the detection circuit includes at least the second detection circuit, 2. The AD conversion circuit according to claim 1, further comprising a non-volatile memory configured to store the second voltage value and the correction amount in the correction circuit in a non-volatile manner.

4. the detection circuit includes at least the first detection circuit, 2. The AD conversion circuit according to claim 1, wherein the first detection circuit is configured to detect that the analog input voltage is lower than the first voltage value when the 1-bit digital output data is 0 an arbitrary number of times in succession.

5. the detection circuit includes at least the second detection circuit, 2. The AD conversion circuit according to claim 1, wherein the second detection circuit is configured to detect that the analog input voltage is higher than the second voltage value when the 1-bit digital output data is 1 an arbitrary number of times in succession.

6. 6. The AD conversion circuit according to claim 1, wherein the correction circuit is configured to adjust an amount of correction in accordance with an output of a temperature sensor.

7. the ΔΣ converter is driven by a power supply voltage; 6. The AD conversion circuit according to claim 1, wherein the correction circuit is configured to adjust a correction amount according to an output of a first monitor circuit configured to monitor the power supply voltage.

8. The ΔΣ converter operates based on a clock signal; The AD conversion circuit according to any one of claims 1 to 5, wherein the correction circuit is configured to adjust the amount of correction according to an output of a second monitor circuit configured to monitor the frequency of the clock signal.

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