Display panel

Abstract

To provide a display panel in which a poor residual image is improved.SOLUTION: A display panel can include: a drive element layer including a first pixel drive section including a first conductive pattern and a second pixel drive section including a second conductive pattern; a light emitting element that is disposed on the drive element layer and includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a connection electrode that is disposed on the drive element layer and is electrically connected to the first pixel drive section and the second electrode; and a metal layer disposed between the second conductive pattern and the connection electrode in a cross-section view when cutting in a direction vertical to the drive element layer.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a display panel, and more particularly to a display panel with improved image retention. [Background technology]

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation systems, game consoles, etc. include display panels for displaying images. The display panels include light emitting elements and circuits for driving the light emitting elements. The light emitting elements included in the display panel emit light in response to a voltage applied from the circuit to generate images. Research into the connection between the light emitting elements and the circuits has been ongoing in order to improve the reliability of the display panels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0165818 [Patent Document 2] Korean Patent No. 1348408 [Patent Document 3] US Patent Application Publication No. 2023 / 0010053 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display panel in which the afterimage defect is improved. [Means for solving the problem]

[0005] A display panel according to one embodiment of the present invention may include: a driving element layer including a first pixel driving unit including a first conductive pattern and a second pixel driving unit including a second conductive pattern; a light-emitting element arranged on the driving element layer and including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer; a connecting electrode arranged on the driving element layer and electrically connected to the first pixel driving unit and the second electrode; and a metal layer arranged between the second conductive pattern and the connecting electrode in a cross-sectional view.

[0006] The first conductive pattern may include a 1-1 pattern and a 2-1 pattern electrically connected to the connecting electrode.

[0007] The second conductive pattern may include a 1-2 pattern and a 2-2 pattern.

[0008] The 1-2 pattern and the 2-2 pattern may overlap the metal layer in a plan view.

[0009] The 1-2 pattern and the 2-2 pattern may overlap the connecting electrode in a plan view.

[0010] The first pattern and the second pattern may be source electrode patterns.

[0011] The 2-1 pattern and the 2-2 pattern may be drain electrode patterns.

[0012] The display panel may further include an intermediate connecting electrode electrically connecting the first pixel driving part and the connecting electrode.

[0013] The metal layer may include the same material as the intermediate connecting electrode and may be disposed on the same layer as the intermediate connecting electrode.

[0014] The metal layer may include the same material as the first electrode and may be connected to the first electrode.

[0015] The display panel may further include a pixel defining film disposed on the driving element layer and defining a light-emitting opening exposing at least a portion of the first electrode, and the connecting electrode may have a ring shape surrounding the light-emitting opening.

[0016] A lower surface of the second electrode may be in contact with an upper surface of the connecting electrode.

[0017] The display panel may further include a separator disposed on the connecting electrode, and the second electrode and the connecting electrode may be connected to an area adjacent to the separator.

[0018] The connecting electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap the separator.

[0019] A display panel according to one embodiment of the present invention may include a driving element layer including a pixel driving unit including a conductive pattern, a light-emitting element arranged on the driving element layer and including a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer, a connecting electrode arranged on the driving element layer and electrically connected to the pixel driving unit and the second electrode, and a metal layer overlapping the connecting electrode and the conductive pattern in a planar view.

[0020] The conductive pattern may include a first pattern electrically connected to the connecting electrode and a second pattern.

[0021] The first pattern may be a source electrode pattern, and the second pattern may be a drain electrode pattern.

[0022] The display panel may further include an intermediate connecting electrode electrically connecting the pixel driving part and the connecting electrode.

[0023] The metal layer may include the same material as the intermediate connecting electrode and may be disposed on the same layer as the intermediate connecting electrode.

[0024] The metal layer may include the same material as the first electrode and may be connected to the first electrode. Effect of the Invention

[0025] According to the above, by extending the intermediate connecting electrodes and / or the first electrodes of the display panel, coupling noise formed between the conductive patterns and the connecting electrodes may be reduced or eliminated. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2a] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 2b] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 2c] 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 3a] 1 is a plan view simply illustrating a display panel according to an embodiment of the present invention. [Figure 3b] 1 is a plan view simply illustrating a display panel according to an embodiment of the present invention. [Figure 4a] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 4b] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 4c] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 4d] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Diagram 5] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 6] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 7] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 8]1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 9] 2 is an enlarged cross-sectional view of a partial region of a display panel according to an embodiment of the present invention. [Figure 10] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on," "coupled," or "bonded" to another component, it means that it may be directly disposed, coupled, or bonded to the other component, or that a third component may be disposed therebetween.

[0028] The same reference numerals refer to the same components. Also, in the drawings, thicknesses, ratios, and dimensions of the components are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all combinations of one or more of the components defined by the associated components.

[0029] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. The terms are used only to distinguish one component from another. For example, the first component may be named the second component without departing from the scope of the present invention, and similarly, the second component may be named the first component. A singular surface includes a plural expression unless the context clearly indicates otherwise.

[0030] In addition, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0031] It should be understood that terms such as "comprise" or "have" specify the presence of any feature, number, step, operation, component, part, or combination thereof described hereinabove in the specification, but do not preclude the presence or additional possibility of one or more other features, number, steps, operations, components, parts, or combinations thereof.

[0032] The terms "part" and "unit" refer to a software component or hardware component that performs a specific function. Hardware components include, for example, a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). A software component refers to executable code and / or data used by executable code in an addressable storage medium. Thus, software components are, for example, object-oriented software components, class components, and operation components, and include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms defined in commonly used dictionaries should be interpreted as having the same meaning as they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless expressly defined herein.

[0034] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0035] FIG. 1 is a block diagram of a display device DD according to an embodiment of the present invention.

[0036] Referring to FIG. 1, the display device DD may include a display panel DP, a panel driver SDC, EDC, DDC, a power supply unit PWS, and a timing controller TC. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following embodiment, an organic light-emitting display panel will be taken as an example for detailed description. The panel driver SDC, EDC, DDC may include a scan driver SDC, an emission driver EDC, and a data driver DDC.

[0037] The display panel DP may include scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm (where m and n are integers greater than 1).

[0038] For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or ith pixel row) and jth vertical line (or jth pixel column) may be connected to the ith first scan line (or write scan line) GWLi, the ith second scan line (or compensation scan line) GCLi, the ith third scan line (or first initialization scan line) GILi, the ith fourth scan line (or second initialization scan line) GBLi, the ith fifth scan line (or reset scan line) GRLi, the jth data line DLj, and the ith emission line ESLi.

[0039] The pixel PXij may include a plurality of light emitting elements, a plurality of transistors, and a plurality of capacitors. The pixel PXij may be supplied with a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage (or reference voltage) VREF, a fourth power supply voltage (or first initialization voltage) VINT1, a fifth power supply voltage (or second initialization voltage) VINT2, and a sixth power supply voltage (or compensation voltage) VCOMP via a power supply unit PWS.

[0040] The first and second power supply voltages VDD and VSS are set to a voltage value such that a current flows through the light emitting device to emit light, For example, the first power supply voltage VDD may be set to a voltage higher than the second power supply voltage VSS.

[0041] The third power supply voltage VREF may be a voltage for initializing a gate of a driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to realize a predetermined gray scale by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0042] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor. However, the present invention is not limited thereto.

[0043] The fifth power supply voltage VINT2 may be a voltage for initializing the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto. The fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0044] The sixth power supply voltage VCOMP may provide a predetermined current to the drive transistor in compensating for the threshold voltage of the drive transistor.

[0045] 1, the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied from the power supply unit PWS, but the present invention is not limited thereto. For example, the first power supply voltage VDD and the second power supply voltage VSS are all supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied in accordance with the structure of the pixel PXij.

[0046] In the embodiment of the present invention, the signal lines connected to the pixels PXij may be variously set in accordance with the circuit structure of the pixels PXij.

[0047] The scan driver SDC receives a first control signal SCS from the timing controller TC, and can supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0048] The scan signal may be set to a voltage at which a transistor to which the scan signal is supplied can be turned on. For example, the scan signal supplied to a P-type transistor may be set to a logic low level, and the scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, the meaning of "a scan signal is supplied" may be interpreted as the scan signal being supplied to a logic level that turns on a transistor controlled by the scan signal.

[0049] 1, for convenience of explanation, the scan driver SDC is shown as a single configuration, but the present invention is not limited thereto. According to an embodiment, a plurality of scan drivers may be included for supplying scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively.

[0050] The light emitting driver EDC may provide light emitting signals to the light emitting lines ESL1 to ESLn based on the second control signal ECS, for example, the light emitting signals may be sequentially provided to the light emitting lines ESL1 to ESLn.

[0051] The transistors connected to the light emitting lines ESL1 to ESLn of the present invention may be N-type transistors. In this case, the light emitting signals provided to the light emitting lines ESL1 to ESLn may be set to a gate-off voltage. The transistors receiving the light emitting signals may be turned off when the light emitting signals are provided, and may be turned on otherwise.

[0052] The second control signal ECS includes a light emission start signal and a clock signal, and the light emission driver EDC may be implemented as a shift register that sequentially shifts the pulse-shaped light emission start signal using the clock signal to sequentially generate and output the pulse-shaped light emission signals.

[0053] The data driver DDC may receive a third control signal DCS and image data RGB from the timing controller TC. The data driver DDC may convert the digital image data RGB into an analog data signal (i.e., a data signal). The data driver DDC may provide a data signal to the data lines DL1 to DLm in response to the third control signal DCS.

[0054] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register for shifting the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch for latching image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) for converting the latched image data (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​for outputting the data signal to the data lines DL1 to DLm.

[0055] The power supply unit PWS may supply a first power supply voltage VDD, a second power supply voltage VSS, and a third power supply voltage VREF to the display panel DP for driving the pixels PXij, and may also supply at least one of a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP.

[0056] As an example, the power supply unit PWS may supply a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF, a fourth power supply voltage VINT1, a fifth power supply voltage VINT2, and a sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 2a), a second power supply line VSL (see FIG. 2a), a third power supply line VRL (or a reference voltage line, see FIG. 2a), a fourth power supply line VIL1 (or a first initialization voltage line, see FIG. 2a), a fifth power supply line VIL2 (or a second initialization voltage line, see FIG. 2a), and a sixth power supply line VCL (or a compensation voltage line, see FIG. 2a), which are not shown.

[0057] The power supply unit PWS may be implemented as a power management integrated circuit, but is not limited thereto.

[0058] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal, etc. The first control signal SCS may be supplied to the scan driver SDC, the second control signal ECS may be supplied to the emission driver EDC, the third control signal DCS may be supplied to the data driver DDC, and the fourth control signal PCS may be supplied to the power driver PWS. The timing controller TC may realign the input image data IRGB in response to an arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0059] Meanwhile, the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply PWS, and / or the timing controller TC may be directly formed on the display panel DP or may be provided in the form of a separate driver chip and connected to the display panel DP. At least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply PWS, and the timing controller TC may be provided on one driver chip. For example, the data driver DDC and the timing controller TC may be provided on one driver chip.

[0060] Although the display device DD according to an embodiment has been described with reference to FIG. 1, the display device of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Also, the connection relationship between one pixel and the signal lines may be changed. If any one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0061] 2a, 2b, and 2c are equivalent circuit diagrams of a pixel according to an embodiment of the present invention, which exemplarily illustrate equivalent circuit diagrams of pixels (PXij, PXij-1, PXij-2) connected to an i-th first scan line GWLi (hereinafter, first scan line) and a j-th data in DLj (hereinafter, data line), respectively.

[0062] As shown in Fig. 2a, the pixel PXij may include a light emitting element LD and a pixel driving circuit PDC. The light emitting element LD is connected to a first power line VDL and the pixel driving circuit PDC.

[0063] The pixel driving unit PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, VCL. The pixel driving unit PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8, a first capacitor C1, and a second capacitor C2. Hereinafter, the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 are all N-type transistors. However, the present invention is not limited thereto, and some of the first to eighth transistors T1 to T8 may be N-type transistors and the rest may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be P-type transistors, and is not limited to any one of the embodiments.

[0064] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL through the light emitting element LD to the second power line VSL in response to the voltage of the first node N1. In this case, the first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0065] In this specification, "electrically connected between a transistor and a signal line or between transistors" means "the source, drain, and gate of a transistor are integral with the signal line or are connected via a connecting electrode."

[0066] The second transistor T2 may include a gate coupled to the write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. The second transistor T2 may be turned on when the write scan signal GW is supplied to the write scan line GWLi to electrically connect the data line DLj to the first node N1.

[0067] The third transistor T3 may be coupled between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF via the reference voltage line VRL, and a second electrode of the third transistor T3 may be coupled to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR via an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0068] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 providing the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI through an i-th third scan line GILi (hereinafter, a first initialization scan line). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided to the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0069] The fifth transistor T5 may be connected between the compensation power line VCL and the second node N2. A first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 may be connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, a compensation scan line). When the compensation scan signal GC is supplied to the compensation scan line CGLi, the fifth transistor T5 may be turned on to provide the compensation voltage VCOMP to the second node N2, and the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0070] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. In particular, a gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, emission line). A first electrode of the sixth transistor T6 may be connected to a cathode of the light emitting element LD through a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to a first electrode of the first transistor T1 through a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0071] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 via the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS via the second power line VSL. A gate of the seventh transistor T7 may be electrically connected to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. When an emission signal EM is provided to the emission line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0072] Meanwhile, in the present embodiment, the sixth transistor T6 and the seventh transistor T7 are connected to the same emission line ESLi and turned on by the same emission signal EM, but this is merely an example, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driving unit PDC according to an embodiment of the present invention, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0073] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first power supply connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0074] Meanwhile, in this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be simultaneously turned on / off by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as a substantially single scan line. Thereby, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0075] In addition, according to the present invention, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 may be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor may be performed with one power supply voltage, and the design of the driving unit may be simplified. However, this is merely an example, and the present invention is not limited to any one embodiment.

[0076] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0077] The second capacitor C2 may be disposed between the third node N3 and the second power supply VSL. That is, one electrode of the second capacitor C2 may be connected to the second power supply line VSL that receives the second power supply voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacitance than the first capacitor C1. Thus, the second capacitor C2 may minimize a voltage change at the third node N3 in response to a voltage change at the first node N1.

[0078] In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode facing the anode. In this embodiment, the light emitting element LD may be connected to the pixel driving part PDC through a cathode. That is, in the pixel PXij according to the present invention, the connection node where the light emitting element LD and the pixel driving part PDC are connected may be the fourth node N4, and the fourth node N4 may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Thus, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0079] In detail, the anode of the light emitting element LD may be connected to the first power line VDL to receive the first power voltage VDD, which is a static voltage, and the cathode may be connected to the first transistor T1 via the sixth transistor T6. That is, in this embodiment in which the first to eighth transistors T1 to T8 are N-type transistors, the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if the light emitting element LD is deteriorated, the influence on the transistors constituting the pixel driving unit PDC, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. That is, the amount of change in the driving current due to deterioration of the light emitting element LD may be reduced, and the afterimage defect of the display panel due to the increase in the usage time may be reduced, thereby improving the lifespan.

[0080] Alternatively, as shown in Fig. 2b, the pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1, T2 and one capacitor C1. The pixel driver PDC-1 is connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in Fig. 2b may correspond to the pixel driver PDC shown in Fig. 2a with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0081] Each of the first and second transistors T1 and T2 may be an N-type or P-type transistor. In this embodiment, the first and second transistors T1 and T2 are exemplarily described as N-type transistors.

[0082] The first transistor T1 may include a gate coupled to a first node N1, a first electrode coupled to a second node N2, and a second electrode coupled to a third node N3. The second node N2 may be a node coupled to a first power line VDL, and the third node N3 may be a node coupled to a second power line VSL. The first transistor T1 may be coupled to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0083] The second transistor T2 may include a gate receiving a write scan signal GW via a write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted via the write scan line GWLi.

[0084] The first capacitor C1 may include an electrode coupled to the first node N1 and an electrode coupled to the third node N3, and may store a data signal DATA transmitted to the first node N1.

[0085] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving part PDC-1 via the second node N2. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving part PDC-1.

[0086] In this embodiment, the first and second transistors T1 and T2 are N-type transistors, and the second node N2 to which the cathode of the light emitting element LD and the pixel driving part PDC-1 are connected may correspond to the drain of the first transistor T1. That is, the change in the gate-source voltage Vgs of the first transistor T1 due to the light emitting element LD may be prevented. As a result, the amount of change in the driving current due to the deterioration of the light emitting element LD may be reduced, and the image retention defect of the display panel due to the increase in the usage time may be reduced, thereby improving the life span.

[0087] Alternatively, as shown in FIG. 2c, pixel PXij-2 may include a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a, T6a, and two capacitors C1, C2.

[0088] The pixel driving unit PDC-2 may be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first light emitting line ESL1i (hereinafter, the first light emitting line), the i-th second light emitting line ESL2i (hereinafter, the second light emitting line), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL, and the initialization voltage line VIL.

[0089] The pixel driver PDC-2 shown in Fig. 2c has a structure similar to that of the pixel driver PDC shown in Fig. 2a, except that the fourth transistor T4 and the fifth transistor T5 are omitted. Since the area of ​​the pixel driver PDC-2 shown in Fig. 2c is smaller than the area of ​​the pixel driver PDC-1 shown in Fig. 2a, it may be easier to implement a high resolution.

[0090] Each of the first and sixth transistors T1, T2, T3, T4a, T5a, and T6a may be an N-type or P-type transistor. In this embodiment, a case in which each of the first and sixth transistors T1, T2, T3, T4a, T5a, and T6a is an N-type transistor will be described as an example.

[0091] The first transistor T1 may include a gate coupled to a first node N1, a first electrode coupled to a second node N2, and a second electrode coupled to a third node N3. The second node N2 may be a node coupled to a first power line VDL, and the third node N3 may be a node coupled to a second power line VSL. The first transistor T1 may be coupled to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0092] The second transistor T2 may include a gate receiving a write scan signal GW via a write scan line GWLi, a first electrode coupled to the data line DLj, and a second electrode coupled to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted via the write scan line GWLi.

[0093] The third transistor T3 may be coupled between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive a reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be coupled to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 may be turned on to provide the reference voltage VREF to the first node N1.

[0094] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. In particular, the gate of the fourth transistor T4a may receive a first light emitting signal EM1 through a first light emitting line ESLi. A first electrode of the fourth transistor T4a may be connected to a cathode of the light emitting element LD through a fourth node N4, and a second electrode of the fourth transistor T4a may be connected to a first electrode of the first transistor T1 through a second node N2. The fourth transistor T4a may be referred to as a first light emitting control transistor. When the first light emitting signal EM1 is provided to the first light emitting line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0095] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 via the third node N3, and a second electrode of the fifth transistor T5a may receive the second power voltage VSS via the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a may be referred to as a second light-emitting control transistor. When a second light-emitting signal EM2 is provided to the second light-emitting line ESL2i, the fifth transistor T5a is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0096] Meanwhile, in the present embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the first and second light-emitting lines ESL1i and ESL2i that are distinct from each other and may be turned on via the first and second light-emitting signals EM1 and EM2 that are distinct from each other. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently from each other. However, this is an example and is not limited thereto. For example, in the present embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to the same light-emitting line and controlled by the same light-emitting signal. Also, in the pixel driving unit PDC-2 according to an embodiment of the present invention, either one of the fourth transistor T4a and the fifth transistor T5a may be omitted.

[0097] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0098] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a difference voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0099] The second capacitor C2 may be disposed between the third node N3 and the second power supply VSL. That is, one electrode of the second capacitor C2 may be coupled to the first power supply line VSL supplied with the second power supply VSS, and the other electrode of the second capacitor C2 may be coupled to the third node N3. The second capacitor C2 may store a charge corresponding to a voltage difference between the second power supply voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor.

[0100] The light emitting element LD may include an anode and a cathode. In this embodiment, the anode of the light emitting element LD is connected to the first power line VDL, and the cathode is connected to the pixel driving part PDC-2 via a fourth node N4. In this embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 via a fourth transistor T4a. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving part PDC-2.

[0101] In this embodiment, the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, so that the potential of the third node N3 corresponding to the source of the first transistor T1, which is a driving transistor, may not be directly affected by the characteristics of the light emitting device LD. Therefore, even if the light emitting device LD is deteriorated, the influence on the transistors constituting the pixel driving unit PDC-2, particularly the gate-source voltage Vgs of the driving transistor, may be reduced. In other words, the amount of change in driving current due to deterioration of the light emitting device LD may be reduced, and image retention defects of the display panel due to the increase in usage time may be reduced, thereby improving the life span.

[0102] Meanwhile, Figures 2a, 2b, and 2c show circuits for pixel driving units PDC, PDC-1, and PDC-2 according to an embodiment of the present invention, and the display panel according to an embodiment of the present invention can be designed in various ways in terms of the number and arrangement of transistors and the number and arrangement of capacitors as long as the circuit is connected to the cathode of the light emitting element LD, and is not limited to any one of the embodiments.

[0103] 3A and 3B are plan views each showing a display panel according to an embodiment of the present invention, with some components omitted. Hereinafter, a description will be given with reference to FIGS. 3A and 3B.

[0104] 3a, a display panel DP according to an embodiment is divided into a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a plurality of light emitting units EP.

[0105] The light-emitting portions EP may be areas that are respectively emitted by the pixels PXij (see FIG. 1). In more detail, each light-emitting portion EP may correspond to a light-emitting aperture portion OP-PDL (see FIG. 5) described later.

[0106] The peripheral area NDA may be disposed adjacent to the display area DA. In the present embodiment, the peripheral area NDA is illustrated as surrounding the edge of the display area DA. However, this is merely an example, and the peripheral area NDA may be disposed on one side of the display area DA or may be omitted, and is not limited to any one embodiment.

[0107] In this embodiment, the scan driver SDC and the data driver DDC may be implemented in a display panel DP. In one embodiment, the scan driver SDC may be disposed in a display area DA, and the data driver DDC may be disposed in a peripheral area NDA. The scan driver SDC may overlap at least some of the light emitting units EP disposed in the display area DA in a plan view. By disposing the scan driver SDC in the display area DA, the area of ​​the peripheral area NDA may be reduced compared to a conventional display panel in which a scan driver is disposed in the peripheral area, and a display device with a thin bezel may be easily realized.

[0108] Meanwhile, unlike the illustration of Fig. 3a, the scan driver SDC may be provided in two parts separated from each other. The two scan drivers SDC may be disposed spaced apart on the left and right sides of the center of the display area DA. Alternatively, the scan driver SDC may be provided in a greater number than two, and the present invention is not limited to any one embodiment.

[0109] 3A shows an example of a display panel, and the data driver DDC may be disposed in the display area DA. In this case, a part of the light emitting unit EP disposed in the display area DA may overlap with the data driver DDC in a plan view.

[0110] In one embodiment, the data driver DDC may be provided in the form of a separate driver chip independent of the display panel DP and connected to the display panel DP, but this is merely an example, and the data driver DDC may be formed in the same process as the scan driver SDC to configure the display panel DP, and is not limited to any one embodiment.

[0111] As shown in Fig. 3b, the display panel DP may have a length in a first direction DR1 that is longer than a length in a second direction DR2. A plurality of pixels PX11 to PXnm are exemplarily illustrated as being arranged in n rows and m columns in the display area DA. In this embodiment, the display panel DP may include a plurality of pixel driving parts SDC1 and SDC2. The scan driving parts SDC1 and SDC2 are exemplarily illustrated as including a first scan driving part SDC1 and a second scan driving part SDC2 that are spaced apart from each other in the first direction.

[0112] The first scan driver SDC1 may be connected to some of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other parts of the scan lines GL1 to GLn. For example, the first scan driver SDC1 may be connected to odd-numbered scan lines of the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines of the scan lines GL1 to GLn.

[0113] For ease of explanation, pads PD of the data lines DL1 to DLm are shown in Fig. 3b. The pads PD may be defined at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to a data driver DDC (see Fig. 3a) via the pads PD.

[0114] According to the present invention, the pads PD may be divided and arranged at positions spaced apart from each other across the display area DA in the peripheral area NDA. For example, some of the pads DP may be arranged on the upper side, i.e., adjacent to the first scan line GL1 of the scan lines GL1 to GLn, and other parts of the pads DP may be arranged on the lower side, i.e., adjacent to the last scan line GLn of the scan lines GL1 to GLn. In this embodiment, the pads PD connected to odd-numbered data lines of the data lines DL1 to DLm may be arranged on the upper side, and the pads PD connected to even-numbered data lines of the data lines DL1 to DLm may be arranged on the lower side.

[0115] Although not shown, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged on the upper side and / or a plurality of lower data drivers connected to the pads PD arranged on the lower side. However, this is an exemplary description, and the display panel DP may include one upper data driver connected to the pads PD arranged on the upper side and / or one lower data driver connected to the pads PD arranged on the lower side. The pads PD according to an embodiment of the present invention may be arranged on only one side of the display panel DP and connected to a single data driver, and is not limited to any one embodiment.

[0116] Furthermore, as described in FIG. 3a, the display panel DP in FIG. 3b may also have a scan driver and / or a data driver arranged in the display area DA, whereby some of the light emitting units arranged in the display area DA may overlap with the scan driver and / or the data driver in a planar view.

[0117] 4a to 4d are enlarged plan views of a partial region of a display panel according to an embodiment of the present invention.

[0118] 4a exemplarily shows two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. Referring to FIG 4a, the first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22.

[0119] Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a light-emitting opening OP-PDL (see FIG. 5) described later. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area where light is emitted by the light-emitting elements described above. Each of the light-emitting portions EP1, EP2, and EP3 may correspond to a unit that configures an image displayed on the display panel DP (see FIG. 1). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL described later, in particular, an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0120] The light emitting units EP1, EP2, and EP3 may include a first light emitting unit EP1, a second light emitting unit EP2, and a third light emitting unit EP3. The first light emitting unit EP1, the second light emitting unit EP2, and the third light emitting unit EP3 may emit light of different colors. For example, the first light emitting unit EP1 may emit red light, the second light emitting unit EP2 may emit green light, and the third light emitting unit EP3 may emit blue light, but the color combination is not limited to this. In addition, at least two of the first to third light emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first to third light emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0121] The third light emitting part EP3 displaying light emitted by a third light emitting element among the first to third light emitting parts EP1, EP2, and EP3 may include two sub-light emitting parts EP31, EP32 spaced apart from each other in the second direction DR2. However, this is an exemplary illustration, and the third light emitting part EP3 may be provided in a single pattern having an integral shape like the first and second light emitting parts EP1, EP2, or any one of the first and second light emitting parts EP1, EP2 may have a spaced apart sub-light emitting part, and is not limited to any one embodiment.

[0122] The first row Rk light-emitting section may include first to third light-emitting sections EP1, EP2, EP3 that constitute the first row, first column light-emitting unit UT11, and first to third light-emitting sections EP1, EP2, EP3 that constitute the first row, second column light-emitting unit UT12, and the second row Rk+1 light-emitting section may include first to third light-emitting sections EP1, EP2, EP3a that constitute the second row, first column light-emitting unit UT21, and first to third light-emitting sections EP1, EP2, EP3 that constitute the second row, second column light-emitting unit UT22.

[0123] In one embodiment of the present invention, the light emitting portion constituting the first row, first column light emitting unit UT11 and the light emitting portion constituting the second row, second column light emitting unit UT22 may have substantially the same shape. Also, the light emitting portion constituting the first row, second column light emitting unit UT12 and the light emitting portion constituting the second row, first column light emitting unit UT21 may have substantially the same shape. The shape of the light emitting portion constituting the first row, first column light emitting unit UT11 may be different from the shape of the light emitting portion constituting the first row, second column light emitting unit UT12. For example, a part of the first row Rk light emitting portion and a part of the second row RK+1 light emitting portion may have symmetrical shapes.

[0124] In an embodiment of the present invention, the third light emitting part EP3a of the second row, first column light emitting unit UT21 and the third light emitting part EP3 of the first row, first column light emitting unit UT11 may have a shape and arrangement that is line symmetrical with respect to an axis parallel to the first direction DR1, and the third light emitting part EP3 of the second row, second column light emitting unit UT22 and the third light emitting part EP3a of the first row, second column light emitting unit UT12 may have a shape and arrangement that is line symmetrical with respect to an axis parallel to the first direction DR1, but this is merely an example and is not limited thereto.

[0125] Fig. 4b shows light emitting portions arranged in a row. For ease of explanation, Fig. 4b shows a plurality of second electrodes EL2_1, EL2_2, EL2_3, a plurality of circuit driving units PDC1, PDC2, PDC3, first to third connecting electrodes CNE1, CNE2, CNE3, and a separator SPR. Fig. 4c shows the separator SPR, a plurality of light emitting portions EP1, EP2, EP3, and a plurality of connecting electrodes CNE1, CNE2, CNE3 arranged in an area partitioned by the separator SPR, which are included in the configuration of the display panel.

[0126] 4b and 4c, the second electrodes EL2_1, EL2_2, and EL2_3 may be electrically disconnected by being separated from each other by a separator SPR. In this embodiment, one light emitting unit UT11 may include three light emitting parts EP1, EP2, and EP3. Accordingly, the light emitting unit UT11 may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter, first to third cathodes), three pixel driving parts PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light emitting parts included in the light emitting unit UT11 may be variously designed, and is not limited to any one embodiment.

[0127] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the first to third light emitting elements LD1, LD2, and LD3 including the first to third light emitting units EP1, EP2, and EP3, respectively. In this specification, "connected" includes not only a case where they are connected by direct physical contact, but also a case where they are electrically connected.

[0128] Also, as shown in FIG. 4b, each area in which the first to third pixel driving units PDC1, PDC2, and PDC3 are defined on a plane may correspond to a unit in which transistors and capacitor elements constituting a circuit PDC (see FIG. 2a) for driving a light emitting element of a pixel are repeatedly arranged.

[0129] The first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along a first direction DR1. Meanwhile, the arrangement positions of the first, second, and third pixel driving units PDC1, PDC2, and PDC3 may be designed independently of the positions and shapes of the first, second, and third light emitting units EP1, EP2, and EP3.

[0130] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged in a region defined by the separator SPR, i.e., at a position different from the position where the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged, or may be designed to have a shape and area different from the shape of the first to third cathodes EL2_1, EL2_2, and EL2_3. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged to overlap the positions where the first to third light emitting units EP1, EP2, and EP3 are present, respectively, and may be designed to have a shape having an area similar to that of the region defined by the separator SPR, for example, the first to third cathodes EL2_1, EL2_2, and EL2_3.

[0131] In this embodiment, the first to third pixel driving units PDC1, PDC2, and PDC3 are each shown in a rectangular shape, the first to third light emitting units EP1, EP2, and EP3 are each arranged in a different shape with a smaller area than the rectangular shape, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3, but are shown in an irregular shape.

[0132] 4b, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitting units. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third cathode EL2_3. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. However, this is merely an example, and the positions of the first to third pixel driver PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independent of the first to third light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0133] The light emitting unit UT11 may include first to third connecting electrodes CNE1, CNE2, and CNE3. The first connecting electrode CNE1 may electrically connect the first light emitting element LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 is defined) to the first pixel driving part PDC1, the second connecting electrode CNE2 may electrically connect the second light emitting element LD2 forming the second light emitting part EP2 to the second pixel driving part PDC2, and the third connecting electrode CNE3 may electrically connect the third light emitting element LD3 forming the third light emitting part EP3 to the third pixel driving part PDC3. Each of the first to third light emitting elements LD1, LD2, and LD3 may include a first electrode EL1, an intermediate layer IML disposed on the first electrode EL1, and a second electrode EL2 disposed on the intermediate layer.

[0134] In detail, the first to third connecting electrodes CNE1, CNE2, CNE3 may electrically connect the first to third cathodes EL2_1, EL2_2, EL2_3 to the first to third pixel driving parts PDC1, PDC2, PDC3 in a one-to-one correspondence, respectively. For example, the first connecting electrode CNE1 may be electrically connected to the first pixel connecting part PDC1 and the first cathode EL2_1, the second connecting electrode CNE2 may be electrically connected to the second pixel connecting part PDC2 and the second cathode EL2_2, and the third connecting electrode CNE3 may be electrically connected to the third pixel connecting part PDC3 and the third cathode EL2_3.

[0135] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel definition film PDL (see FIG. 5) described later. The first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting portions EP1, EP2, and EP3. In the embodiment of the present invention, the first to third connecting electrodes CNE1, CNE2, and CNE3 each have a ring shape of a closed line, but the present invention is not limited to this. For example, at least some of the first to third connecting electrodes CNE1, CNE2, and CNE3 may have an open ring shape with a part interrupted.

[0136] Since the first to third connecting electrodes CNE1, CNE2, and CNE3 have an annular shape, the degree of freedom of positions at which the first to third connecting electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving parts PDC1, PDC2, and PDC3 may be improved. For example, the first connecting electrode CNE1 may be connected to the first pixel driving part PDC1 via the first connecting part CE1, the second connecting electrode CNE2 may be connected to the second pixel driving part PDC2 via the second connecting part CE2, and the third connecting electrode CNE3 may be connected to the third pixel driving part PDC3 via a connecting wire CN3. That is, a connecting wire additionally connected to the first and second connecting electrodes CNE1 and CNE2 may be omitted.

[0137] One connection wire CN3 may electrically connect the third pixel driving part PDC3 and the third light emitting element LD3 constituting the third light emitting part EP3. In detail, the connection wire CN3 may correspond to a node (see the fourth node N4 in FIG. 2a, the second node N2 in FIG. 2b, or the fourth node N4 in FIG. 2c) at which the light emitting element LD (see FIG. 2a) is connected to the pixel driving part (PDC in FIG. 2a, PDC-1 in FIG. 2b, or PDC-2 in FIG. 2c).

[0138] The connecting wire CN3 may include a connection part CE3 and a driving connection part CD3. The third connection part CE3 may be provided on one side of the connecting wire CN3, and the driving connection part CD3 may be provided on the other side of the connecting wire CN3.

[0139] The driving connection part CD3 may be a part of the connecting wire CN3 that is connected to the pixel driving part PDC3. In this embodiment, the driving connection part CD3 may be connected to one electrode of a transistor constituting the pixel driving part PDC3. In particular, the driving connection part CD3 may be connected to the drain of the sixth transistor T6 shown in FIG. 2a, the drain of the first transistor T1 shown in FIG. 2b, or the drain of the fourth transistor T4a shown in FIG. 2c. Thus, the position of the driving connection part CD3 may correspond to the position of a transistor physically connected to the connecting wire CN3 in the pixel driving part. The third connection part CE3 may be a part of the connecting wire CN3 that is connected to the third light emitting element LD3. In this embodiment, the third connection part CE3 may be connected to the third connecting electrode CNE3.

[0140] The first connecting electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light-emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connecting electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light-emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connecting electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light-emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0141] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be arranged to be spaced apart from each other. For example, gaps GP1, GP2, and GP3 between adjacent connecting electrodes among the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. For example, first edges EG11, EG21, and EG31 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not be covered by the separator SPR, and second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with the separator SPR. Or, the second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be covered by the separator SPR.

[0142] In an embodiment of the present invention, the first to third connection parts CE1, CE2, and CE3 may be disposed at positions that do not overlap the first to third light emitting parts EP1, EP2, and EP3 in a plan view. For example, a light emitting opening OP-PDL (see FIG. 5) and a through hole OP-P (see FIG. 5) separated from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL.

[0143] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection parts CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light emitting opening part OP-PDL may include a first light emitting opening part OP-PDL1, a second light emitting opening part OP-PDL2, and a third light emitting opening part OP-PLD3. The first to third light emitting parts EP1, EP2, and EP3 may be defined corresponding to the first to third light emitting opening parts OP-PDL1, OP-PDL2, and OP-PDL3, respectively. Therefore, the first to third connection parts CE1, CE2, and CE3 may be arranged at positions spaced apart from the first to third light emitting parts EP1, EP2, and EP3.

[0144] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on the pixel definition film PDL (see FIG. 5). In a plan view, the first connecting electrode CNE1 may surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 may surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 may surround the third light-emitting opening OP-PDL3.

[0145] According to an embodiment of the present invention, the driving connection part CD3, which is a position where the connecting wire CN3 is connected to the transistor TR (see FIG. 5) of the third pixel driving part PDC3, may be defined at a position that does not overlap with the third connection part CE3 in a plan view, and may be disposed at a position that overlaps with the third light emitting part EP3. For example, the connecting wire CN3 may correspond to the connecting wire CN-ad shown in FIG. 10, the driving connection part CD3 may correspond to a portion that contacts the intermediate connecting electrode CN shown in FIG. 10, and the third connection part CE3 may correspond to a portion that contacts the connecting electrode CNEa shown in FIG. 10. By connecting the third cathode EL2_3 and the pixel driving part PDC3 through the connecting wire CN3, restrictions due to the position and shape of the third light emitting part EP3 in designing the pixel driving part PDC3 may be reduced, and the degree of freedom in designing may be improved.

[0146] The first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to the first to third connecting electrodes CE1, CE2, and CE3. For example, the lower surfaces of the first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected (or in contact) with the upper surfaces of the first to third connecting electrodes CE1, CE2, and CE3, respectively. Therefore, the contact reliability (or connection stability) between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CE1, CE2, and CE3 may be further improved.

[0147] Also, the connection region where the first to third cathodes EL2_1, EL2_2, EL2_3 and the first to third connecting electrodes CE1, CE2, CE3 are connected may surround at least a part of each of the first to third light emitting openings OP-PDL1, OP-PDL2, OP-PDL3. The first to third cathodes EL2_1, EL2_2, EL2_R and the first to third connecting electrodes CE1, CE2, CE3 may be connected in a region adjacent to the separator SPR, and each of the connection regions may be defined adjacent to the separator SPR. That is, the first to third cathodes EL2_1, EL2_2, EL2_R and the first to third connecting electrodes CE1, CE2, CE3 may not be connected at a specific point, but may be connected over a relatively wide region, for example, a region similar in shape to each of the first to third connecting electrodes CE1, CE2, CE3. That is, the area of ​​the connection region is increased, and the connection may be stable.

[0148] FIG. 4d shows the separator SPR, the light emitting portions EP1, EP2, EP3, and the first electrode EL1.

[0149] 4d, a first electrode EL1 (hereinafter, anode) of the light emitting element LD (see FIG. 5) according to an embodiment of the present invention may be provided in common to the first to third light emitting parts EP1, EP2, and EP3. That is, the anode EL1 may be formed of a single layer over the entire display area DA, whereby the anode EL1 layer may be disposed overlapping the separator SPR. Alternatively, the anode EL1 of each light emitting element LD may be formed of independent conductive patterns spaced apart from each other and electrically connected to each other via another conductive layer, whereby the anode EL1 pattern may be disposed without overlapping the separator SPR.

[0150] As described above, the first power supply voltage VDD (see FIG. 2a) is applied to the anode EL1, and a common voltage may be provided to all the light emitting units. The anode EL1 may be connected to the first power supply line VDL (see FIG. 2a) that provides the first power supply voltage VDD in the peripheral area NDA, or may be connected to the first power supply line VDL (see FIG. 2a) in the display area DA, and is not limited to any one of the embodiments.

[0151] Meanwhile, a plurality of openings may be defined in the anode EL1 according to the present invention, and the openings may penetrate the anode EL1 layer. The openings in the anode EL1 layer may be disposed at a position that does not overlap with the light emitting portion EP (see FIG. 3a), and may be defined at a position that overlaps with the separator SPR. The openings may facilitate the discharge of gas generated from an organic layer disposed below the anode EL1, for example, a sixth insulating layer 60 (see FIG. 5) described below. As a result, gas generated from an organic layer disposed below the light emitting element during the manufacturing process of the display panel may be sufficiently discharged, and the gas discharged from the organic layer after manufacturing may be reduced, thereby reducing the rate at which the light emitting element deteriorates.

[0152] Fig. 5 is a cross-sectional view of a display panel DP according to an embodiment of the present invention, showing a portion corresponding to line II' in Fig. 4a.

[0153] 5, the display panel DP according to an embodiment may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, a sealing layer ECL, and a sensing layer ISL. However, this is only an example, and in an embodiment, the display panel DP may not include the sensing layer ISL.

[0154] The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, 60 to constitute pixel driving units PDC1, PDC2. For ease of explanation, FIG. 5 exemplarily illustrates a cross section of one of the regions in which one light emitting unit is disposed.

[0155] The base layer BS may be a member that provides a base surface on which the pixel driving units PDC1 and PDC2 are disposed. The base layer BS may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, the embodiment of the present invention is not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0156] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer and a silicon oxide (SiO x The silicon oxide layer and the amorphous silicon layer may include a base barrier layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymeric resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0157] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in this specification, a "XX-based" resin means that it contains a functional group of "XX".

[0158] The insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may be formed by coating, deposition, etc. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by multiple lithography processes to form holes in the insulating layer, or to form semiconductor patterns, conductive patterns, signal lines, etc.

[0159] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, 60 sequentially stacked on the base layer BS, and pixel driving units PDC1 and PDC2. Figure 5 exemplarily illustrates the first pixel driving unit PDC1 and the second pixel driving unit PDC2 illustrated in Figure 4b, with one transistor TR1 and two capacitors C1 and C2 illustrated in the first pixel driving unit PDC1, and one transistor TR2 illustrated in the second pixel driving unit PDC2. The transistor TR2 may be one of a plurality of transistors included in the second pixel driving unit PDC2.

[0160] The transistor TR1 of the first pixel driver PDC1 corresponds to a transistor connected to the light emitting element LD via the intermediate connecting electrode CN and the connecting electrode CNE, that is, a connecting transistor connected to a node corresponding to the cathode of the light emitting element LD (the fourth node N4 in FIG. 2a, the second node N2 in FIG. 2b, or the fourth node N4 in FIG. 2c), and more specifically, may correspond to the sixth transistor T6 in FIG. 2a, the first transistor T1 in FIG. 2b, or the fourth transistor T4a in FIG. 2c. Hereinafter, the transistor TR1 of the first pixel driver PDC1 may be referred to as a connecting transistor. The light emitting element LD electrically connected to the first pixel driver PDC1 may be a first light emitting element LD1 (see FIG. 4c).

[0161] The second pixel driving part PDC2 may be electrically connected to a second light emitting element LD2 (see FIG. 4c) adjacent to the first light emitting element LD1. For example, the second pixel driving part PDC2 may be electrically connected to the second light emitting element LD2 via an intermediate connecting electrode and a second connecting electrode CNE2 (see FIG. 4).

[0162] Meanwhile, although not shown, other transistors constituting the pixel driving unit PDC1 or PDC2 may have the same structure as the transistor TR1 or TR2 shown in Fig. 5. However, this is merely an exemplary explanation, and other transistors constituting the pixel driving unit PDC1 or PDC2 may have a different structure from the transistor TR1 or TR2 shown in Fig. 5, and the present invention is not limited to any one embodiment.

[0163] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single layer or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 is illustrated as a single layer silicon oxide layer. Meanwhile, an insulating layer, which will be described later, may be an inorganic layer and / or an organic layer, and may have a single layer or a multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0164] Meanwhile, the first insulating layer 10 may cover the lower conductive layers BCL1, BCL2. That is, the display panel DP may further include lower conductive layers BCL1, BCL2 arranged to overlap the transistor TR1 or TR2. The lower conductive layers BCL1, BCL2 may block the electric potential caused by the polarization phenomenon of the base layer BS from affecting the transistor TR1 or TR2. In addition, the lower conductive layers BCL1, BCL2 may block light incident on the transistor TR1 or TR2 from below. At least one of an inorganic barrier layer and a buffer layer may be further arranged between the lower conductive layers BCL1, BCL2 and the base layer BS.

[0165] The lower conductive layers BCL1 and BCL2 may include a reflective metal. For example, the lower conductive layers BCL1 and BCL2 may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0166] The lower conductive layers BCL1, BCL2 may include a first lower conductive layer BCL1 and a second lower conductive layer BCL2. In this embodiment, the first lower conductive layer BCL1 may be connected to the source of the connection transistor T1 through a first source electrode pattern S1 or a 1-1 pattern. In this case, the first lower conductive layer BCL1 may be synchronized with the source of the connection transistor TR1. The second lower conductive layer BCL2 may be connected to the source of the transistor TR2 through a second source electrode pattern S2 or a 1-2 pattern. In this case, the second lower conductive layer BCL2 may be synchronized with the source of the transistor TR2.

[0167] However, this is merely an example, and the lower conductive layer BCL1 or BCL2 may be connected to the gate of the transistor TR1 or TR2 and synchronized with the gate. Alternatively, the lower conductive layer BCL1 or BCL2 may be connected to another electrode and a static voltage or a pulse signal may be applied to the lower conductive layer BCL1 or BCL2 independently. Alternatively, the lower conductive layer BCL1 or BCL2 may be provided in an isolated form from other conductive patterns. The lower conductive layer BCL1 or BCL2 according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0168] A transistor TR1 of the first pixel driving unit PDC1 and a transistor TR2 of the second pixel driving unit PDC2 may be disposed on the first insulating layer 10. The transistor TR1 of the first pixel driving unit PDC1 may include a first semiconductor pattern SP1 and a first gate electrode GE1. The transistor TR2 of the second pixel driving unit PDC2 may include a second semiconductor pattern SP2 and a second gate electrode GE2. The first and second semiconductor patterns SP1 and SP2 may be disposed on the first insulating layer 10. The first and second semiconductor patterns SP1 and SP2 may include an oxide semiconductor. For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 However, the first and second semiconductor patterns SP1 and SP2 may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0169] Each of the first and second semiconductor patterns SP1 and SP2 may include a source region, a drain region, and a channel region that are differentiated according to the degree of conductivity. For example, the first semiconductor pattern SP1 may include a first source region SR1, a first drain region DR_1, and a first channel region CR1. The first source region SR1 and the first drain region DR_1 may be separated with the first channel region CR1 therebetween. The first channel region CR1 may be a portion that overlaps with the first gate electrode GE1 in a plan view. The second semiconductor pattern SP2 may include a second source region SR2, a second drain region (not shown), and a second channel region CR2. The second source region SR2 and the second drain region may be separated with the second channel region CR2 therebetween. The second channel region CR2 may be a portion that overlaps with the second gate electrode GE2 in a plan view. The I-I' cutting line does not pass through the second drain region of the second semiconductor pattern SP2, and the second drain region is not shown in FIG. 5.

[0170] If the semiconductor pattern SP1 or SP2 is an oxide semiconductor, the source region SR1 or SR2 and the drain region DR_1 may be reduced regions, so that the source region SR1 or SR2 and the drain region DR_1 have a relatively high reduced metal content compared to the channel region CR1 or CR2, or if the semiconductor pattern SP1 or SP2 is polycrystalline silicon, the source region SR1 or SR2 and the drain region DR_1 may be highly doped regions.

[0171] The source region SR1 or SR2 and the drain region DR_1 may have a relatively high conductivity compared to the channel region CR1 or CR2. The source region SR1 or SR2 may correspond to a source electrode of the transistor TR1 or TR2, and the drain region DR_1 may correspond to a drain electrode of the transistor TR1 or TR2. As shown in FIG. 5, a separate source electrode pattern S1 or S2 and a drain electrode pattern D1 or D2 connected to the source region SR1 or SR2 and the drain region DR_1, respectively, may be further provided. In particular, each of the separate source electrode pattern S1 or S2 and the drain electrode pattern D1 or D2 may be integrally formed with one of the lines constituting the pixel driving unit (see PDC in FIG. 2a, PDC-1 in FIG. 2b, or PDC-2 in FIG. 2c), and is not limited to any one embodiment.

[0172] The second insulating layer 20 may overlap a plurality of pixels in common and cover the semiconductor pattern SP1 or SP2. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 may be a single silicon oxide layer.

[0173] The gate electrodes GE1 and GE2 may be disposed on the second insulating layer 20. The first gate electrode GE1 may correspond to the gate of the transistor TR1 of the first pixel driving part PDC1, and the second gate electrode GE2 may correspond to the gate of the transistor TR2 of the second pixel driving part PDC2. The gate electrodes GE1 and GE2 may be disposed above the semiconductor patterns SP1 and SP2, respectively. However, this is merely an example, and the gate electrodes GE1 and GE2 may be disposed below the semiconductor patterns SP1 and SP2, respectively, and are not limited to any one embodiment.

[0174] The gate electrodes GE1 and GE2 may include, but are not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0175] A third insulating layer 30 may be disposed on the gate electrodes GE1 and GE2. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0176] Among the conductive patterns S1, S2, D1, D2, CPE, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart with a first insulating layer 10 and a second insulating layer 20 interposed therebetween.

[0177] In an embodiment of the present invention, the first capacitor electrode CPE1 and the first lower conductive layer BCL1 may have an integral shape. Also, the second capacitor electrode CPE2 and the first gate electrode GE1 may have an integral shape connected to each other, and the capacitor electrode CPE and the second gate electrode GE2 may have an integral shape connected to each other. However, this is only an example and is not particularly limited to this. For example, the first capacitor electrode CPE1 and the first lower conductive layer BCL1 may be disposed on the same layer and separated from each other. The first capacitor electrode CPE2 and the first gate electrode GE1 may be disposed on the same layer and separated from each other. The capacitor electrode CPE and the second gate electrode GE2 may be disposed on the same layer and separated from each other.

[0178] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be separated from the second capacitor electrode CPE2 with the third insulating layer 30 therebetween and overlap with each other in a plan view. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0179] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single layer or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0180] A first source electrode pattern S1 and a first drain electrode pattern D1 connected to the first semiconductor pattern SP1, and a second source electrode pattern S2 and a second drain electrode pattern D2 connected to the second semiconductor pattern SP2 may be disposed on the fourth insulating layer 40.

[0181] The first source electrode pattern S1 may be connected to the first source region SR1 of the connection transistor TR1 through the first contact hole CNT1, and the first source electrode pattern S1 and the first source region SR1 of the first semiconductor pattern SP may function as the source of the connection transistor TR1. The first drain electrode pattern D1 may be connected to the first drain region DR_1 of the connection transistor TR1 through the second contact hole CNT2, and the first drain electrode pattern D1 and the first drain region DR_1 of the first semiconductor pattern SP1 may function as the drain of the connection transistor TR1.

[0182] The second source electrode pattern S2 may be connected to a second source region SR2 and a second lower conductive layer BCL2 of a transistor TR2 of the second pixel driving unit PDC2 through a contact hole. The second source electrode pattern S2 and the second source region SR2 of the second semiconductor pattern SP2 may function as a source of the transistor TR2. The second drain electrode pattern D2 may be connected to a second gate electrode GE2 through a contact hole, and the second gate electrode GE2 may be connected to a second drain region (not shown) of the second semiconductor pattern SP2. That is, the second drain electrode pattern D2 may be connected to the second drain region of the transistor TR2, and the second drain electrode pattern D2 and the second drain region may function as a drain of the transistor TR2.

[0183] The fifth insulating layer 50 may be disposed on the first source electrode pattern S1, the first drain electrode pattern D1, the second source electrode pattern S2, and the second drain electrode pattern D2.

[0184] An intermediate connecting electrode CN may be disposed on the fifth insulating layer 50. The intermediate connecting electrode CN may electrically connect the first pixel driver PDC1 and the connecting electrode CNE. That is, the intermediate connecting electrode CN may electrically connect the first pixel driver PDC1 (more specifically, the connection transistor TR1 of the first pixel driver PDC1) and the light emitting element LD. The intermediate connecting electrode CN may be a connection node connecting the first pixel driver PDC1 and the light emitting element LD. That is, the intermediate connecting electrode CN may correspond to the fourth node N4 (see FIG. 2a) shown in FIG. 2a, the second node N2 (see FIG. 2b) shown in FIG. 2b, or the fourth node N4 (see FIG. 2c) shown in FIG. 2c.

[0185] A sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connecting electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethylmethacrylate), or PS (polystyrene), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0186] The sixth insulating layer 60 may have a through hole OP-60 exposing at least a portion of the intermediate connecting electrode CN. The intermediate connecting electrode CN may be connected to the connecting electrode CE through a portion exposed from the sixth insulating layer 60, and may be electrically connected to the light emitting element LD. That is, the intermediate connecting electrode CN may electrically connect the connection transistor TR1 and the light emitting element LD together with the connecting electrode CNE. Meanwhile, in the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or may be provided in a plurality of layers, and is not limited to any one embodiment. If the sixth insulating layer 60 is omitted, the intermediate connecting electrode CN may also be omitted.

[0187] The intermediate connecting electrode CN may include a first layer L1, a second layer L2, and a third layer L3 that are sequentially stacked along a third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a material with high conductivity. In one embodiment, the second layer L2 may include aluminum (Al).

[0188] A light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining film PDL, a light emitting element LD, and a separator SPR.

[0189] The pixel-defined membrane PDL can be an organic layer. For example, the pixel-defined membrane PDL can include common general-purpose polymers such as BCB (benzocyclobutene), polyimide, HMDSO (hexamethyldisiloxane), PMMA (polymethylmethacrylate), PS (polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0190] In one embodiment, the pixel defined layer PDL may have a light absorbing property, for example, a blocking hue. That is, the pixel defined layer PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defined layer PDL may correspond to a light blocking pattern having a light blocking property.

[0191] An opening OP-PDL (hereinafter, light-emitting opening) exposing at least a portion of a first electrode EL1 described later may be defined in the pixel defining layer PDL. A plurality of light-emitting openings OP-PDL may be provided and arranged corresponding to each light-emitting element. All components of the light-emitting element LD may be arranged to overlap in the light-emitting opening OP-PDL, and the light-emitting opening OP-PDL may be an area in which holes emitted by the light-emitting element LD are substantially displayed. Thus, the shape of the first light-emitting portion EP1 (see FIG. 4a) may substantially correspond to the shape of the light-emitting opening OP-PDL in a plan view.

[0192] A connecting electrode CNE may be disposed on the pixel defining layer PDL. The connecting electrode CNE may electrically connect the pixel driving part PDC and the light emitting element LD. That is, the pixel driving part PDC may be electrically connected to the light emitting element LD via the intermediate connecting electrode CN and the connecting electrode CNE. The connecting electrode CNE may correspond to the first connecting electrode CNE1 shown in FIG. 4a. The second connecting electrode CNE2 (see FIG. 4a) and the third connecting electrode CNE3 (see FIG. 4a) may also have a similar structure to the connecting electrode CNE.

[0193] The connecting electrode CNE may include a first edge EG1c adjacent to the light emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light emitting element LD may be in contact with the connecting electrode CNE in a region adjacent to the second edge EG2.

[0194] The connecting electrode CNE may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 However, the material constituting the connecting electrode CNE is not limited to the above examples.

[0195] A through hole OP-P separated from a light emitting opening OP-PDL may be defined in the pixel defining layer PDL. A plurality of through holes OP-P may be provided and disposed corresponding to each light emitting element. The size of the through hole OP-P defined in the pixel defining layer PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connecting electrode CNE may be disposed in the through hole OP-P and the through hole OP-60 and connected to the intermediate connecting electrode CN.

[0196] The light emitting element LD can include a first electrode EL1, an intermediate layer IML, and a second electrode layer EL2.

[0197] The first electrode EL1 may be a semi-transparent, transparent, or reflective electrode. According to an embodiment of the present invention, the first electrode EL1 may include a reflective layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may be made of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 For example, the first electrode EL1 may include a stacked structure of ITO / Ag / ITO.

[0198] In this embodiment, the first electrode EL1 may be an anode of the light emitting element LD. That is, the first electrode EL1 may be connected to the first power supply line VDL (see FIG. 2a) and a first power supply voltage VDD (see FIG. 2a) may be applied to the first electrode EL1. The first electrode EL1 may be connected to the first power supply line VDL in the display area DA (see FIG. 2a or FIG. 3b) or may be connected to the first power supply line VDL in the peripheral area NDA. In the latter case, the first power supply line VDL may be disposed in the peripheral area NDA (see FIG. 3a or FIG. 3b) and the first electrode EL1 may have a shape extended to the peripheral area NDA.

[0199] 5, the first electrode EL1 overlaps the light emitting opening OP-PDL and does not overlap the separator SPR, but as described above in FIG 4d, the first electrode EL1 of the light emitting element may have a mesh or lattice shape with an opening defined in a part of the shape. In other words, as long as the same first power supply voltage VDD can be applied to the first electrode EL1 of each of the plurality of light emitting elements, the shape of the first electrode EL1 may be variously provided and is not limited to any one embodiment.

[0200] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light emitting element LD may include the intermediate layer IML of various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided in a plurality of layers, or may be provided in two or more layers spaced apart with the emitting layer EML therebetween.

[0201] The emission layer EML may include an organic light-emitting material. The emission layer EML may also include an inorganic light-emitting material, or may be provided as a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In this embodiment, the emission layers EML included in each of the adjacent emission units EP (see FIG. 3a) may include light-emitting materials that display different colors. For example, the emission layer EML included in each emission unit EP may provide any one of blue, red, and green light. However, the present invention is not limited to this, and the emission layers EML disposed in all the emission units EP may include light-emitting materials that display the same color. In this case, the emission layer EML may provide blue light or white light.

[0202] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. In particular, the functional layer FNL may include a first intermediate functional layer FNLa (see FIG. 9) disposed between the first electrode EL1 and the emitting layer EML, and a second intermediate functional layer FNLb (see FIG. 9) disposed between the second electrode EL2 and the emitting layer EML. In one embodiment of the present invention, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb may be omitted. In this embodiment, the emitting layer EML is shown to be inserted in the functional layer FNK. That is, it may be understood that the emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0203] The functional layer FNL can control the transfer of charges between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0204] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may be connected to the connecting electrode CNE as described above and electrically connected to the first pixel driving part PDC1. That is, the second electrode EL2 may be electrically connected to the connecting transistor TR1 via the connecting electrode CNE.

[0205] The separator SPR may be disposed on the pixel defining layer PDL. Also, the separator SPR may be disposed on the connecting electrode CNE disposed on the pixel defining layer PDL and on the gap GP between the connecting electrode CNE and the adjacent connecting electrode CNEn.

[0206] In one embodiment, the second electrode EL2 and the functional layer FNL may be formed by common deposition on a plurality of pixels using an open mask. In this case, the second electrode EL2 and the functional layer FNL may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape for each light emitting portion, and therefore the second electrode EL2 and the functional layer FNL may have a shape divided for each light emitting portion. In other words, the second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel. Details of the separator will be described later with reference to FIG. 9.

[0207] An encapsulation layer ECL may be disposed on the light-emitting element layer LDL. The encapsulation layer ECL may cover the light-emitting element LD and may cover the separator SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 that are sequentially stacked. However, the encapsulation layer ECL is not limited thereto, and may further include a plurality of inorganic layers and organic layers. The encapsulation layer ECL may also be a glass substrate.

[0208] The first and second inorganic layers IL1 and IL2 may protect the light emitting element LD from water and oxygen outside the display panel DP, and the organic layer OL may protect the light emitting element LD from foreign matter such as particles remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, but the type of material is not limited to one of them.

[0209] The sensing layer ISL may sense an external input. In the present embodiment, the sensing layer ISL may be formed on the encapsulation layer ECL by a continuous process. In this case, the sensing layer ISL may be expressed as being directly disposed on the encapsulation layer ECL. Disposed directly may mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. In other words, no separate adhesive member may be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is merely an exemplary illustration, and in the display panel DP according to an embodiment of the present invention, the sensing layer ISL may be formed separately and then coupled to the display panel DP via an adhesive member, and is not limited to any one embodiment.

[0210] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0211] Each of the first to third sensing insulation layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulation layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulation layers 71, 72, and 73 may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0212] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing insulating layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0213] The single-layered sensing conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (ITO), etc. Alternatively, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0214] The multi-layered sensing conductive layer may include a metal layer, for example, a titanium (Ti) / aluminum (Al) / titanium (Ti) triple-layer structure, or the multi-layered sensing conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0215] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input in the sensing layer ISL. The sensor may be driven in a capacitive manner, and may be driven by any one of a mutual capacitance manner or a self-capacitance manner. However, this is an exemplary description, and the sensor may be driven by a resistive film manner, an ultrasonic manner, or an infrared manner other than the capacitive manner, and is not limited to any one of the embodiments.

[0216] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a metal mesh shape made of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0217] Fig. 6 is an enlarged plan view of a part of a display panel according to an embodiment of the present invention, which is a schematic diagram showing a part of the configuration of Fig. 4c (connecting electrodes CNE1, CNE2, CNE3 and light emitting portions EP1, EP2, EP3) and first to third conductive patterns CP1, CP2, CP3.

[0218] 5 and 6, the display panel DP may include first to third pixel driving parts PDC1, PDC2, and PDC3 (see FIG. 4b). The first pixel driving part PDC1 may include a first conductive pattern CP1, the second pixel driving part PDC2 may include a second conductive pattern CP2, and the third pixel driving part PDC3 may include a third conductive pattern CP3.

[0219] The first conductive pattern CP1 may include a 1-1 pattern S1 and a 2-1 pattern D1 electrically connected to the first connecting electrode CNE1. The second conductive pattern CP2 may include a 1-2 pattern S2 and a 2-2 pattern D2 electrically connected to the second connecting electrode CNE2. The third conductive pattern CP3 may include a 1-3 pattern S3 and a 2-3 pattern D3 electrically connected to the third connecting electrode CNE3. The 1-1 pattern S1, the 1-2 pattern S2, and the 1-3 pattern S3 may correspond to source electrode patterns of transistors, and the 2-1 pattern D1, the 2-2 pattern D2, and the 2-3 pattern D3 may correspond to drain electrode patterns of transistors.

[0220] The conductive patterns CP1, CP2, and CP3 may overlap adjacent connecting electrodes CNE1, CNE2, and CNE3 that are not electrically connected to each other. For example, the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 may overlap the second connecting electrode CNE2 in a plan view even though they are not electrically connected to the second connecting electrode CNE2, and the 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 may overlap the first connecting electrode CNE1 in a plan view even though they are not electrically connected to the first connecting electrode CNE1. When the conductive patterns and the connecting electrodes that are not electrically connected to each other overlap each other in a plan view, the electric field may fluctuate, and coupling noise caused by the fluctuation in the electric field may occur or increase.

[0221] 5, the display panel DP may further include a first metal layer ML1. The first metal layer ML1 may include the same material as the first electrode EL1 and may be connected to the first electrode E1. That is, the first metal layer ML1 may be formed by the same process as the first electrode EL1. The first metal layer ML1 may be disposed between the 1-2 pattern S2 and the 2-2 pattern D2 and the connecting electrode CNE in a cross-sectional view. The 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 may overlap the first metal layer ML1 in a plan view.

[0222] The connecting electrode CNE in Fig. 5 may be an electrode that is not electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. For example, referring to Fig. 6, the first metal layer ML1 may include the same material as the first electrode EL1 of the first light emitting unit EP1 and may be connected to the first electrode EL1 of the first light emitting unit EP1. The first metal layer ML1 may be disposed between the second conductive pattern CP2 and the first connecting electrode CNE1 in a cross-sectional view, and the first metal layer ML1 may overlap the 1-2 pattern S2 and the 2-2 pattern D2 of the second conductive pattern CP2 in a plan view.

[0223] However, this is merely an example, and the position of the first metal layer ML1 is not limited to the above example. For example, the first metal layer ML1 may be disposed between the first conductive pattern CP1 and the second connecting electrode CNE2 in a cross-sectional view, and the first metal layer ML1 may overlap the 1-1 pattern S1 and the 2-1 pattern D1 of the first conductive pattern CP1 in a plan view.

[0224] According to the present invention, a first electrode EL1 of a display panel DP may be extended and disposed between the conductive patterns CP1, CP2, CP3 and the connecting electrode CNE. A first power supply voltage VDD (see FIG. 2a) may be provided to the first electrode EL1. That is, when the conductive patterns CP1, CP2, CP3 and the connecting electrode CNE are shielded using the first electrode EL1 to which a static voltage is provided, coupling noise formed between the conductive patterns CP1, CP2, CP3 and the connecting electrode CNE may be reduced or eliminated.

[0225] Fig. 7 is a cross-sectional view of a display panel DP-1 according to an embodiment of the present invention. Fig. 7 shows a cross-sectional view of a portion corresponding to line II' in Fig. 4a. Fig. 7 will be described with reference to Fig. 5, and the description of the same reference numerals will be omitted.

[0226] 7, the display panel DP-1 may further include a second metal layer ML2. The second metal layer ML2 may include the same material as the intermediate connecting electrode CN and may be disposed on the same layer as the intermediate connecting electrode CN. That is, the second metal layer ML2 may be formed by the same process as the intermediate connecting electrode CN. The second metal layer ML2 may be disposed between the 1-2 pattern S2 and the 2-2 pattern D2 and the connecting electrode CNE. The 1-2 pattern S2 and the 2-2 pattern D2 may overlap with the second metal layer ML2 in a plan view.

[0227] The connecting electrode CNE in Fig. 7 may be an electrode that is not electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. For example, referring to Fig. 6, the second metal layer ML2 may include the same material as the intermediate connecting electrode CN that electrically connects the first pixel driving part PDC1 and the first connecting electrode CNE1, and may be disposed on the same layer as the intermediate connecting electrode CN that electrically connects the first pixel driving part PDC1 and the first connecting electrode CNE1. The second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connecting electrode CNE1 in a cross-sectional view, and the second metal layer ML2 may overlap the 1-2 pattern S2 and the 2-2 pattern D2 in a plan view.

[0228] However, this is merely an example, and the position of the second metal layer ML2 is not limited to the above form. For example, the second metal layer ML2 may be disposed between the first conductive pattern CP1 and the second connecting electrode CNE2 in a cross-sectional view, and the second metal layer ML2 may overlap the 1-1 pattern S1 and the 2-1 pattern D1 in a plan view.

[0229] According to the present invention, by extending the intermediate connecting electrode CN of the display panel DP-1, it is possible to reduce or eliminate coupling noise generated between the conductive patterns CP1, CP2, CP3 and the connecting electrode CNE.

[0230] Fig. 8 is a cross-sectional view of a display panel DP-2 according to an embodiment of the present invention. Fig. 8 shows a cross-sectional view of a portion corresponding to line II' in Fig. 4a. Fig. 8 will be described with reference to Fig. 5, and description of the same reference numerals will be omitted.

[0231] 8, the display panel DP-2 may further include a first metal layer ML1 and a second metal layer ML2. The first metal layer ML1 may include the same material as the first electrode EL1 and may be connected to the first electrode E1. The second metal layer ML2 may include the same material as the intermediate connecting electrode CN and may be disposed on the same layer as the intermediate connecting electrode CN. That is, the first metal layer ML1 may be formed by the same process as the first electrode EL1, and the second metal layer ML2 may be formed by the same process as the intermediate connecting electrode CN.

[0232] The first metal layer ML1 and the second metal layer ML2 may be disposed between the first-2 pattern S2 and the second-2 pattern D2 and the connecting electrode CNE. The first-2 pattern S2 and the second-2 pattern D2 may overlap with the second metal layer ML2 in a plan view.

[0233] The connecting electrode CNE in FIG. 8 may be an electrode that is not electrically connected to the 1-2 pattern S2 and the 2-2 pattern D2. For example, referring to FIG. 6, the first metal layer ML1 may include the same material as the first electrode EL1 of the first light emitting unit EP1 and may be connected to the first electrode EL1 of the first light emitting unit EP1. The second metal layer ML2 may include the same material as the intermediate connecting electrode CN that electrically connects the first pixel driving unit PDC1 and the first connecting electrode CNE1 and may be disposed on the same layer as the intermediate connecting electrode CN that electrically connects the first pixel driving unit PDC1 and the first connecting electrode CNE1. The first metal layer ML1 and the second metal layer ML2 may be disposed between the second conductive pattern CP2 and the first connecting electrode CNE1 in a cross-sectional view, and the first metal layer ML1 and the second metal layer ML2 may overlap the 1-2 pattern S2 and the 2-2 pattern D2 in a plan view.

[0234] However, this is merely an example, and the positions of the first metal layer ML1 and the second metal layer ML2 are not limited to the above example. For example, the first metal layer ML1 and the second metal layer ML2 may be disposed between the first conductive pattern CP1 and the second connecting electrode CNE2 in a cross-sectional view, and the first metal layer ML1 and the second metal layer ML2 may overlap the 1-1 pattern S1 and the 2-1 pattern D1 in a plan view.

[0235] According to the present invention, by extending the intermediate connecting electrode CN and / or the first electrode EL1 of the display panel DP-2, it is possible to reduce or eliminate coupling noise generated between the conductive patterns CP1, CP2, CP3 and the connecting electrode CNE.

[0236] 9 is an enlarged cross-sectional view of a portion of a display panel DP according to an embodiment of the present invention, taken along the line AA' in FIG.

[0237] 5 and 9, in one embodiment, the separator SPR may have an inverse taper shape. That is, the separator SPR may have a shape in which the width increases as it moves away from the upper surface of the pixel defining film PDL. The side surface TP of the separator SPR may have a shape in which the taper angle inclined from the upper surface of the pixel defining film PDL is an obtuse angle. However, this is an exemplary illustration, and the separator SPR may have various taper angles as long as the separator SPR can electrically disconnect the second electrode EL2 for each pixel. For example, the separator SPR may have a double structure with different taper angles. In addition, the separator SPR may have a structure such as a tip portion, and is not limited to any one embodiment.

[0238] The separator SPR may include a material having insulating properties, and may particularly include an organic insulating material. The separator SPR may include an inorganic insulating material, may be configured with multiple layers of an organic insulating material and an inorganic insulating material, or may include a conductive material depending on the embodiment. In other words, as long as the second electrode EL2 can be electrically disconnected for each pixel, the separator SPR is not particularly limited in terms of the type of material.

[0239] A dummy layer UP may be disposed on the upper portion of the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may contain the same material. The first dummy layer UP1 may include a 1-1 dummy layer UP1a and a 1-2 dummy layer UP1b. The 1-1 dummy layer UP1a may be formed in the same process as the first intermediate functional layer FNLa and may contain the same material. The 1-2 dummy layer UP1b may be formed in the same process as the second intermediate functional layer FNLb and may contain the same material. The second dummy layer UP2 may be formed in the same process as the second electrode EL2 and may contain the same material. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the functional layer FNL and the second power source EL2. 9, the dummy layer UP may be formed not only on the top surface of the separator SPR but also on a part of the side surface TP. In another embodiment, the display panel DP may not include the dummy layer UP. The dummy layer UP may not be in contact with the connecting electrode CNE and the second power source EL2. The second dummy layer UP2 included in the dummy layer UP may not be in contact with the connecting electrode CNE and the second power source EL2.

[0240] A portion where the second electrode EL2 contacts the connecting electrode CNE may be defined as a contact region. The contact region is provided adjacent to the separator SPR. In the contact region, an upper surface CNE-us of the connecting electrode CNE contacts a lower surface EL2-bs of the second electrode EL2. Meanwhile, since the separator SPR has an inverse tapered shape and the contact region is provided adjacent to the separator SPR, at least a portion of the contact region where the second electrode EL2 contacts the connecting electrode CNE may be disposed under a side surface TP of the separator SPR.

[0241] Meanwhile, in one embodiment, at least a portion of the connecting electrode CNE may be disposed under the separator SPR. The separator SPR may be disposed on the connecting electrode CNE and the gap GP between the connecting electrode CNE and an adjacent connecting electrode, and the second edge EG2c of the second electrode EL2 may be barred by the separator SPR.

[0242] According to an embodiment of the present invention, the connecting electrode CNE has a shape surrounding at least a part of the light emitting area EA in which the light emitting element LD is disposed. Therefore, the degree of freedom of the position at which the connecting electrode CNE and the light emitting element LD are connected and the degree of freedom of the position at which the connecting electrode CNE and the pixel driving unit PDC are connected may be improved. In addition, the upper surface CNE-us of the connecting electrode CNE may be in contact with the lower surface EL2-bs of the second electrode EL2 of the light emitting element LD through the contact region defined adjacent to the separator SPR. As a result, the contact reliability between the connecting electrode CNE and the second electrode EL2 may be improved, and the lower surface of the connecting electrode CNE and the upper surface of the intermediate connecting electrode CN may be in contact with each other, thereby improving the contact reliability. In the display panel DP according to the embodiment, the size of the through holes OP-P and OP-60 for connecting the connecting electrode CNE and the intermediate connecting electrode CN may be reduced or minimized through the above-described structure, thereby easily increasing the area or resolution of the light emitting portion of the display panel DP.

[0243] Fig. 10 is a cross-sectional view of a display panel DP-3 according to an embodiment of the present invention. Fig. 10 shows a cross-sectional view of a portion corresponding to line I-I' in Fig. 4a. Fig. 10 will be described with reference to Fig. 5, and description of the same reference numerals will be omitted.

[0244] 10, the display panel DP-3 may further include a connecting wire CN-ad disposed between the sixth insulating layer 60 and the pixel defining film PDL. The connecting wire CN-ad may be connected to the intermediate connecting electrode CN through a through hole OP-60 that exposes at least a portion of the intermediate connecting electrode CN.

[0245] In an embodiment of the present invention, the connecting wire CN-ad may be disposed on the same layer as the first electrode EL1. For example, the connecting wire CN-ad may have the same material and layer structure as the first electrode EL1. Also, the connecting wire CN-ad may be formed by the same process as the first electrode EL1. However, this is merely an example and is not limited thereto. For example, the connecting wire CN-ad may include a different material from the first electrode EL1 and be formed by a different process.

[0246] A through hole OP-Pa may be defined in the pixel defining layer PDL. The through hole OP-Pa and the through hole OP-60 may not overlap each other, but is not limited thereto. For example, the through hole OP-Pa and the through hole OP-60 may overlap each other. A connecting electrode CNE may be disposed in the through hole OP-Pa. The connecting electrode CNEa may be connected to a portion of the connecting wire CN-ad exposed by the through hole OP-Pa.

[0247] Although the present invention has been described with reference to preferred embodiments thereof, it should be understood by those skilled in the art or those having ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as described in the claims below. Therefore, the technical scope of the present invention should be determined by the claims, not by the contents described in the detailed description of the specification. [Explanation of symbols]

[0248] DP: Display panel DDL: Driver element layer PDC1: First pixel drive unit PDC2: Second pixel drive unit EL1: 1st electrode IML: Intermediate layer EL2: Second electrode LD: Light emitting element CNE: Connecting electrode CN: Intermediate connecting electrode ML1, ML2: first and second metal layers

Claims

1. a driving element layer including a first pixel driving unit including a first conductive pattern and a second pixel driving unit including a second conductive pattern; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a connection electrode disposed on the driving element layer and electrically connected to the first pixel driving part and the second electrode; a metal layer disposed between the second conductive pattern and the connecting electrode in a cross-sectional view.

2. 2. The display panel of claim 1, wherein the first conductive pattern includes a 1-1 pattern and a 2-1 pattern electrically connected to the connecting electrode.

3. 3. The display panel according to claim 2, wherein the second conductive pattern includes a 1-2 pattern and a 2-2 pattern.

4. 4. The display panel according to claim 3, wherein the first-2 pattern and the second-2 pattern overlap with the metal layer in a plan view.

5. 4. The display panel according to claim 3, wherein the first-2 pattern and the second-2 pattern overlap with the connecting electrode in a plan view.

6. 4. The display panel of claim 3, wherein the first-1 pattern and the first-2 pattern are source electrode patterns.

7. 4. The display panel of claim 3, wherein the second-1 pattern and the second-2 pattern are drain electrode patterns.

8. The display panel of claim 1 , further comprising an intermediate connecting electrode electrically connecting the first pixel driving part and the connecting electrode.

9. The display panel of claim 8 , wherein the metal layer includes the same material as the intermediate connecting electrode and is disposed on the same layer as the intermediate connecting electrode.

10. The display panel of claim 1 , wherein the metal layer includes the same material as the first electrode and is connected to the first electrode.

11. a pixel defining film disposed on the driving element layer and having a light emitting opening that exposes at least a portion of the first electrode defined therein; The display panel according to claim 1 , wherein the connecting electrode has a ring shape surrounding the light-emitting opening.

12. The display panel of claim 1 , wherein a lower surface of the second electrode contacts an upper surface of the connecting electrode.

13. The liquid crystal display further includes a separator disposed on the connecting electrode, The display panel of claim 1 , wherein the second electrode and the connecting electrode are connected to an area adjacent to the separator.

14. The display panel of claim 13 , wherein the connecting electrode includes a first edge and a second edge surrounding the first edge, the second edge overlapping the separator.

15. a driving element layer including a pixel driving unit including a conductive pattern; a light-emitting element disposed on the driving element layer, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a connection electrode disposed on the driving element layer and electrically connected to the pixel driving part and the second electrode; a metal layer overlapping the connecting electrode and the conductive pattern in a plan view.

16. The display panel of claim 15, wherein the conductive pattern includes a first pattern and a second pattern electrically connected to the connecting electrode.

17. The display panel of claim 16, wherein the first pattern is a source electrode pattern and the second pattern is a drain electrode pattern.

18. The display panel of claim 15, further comprising an intermediate connecting electrode electrically connecting the pixel driving part and the connecting electrode.

19. The display panel of claim 18 , wherein the metal layer includes the same material as the intermediate connecting electrode and is disposed on the same layer as the intermediate connecting electrode.

20. The display panel of claim 15 , wherein the metal layer includes the same material as the first electrode and is connected to the first electrode.

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