Semiconductor devices and communication method between semiconductor devices

Abstract

To provide a semiconductor device and a communication method between semiconductor devices that utilize a plurality of pins for transmitting data by parallel transmission to improve transmission performance while reducing frequency of transmission.SOLUTION: A semiconductor device includes a plurality of pins, semiconductor components, and a scalable digital interface circuit. The pins are divided into a plurality of data sending groups and a plurality of data receiving groups. The semiconductor components provide output data and receive input data. The scalable digital interface circuit is coupled to the data sending groups, the data receiving groups, and the semiconductor components, wherein the scalable digital interface circuit reorganizes the output data into parallel transmission data to send the parallel transmission data to an external semiconductor device by parallel transmission, and receives parallel reception data from the external semiconductor device by parallel transmission to reorganize the parallel reception data into the input data.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a semiconductor device using parallel transmission, and a communication method between semiconductor devices.

Background Art

[0002] The process of semiconductor manufacturing technology has been continuously progressing over a long period of time to increase the number of transistors on a chip in order to improve computing performance. As a result, the gate length has gradually become shorter and is gradually approaching the known physical limits at present. However, with the rapid development of artificial intelligence (AI), AI-generated content (AIGC), and other related applications, the performance requirements for the equipment for core chips are increasing more and more. When the improvement of manufacturing technology encounters a bottleneck, increasing the number of transistors on a chip by advanced packaging technology of chip stacking has become a necessary choice. However, in view of the fact that the demand for computing resources continues to rise with the computing demand, improving the chip performance in the current packaging technology is still an important issue.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Embodiments of the present invention provide a semiconductor device and a communication method between semiconductor devices that use a plurality of pins to transmit data by parallel transmission in order to improve transmission performance and reduce transmission frequency.

Means for Solving the Problems

[0004] One embodiment of the present invention provides a semiconductor device, which includes a plurality of pins, at least one semiconductor component, and a scalable digital interface circuit. The pins are divided into a plurality of data transmission groups and a plurality of data reception groups. The at least one semiconductor component provides at least one output data and receives at least one input data. The scalable digital interface circuit is coupled to at least one data transmission group, at least one data reception group, and at least one semiconductor component. The scalable digital interface circuit reconstructs at least one output data into at least one parallel transmission data, transmits at least one parallel transmission data to an external semiconductor device by parallel transmission, and reconstructs at least one parallel reception data into at least one input data.

[0005] Another embodiment of the present invention provides a communication method between semiconductor devices, which includes the following steps. At least one output data provided by at least one semiconductor component is reconstructed by a scalable digital interface circuit into at least one parallel transmission data. At least one parallel transmission data is transmitted to an external semiconductor device through parallel transmission by at least one of a plurality of data transmission groups of a plurality of pins. At least one parallel reception data is received from the external semiconductor device by at least one of a plurality of data reception groups of the pins. The scalable digital interface circuit reconstructs at least one parallel reception data into at least one input data and provides it to at least one semiconductor component.

Advantages of the Invention

[0006] Based on the above, in the semiconductor device and the communication method between semiconductor devices according to the embodiments of the present invention, data is transmitted between semiconductor devices via parallel transmission. The use of parallel transmission increases the speed of huge data transmission and can be executed even at a low signal frequency. In this way, the transmission performance can be improved and the transmission frequency can be reduced.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 6

Figure 7

Figure 8

Figure 9

Modes for Carrying Out the Invention

[0008] FIG. 1 is a schematic diagram of a system for packaging a plurality of semiconductor devices according to one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, the integrated circuit 10 includes at least semiconductor devices 100 and 200, and the semiconductor devices 100 and 200 are, for example, chips. The semiconductor devices 100 and 200 can be packaged as a single integrated circuit using three-dimensional (3D) chip packaging or chiplet packaging. That is, the semiconductor devices 100 and 200 can be stacked adjacent to or close to each other in the integrated circuit by different methods, but the present invention is not limited thereto.

[0009] In the present embodiment, the semiconductor device 100 includes, for example, a plurality of pins (for example, a plurality of transmission pins GPTX1 and a plurality of reception pins GPRX1), at least one semiconductor component (for example, memory units 110_1 to 110_n and / or arithmetic units 120_1 to 120_m, where n and m may be any positive integers and depend on the circuit design), a signal bus 130, and a scalable digital interface circuit 140. The transmission pins GPTX1 are divided into a plurality of data transmission groups (GTX1 to GTX5 shown in FIG. 8), and the reception pins GPRX1 are divided into a plurality of data reception groups (GRX1 to GRX5 shown in FIG. 8). The scalable digital interface circuit 140 is based on a data transmission group (GTX1 to GTX5 shown in FIG. 8) for data output and a data reception group (GRX1 to GRX5 shown in FIG. 8) for data input.

[0010] The signal bus 130 is coupled to the memory units 110_1 to 110_n, the arithmetic units 120_1 to 120_m, and the scalable digital interface circuit. That is, the scalable digital interface circuit 140 is coupled to the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m via the signal bus 130. The scalable digital interface circuit 140 is coupled to at least one of the data transmission groups (GTX1 to GTX5 shown in FIG. 8) of the transmission pins GPTX1 and at least one of the data reception groups (GRX1 to GRX5 shown in FIG. 8) of the reception pins GPRX1.

[0011] When at least one of the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m provides the output data Dout, the scalable digital interface circuit 140 receives at least one output data Dout via the signal bus 130. Then, at least one output data Dout is reconfigured into at least one parallel transmission data Dpsent, and at least one parallel transmission data Dpsent is transmitted in parallel via the combined data transmission group (GTX1 to GTX5 shown in FIG. 8) to another external semiconductor device (for example, semiconductor device 200).

[0012] When the scalable digital interface circuit 140 receives at least one parallel reception data Dprce from another external semiconductor device (for example, semiconductor device 200) in parallel via the combined data reception group (GRX1 to GRX5 shown in FIG. 8), the scalable digital interface circuit 140 may reconfigure at least one parallel reception data Dprce into at least one input data Din and then transmit it to the signal bus 130. The input data Din may correspond to the data format of the reception target (that is, one of the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m). Then, one or more of the memory units 110_1 to 110_n and the arithmetic units 120_1 to 120_m receive the corresponding one of at least one input data Din via the signal bus 130.

[0013] Based on the above, in 3D chip packaging or chiplet packaging, chips are stacked adjacent to or close to each other, and a number of channels (e.g., through-silicon vias (TSVs) or redistribution layers (RDLs)) can be established between semiconductor devices 100 and 200. The data transmission speed (e.g., bandwidth) can be increased through a number of channels, and it is not necessarily required to execute at a high signal frequency. In this way, it is possible to improve the transmission performance while reducing power consumption and cost. Also, signals are transmitted between semiconductor devices 100 and 200 by digital connection via scalable digital interface circuits 140 and 240, so that the manufacturing process of semiconductor components can be freely switched.

[0014] In this embodiment, semiconductor device 200 includes, for example, a plurality of pins (e.g., a plurality of transmission pins GPTX2 and a plurality of reception pins GPRX2), at least one semiconductor component (e.g., memory units 210_1 to 210_p and / or arithmetic units 220_1 to 220_q, where p and q may be any positive integer or 0 and depend on the circuit design), a signal bus 230, and a scalable digital interface circuit 240. The coupling structure and operation mode of semiconductor device 200 can refer to the description of semiconductor device 100 and will not be repeated here.

[0015] In this embodiment, memory units 110_1 to 110_n and / or arithmetic units 120_1 to 120_m may be integrated into at least one die. For example, depending on the circuit design, memory units 110_1 to 110_n may be integrated into one or more dies, and arithmetic units 120_1 to 120_m may be integrated into one or more dies, and the embodiments of the present invention are not limited thereto. Similarly, memory units 210_1 to 210_p and / or arithmetic units 220_1 to 220_q may also be integrated into at least one die.

[0016] In the present embodiment, according to the circuit designs of the memory units 110_1 to 110_n and / or the arithmetic units 120_1 to 120_m, each of the output data Dout and the input data Din may include, for example, at least one of an Advanced High-Performance Bus (AHB) signal, an Advanced eXtensible Interface (AXI) signal, a serial bus signal, and a parallel bus signal.

[0017] In the present embodiment, the arithmetic units 120_1 to 120_m and 220_1 to 220_q include, for example, at least one of a Central Processing Unit (CPU), an Application Processor (AP), and a Graphics Processing Unit (GPU).

[0018] In the present embodiment, the memory units 110_1 to 110_n and 210_1 to 210_p may include a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a Thyristor Random Access Memory (TRAM) device, a NAND type flash memory device, a NOR type flash memory device, a Resistive Random Access Memory (RRAM) device, a Ferroelectric Random Access Memory (FRAM) device, a Phase Change Memory (PRAM) device, a Magnetic Random Access Memory (MRAM) device, a Solid State Drive (SSD), a memory card, a Universal Flash Storage (UFS), or a similar device.

[0019] FIG. 2 is a connection diagram of pins for connecting semiconductor devices according to one embodiment of the present invention. Referring to FIGS. 1 and 2, in this embodiment, for semiconductor devices 300 and 400, reference may be made to those shown in the embodiments of semiconductor devices 100 and 200. In this embodiment, the number of transmission pins GPTX3 of semiconductor device 300 may be different from the number of reception pins GPRX4 of semiconductor device 400, and the number of reception pins GPRX3 of semiconductor device 300 may be different from the number of transmission pins GPTX4 of semiconductor device 400. However, the transmission pins GPTX3 of semiconductor device 300 and the reception pins GPRX4 of semiconductor device 400 can be grouped into a plurality of data transmission groups and a plurality of data reception groups based on the same pin base number (for example, 40 pins), and the data transmission group of semiconductor device 300 and the data reception group of semiconductor device 400 can be connected group-to-group. Thereby, semiconductor device 300 and semiconductor device 400 can transmit data from semiconductor device 300 to semiconductor device 400 via the combined data transmission group and data reception group.

[0020] In this embodiment, the connection number of the transmission pins GPTX3 of semiconductor device 300 and the reception pins GPRX4 of semiconductor device 400 is based on the pin base number of a single data transmission group / single data reception group (for example, 40 pins) as a unit, and is less than or equal to the smaller number of the transmission pins GPTX3 of semiconductor device 300 and the reception pins GPRX4 of semiconductor device 400. For example, the connection number of the transmission pins GPTX3 (for example, 640 pins) of semiconductor device 300 and the reception pins GPRX4 (for example, 560 pins) of semiconductor device 400 may be 14 sets of data transmission group - data transmission group (that is, 14×40 = 560 pins).

[0021] Based on the above, semiconductor devices 300 and 400 can be connected without defining the same number of pins via a digital connection, that is, it is possible to connect semiconductor devices with different pin numbers, thereby improving the flexibility of semiconductor device connection.

[0022] In this embodiment, when the transmission speed of the transmission pin GPTX3 of the semiconductor device 300 is higher than the transmission speed of the reception pin GPRX4 of the semiconductor device 400, in order to avoid signal transmission delay, the usage rate of the connection portion between the transmission pin GPTX3 of the semiconductor device 300 and the reception pin GPRX4 of the semiconductor device 400 may be increased. Relatively, when the transmission speed of the transmission pin GPTX3 of the semiconductor device 300 is lower than the transmission speed of the reception pin GPRX4 of the semiconductor device 400, in order to reduce waste of system performance without affecting signal transmission, the usage rate of the connection portion between the transmission pin GPTX3 of the semiconductor device 300 and the reception pin GPRX4 of the semiconductor device 400 may be decreased.

[0023] In this embodiment, when the transmission speeds of the output data Dout and the input data Din increase, in order to reduce the idle rate of the scalable digital interface circuit (for example, the scalable digital interface circuits 140 and 240) or the time during which the signal to be transmitted is accumulated in the scalable digital interface circuit (for example, the scalable digital interface circuits 140 and 240), the usage rate of the transmission pin GPTX3 of the semiconductor device 300 and the reception pin GPRX4 of the semiconductor device 400 may be increased. Relatively, when the transmission speeds of the output data Dout and the input data Din decrease, the usage rate of the transmission pin GPTX3 of the semiconductor device 300 and the reception pin GPRX4 of the semiconductor device 400 may be decreased.

[0024] FIG. 3 is a system diagram of a scalable digital interface circuit according to one embodiment of the present invention. Referring to FIGS. 1 to 3, in this embodiment, the semiconductor device 300 includes, for example, a scalable digital interface circuit 340, and for the scalable digital interface circuits 140 and 240, reference may be made to this scalable digital interface circuit 340. Further, the scalable digital interface circuit 340 includes a bus package circuit 341, an address / data reconstruction register 342, a transmission reassembler 343, a reception reassembler 344, a transmission buffer 345, an input / output controller 346, a reception buffer 347, and a general-purpose input / output interface circuit 348.

[0025] The bus package circuit 341 is coupled to the signal bus 130. The address / data reconstruction register 342 is coupled to the bus package circuit 341. The transmission reassembler 343 is coupled to the address / data reconstruction register 342. The reception reassembler 344 is coupled to the address / data reconstruction register 342. The transmission buffer 345 is coupled to the transmission reassembler 343. The reception buffer 347 is coupled to the reception reassembler 344. The general-purpose input / output interface circuit 348 is coupled to the transmission buffer 345 and the reception buffer 347. The input / output controller 346 is coupled to the transmission buffer 345 and the reception buffer 347.

[0026] The input / output controller 346 is used to control the transmission buffer 345 and the reception buffer 347. When the bus package circuit 341 receives output data (e.g., output data Dout) from a storage unit (e.g., storage units 110_1 to 110_n and 210_1 to 210_p) via a signal bus (e.g., signal buses 130, 230), the bus package circuit 341 temporarily stores the output data (e.g., output data Dout) in the address / data reconstruction register 342. Next, the transmission reassembler 343 reconstructs the output data (e.g., output data Dout) into parallel transmission data (e.g., parallel transmission data Dpsent) for temporary storage in the transmission buffer 345, and the transmission reassembler 343 is responsible for configuring the execution sequence of read and write commands into small packets of continuous data to provide the parallel transmission data (e.g., parallel transmission data Dpsent). Also, the general-purpose input / output interface circuit 348 transmits the parallel transmission data (e.g., parallel transmission data Dpsent) temporarily stored in the transmission buffer 345 to another external semiconductor device (e.g., semiconductor device 400) via at least one data transmission group of the transmission pin GPTX3.

[0027] On the one hand, when the general-purpose input / output interface circuit 348 receives parallel reception data (e.g., parallel reception data Dprce) via at least one reception group of the reception pin GPRX3 from another external semiconductor device (e.g., semiconductor device 300), the general-purpose input / output interface circuit 348 temporarily stores the parallel reception data (e.g., parallel reception data Dprce) in the reception buffer 347. Next, the reception reassembler 344 reconstructs the parallel reception data (e.g., parallel reception data Dprce) temporarily stored in the reception buffer 347 into input data (e.g., input data Din) and temporarily stores it in the address / data reconstruction register 342, and the reception reassembler 344 is responsible for restoring the small packets of data (i.e., parallel reception data Dprce) into an execution sequence that can be randomly written to provide the input data (e.g., input data Din). Also, the bus packaging circuit 341 provides the input data (e.g., input data Din) temporarily stored in the address / data reconstruction register 342 to the storage unit (e.g., storage units 110_1 to 110_n, 210_1 to 210_p) and / or the arithmetic unit (e.g., arithmetic units 120_1 to 120_m, 220_1 to 220_q) via a signal bus (e.g., signal buses 130, 230).

[0028] FIG. 4 is a coupling diagram of pins connecting semiconductor devices according to another embodiment of the present invention. Referring to FIGS. 1, 2, and 4, in this embodiment, for semiconductor devices 500, 600, and 700, reference may be made to the embodiments of semiconductor devices 100 and 200. In this embodiment, the transmission pins GPTX51 and GPTX52 of the semiconductor device 500 can be divided into a plurality of data transmission groups, and the reception pins GPRX51 and GPRX52 of the semiconductor device 500 can be divided into a plurality of data reception groups. Similarly, the transmission pin GPTX6 of the semiconductor device 600 and the transmission pin GPTX7 of the semiconductor device 700 can be divided into a plurality of data transmission groups, and the reception pin GPRX6 of the semiconductor device 600 and the GPRX7 of the semiconductor device 700 can be divided into a plurality of data reception groups.

[0029] In this embodiment, the data transmission group of the transmission pin GPTX51 of the semiconductor device 500 and the data reception group of the reception pin GPRX6 of the semiconductor device 600 can be coupled in a group-to-group manner. The data transmission group of the transmission pin GPTX52 of the semiconductor device 500 and the data reception group of the reception pin GPRX7 of the semiconductor device 700 can be coupled in a group-to-group manner. The data reception group of the reception pin GPRX51 of the semiconductor device 500 and the data transmission group of the transmission pin GPTX6 of the semiconductor device 600 can be coupled in a group-to-group manner. And the data reception group of the reception pin GPRX52 of the semiconductor device 500 and the data transmission group of the transmission pin GPTX7 of the semiconductor device 700 can be coupled in a group-to-group manner.

[0030] The ratio of the reception pins GPRX51 and GPRX52 of the semiconductor device 500 may be related to the ratio of the transmission speed of the transmission pin GPTX7 of the semiconductor device 700 to the transmission speed of the transmission pin GPTX6 of the semiconductor device 600, or may be related to the ratio of the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside the semiconductor device 600 to the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside the semiconductor device 700, that is, the higher the transmission speed, the higher the ratio.

[0031] On the other hand, the ratio of the transmission pins GPTX51 and GPTX52 of the semiconductor device 500 may be related to the ratio of the transmission speed of the reception pin GPRX7 of the semiconductor device 700 to the transmission speed of the reception pin GPRX6 of the semiconductor device 600, that is, the lower the transmission speed, the higher the ratio, or may be related to the ratio of the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside the semiconductor device 600 to the transmission speed of the output data (e.g., output data Dout) and / or input data (e.g., input data Din) inside the semiconductor device 700, that is, the higher the transmission speed, the higher the ratio.

[0032] FIG. 5 is a system diagram of a scalable digital interface circuit according to another embodiment of the present invention. Referring to FIGS. 1 to 5, in this embodiment, the semiconductor device 500 includes, for example, a scalable digital interface circuit 540. For the scalable digital interface circuits 140 and 240, reference may be made to this scalable digital interface circuit 540. Further, the scalable digital interface circuit 540 includes a bus package circuit 541, an address / data reconstruction register 542, transmission reassemblers 543_1 to 543_x, reception reassemblers 544_1 to 544_x, transmission buffers 545_1 to 545_x, input / output controllers 546_1 to 546_x, reception buffers 547_1 to 547_x, and general-purpose input / output interface circuits 548_1 to 548_x, where x may be any positive integer. The operation of the scalable digital interface circuit 540 may be referred to the scalable digital interface circuit 340, which will not be repeated here. In addition, since parallel transmission requires a large number of connections, semiconductor devices (e.g., semiconductor devices 500, 600) do not span a long distance, and usually x < 4. However, when long-distance transmission is required, other connection protocols such as PCIE (Peripheral Component Interconnect Express), UCIE (Universal Chip Interconnect Express), etc. may be adopted, and the embodiments of the present invention are not limited thereto.

[0033] FIG. 6 is a stacked diagram of a semiconductor device according to one embodiment of the present invention. Referring to FIGS. 1 to 6, in this embodiment, the semiconductor devices 100a and 200a are directly stacked, that is, the semiconductor devices 100a and 200a are packaged using a 3D chip packaging method.

[0034] FIG. 7 is a stacked view of a semiconductor device according to another embodiment of the present invention. Referring to FIGS. 1 to 7, in this embodiment, semiconductor devices 100b and 200b are stacked adjacent to each other on the same surface of an interposer or a substrate 800, that is, semiconductor devices 100b and 200b are packaged using a chiplet packaging method. Semiconductor devices 100b and 200b are coupled to each other via paths formed by a redistribution layer (RDL) and / or a through-silicon via (TSV) on the interposer or substrate 800.

[0035] FIG. 8 is a circuit diagram of a general-purpose input / output interface according to an embodiment of the present invention. Referring to FIGS. 1, 3, and 8, in this embodiment, for the general-purpose input / output interface circuit 348, reference may be made to the general-purpose input / output interface circuit 348a, which includes a plurality of general-purpose input / output transmission circuits GPX1 to GPX5, a plurality of general-purpose input / output reception circuits GPE1 to GPE5, a plurality of transmission multiplexers TMX1 to TMX3, and a plurality of reception multiplexers RMX1 to RMX4.

[0036] In this embodiment, it is assumed that the parallel transmission data (e.g., parallel transmission data Dpsent) stored in the transmission buffer 345a has four transmission data parts DPX1 to DPX4, and the received parallel reception data (e.g., parallel reception data Dprce) has four reception data parts DPE1 to DPE4 and is stored in the reception buffer 347a. At this time, the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output transmission circuits GPX1 to GPX5 to transmit the parallel transmission data (e.g., parallel transmission data Dpsent), and the general-purpose input / output interface circuit 348a can selectively use the general-purpose input / output reception circuits GPE1 to GPE5 to receive the parallel reception data (e.g., parallel reception data Dprce).

[0037] In this embodiment, transmission multiplexers TMX1 to TMX3 each have a first input terminal that receives one of transmission data units DPX1 to DPX4 (corresponding to the first transmission data unit) from transmission buffer 345a, a second input terminal that receives another one of transmission data units DPX1 to DPX4 (corresponding to the second transmission data unit) adjacent to the first transmission data unit from transmission buffer 345a, and an output terminal coupled to one of general-purpose input / output transmission circuits GPX1 to GPX5.

[0038] Furthermore, transmission multiplexer TMX1 receives transmission data units DPX1 and DPX2 and is coupled to general-purpose input / output transmission circuit GPX2. Transmission multiplexer TMX2 receives transmission data units DPX2 and DPX3 and is coupled to general-purpose input / output transmission circuit GPX3. Transmission multiplexer TMX3 receives transmission data units DPX3 and DPX4 and is coupled to general-purpose input / output transmission circuit GPX4. General-purpose input / output transmission circuit GPX1 directly receives transmission data unit DPX1, and general-purpose input / output transmission circuit GPX5 directly receives transmission data unit DPX5. Based on the above, general-purpose input / output transmission circuits GPX1 to GPX5 are individually used to receive one of transmission data units DPX1 to DPX4, and data is allocated via transmission multiplexers TMX1 to TMX3.

[0039] Reception multiplexers RMX1 to RMX4 each have a first input terminal coupled to one of general-purpose input / output reception circuits GPE1 to GPE5 (corresponding to the first general-purpose input / output reception circuit), a second input terminal coupled to another one of general-purpose input / output reception circuits GPE1 to GPE5 (corresponding to the second general-purpose input / output reception circuit) adjacent to the first general-purpose input / output reception circuit, and an output terminal that provides one of reception data units DPE1 to DPE4.

[0040] Furthermore, the receive multiplexer RMX1 is coupled to the general-purpose input / output receive circuits GPE1 and GPE2 and provides a received data section DPE1. The receive multiplexer RMX2 is coupled to the general-purpose input / output receive circuits GPE2 and GPE3 and provides a received data section DPE2. The receive multiplexer RMX3 is coupled to the general-purpose input / output receive circuits GPE3 and GPE4 and provides a received data section DPE3. The receive multiplexer RMX4 is coupled to the general-purpose input / output receive circuits GPE4 and GPE5 and provides a received data section DPE4. Based on the above, the general-purpose input / output receive circuits GPE1 to GPE5 are individually used to receive one of the received data sections DPE1 to DPE4, and data is assigned via the receive multiplexers RMX1 to RMX4.

[0041] Based on the above, when a failure or error occurs in one of the general-purpose input / output transmission circuits GPX1 to GPX5, data can be transmitted by another general-purpose input / output transmission circuit. And when a failure or error occurs in one of the general-purpose input / output receive circuits GPE1 to GPE5, data can be received by another general-purpose input / output receive circuit.

[0042] In this embodiment, the general-purpose input / output interface circuit 348a further includes a plurality of transmission synchronization circuits T1 to T5 and a plurality of receive synchronization circuits R1 to R5. One of the general-purpose input / output transmission circuits GPX1 to GPX5 and one of the transmission synchronization circuits T1 to T5 are grouped as pins coupled to the same data transmission group (for example, data transmission groups GTX1 to GTX5). For example, the general-purpose input / output transmission circuit GPX1 and the transmission synchronization circuit T1 are grouped as pins coupled to the data transmission group GTX1, and the general-purpose input / output transmission circuit GPX2 and the transmission synchronization circuit T2 are grouped as pins coupled to the data transmission group GTX2. The remaining parts can also be estimated in this way and can be shown in the drawings, so they will not be repeated here.

[0043] One of the general-purpose input / output receiving circuits GPE1 to GPE5 and one of the reception synchronization circuits R1 to R5 are grouped as pins coupled to the same data reception group (for example, data reception groups GRX1 to GRX5). For example, the general-purpose input / output receiving circuit GPE1 and the reception synchronization circuit R1 are grouped as pins coupled to the data reception group GRX1, and the general-purpose input / output receiving circuit GPE2 and the reception synchronization circuit R2 are grouped as pins coupled to the data reception group GRX2. The remaining parts can also be estimated in this way and can be shown in the drawings, so they will not be repeatedly described here.

[0044] The transmission synchronization circuits T1 to T5 are used to transmit a transmission synchronization signal (usually a clock signal or a data ready signal) and to receive a reception synchronization signal (usually a clock signal or a data ready signal at the receiving end). The reception synchronization signals R1 to R5 are used to receive a transmission synchronization signal (usually a clock signal or a data ready signal at the transmitting end) and to transmit a reception synchronization signal (usually a clock signal or a data ready signal).

[0045] In an embodiment of the present invention, the semiconductor device (e.g., semiconductor device 100) further includes a channel controller 810. The channel controller 810 is coupled to the output terminals of each of the transmission multiplexers TMX1 to TMX3 coupled to one of the first input terminal and the second input terminal, and to the output terminals of each of the reception multiplexers RMX1 to RMX4 coupled to one of the first input terminal and the second input terminal, for controlling the output terminals of the transmission multiplexers TMX1 to TMX3 and the reception multiplexers RMX1 to RMX4 based on a channel test. Further, the channel controller 810 may first test the channel (i.e., between the connected pins / between the data transmission group and the data reception group) before starting communication, that is, test whether the channel is valid by transmitting and receiving data. If all channels are valid, data may be transmitted and received through a preset channel. If there is an invalid channel and it is within the fault tolerance range, data may be transmitted and received through a valid channel. Also, after communication, the channel controller 810 may perform data / channel handshaking by a transmission synchronization circuit (e.g., transmission synchronization circuits T1 to T5) and a reception synchronization circuit (e.g., reception synchronization circuits R1 to R5).

[0046] In an embodiment of the present invention, the channel controller 810 may be configured in the input / output controller 346, and the channel controllers 810 between various semiconductor devices (e.g., semiconductor devices 100 to 700) may be communicably connected to each other to perform a channel test.

[0047] FIG. 9 is a flowchart of a communication method for a plurality of semiconductor devices according to one embodiment of the present invention. Referring to FIG. 9, in this embodiment, the communication method for the semiconductor device includes the following steps. In step S110, at least one output data provided by at least one semiconductor component is reconfigured into at least one parallel transmission data by a scalable digital interface circuit. In step S120, at least one parallel transmission data is transmitted to an external semiconductor device via parallel transmission by at least one of a plurality of data transmission groups of a plurality of pins. In step S130, at least one parallel reception data is received from the external semiconductor device by at least one of a plurality of data reception groups of the pins. In step S140, at least one parallel reception data is reconfigured into at least one input data by a scalable digital interface circuit and provided to at least one semiconductor component. The order of steps S110, S120, S130, and S140 is illustrative, and embodiments of the present invention are not limited thereto. Details of steps S110, S120, S130, and S140 may be referred to the embodiments of FIGS. 1 to 8 and will not be repeated here.

[0048] In summary, the semiconductor device and the communication method of the semiconductor device according to the embodiment of the present invention transmit data via a large number of channels used for parallel transmission. At this time, in order to save interface power consumption and reduce the complexity and manufacturing cost of the interface circuit, the signal frequency can be further reduced. In addition, large-scale parallel transmission can improve the actual transmission performance while achieving low power consumption and a high-performance data transmission interface. Further, since signals are transmitted between semiconductor devices via a digital connection, the manufacturing process of the semiconductor device can be freely changed without affecting the connection method. Furthermore, it is not necessary to equalize the number of pins for transmitting signals between semiconductor devices, and the flexibility of mixed and matched transmission between semiconductor devices is improved.

[0049] Although the present invention has been disclosed as above in the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the claims.

Industrial Applicability

[0050] The semiconductor device using parallel transmission of the present invention and the communication method between semiconductor devices can be applied to a system for packaging a plurality of semiconductor devices.

Explanation of Reference Numerals

[0051] 10: Integrated circuit 100, 200, 100a, 200a, 100b, 200b, 300, 400, 500, 600, 700: Semiconductor device 110_1~110_n, 210_1~210_p: Memory unit 120_1~120_m, 220_1~220_q: Arithmetic unit 130, 230: Signal bus 140, 240, 340, 540: Scalable digital interface circuit 341, 541: Bus packaging circuit 342, 542: Address / data reconstruction register 343, 543_1~543_x: Transmission reassembler 344, 544_1~544_x: Reception reassembler 345, 345a, 545_1~545_x: Transmission buffer 346, 546_1~546_x: Input / output controller 347, 347a, 547_1~547_x: Reception buffer 348, 348a, 548_1~548_x: General-purpose input / output interface circuit 800: Substrate Din: Input data Dout: Output data DPE1~DPE4: Received data part Dprce: Parallel received data Dpsent: Parallel transmission data DPX1~DPX4: Transmission data section GPE1~GPE5: General-purpose input / output receiving circuit GPRX1, GPRX2, GPRX3, GPRX4, GPRX51, GPRX52, GPRX6, GPRX7: Receiver pins GPTX1, GPTX2, GPTX3, GPTX4, GPTX51, GPTX52, GPTX6, GPTX7: Transmitter pins GPX1~GPX5: General-purpose input / output transmission circuit R1~R5: Receiver synchronization circuit RMX1~RMX4: Receiver multiplexer T1~T5: Transmitter synchronization circuit RDL: Redistribution layer TMX1~TMX3: Transmitter multiplexer TVA: Through-silicon via S110, S120, S130, S140: Steps

Claims

1. A plurality of pins divided into a plurality of data transmission groups and a plurality of data reception groups; at least one semiconductor component providing at least one output data and receiving at least one input data; a scalable digital interface circuit coupled to at least one of the data transmitting groups, to at least one of the data receiving groups, and to the at least one semiconductor component; Including, The scalable digital interface circuit reconstructs the at least one output data into the at least one parallel transmission data for transmitting at least one parallel transmission data to an external semiconductor device by parallel transmission, receives at least one parallel reception data from the external semiconductor device by parallel transmission, and reconstructs the at least one parallel reception data into the at least one input data. Semiconductor device.

2. the at least one output data and the at least one input data each include at least one of an advanced high performance bus signal, an advanced extensible interface signal, a serial bus signal, and a parallel bus signal; The semiconductor device according to claim 1 .

3. the number of connections between the pins of the data transmission group and a plurality of data reception pins of the external semiconductor device is defined in units of a pin base of a single data transmission group, and is equal to or less than the smaller of the number of the pins of the data transmission group and the number of the data reception pins; The semiconductor device according to claim 1 .

4. when the transmission speed of the pins of the data transmission group is higher than the transmission speed of the data transmission group, the utilization rate of the connection portion between the pins of the data transmission group and the data receiving pins of the external semiconductor device becomes high; The semiconductor device according to claim 3 .

5. when the transmission speed of the at least one output data and the at least one input data increases, the utilization rate of the connection portion between the pin of the data transmission group and the data reception pin of the external semiconductor device increases; The semiconductor device according to claim 3 .

6. a signal bus coupled to the at least one semiconductor component and to the scalable digital interface circuit; Further comprising: The semiconductor device according to claim 1 .

7. The scalable digital interface circuit comprises: a bus package circuit coupled to the signal bus; an address / data reconfiguration register coupled to the bus package circuit; a transmit reassembler coupled to the address / data reconfiguration register; a receiving reassembler coupled to the address / data reconstructor register; a transmit buffer coupled to the transmit reassembler; a receive buffer coupled to the receive reassembler; a general purpose input / output interface circuit coupled to said transmit buffer and said receive buffer; an input / output controller coupled to the transmit buffer and the receive buffer and configured to control the transmit buffer and the receive buffer; Including, When the bus package circuit receives the at least one output data from the at least one semiconductor component via the signal bus, the at least one output data is temporarily stored in the address / data reconfiguration register, and then the transmit reassembler reconfigures the at least one output data into the at least one parallel transmit data for temporary storage in the transmit buffer, and the general-purpose input / output interface circuit transmits the at least one parallel transmit data temporarily stored in the transmit buffer to the external semiconductor device via at least one of the data transmit groups; When the general-purpose input / output interface circuit receives at least one parallel receive data from the external semiconductor device via at least one of the data receiving groups, the at least one parallel receive data is temporarily stored in the receive buffer, and then the receive reassembler reconstructs the at least one parallel receive data into the at least one input data for temporary storage in the address / data reconstructing register, and the bus package circuit provides the at least one input data temporarily stored in the address / data reconstructing register to the at least one semiconductor component via the signal bus. The semiconductor device according to claim 6.

8. The general-purpose input / output interface circuit includes: a plurality of general purpose input / output transmit circuits each configured to receive one of the at least one transmit data portion of the at least one parallel transmit data; a plurality of transmit synchronization circuits configured to send transmit synchronization signals and receive receive synchronization signals; a plurality of general purpose input / output receiving circuits each configured to receive one of the at least one receive data portion of the at least one parallel receive data via the pin; a plurality of receive synchronization circuits configured to receive the transmit synchronization signal and to send the receive synchronization signal; a plurality of transmit multiplexers, each having a first input for receiving a first transmit data portion of the at least one transmit data portion from the transmit buffer, a second input for receiving a second transmit data portion of the at least one transmit data portion adjacent to the first transmit data portion from the transmit buffer, and an output coupled to one of the general purpose input / output transmit circuits; a plurality of receive multiplexers each having a first input coupled to a first one of the general purpose input / output receiver circuits, a second input coupled to a second one of the general purpose input / output receiver circuits adjacent to the first one of the general purpose input / output receiver circuits, and an output providing said one of the at least one receive data portion; Including, each of the transmission synchronization circuit and the general purpose input / output transmission circuit is coupled to a plurality of pins of the same data transmission group in the data transmission group; each of said receiver synchronization circuit and said general purpose input / output receiver circuit is coupled to a plurality of pins of the same data receiver group of said data receiver groups; The semiconductor device according to claim 7.

9. a channel controller coupled to the transmit multiplexers and the receive multiplexers for controlling the output of each of the transmit multiplexers to be coupled to one of the first input and the second input based on a channel test, and for controlling the output of each of the receive multiplexers to be coupled to one of the first input and the second input. Further comprising: The semiconductor device according to claim 8.

10. the semiconductor device and the external semiconductor device include a chip, and the at least one semiconductor component includes at least one grain; The semiconductor device according to claim 1 .

11. A method for communication between semiconductor devices, comprising: reconfiguring at least one output data provided by the at least one semiconductor component into at least one parallel transmission data by a scalable digital interface circuit; Transmitting the at least one parallel transmit data to an external semiconductor device via parallel transmission over at least one of a plurality of data transmit groups of a plurality of pins; receiving at least one parallel receive data from the external semiconductor device by at least one of a plurality of data receiving groups of the pins; reconstructing the at least one parallel received data into at least one input data and providing the at least one input data to the at least one semiconductor component by the scalable digital interface circuit; Including, Communication methods.

12. the at least one output data and the at least one input data each include at least one of an advanced high performance bus signal, an advanced extensible interface signal, a serial bus signal, and a parallel bus signal; The communication method according to claim 11.

13. the number of connections between the pins of the data transmission group and a plurality of data reception pins of the external semiconductor device is defined in units of a pin base of a single data transmission group, and is equal to or less than the smaller of the number of the pins of the data transmission group and the number of the data reception pins; The communication method according to claim 11.

14. When the transmission speed of the pins of the data transmission group is higher than the transmission speed of the data transmission group, the utilization rate of the connection portion between the pins of the data transmission group and the data reception pins of the external semiconductor device is increased. Further comprising: The communication method according to claim 13.

15. When the transmission speed of the at least one output data and the at least one input data is increased, a utilization rate of a connection portion between the pin of the data transmission group and the data reception pin of the external semiconductor device is increased. Further comprising: The communication method according to claim 13.

16. the semiconductor device and the external semiconductor device include a chip, and the at least one semiconductor component includes at least one grain; The communication method according to claim 11.

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