Semiconductor device manufacturing method

Abstract

To manufacture and provide a semiconductor device which has a thin film transistor having stable electric characteristics and which has high reliability.SOLUTION: A manufacturing method of a semiconductor device having a thin film transistor which uses an oxide semiconductor film as a semiconductor layer including a channel formation region comprises the steps of: performing a heat treatment (heat treatment for dehydration or dehydrogenation) of increasing purity of the oxide semiconductor film to reduce moisture as an impurity; and reducing an impurity such as moisture which exists not only in the oxide semiconductor film but in a gate insulation layer to reduce an impurity such as moisture which exists in boundary faces among the oxide semiconductor film and films provided on and under and adjacent to the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) has been attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. There are many types of metal oxides and they are used for various purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, Homologous phase InGaO 3 (ZnO) m (m: natural number) is In, Ga, and Zn It is known as a multi-component oxide semiconductor having the above structure (Non-Patent Documents 2 to 4).

[0006] And, it has been confirmed that an oxide semiconductor composed of an In-Ga-Zn-based oxide as described above can be applied as a channel layer of a thin-film transistor (Patent Document 5, Non-Patent Documents 5 and 6).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0009] To fabricate a reliable semiconductor device having a thin film transistor with stable electrical characteristics is one of the problems to be solved.

Means for Solving the Problem

[0010] In a method of manufacturing a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor film, a heat treatment (heat treatment for dehydration or dehydrogenation) is performed to increase the purity of the oxide semiconductor film and reduce impurities such as moisture. Further, not only in the oxide semiconductor film but also impurities such as moisture present in the gate insulating layer are reduced, and impurities such as moisture present at the interface between the film provided in contact with the oxide semiconductor film and the oxide semiconductor film are reduced. In order to reduce impurities such as moisture, after forming the oxide semiconductor film, in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.) or under reduced pressure in a state where the oxide semiconductor film is exposed, a heat treatment at 200 ° C or higher, preferably 400 ° C or higher and 600 ° C or lower is performed to reduce the contained moisture in the oxide semiconductor film. After heating, it is gradually cooled to a range of room temperature or higher and less than 100 ° C in an inert gas atmosphere. Using an oxide semiconductor film in which the contained moisture in the film is reduced by heat treatment in an inert gas atmosphere of nitrogen or argon or under reduced pressure, the electrical characteristics of the thin film transistor are improved, and a thin film transistor having both mass productivity and high performance is realized. The conditions of the heating temperature were varied, and the results of measuring a plurality of samples heat-treated in a nitrogen atmosphere by temperature-programmed desorption analysis TD S (Thermal Desorption Spectroscopy) measurement are shown in FIGS. 2, 3, and 4.

[0011]

[0012]

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[0014] The temperature-programmed desorption analyzer is a device that detects and identifies gas components desorbed and generated from a sample during heating and temperature rise in a high vacuum. It can observe gases and molecules desorbed from the surface and inside of the sample. Using a temperature-programmed desorption analyzer manufactured by Electronic Science Co., Ltd. (product name: EMD-WA1 000S), the measurement conditions were a temperature rise of approximately 10 °C / min, and a vacuum degree of approximately 1×10 (Pa -7 ) during measurement. Also, the SEM voltage was set to 1500 V, the Dwell Time was set to 0. 2 [sec], and the number of channels used was 23. In addition, the ionization coefficient of H 2O was set to 1. 2 0, the fragmentation coefficient of H 2O was set to 0.805, the throughput coefficient of H 2 2O was set to 1.5 2 6, and the pumping rate of H 2O was set to 1.0. 2

[0015] Figure 2 is a graph showing the results of TDS comparing a sample of only a glass substrate (comparison sample) and a sample (Sample 1) on which an In-Ga-Zn-O-based polycrystalline film with a set film thickness of 50 nm (actual film thickness after etching was approximately 30 nm) was formed on the glass substrate. Figure 2 shows the results of measurement for H 2O, and since a peak is observed around 300 °C, it can be confirmed that impurities such as moisture (H 2 2O) are desorbed from the In-Ga-Zn-O-based polycrystalline film. 2

[0016] Also, Figure 3 shows a sample (Sample 1) on which an In-Ga-Zn-O-based polycrystalline film with a set film thickness of 50 nm was formed on a glass substrate, and an In-Ga-Zn- O-based polycrystalline film with a set film thickness of 50 nm was formed on a glass substrate, and then heat treatment was performed at a heating temperature of 350 °C for 1 hour in an air atmosphere. The tested sample (Sample 2) and the sample (Sample 3) that was heat-treated at a heating temperature of 350°C for 1 hour in a nitrogen atmosphere were compared, and it is a graph showing the TDS measurement results for H O. From the results in Fig. 3, in Sample 3, since the peak around 300°C is reduced compared to Sample 2 2, it can be confirmed that impurities such as moisture (H O) are desorbed by the heat treatment in a nitrogen atmosphere. Therefore, it can be seen that heat treatment in a nitrogen atmosphere reduces impurities such as moisture (H O) in the film more than in an air atmosphere. 2 O) and the like Also, Fig. 4 shows a sample (Sample 1) with an In-Ga-Zn-O-based polycrystalline film having a set film thickness of 50 nm formed on a glass substrate, a sample (Sample 4) that was heat-treated at a heating temperature of 250°C for 1 hour in a nitrogen atmosphere, a sample (Sample 3) that was heat-treated at a heating temperature of 350°C for 1 hour in a nitrogen atmosphere, a sample (Sample 5) that was heat-treated at a heating temperature of 450°C for 1 hour in a nitrogen atmosphere, and a sample (Sample 6) that was heat-treated at a heating temperature of 350°C for 10 hours in a nitrogen atmosphere. It is a graph showing the TDS measurement results for H O. From the results in Fig. 4, it can be seen that the higher the heating temperature in a nitrogen atmosphere, the more impurities such as moisture (H 2 O) desorbed from the In-Ga-Zn-O-based polycrystalline film are reduced.

[0017]

[0018] 2 O. It is a graph showing the TDS measurement results for O. From the results in Fig. 4, it can be seen that the higher the heating temperature in a nitrogen atmosphere, the more impurities such as moisture (H O) desorbed from the In-Ga-Zn-O-based polycrystalline film are reduced. 2 O) and the like It can be seen that impurities are reduced.

[0018] 2 O) such as impurities are desorbed, and a first peak indicating that moisture (H 2 O) and the like A second peak indicating the desorption of impurities can be confirmed.

[0019] Note that for a sample heat-treated at 450 °C in a nitrogen atmosphere, even if it is left at room temperature in the air for about one week, no water desorbing at 200 °C or higher is observed, and it has been found that the In-Ga-Zn-O-based polycrystalline film is stabilized by the heat treatment. week, and no water desorbing at 200 °C or higher is observed, and it has been found that the In-Ga-Zn-O-based polycrystalline film is stabilized by the heat treatment. Ga-Zn-O-based polycrystalline film is stabilized by the heat treatment.

[0020] Also, the heating temperature conditions in a nitrogen atmosphere were varied as 150 °C, 175 °C, 200 °C, 225 °C, 25 0 °C, 275 °C, 300 °C, 325 °C, 350 °C, 375 °C, 400 °C, 425 °C, 45 0 °C, and the results of measuring the carrier concentration for each are shown in FIG. 1.

[0021] FIG. 5(A) shows a perspective view of a physical property evaluation sample 510 for evaluating the physical properties (carrier concentration and Hall mobility) of an oxide semiconductor film (In-Ga-Zn-O-based polycrystalline film). The physical property evaluation sample 510 was fabricated, and Hall effect measurement was performed at room temperature to evaluate the carrier concentration and Hall mobility (hole mobility) of the oxide semiconductor film. The physical property evaluation sample 510 was fabricated by forming an insulating film 501 made of silicon oxynitride on a substrate 50 0, forming an oxide semiconductor film 502 of 10 mm × 1 0 mm to be evaluated thereon, and forming electrodes 503 to 506 each having a diameter of 1 mm thereon. The carrier concentration of the oxide semiconductor film obtained from the Hall effect measurement is shown in FIG. 1, the Hall mobility is shown in FIG. 5(B), and the conductivity is shown in FIG. 5(C). 0, forming an insulating film 501 made of silicon oxynitride on it, forming an oxide semiconductor film 502 of 10 mm × 1 0 mm to be evaluated thereon, and forming electrodes 503 to 506 each having a diameter of 1 mm thereon. The carrier concentration of the oxide semiconductor film obtained from the Hall effect measurement is shown in FIG. 1, the Hall mobility is shown in FIG. 5(B), and the conductivity is shown in FIG. 5(C). is shown in FIG. 1, the Hall mobility is shown in FIG. 5(B), and the conductivity is shown in FIG. 5(C).

[0022] From the results of FIGS. 1, 2, 3, and 4, at 250 °C or higher in the TDS measurement, impurities such as water (H O) desorb from the In-Ga-Zn-O-based polycrystalline film, and the carrier concentration 2 O) desorb from the In-Ga-Zn-O-based polycrystalline film, and the carrier concentration It is found that there is a relationship with the degree of fluctuation. Water molecules (H 2 2O) and other impurities are desorbed from the In-Ga-Zn-O based non-single crystal film, increasing the carrier concentration.

[0023] Also, by TDS measurement, in addition to H 2 2O, H, O, OH, H 2 , O 2 , N, N 2 , and Ar were measured respectively. For H 2 2O, H, O, and OH, distinct peaks were observed, but for H , O 2 , N, N 2 , and Ar, no peaks were observed. The sample 2 used was an In-Ga-Zn-O based non-single crystal film with a set film thickness of 50 nm formed on a glass substrate . The heating conditions were 250 °C for 1 hour in a nitrogen atmosphere, 350 °C for 1 hour in a nitrogen atmosphere , 350 °C for 10 hours in a nitrogen atmosphere, 450 °C for 1 hour. As a comparative example, an In-Ga-Zn-O based non-single crystal film without heat treatment and only the glass substrate were measured respectively. Fig. 37 shows the TDS results of H , Fig. 38 shows the TDS results of O, Fig. 39 shows the TDS results of OH , Fig. 40 shows the TDS results of H . Note that the oxygen concentration in the nitrogen atmosphere under the above heating conditions is 20 ppm or less. 2 . From the above results, it can be seen that by performing heat treatment on the In-Ga-Zn-O based non-single crystal film, mainly water (H

[0024] 2O) is released. That is, by heat treatment, desorption of water (H 2O) mainly occurs from the In-Ga-Zn-O based non-single crystal film. The measured values of TDS of H shown in Fig. 37, O shown in Fig. 2 38, and OH shown in Fig. 39 are those generated by the decomposition of water molecules. 2 2 2O), H shown in Fig. 37, O shown in Fig. 38, and OH shown in Fig. 39 are those generated by the decomposition of water molecules. This is affected. Note that the In-Ga-Zn-O-based polycrystalline film also contains hydrogen and OH. Since it is considered that these are also released concomitantly by the heat treatment.

[0025] In this specification, heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or heat treatment under reduced pressure is called heat treatment for dehydration or dehydrogenation. In this specification, only the desorption of H 2 as such is called dehydrogenation, right? Rather, for the sake of convenience, dehydration or dehydrogenation including the desorption of H, OH, etc. is called so.

[0026] By performing heat treatment under an inert gas, impurities (H 2 O) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed. After slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer, etc., to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in reliability.

[0027] The oxide semiconductor layer is made to have a lower resistance (the carrier concentration increases preferably to 1×10 18 / cm 3 or more) by heat treatment in a nitrogen atmosphere, and a low-resistance oxide semiconductor layer is obtained in this way. Then, when an oxide insulating film is formed in contact with the low-resistance oxide semiconductor layer, at least the region in contact with the oxide insulating film in the low-resistance oxide semiconductor layer is made to have a higher resistance ( the carrier concentration decreases, preferably to less than 1×10 18 / cm 3 and more preferably to 1×1 0 14 / cm 3 or less), and a high-resistance oxide semiconductor region can be obtained. For the semiconductor device During the process, it is important to increase or decrease the carrier concentration of the oxide semiconductor layer by heating, slow cooling, and forming an oxide insulating film in an inert gas atmosphere (or under reduced pressure). Also, by performing a heat treatment of dehydration or dehydrogenation on the oxide semiconductor layer, the oxide semiconductor layer becomes oxygen-deficient and is N-type (N , N etc.), and then, it can be said that the oxide semiconductor layer is made into an oxygen-excess state and is made into an I-type by forming an oxide insulating film. Further, when an oxide insulating film is formed on an In-Ga-Zn-O-based non-single crystal film, the carrier concentration shown by the dotted line 10 in FIG. 1 (1×10 / cm - / cm + or less) becomes or less. Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. In addition, the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film that blocks impurities such as moisture, hydrogen ions, and OH etc., and specifically, a silicon oxide film or a silicon oxynitride film is used. Furthermore, after forming an oxide insulating film as a protective film in contact with the low-resistance oxide semiconductor layer, a second heating may be performed. When a second heating is performed after forming an oxide insulating film as a protective film in contact with the oxide semiconductor layer, the variation in the electrical characteristics of the thin film transistor can be reduced. 14 / cm 3 or less). Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. In addition, the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film that blocks impurities such as moisture, hydrogen ions, and OH etc., and specifically, a silicon oxide film or a silicon oxynitride film is used.

[0028] In addition, the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film that blocks impurities such as moisture, hydrogen ions, and OH ions and OH - groups, and specifically, a silicon oxide film or a silicon oxynitride film is used. Furthermore, after forming an oxide insulating film as a protective film in contact with the low-resistance oxide semiconductor layer, a second heating may be performed. When a second heating is performed after forming an oxide insulating film as a protective film in contact with the oxide semiconductor layer, the variation in the electrical characteristics of the thin film transistor can be reduced.

[0029] Furthermore, after forming an oxide insulating film as a protective film in contact with the low-resistance oxide semiconductor layer, a second heating may be performed. When a second heating is performed after forming an oxide insulating film as a protective film in contact with the oxide semiconductor layer, the variation in the electrical characteristics of the thin film transistor can be reduced. In addition, the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film that blocks impurities such as moisture, hydrogen ions, and OH ions and OH groups, and specifically, a silicon oxide film or a silicon oxynitride film is used.

[0030] One aspect of the invention disclosed in this specification has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, and an insulating layer on the oxide semiconductor layer, and the above In the gate insulating layer, the oxide semiconductor layer, and the insulating layer, and at the interfaces between the gate insulating layer and the oxide semiconductor layer and between the oxide semiconductor layer and the insulating layer, the hydrogen concentration is a semiconductor device that is 3×10 3×10 20 cm -3 or less.

[0031] The oxide semiconductor layer may contain not only hydrogen contained therein but also various forms such as water (H 2 O), M-OH, and M-H. However, the average value or peak value of the hydrogen concentration, which is an absolute amount, is 3×10 3×10 20 cm -3 or less, preferably 1×10 20 cm -3 or less.

[0032] These concentration ranges are obtained by secondary ion mass spectrometry (SIMS) or are obtained based on the data thereof.

[0033] The above configuration solves at least one of the above problems.

[0034] Also, one aspect of the present invention for realizing the above structure is to form a gate electrode layer, form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, dehydrate or dehydrogenate the oxide semiconductor layer, and form a source electrode layer and a drain electrode layer on the dehydrated or dehydrogenated oxide semiconductor layer, and form an oxide insulating film in contact with a part of the oxide semiconductor layer on the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The dehydration or dehydrogenation is heating under a nitrogen atmosphere, or a rare gas atmosphere, or under reduced pressure. This is a method for manufacturing a semiconductor device.

[0035] Another aspect of the present invention for realizing the above structure is to form a gate electrode layer, and form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, heat the oxide semiconductor layer in an inert atmosphere to increase the carrier concentration, and then form a source electrode layer and a drain electrode layer on the oxide semiconductor layer with increased carrier concentration, and form an oxide insulating film in contact with a part of the heated oxide semiconductor layer on the gate insulating layer, the heated oxide semiconductor layer, the source electrode layer, and the drain electrode layer to reduce the carrier concentration. A method for manufacturing a semiconductor device is characterized by this. Note that after heating the oxide semiconductor layer in an inert atmosphere at a temperature of 400 °C or higher, it is characterized by performing slow cooling from the heating temperature to a temperature of room temperature or higher and lower than 100 °C.

[0036] Another aspect of the present invention for realizing the above structure is to form a gate electrode layer, and form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, heat the oxide semiconductor layer under reduced pressure to increase the carrier concentration, and then form a source electrode layer and a drain electrode layer on the oxide semiconductor layer with increased carrier concentration, and form an oxide insulating film in contact with a part of the heated oxide semiconductor layer on the gate insulating layer, the heated oxide semiconductor layer, the source electrode layer, and the drain electrode layer to reduce the carrier concentration. A method for manufacturing a semiconductor device is characterized by this.

[0037] In the configuration of each of the above manufacturing methods, the carrier concentration of the oxide semiconductor layer with increased carrier concentration is 1×10 18 / cm 3 or more. Also, the carrier concentration of the oxide semiconductor layer with the carrier concentration reduced by forming the oxide insulating film is less than 1×10 18 / cm 3 and preferably 1×1 0 14 / cm 3 is as follows.

[0038] The oxide semiconductor used in this specification is, for example, InMO 3 (ZnO) m (m > 0) is denoted, a thin film is formed, and a thin film transistor using the thin film as a semiconductor layer is manufactured. Further, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where Ga and Ni or Ga and Fe, etc., the above metal elements other than Ga are included. Also, in the above oxide semiconductor, in addition to the metal elements included as M, as impurities, there are those containing Fe, Ni, other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure denoted by InMO (ZnO) 3 (Z nO) m (m > 0), the oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an In-Ga- Zn-O-based non-single crystal film.

[0039] In addition to the above, as the oxide semiconductor applied to the oxide semiconductor layer, those of In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O-based, In-Zn-O-based, In-Ga-O-based, Sn-Zn-O-based, Al -Zn-O-based, In-O-based, Sn-O-based, Zn-O-based oxide semiconductors can also be applied. Also, silicon oxide may be included in the above oxide semiconductor layer. By including silicon oxide (SiOx (X > 0)) that inhibits crystallization in the oxide semiconductor layer, during the manufacturing process, the acid ​​​When heat treatment is performed after the formation of the oxide semiconductor layer, crystallization can be suppressed. The oxide semiconductor layer is preferably in an amorphous state, and may be partially crystallized.

[0040] The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. In order to make the oxide semiconductor layer of type I (intrinsic), it is effective to go through a dehydration or dehydrogenation process.

[0041] In addition, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for driving circuit protection on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor.

[0042] Also, the gate insulating layer and the oxide semiconductor film may be continuously processed (also referred to as continuous processing, in-situ process, continuous film formation) without being exposed to the atmosphere. By performing continuous processing without being exposed to the atmosphere, the interface between the gate insulating layer and the oxide semiconductor film is not contaminated by atmospheric components such as water and hydrocarbons or impurity elements floating in the atmosphere, and each laminated interface can be formed, so that variations in thin film transistor characteristics can be reduced.

[0043] In this specification, continuous processing means that during a series of processes from a first processing step performed by the PCVD method or the sputtering method to a second processing step performed by the PCVD method or the sputtering method, the atmosphere in which the substrate to be processed is placed is always in a vacuum or an inert gas without being exposed to a contaminated atmosphere such as the atmosphere. ​​​​​​​​​​​​It means that it is controlled in an atmosphere (nitrogen atmosphere or rare gas atmosphere). A continuous process is carried out to avoid reattachment of moisture and the like on the cleaned substrate to be processed and perform processes such as film formation can be achieved.

[0044] Performing a series of processes from the first processing step to the second processing step within the same chamber is considered to be within the scope of continuous processing in this specification. Also, when performing a series of processes from the first processing step to the second processing step in different chambers, after finishing the first processing step, transferring the substrate between chambers without exposure to the atmosphere and performing the second processing is also considered to be within the scope of continuous processing in this specification as well.

[0045] Note that between the first processing step and the second processing step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc., and it is still considered to be within the scope of continuous processing in this specification even so.

[0046] However, if a step using a liquid such as a cleaning step, wet etching, or resist formation is between the first processing step and the second processing step, it is not considered to be within the scope of continuous processing as defined in this specification and is so stated.

Advantages of the Invention

[0047] A thin film transistor having stable electrical characteristics can be fabricated and provided. Also, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be provided as well.

Brief Description of the Drawings

[0048]

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Embodiments for Carrying Out the Invention

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not to be construed as limited to the description of the embodiments shown below. Moreover, the present invention is not to be construed as limited to the description of the embodiments shown below. It is not to be construed as limited to the description of the embodiments shown below.

[0050] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 6 and 7.

[0051] FIG. 7(A) is a plan view of a thin film transistor 470 included in the semiconductor device, and FIG. 7(B) is a cross-sectional view taken along line C1-C2 in FIG. 7(A). The thin film transistor 470 is a bottom gate type thin film transistor, and on a substrate 400 which is a substrate having an insulating surface, a gate electrode layer 401, a gate insulating layer 402, a semiconductor layer 403, a source electrode layer or a drain electrode layer 4 05a, 405b are included. Further, an oxide insulating film 407 that covers the thin film transistor 470 and is in contact with the semiconductor layer 403 is provided. The semiconductor layer 403 made of an oxide semiconductor is subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) for reducing impurities such as moisture after at least forming the oxide semiconductor film,

[0052] and after being made to have a lower resistance (the carrier concentration increases, preferably 1×10 / cm or more), it is formed in contact with the oxide insulating film 407 to increase the resistance (the carrier concentration decreases, preferably 18 / cm 3 or more), and then it is formed in contact with the oxide insulating film 407 to increase the resistance (the carrier concentration decreases, preferably 1×10 18 / cm3 less than, more preferably 1×10 14 / cm 3 or less), and then an oxide semiconductor film can be used as a channel formation region.

[0053] Furthermore, after the process of desorbing impurities such as moisture (H 2 O) by heat treatment for dehydration or dehydrogenation, it is preferable to perform slow cooling in an inert atmosphere. After the heat treatment for dehydration or dehydrogenation and slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer and the like to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the reliability of the thin film transistor 470.

[0054] Also, not only within the semiconductor layer 403, but also within the gate insulating layer 402 and at the interfaces between the films provided in contact with the upper and lower sides and the semiconductor layer 403 which is an oxide semiconductor, specifically, the interface between the gate insulating layer 402 and the semiconductor layer 403, and the interface between the oxide insulating film 407 and the semiconductor layer 403, impurities such as moisture present are reduced.

[0055] Here, an example showing the results of the reliability test of the thin film transistor 470 will be described with reference to FIG. 41.

[0056] One of the methods for examining the reliability of a thin film transistor is a bias - thermal stress test (hereinafter referred to as a BT test). The BT test is a type of accelerated test, and it can evaluate the characteristic changes of a thin film transistor that occur due to long - term use in a short time. In particular, the amount of change in the threshold voltage of the thin film transistor before and after the BT test is an important indicator for examining reliability. The smaller the amount of change in the threshold voltage before and after the BT test, the higher the reliability.

[0057] ​​​​​​​​​ Specifically, the temperature of the substrate on which the thin film transistor is formed (substrate temperature) is maintained constant , the source and drain of the thin film transistor are set to the same potential, and a potential different from that of the source and drain is applied to the gate for a certain period of time. The substrate temperature may be appropriately set according to the test purpose. When the potential applied to the gate is higher than the same potential of the source and drain, it is called the +BT test, and when the potential applied to the gate is lower than the same potential of the source and drain, it is called the -BT test.

[0058] The test intensity of the BT test can be determined by the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film is determined by dividing the potential difference between the gate, source, and drain by the film thickness of the gate insulating film. For example, when the electric field strength applied to a gate insulating film with a film thickness of 100 nm is to be 2 MV / cm, the potential difference may be set to 20 V.

[0059] In this embodiment, the results of the BT test for three types of samples with heat treatments at 250 °C, 350 °C, and 450 °C in a nitrogen atmosphere, respectively, performed before the formation of the source and drain during the fabrication of the thin film transistor will be described.

[0060] In general, voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical positional energy) possessed by a unit charge in an electrostatic field at a certain point. However, in an electronic circuit, since the potential difference between a potential at a certain point and a reference potential (e.g., ground potential) is often shown as the potential at that certain point, in this specification, the difference between the potential at a certain point and the reference potential (e.g., ground potential) is taken as the potential at that certain point. ​ When shown as the potential at a certain point, unless otherwise specified, the potential at that certain point is also referred to as voltage.

[0061] The BT test was performed for both the +BT test and the -BT test with the substrate temperature at 150 °C, the electric field strength applied to the gate insulating film at 2 MV / cm, and the application time at 1 hour. and the application time at 1 hour.

[0062] First, the +BT test will be described. To measure the initial characteristics of the thin-film transistor to be subjected to the BT test, the substrate temperature was set to 40 °C, the source-drain voltage (hereinafter referred to as the drain voltage) was set to 10 V, and the source-gate voltage (hereinafter referred to as the gate voltage) was changed from -20 V to + 20 V, and the change characteristics of the source-drain current (hereinafter referred to as the drain current), that is, the Vg-Id characteristics, were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface, but if there are no particular problems, it may be measured at room temperature (25 °C). 20 V, and the change characteristics of the source-drain current (hereinafter referred to as the drain current), that is, the Vg-Id characteristics, were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface, but if there are no particular problems, it may be measured at room temperature (25 °C). 20 V, and the change characteristics of the source-drain current (hereinafter referred to as the drain current), that is, the Vg-Id characteristics, were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface, but if there are no particular problems, it may be measured at room temperature (25 °C). characteristics, that is, the Vg-Id characteristics, were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface, but if there are no particular problems, it may be measured at room temperature (25 °C). characteristics, that is, the Vg-Id characteristics, were measured. Here, the substrate temperature is set to 40 °C as a measure against moisture absorption on the sample surface, but if there are no particular problems, it may be measured at room temperature (25 °C). is also acceptable.

[0063] Next, after raising the substrate temperature to 150 °C, the potentials of the source and drain of the thin-film transistor were set to 0 V. Subsequently, a voltage was applied to the gate so that the electric field strength applied to the gate insulating film became 2 MV / cm. Here, since the thickness of the gate insulating film of the thin-film transistor was Next, after raising the substrate temperature to 150 °C, the potentials of the source and drain of the thin-film transistor were set to 0 V. Subsequently, a voltage was applied to the gate so that the electric field strength applied to the gate insulating film became 2 MV / cm. Here, since the thickness of the gate insulating film of the thin-film transistor was 100 nm, +20 V was applied to the gate and held for 1 hour. Here 100 nm, +20 V was applied to the gate and held for 1 hour. Here the application time was set to 1 hour, but it may be changed as appropriate according to the purpose.

[0064] Next, while voltages were still applied to the source, drain, and gate, the substrate temperature was lowered to 40 °C. At this time, if the application of the voltage is stopped before the substrate temperature has fully dropped, due to the influence of the residual heat Next, while voltages were still applied to the source, drain, and gate, the substrate temperature was lowered to 40 °C. At this time, if the application of the voltage is stopped before the substrate temperature has fully dropped, due to the influence of the residual heat Since the damage inflicted on the thin-film transistor during the BT test is restored, it is necessary to lower the substrate temperature while the voltage is being applied. After the substrate temperature reached 40 °C, the application of the voltage was terminated.

[0065] Next, the Vg-Id characteristics were measured under the same conditions as for the measurement of the initial characteristics, and the Vg-Id characteristics after the +BT test were obtained.

[0066] Subsequently, the -BT test will be described. The -BT test is also conducted in the same procedure as the +BT test, except that the voltage applied to the gate is set to -20 V after the substrate temperature is raised to 150 °C.

[0067] Note that in the BT test, it is important to use a thin-film transistor that has not undergone the BT test even once. For example, if a -BT test is performed using a thin-film transistor that has already undergone a +BT test, the -BT test results cannot be correctly evaluated due to the influence of the previously performed +BT test. The same applies when a +BT test is performed again using a thin-film transistor that has already undergone a +BT test. However, this does not apply when the BT test is deliberately repeated taking these influences into account.

[0068] Figures 41(A) to 41(C) show the Vg-Id characteristics of the thin-film transistor before and after the BT test. Figure 41(A) shows the BT test results of a thin-film transistor fabricated with the heat treatment performed before source and drain formation at 250 °C in a nitrogen atmosphere. Figure 41(B) shows the BT test results of a thin-film transistor fabricated with the heat treatment performed before source and drain formation at 350 °C in a nitrogen atmosphere, and Figure 41(C) shows the results of the heat treatment performed before source and drain formation. These are the BT test results of thin film transistors fabricated with a heat treatment at 450°C in a nitrogen atmosphere. This is the case.

[0069] In each figure, the horizontal axis represents the gate voltage (Vg), and the vertical axis represents the drain current (Id ) with a logarithmic scale with respect to the gate voltage. Also, the initial characteristics 711, 721, 731 are the Vg-Id characteristics of the thin film transistor before the +BT test, +BT712, 722, 732 are the Vg-Id characteristics of the thin film transistor after the +BT test, -BT713, 723, 733 are the Vg-Id characteristics of the thin film transistor after the -BT test. Note that the Vg-Id characteristics of the thin film transistor before the -BT test were almost the same as those before the +BT test, so they are not shown in the figure. They are not described in the figure.

[0070] According to FIGS. 41(A) to 41(C), compared with the initial characteristics 711, 721, 731, +BT712, 722, 732 show that the threshold voltage has changed in the positive direction, and -BT713, 723, 7 33 show that the threshold voltage has changed in the negative direction. Also, as shown in FIGS. 41(A) to 41(B) and FIGS. 41(B) to 41(C), as the temperature of the heat treatment performed before forming the source and drain is increased from 250°C to 350°C and then to 450°C, it can be seen that the amount of change in the threshold voltage after the +BT test becomes smaller. By setting the heat treatment temperature to 450°C or higher, at least the reliability in the +BT test can be improved. It can be seen that there is a relationship between the desorption of impurities such as moisture (H O) from the In-Ga-Zn-O based non-single crystal film and the results of the BT stress test.

[0071] 2 O) and others from the In-Ga-Zn-O based non-single crystal film and the results of the BT stress test.

[0072] Also, the source electrode layer or the drain electrode layer 4 that is in contact with the semiconductor layer 403 which is an oxide semiconductor layer 05a and 405b are made of a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium ium, and beryllium. Also, an alloy film or the like in which the above-described elements are combined may be laminated.

[0073] As the semiconductor layer 403 including the channel formation region, an oxide material having semiconductor characteristics may be used and, typically, an In-Ga-Zn-O-based non-single crystal film is used.

[0074] FIGS. 6(A) to (D) show cross-sectional views of the manufacturing process of the thin film transistor 470.

[0075] In FIG. 6(A), a gate electrode layer 401 is provided on a substrate 400 which is a substrate having an insulating surface An insulating film serving as an underlayer may be provided between the substrate 400 and the gate electrode layer 401. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 400 and is formed by a stacked structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film The material of the gate electrode layer 401 can be formed as a single layer or by lamination using a metal material such as molybdenum, titanium, chromium ium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. or an alloy material having these as main components For example, as a two-layer stacked structure of the gate electrode layer 401, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, or a two-layer structure in which a titanium nitride layer or tantalum nitride is stacked on a copper layer, a titanium nitride layer and molybdenum .

[0076] For example, as a two-layer stacked structure of the gate electrode layer 401, a two-layer stacked structure in which a molybdenum layer is stacked on an aluminum layer, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, or a two-layer structure in which a molybdenum layer is stacked on a copper layer, or a two-layer structure in which a titanium nitride layer or tantalum nitride is stacked on a copper layer, a titanium nitride layer and molybdenum layer are stacked, or a two-layer structure in which a titanium nitride layer or tantalum nitride is stacked on a copper layer, a titanium nitride layer and molybdenum It is preferable to form a two-layer structure in which a [Budden layer] is laminated. As a three-layer laminated structure, it is preferable to form a laminate in which a [tungsten layer or tungsten nitride], an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. A [tungsten layer or tungsten nitride], an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a [titanium nitride layer or a titanium layer] are preferably laminated.

[0077] Next, a gate insulating layer 402 is formed on the gate electrode layer 401.

[0078] The gate insulating layer 402 can be formed as a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer may be formed by plasma CVD using SiH, oxygen, and nitrogen as the film-forming gas. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be formed as a single layer or a laminate. For example, a silicon oxynitride layer may be formed by plasma CVD using SiH, oxygen, and nitrogen as the film-forming gas. 4 Using oxygen and nitrogen as the film-forming gas, a silicon oxynitride layer can be formed by plasma CVD. That is all that is necessary.

[0079] Next, an oxide semiconductor film is formed on the gate insulating layer 402.

[0080] Before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas to remove dust adhering to the surface of the gate insulating layer 402. Reverse sputtering is a method of forming plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to modify the surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas to remove dust adhering to the surface of the gate insulating layer 402. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to form plasma near the substrate and modify the surface. Reverse sputtering is a method of forming plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to modify the surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Also, the process may be performed in an atmosphere in which oxygen, NO, or the like is added to the argon atmosphere. Further, the process may be performed in an atmosphere in which Cl, CF, or the like is added to the argon atmosphere. Also, the process may be performed in an atmosphere in which oxygen, NO, or the like is added to the argon atmosphere. 2 Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Also, the process may be performed in an atmosphere in which oxygen, NO, or the like is added to the argon atmosphere. Also, the process may be performed in an atmosphere in which Cl, CF, or the like is added to the argon atmosphere. 2 Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Also, the process may be performed in an atmosphere in which oxygen, NO, or the like is added to the argon atmosphere. 4 Also, the process may be performed in an atmosphere in which Cl, CF, or the like is added to the argon atmosphere.

[0081] It should be noted that the terms in square brackets in the translation are placeholders that need to be filled with the correct terms according to the actual context.The oxide semiconductor film is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target. It can also be formed by sputtering in an atmosphere of a noble gas (typically argon), in an oxygen atmosphere, or in a mixed atmosphere of a noble gas (typically argon) and oxygen.

[0082] The gate insulating layer 402 and the oxide semiconductor film can be continuously formed without exposing them to the atmosphere. By continuously forming the film without exposing it to the atmosphere, each laminated interface can be formed without being contaminated by atmospheric components such as water and hydrocarbons and impurity elements floating in the air, so that variations in thin film transistor characteristics can be reduced.

[0083] The oxide semiconductor film is processed into an island-shaped oxide semiconductor layer 430 (first oxide semiconductor layer) by a photolithography process (see Fig. 6(A)).

[0084] After heat-treating the oxide semiconductor layer in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, it is gradually cooled in an inert atmosphere (see Fig. 6(B)). By heat-treating the oxide semiconductor layer 430 in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 430 can be removed.

[0085] In the heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably ​​​​​​ It is preferably set to 0.1 ppm or less.

[0086] In addition, the heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas, or a rapid heating method such as an LRTA (La mp Rapid Thermal Anneal) method using lamp light. It can be used.

[0087] Here, as one form of the heat treatment of the oxide semiconductor layer 430, a heating method using an electric furnace 601 will be described with reference to FIG. 14. FIG. 14 is a schematic diagram of the electric furnace 601. A heater 603 is provided outside the chamber 602 to heat the chamber 602. Also, inside the chamber 602, a susceptor 605 for mounting the substrate 604 is provided to carry the substrate 604 into or out of the chamber 602. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted or depressurized by the exhaust means 607. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less.

[0088] FIG. 14 is a schematic diagram of the electric furnace 601. A heater 603 is provided outside the chamber 602 to heat the chamber 602. Also, inside the chamber 602, a susceptor 605 for mounting the substrate 604 is provided to carry the substrate 604 into or out of the chamber 602. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted or depressurized by the exhaust means 607. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. provided, and the chamber 602 is heated. Also, inside the chamber 602, a susceptor 605 for mounting the substrate 604 is provided to carry the substrate 604 into or out of the chamber 602. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted or depressurized by the exhaust means 607. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. provided, and the substrate 604 is carried into or out of the chamber 602. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted or depressurized by the exhaust means 607. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. carried in or out. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted or depressurized by the exhaust means 607. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. 7 are provided. Gas is introduced into the chamber 602 by the gas supply means 606. Also, the inside of the chamber 602 is exhausted by the exhaust means 607, or the inside of the chamber 602 is depressurized. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. It is preferably that the temperature rising characteristic of the electric furnace 601 is 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less. It is preferably that the temperature falling characteristic of the electric furnace 601 is 0.1 ° C / min or more and 15 ° C / min or less.

[0089] The gas supply means 606 includes a gas supply source 611, a pressure regulating valve 612, a purifier 613, a mass flow controller 614, and a stop valve 615. In this embodiment, the gas supply source It is preferable to provide a purifier 613 between the gas supply source 611 and the chamber 602. By providing the purifier 613, it is possible to remove impurities such as water and hydrogen in the gas introduced from the gas supply source 611 into the chamber 602 by the purifier 613, and invasion of water, hydrogen, etc. into the chamber 602 can be reduced.

[0090] In this embodiment, nitrogen or a noble gas is introduced from the gas supply source 611 into the chamber 602, the inside of the chamber is made into a nitrogen or noble gas atmosphere, and in the chamber 602 heated to 200°C or higher and 600°C or lower, preferably 400°C or higher and 450°C or lower, by heating the oxide semiconductor layer 430 formed on the substrate 604, dehydration or dehydrogenation of the oxide semiconductor layer 430 can be performed.

[0091] Alternatively, under reduced pressure by an exhaust means, in the chamber 602 heated to 200°C or higher and 600°C or lower, preferably 400°C or higher and 450°C or lower, by heating the oxide semiconductor layer 430 formed on the substrate 604, dehydration or dehydrogenation of the oxide semiconductor layer 430 can be performed.

[0092] Next, the heater is turned off, and the chamber 602 of the heating device is gradually cooled. The oxide semiconductor layer is heat-treated and gradually cooled in an inert gas atmosphere or under reduced pressure, resulting in low resistance (the carrier concentration increases, preferably 1×10 / cm 18 or higher), and the oxide semiconductor layer 431 (the second oxide semiconductor layer) with low resistance can be obtained. 3 As a result, the reliability of the thin film transistor formed later can be improved.

[0093] ​​​​​

[0094] If the heat treatment is carried out under reduced pressure, an inert gas is passed through the sample to return it to atmospheric pressure after heating and then the sample is cooled. You can just ignore it.

[0095] After the substrate 604 in the chamber 602 of the heating device was cooled to 300° C., 4 may be moved to a room temperature atmosphere. This can reduce the cooling time of the substrate 604. can.

[0096] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, nitrogen or a rare gas is filled and the temperature is 200°C to 600°C. In the first chamber, which is preferably heated to 400° C. or higher and 450° C. or lower, The oxide semiconductor layer on the plate is heated. Then, the plate is transferred to a transfer chamber into which nitrogen or a rare gas is introduced. A second chamber filled with nitrogen or a noble gas and at a temperature below 100° C., preferably at room temperature. The substrate that has been subjected to the above heat treatment is then moved to the substrate 100 and cooled. can improve

[0097] In addition, the heat treatment of the oxide semiconductor layer under an inert gas atmosphere or under reduced pressure can form island-shaped oxide films. It is also possible to perform this treatment on the oxide semiconductor film before processing it into an oxide semiconductor layer. In that case, an inactive After heat treatment of the oxide semiconductor film under a gas atmosphere or reduced pressure, The substrate is then removed from the heating apparatus and a photolithography process is performed.

[0098] In addition, the state of the oxide semiconductor film after the heat treatment under an inert gas atmosphere or under reduced pressure is amorphous. It is preferable that the crystal is in a crystallized state, but it may be partially crystallized.

[0099] Next, a conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 431.

[0100] Examples of the material of the conductive film include an element selected from Al, Cr, Ta, Ti, Mo, and W, an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, and the like. When a heat treatment is performed after the formation of the conductive film, it is preferable that the conductive film has heat resistance to withstand this heat treatment. Since single Al has problems such as poor heat resistance and easy corrosion, it is formed in combination with a heat-resistant conductive material. Examples of the heat-resistant conductive material combined with Al include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, or a nitride containing the above-described element as a component.

[0101] The oxide semiconductor layer 431 and the conductive film are etched by an etching process to form the oxide semiconductor layer 432 and the source electrode layer or drain electrode layers 405a and 405b (see FIG. 6(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form the oxide semiconductor layer 432 having a groove portion (recess). An oxide insulating film 407 is formed over the oxide semiconductor layer 432 by a sputtering method. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used. An oxide insulating film 407 is formed over the oxide semiconductor layer 432 by a sputtering method. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used. Examples of the heat-resistant conductive material combined with Al include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, or a nitride containing the above-described element as a component. Examples of the heat-resistant conductive material combined with Al include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, or a nitride containing the above-described element as a component. Examples of the heat-resistant conductive material combined with Al include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, or a nitride containing the above-described element as a component. Examples of the heat-resistant conductive material combined with Al include an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc), an alloy containing the above-described element as a component, an alloy film formed by combining the above-described elements, or a nitride containing the above-described element as a component.

[0102] The oxide semiconductor layer 431 and the conductive film are etched by an etching process to form the oxide semiconductor layer 432 and the source electrode layer or drain electrode layers 405a and 405b (see FIG. 6(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form the oxide semiconductor layer 432 having a groove portion (recess). The oxide semiconductor layer 431 and the conductive film are etched by an etching process to form the oxide semiconductor layer 432 and the source electrode layer or drain electrode layers 405a and 405b (see FIG. 6(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form the oxide semiconductor layer 432 having a groove portion (recess). The oxide semiconductor layer 431 and the conductive film are etched by an etching process to form the oxide semiconductor layer 432 and the source electrode layer or drain electrode layers 405a and 405b (see FIG. 6(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form the oxide semiconductor layer 432 having a groove portion (recess). The oxide semiconductor layer 431 and the conductive film are etched by an etching process to form the oxide semiconductor layer 432 and the source electrode layer or drain electrode layers 405a and 405b (see FIG. 6(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form the oxide semiconductor layer 432 having a groove portion (recess).

[0103] An oxide insulating film 407 is formed over the oxide semiconductor layer 432 by a sputtering method. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used. OH - The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Specifically, a silicon oxide film or a silicon oxynitride film is used.

[0104] In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 407. The substrate temperature during film formation may be from room temperature to 300°C, and in this embodiment, it is 100°C. The film formation of the silicon oxide film by sputtering can be carried out in an atmosphere of a rare gas (typically argon), in an oxygen atmosphere, or in an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target may be used as the target. For example, using a silicon target, silicon oxide can be formed by sputtering in an atmosphere of oxygen and nitrogen.

[0105] When the oxide insulating film 407 is formed by sputtering or PCVD method in contact with the low-resistance oxide semiconductor layer 432, at least the region in the low-resistance oxide semiconductor layer 432 that contacts the oxide insulating film 407 becomes highly resistive (the carrier concentration decreases, preferably less than 1×10 / cm ), and a highly resistive oxide semiconductor region can be formed. During the manufacturing process of the semiconductor device, it is important to increase or decrease the carrier concentration of the oxide semiconductor layer by heating, slow cooling, and forming the oxide insulating film in an inert gas atmosphere (or under reduced pressure). 18 / cm 3 The oxide semiconductor layer 432 becomes a semiconductor layer 403 (the third oxide semiconductor layer) having a highly resistive oxide semiconductor region, and a thin film transistor 470 can be manufactured (see Fig. 6(D)). By performing heat treatment for the dehydration treatment or dehydrogenation treatment, impurities (H O, H, OH, etc.) contained in the oxide semiconductor layer are reduced, and after the carrier concentration is increased, slow cooling is performed. .

[0106] After the heat treatment for the dehydration treatment or dehydrogenation treatment is performed to reduce the impurities (H O, H, OH, etc.) contained in the oxide semiconductor layer and increase the carrier concentration, slow cooling is 2 performed. Perform. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer, etc., to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 470. It is possible.

[0107] Also, after forming the oxide insulating film 407, heat treatment (preferably 150°C or higher and less than 350°C) may be performed on the thin film transistor 470 in a nitrogen atmosphere or in an air atmosphere (in air). For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing this heat treatment, the oxide semiconductor layer 432 will be heated in a state of being in contact with the oxide insulating film 407, and variations in the electrical characteristics of the thin film transistor 470 can be reduced. This heat treatment (preferably 150°C or higher and less than 350°C) is not particularly limited as long as it is after the formation of the oxide insulating film 407, and can be performed without increasing the number of steps by combining it with other processes, for example, heat treatment during resin film formation or heat treatment for reducing the resistance of the transparent conductive film.

[0108] (Embodiment 2) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 8 and 9. The same parts or parts having similar functions, and processes, as in Embodiment 1 are performed in the same manner as in Embodiment 1, and repeated explanations are omitted.

[0109] FIG. 9(A) is a plan view of the thin film transistor 460 included in the semiconductor device, and FIG. 9(B) is a cross-sectional view taken along line D1 - D2 in FIG. 9(A). The thin film transistor 460 is a bottom-gate type thin film transistor, and on a substrate 450 which is a substrate having an insulating surface, a gate electrode layer 451, a gate insulating layer 452, a source electrode layer or a drain electrode layer 455a, 455b ​, and includes a semiconductor layer 453. Further, an oxide insulating film 457 that covers the thin film transistor 460 and contacts the semiconductor layer 453 is provided. The semiconductor layer 453 uses an In-Ga-Zn-O based non-single crystal film. An oxide insulating film 457 is provided which contacts the semiconductor layer 453 and covers the thin film transistor 460. The semiconductor layer 453 uses an In-Ga-Zn-O based non-single crystal film.

[0110] The thin film transistor 460 has a gate insulating layer 452 throughout the region including the thin film transistor 460, and a gate electrode layer 451 is provided between the gate insulating layer 452 and a substrate 450 which is a substrate having an insulating surface. On the gate insulating layer 452, source electrode layers or drain electrode layers 455a, 455b are provided. And, a semiconductor layer 453 is provided on the gate insulating layer 452 and the source electrode layers or drain electrode layers 455a, 455b. Also, although not shown, in addition to the source electrode layers or drain electrode layers 455a, 455b on the gate insulating layer 452, there is a wiring layer, and the wiring layer extends outside the outer peripheral portion of the semiconductor layer 453. The thin film transistor 460 has a gate insulating layer 452 throughout the region including the thin film transistor 460, and a gate electrode layer 451 is provided between the gate insulating layer 452 and a substrate 450 which is a substrate having an insulating surface. On the gate insulating layer 452, source electrode layers or drain electrode layers 455a, 455b are provided. And, a semiconductor layer 453 is provided on the gate insulating layer 452 and the source electrode layers or drain electrode layers 455a, 455b. Also, although not shown, in addition to the source electrode layers or drain electrode layers 455a, 455b on the gate insulating layer 452, there is a wiring layer, and the wiring layer extends outside the outer peripheral portion of the semiconductor layer 453. An oxide insulating film 457 is provided which contacts the semiconductor layer 453 and covers the thin film transistor 460. The semiconductor layer 453 uses an In-Ga-Zn-O based non-single crystal film. The semiconductor layer 453 made of an oxide semiconductor is subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) to reduce impurities such as moisture which are present after at least the formation of the oxide semiconductor film, and after making the resistance lower (the carrier concentration increases, preferably 1×10 / cm or more), by forming in contact with the oxide insulating film 457, the resistance is made higher (the carrier concentration decreases, preferably 1×10

[0111] / cm less than), and the oxide semiconductor film can be used as a channel formation region. The semiconductor layer 453 made of an oxide semiconductor is subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) to reduce impurities such as moisture which are present after at least the formation of the oxide semiconductor film, 18 / cm 3 and after making the resistance lower (the carrier concentration increases, preferably 1×10 / cm or more), by forming in contact with the oxide insulating film 457, the resistance is made higher (the carrier concentration decreases, preferably 1×10 18 / cm 3 less than), and the oxide semiconductor film can be used as a channel formation region. Furthermore, impurities such as moisture (H

[0112] O) are 2 removed by the heat treatment for dehydration or dehydrogenation, After going through the process of separation, it is preferable to perform slow cooling in an inert atmosphere. After heat treatment for dehydration or dehydrogenation and slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer or the like to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the reliability of the thin film transistor 460.

[0113] Also, as the source electrode layer or drain electrode layer 4 55a, 455b that is in contact with the semiconductor layer 453 which is the oxide semiconductor layer, use a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium and beryllium.

[0114] Cross-sectional views of the manufacturing process of the thin film transistor 460 are shown in FIGS. 8(A) to (D).

[0115] A gate electrode layer 451 is provided on a substrate 450 which is a substrate having an insulating surface. An insulating film serving as an underlayer film may be provided between the substrate 450 and the gate electrode layer 451. The underlayer film has a function of preventing the diffusion of impurity elements from the substrate 450, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film or a silicon nitride oxide film. The material of the gate electrode layer 451 can be formed by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten sten, aluminum, copper, neodymium, scandium or an alloy material mainly composed of these, either in a single layer or in a laminated manner.

[0116] A gate insulating layer 452 is formed on the gate electrode layer 451.

[0117] The gate insulating layer 452 is formed of a silicon oxide layer using a plasma CVD method, a sputtering method or the like. ​​​​​​, it is possible to form a single layer or a stack of a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. It can be done.

[0118] A conductive film is formed on the gate insulating layer 452 and processed into island-shaped source electrode layers or drain electrode layers 455a and 455b by a photolithography process (see Fig. 8(A)).

[0119] As materials for the source electrode layer or the drain electrode layer 455a and 455b, elements selected from Al, Cr, Ta , Ti, Mo, and W, alloys containing the above-described elements as components, or alloy films combining the above-described elements can be mentioned. Also, any alloy films combining the above-described elements may be stacked. It is also possible to stack any alloy films combining the above-described elements.

[0120] In addition, as materials for the source electrode layer or the drain electrode layer 455a and 455b, high-temperature-resistant molybdenum films that can withstand the heat treatment for dehydration or dehydrogenation to be performed later are preferably used. Also, on the molybdenum film, elements selected from the above Al, Cr, Ta, Ti, and W, alloys containing the above-described elements as components, or alloy films combining the above-described elements may be stacked. It is preferable to use a high-temperature-resistant molybdenum film that can withstand the heat treatment for dehydration or dehydrogenation to be performed later. Also, on the molybdenum film, elements selected from the above Al, Cr, Ta, Ti, and W, alloys containing the above-described elements as components, or alloy films combining the above-described elements may be stacked. It is also possible to stack alloy films and the like.

[0121] Next, an oxide semiconductor film is formed on the gate insulating layer 452 and the source electrode layer or the drain electrode layer 455a and 455b, and processed into an island-shaped oxide semiconductor layer 483 by a photolithography process (see Fig. 8(B)). (the first oxide semiconductor layer) (see Fig. 8(B)).

[0122] Since the oxide semiconductor layer 483 serves as a channel formation region, it is formed in the same manner as the oxide semiconductor film in Embodiment 1. It is formed in the same manner as the oxide semiconductor film in Embodiment 1.

[0123] Before forming the oxide semiconductor layer 483 by sputtering, argon gas is introduced to perform reverse sputtering to generate plasma and remove the dust adhering to the surface of the gate insulating layer 452. This is preferably done.

[0124] After performing heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer 483, it is gradually cooled in an inert atmosphere. As the heat treatment for dehydration or dehydrogenation, heat treatment is performed at 200°C or higher and 600°C or lower, preferably 400°C or higher and 450°C or lower, in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure. The oxide semiconductor layer 483 can be made to have a lower resistance (the carrier concentration increases, preferably 1×10 or more / cm 18 ), and can be made into a low-resistance oxide semiconductor layer 484 (the second oxide 3 semiconductor layer) (see Fig. 8(C)).

[0125] In the heat treatment for dehydration or dehydrogenation, it is preferable that nitrogen, or rare gases such as helium, neon, and argon, do not contain water, hydrogen, etc. Or, the purity of the rare gas such as nitrogen, or helium, neon, argon, etc., introduced into the heat treatment apparatus is 6N (99. 9999%) or higher, preferably 7N (99.99999%) or higher, (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0126] Also, the heat treatment of the oxide semiconductor layer in an inert gas atmosphere or under reduced pressure can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor film in an inert gas atmosphere or under reduced pressure, it is at room temperature or higher and lower than 100°C ​ Cool it slowly until it reaches the temperature, take out the substrate from the heating device, and perform a photolithography process.

[0127] Next, an oxide insulating film is formed by sputtering or PCVD method in contact with the oxide semiconductor layer 484. As the oxide insulating film 457. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 457. The substrate temperature during film formation may be from room temperature to 300 °C, and is set to 100 °C in this embodiment. When an oxide insulating film 457, which is a silicon oxide film, is formed in contact with the low-resistance oxide semiconductor layer 484 by sputtering, at least the region in contact with the oxide insulating film 457, which is a silicon oxide film, in the low-resistance oxide semiconductor layer 484 becomes highly resistive ( the carrier concentration decreases, preferably to less than 1×10 / cm ), and a highly resistive oxide semiconductor region can be formed. During the manufacturing process of the semiconductor device, it is important to increase or decrease the carrier concentration of the oxide semiconductor layer by heating, slow cooling, and forming an oxide insulating film in an inert gas atmosphere (or under reduced pressure). 18 / cm 3 The oxide semiconductor layer 484 becomes a semiconductor layer 453 (third oxide semiconductor layer) having a highly resistive oxide semiconductor region, and a thin film transistor 460 can be fabricated (see Fig. 8(D)). By performing a heat treatment for dehydration or dehydrogenation treatment, impurities (H O, H, OH, etc.) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer, and the reliability of the thin film transistor 460 can be improved. The oxide semiconductor layer 484 becomes a semiconductor layer 453 (third oxide semiconductor layer) having a highly resistive oxide semiconductor region, and a thin film transistor 460 can be fabricated (see Fig. 8(D)). (See Fig. 8(D).)

[0128] By performing a heat treatment for dehydration or dehydrogenation treatment, impurities (H O, H, OH, etc.) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed. 2 After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer, and the reliability of the thin film transistor 460 can be improved. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer, and the reliability of the thin film transistor 460 can be improved. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer, and the reliability of the thin film transistor 460 can be improved.

[0129] After forming the silicon oxide film to be the oxide insulating film 457, in a nitrogen atmosphere or in an air atmosphere (in air), a heat treatment (preferably 150 °C or higher and lower than 350 °C) may be performed on the thin film transistor 460. For example, a heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. The semiconductor layer 453 will be heated in a state of being in contact with the oxide insulating film 457, and performing this heat treatment can reduce the variation in the electrical characteristics of the thin film transistor 460. This heat treatment (preferably 150 °C or higher and lower than 350 °C) is not particularly limited as long as it is after the formation of the oxide insulating film 457 and can be performed without increasing the number of steps by combining it with other processes, for example, the heat treatment during resin film formation or the heat treatment for making the transparent conductive film have low resistance.

[0130] In addition, this embodiment can be freely combined with Embodiment 1.

[0131] (Embodiment 3) The manufacturing process of the semiconductor device including the thin film transistor will be described with reference to FIGS. 10 to 13.

[0132] In FIG. 10(A), a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used as the light-transmissive substrate 100.

[0133] Next, after forming a conductive layer over the entire surface of the substrate 100, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form wiring and electrodes (gate wiring including the gate electrode layer 101, capacitor wiring 108, and the first terminal 121). At this time, etching is performed so that at least a tapered shape is formed at the end of the gate electrode layer 101.

[0134] The gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are As the heat-resistant conductive material, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), scandium (Sc) are selected from the elements, or alloys containing the above-mentioned elements as components, or alloys combining the above-mentioned elements films, or formed of nitrides containing the above-mentioned elements as components.

[0135] Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode layer 101. The gate insulating layer 1 02 is formed using a sputtering method, a PCVD method, etc., and the film thickness is set to 50 to 250 nm.

[0136] For example, a silicon oxide film is used as the gate insulating layer 102 by a sputtering method and formed with a thickness of 100 nm Of course, the gate insulating layer 102 is not limited to such a silicon oxide film but other insulating films such as silicon oxynitride films, silicon nitride films, aluminum oxide, and tantalum oxide films may be used and formed as a single-layer or laminated structure composed of these materials.

[0137] Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed on the gate insulating layer 102. After plasma treatment, the In-Ga-Zn-O-based non-single crystal film is formed without exposing it to the atmosphere This is useful in that it does not attach dust or moisture to the interface between the gate insulating layer and the semiconductor film Here, an oxide semiconductor target containing In, Ga, and Zn with a diameter of 8 inches ( In-Ga-Zn-O-based oxide semiconductor target (In 2 O 3 :Ga 2 O 3 :ZnO = 1 :1:1)) is used, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, A direct current (DC) power supply of 0.5 kW, in an atmosphere of only oxygen, only argon, or argon and oxygen is used for film formation. When using a pulsed DC power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. The film thickness of the In-Ga-Zn-O-based non-single crystal film is set to 5 nm to 200 nm. As the oxide semiconductor film, an In-Ga-Zn-O-based non-single crystal film with a film thickness of 50 nm is formed by sputtering using an In-Ga-Zn-O-based oxide semiconductor target.

[0138] There are an RF sputtering method that uses a high-frequency power supply for the sputtering power supply and a DC sputtering method in sputtering methods. There is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0139] There is also a multi-source sputtering apparatus that can install multiple targets with different materials. The multi-source sputtering apparatus can deposit different material films in the same chamber in a laminated manner, or discharge multiple types of materials simultaneously in the same chamber to form a film.

[0140] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber or an ECR sputtering method that uses plasma generated using microwaves without using glow discharge.

[0141] As a film formation method using sputtering, there is a reactive sputtering method in which a chemical reaction is caused between the target substance and the sputtering gas component during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0142] Next, a second photolithography process is performed to form a resist mask, and the oxide semiconductor film is etched. For example, wet etching using a solution of phosphoric acid, acetic acid, and nitric acid is used to remove unnecessary portions to form the oxide semiconductor layer 133 (see Fig. 10(A)). Note that the etching here is not limited to wet etching, and dry etching may also be used.

[0143] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example chlorine (Cl 2 ), boron chloride (BCl 3 ), silicon chloride (SiCl 4 ), carbon tetrachloride (CC l 4 ) etc.) is preferred.

[0144] Also, a gas containing fluorine (fluorine-based gas, for example carbon tetrafluoride (CF 4 ), sulfur fluoride (SF 6 ), nitrogen fluoride (NF 3 ), trifluoromethane (CHF 3 ) etc.), hydrogen bromide (HBr ), oxygen (O 2 ), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0145] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode temperature, etc.) are appropriately adjusted so that etching can be performed into a desired processed shape.

[0146] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0147] In addition, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced. .

[0148] The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired processed shape.

[0149] Next, a heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor layer 133. The oxide semiconductor layer 133 is heat-treated in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then slowly cooled in an inert atmosphere.

[0150] The heat treatment is preferably performed at 200°C or higher. For example, a heat treatment is performed at 450°C for 1 hour in a nitrogen atmosphere. By this heat treatment in a nitrogen atmosphere, the oxide semiconductor layer 133 has a lower resistance (the carrier concentration increases, preferably 1×10 / cm 18 3 or more), and the conductivity increases. Therefore, an oxide semiconductor layer 134 with a lower resistance is formed (see Fig. 10(B)). The electrical conductivity of the oxide semiconductor layer 134 is preferably 1×10 S / cm or more and 1×10 -1 S / cm or less. 2 ​ Yes.

[0151] Next, a conductive film 132 made of a metal material is formed on the oxide semiconductor layer 134 by sputtering or vacuum evaporation method (see Fig. 10(C)).

[0152] As the material of the conductive film 132, elements selected from Al, Cr, Ta, Ti, Mo, and W, or an alloy containing the above-described elements as components, or an alloy film formed by combining the above-described elements, etc. can be mentioned. are.

[0153] When performing a heat treatment after forming the conductive film 132, it is preferable to give the conductive film heat resistance to withstand this heat treatment.

[0154] Next, a third photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the source electrode layer or drain electrode layers 105a, 105b, and the second terminal 122 (see Fig. 10(D)). As the etching method at this time, wet etching or dry etching is used. For example, when an aluminum film or an aluminum alloy film is used as the conductive film 132, wet etching using a solution mixed with phosphoric acid, acetic acid, and nitric acid can be performed. Also, the conductive film 132 can be etched by wet etching using aqueous ammonia peroxide (hydrogen peroxide: ammonia : water = 5:2:2) to form the source electrode layer or drain electrode layers 105a, 105b. In this etching process, a part of the exposed region of the oxide semiconductor layer 134 is also etched to become the semiconductor layer 135. Therefore, the semiconductor layer 13 5 between the source electrode layer or drain electrode layers 105a, 105b becomes a region with a thin film thickness. In Fig. 10(D), the source electrode layer or drain electrode layer 5 is Etching of 105a, 105b, and the semiconductor layer 135 is performed at once by dry etching Therefore, the ends of the source electrode layer or drain electrode layer 105a, 105b and the semiconductor layer 135 coincide and have a continuous structure.

[0155] Also, in this third photolithography process, the second terminal 122 made of the same material as the source electrode layer or drain electrode layer 1 05a, 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the source wiring (source wiring including the source electrode layer or drain electrode layer 105a, 105b).

[0156] Also, when using a resist mask having a plurality (typically two types) of regions with different thicknesses formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost can be reduced.

[0157] Next, the resist mask is removed, and a protective insulating layer 107 covering the gate insulating layer 102, the oxide semiconductor layer 135, and the source electrode layer or drain electrode layer 105a, 105b is formed. The protective insulating layer 107 uses a silicon oxynitride film formed by the PCVD method. By providing the silicon oxynitride film, which is the protective insulating layer 107, in contact with the exposed region of the oxide semiconductor layer 135 provided between the source electrode layer or drain electrode layer 105a, 105b, the region of the oxide semiconductor layer 135 in contact with the protective insulating layer 107 becomes highly resistive (the carrier concentration decreases, preferably less than 1 ×10 / cm 18 3 ), and a semiconductor layer 103 having a channel formation region with increased resistivity can be formed (see Fig. 11(A)).

[0158] Next, before the protective insulating layer 107 is formed, heat treatment may be performed in an oxygen atmosphere. The heat treatment may be performed at a temperature of 150° C. or higher and lower than 350° C. in an atmosphere containing oxygen.

[0159] Next, after the protective insulating layer 107 is formed, heat treatment may be performed. The heat treatment may be carried out in an air or nitrogen atmosphere at a temperature of 150° C. or higher and lower than 350° C. When this is done, the semiconductor layer 103 is heated in a state where it is in contact with the protective insulating layer 107. Furthermore, the semiconductor layer 103 is made to have a high resistance, thereby improving the electrical characteristics of the transistor and This heat treatment (preferably at 150°C or higher and less than 350°C) can reduce the variation. ) is not particularly limited as long as it is after the formation of the protective insulating layer 107, and may be performed in other steps, such as a resin film formation step. This process can be used in combination with the heat treatment for the deposition and the heat treatment for reducing the resistance of the transparent conductive film, reducing the number of processes. This can be done without increasing it.

[0160] Through the above steps, the thin film transistor 170 can be fabricated.

[0161] Next, a fourth photolithography process is performed to form a resist mask, and a protective insulating layer 10 7 and the gate insulating layer 102 are etched to form a contact that reaches the drain electrode layer 105b. Also, a hole 125 is formed by etching here, which reaches the second terminal 122. A contact hole 127 and a contact hole 126 reaching the first terminal 121 are also formed. The cross section at this stage is shown in Figure 11(B).

[0162] Next, after removing the resist mask, a transparent conductive film is formed. Indium oxide (In 2 O 3 ) and indium tin oxide alloy (In2 O 3 ―SnO 2 (abbreviated as ITO, etc.) is formed by using a sputtering method, a vacuum evaporation method, or the like. In this way The etching treatment of such a material is performed with a hydrochloric acid-based solution. However, in particular, the etching of ITO tends to generate residues. Therefore, in order to improve the etching processability, indium zinc oxide alloy gold (In 2 O 3 ―ZnO) may be used. Also, when performing a heat treatment to reduce the resistance of the transparent conductive film, the semiconductor layer 103 can be made highly resistive to improve the electrical characteristics of the transistor and at the same time, it can serve as a heat treatment to reduce the variation in electrical characteristics.

[0163] Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 110.

[0164] Also, in this fifth photolithography process, using the gate insulating layer 102 and the protective insulating layer 107 as dielectrics, a holding capacitor is formed between the capacitor wiring 108 and the pixel electrode layer 110.

[0165] Also, in this fifth photolithography process, the first terminal 121 and the second terminal 1 22 are covered with a resist mask to leave the transparent conductive films 128 and 129 formed on the terminal portion. The transparent conductive films 128 and 129 serve as electrodes or wirings used for connection to the FPC. The transparent conductive film 128 formed on the first terminal 121 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 is a terminal electrode for connection that functions as an input terminal of the source wiring.

[0166] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in Fig. 11(C). Note that the plan view at this stage corresponds to Fig. 12.

[0167] Also, Figs. 13(A1) and 13(A2) respectively show the plan view and cross-sectional view of the gate wiring terminal portion at this stage. Fig. 13(A1) corresponds to the cross-sectional view along the line C1-C2 in Fig. 13(A2). In Fig. 13(A1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in Fig. 13(A1 ), in the terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode layer 153 formed of the same material as the source wiring overlap via the gate insulating layer 152 and are electrically connected by the transparent conductive film 155. Note that the portion where the transparent conductive film 128 shown in Fig. 11(C) is in contact with the first terminal 121 corresponds to the portion where the transparent conductive film 155 in Fig. 13(A1) is in contact with the first terminal 151. Also, Figs. 13(B1) and 13(B2) respectively show the plan view and cross-sectional view of a source wiring terminal portion different from the source wiring terminal portion shown in Fig. 11(C). Also, Fig. 13( ) B1) corresponds to the cross-sectional view along the line F1-F2 in Fig. 13(B2). In Fig. 13(B1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in Fig. 13(B1), in the terminal portion, an electrode layer 156 formed of the same material as the gate wiring overlaps via the gate insulating layer 152 below the second terminal 150 that is electrically connected to the source wiring. The electrode layer 156 is not electrically

[0168] connected to the second terminal 150. connected to the second terminal 150. B1) corresponds to the cross-sectional view along the line F1-F2 in Fig. 13(B2). In Fig. 13(B1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in Fig. 13(B1), in the terminal portion, an electrode layer 156 formed of the same material as the gate wiring overlaps via the gate insulating layer 152 below the second terminal 150 that is electrically connected to the source wiring. The electrode layer 156 is electrically connected to the second terminal 150. connected to the second terminal 150. formed of the same material as the gate wiring overlaps via the gate insulating layer 152 below the second terminal 150 that is electrically connected to the source wiring. The electrode layer 156 is electrically connected to the second terminal 150. The electrode layer 156 is not electrically connected to the second terminal 150, and is set to a different potential, for example, a floating potential. If you set it to 0V, capacitance for noise prevention or static electricity prevention The second terminal 150 is connected to the protection insulating layer 154 via the It is electrically connected to the transparent conductive film 155 .

[0169] A plurality of gate lines, source lines, and capacitance lines are provided according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0170] In this way, five photolithography steps were performed using five photomasks to produce the bottom A pixel thin film having a thin film transistor 170 which is a gate-type staggered thin film transistor. The film transistor and storage capacitor can then be completed. By forming a pixel section by correspondingly arranging them in a matrix, an active matrix type It can be one of the substrates for manufacturing a display device. Such a substrate is called an active matrix substrate.

[0171] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. It is provided in the section. This fourth terminal is a terminal for setting the common electrode to a fixed potential, such as GND, 0V, etc.

[0172] Also, a storage capacitor may be formed by overlapping the pixel electrodes with the gate wiring of adjacent pixels, the protective insulating layer, and the gate insulating layer without providing a capacitance wiring.

[0173] In an active matrix type liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, so that the optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as a display pattern.

[0174] In the video display of a liquid crystal display device, there is a problem that afterimages occur because the response of the liquid crystal molecules themselves is slow, or blurring of the video occurs. To improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion in which full black display is performed every other frame.

[0175] Also, the video characteristics may be improved by making the normal vertical synchronization frequency 1.5 times, preferably 2 times or more, using a driving technique called so-called double-speed driving.

[0176] Also, to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as a backlight, and there is also a driving technique in which each light source constituting the surface light source is independently driven by intermittent lighting within one frame period. As the surface light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. Independently ​​​​​​​​​​​​Since a plurality of LEDs can be controlled, the light emission timing of the LEDs can also be synchronized with the switching timing of the optical modulation of the liquid crystal layer. Because this driving technique can partially turn off the LEDs, it is possible to reduce power consumption, especially in the case of video displays where the proportion of the black display area occupying one screen is large. By combining these driving techniques, the display characteristics such as the video characteristics of the liquid crystal display device can be improved compared to the prior art. The n-channel type transistor disclosed in this specification uses an oxide semiconductor film for the channel formation region and has good dynamic characteristics, so these driving techniques can be combined. Also, when manufacturing a light-emitting display device, one electrode (also called a cathode) of the organic light-emitting element is set to a low power supply potential, such as GND, 0V, etc. Therefore, a fourth terminal for setting the cathode to a low power supply potential, such as GND, 0V, etc. is provided at the terminal portion. Also, when manufacturing a light-emitting display device, a power supply line is provided in addition to the source wiring and the gate wiring. Accordingly, a fifth terminal electrically connected to the power supply line is provided at the terminal portion.

[0177] Moreover, when manufacturing a light-emitting display device, a partition using an organic resin layer may be provided between the organic light-emitting elements. In that case, since the organic resin layer is heat-treated, it is possible to also serve as a heat treatment for increasing the resistance of the semiconductor layer 103 to improve the electrical characteristics of the transistor and reduce the variation in the electrical characteristics.

[0178]

[0179]

[0180]

[0181] By forming with a thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, by heat treatment for dehydration or dehydrogenation, moisture which is an impurity etc. is reduced to increase the purity of the oxide semiconductor film, so even without using a special sputtering apparatus with a lowered dew point in the film formation chamber or an ultra-high purity oxide semiconductor target, a semiconductor device having a thin film transistor with good electrical

[0182] characteristics and high reliability can be manufactured. Since the semiconductor layer in the channel formation region is a high-resistance region, the electrical characteristics of the thin film transistor are stabilized, and an increase in the off-current etc. can

[0183] be prevented. Therefore, it becomes possible to obtain a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0184] (Embodiment 4) In a display device which is an example of a semiconductor device, an example of manufacturing a thin film transistor to be disposed in a pixel portion and at least a part of a drive circuit on the same

[0185] substrate will be described below. The thin film transistor to be disposed in the pixel portion is formed according to Embodiments 1 to 3. Further, since the thin film transistors shown in Embodiments 1 to 3 are n-channel type TFTs, a part of the drive circuit which can be configured by n-channel type TFTs in the drive circuit is

[0186] formed on the same substrate as the thin film transistor in the pixel portion. shown in 0(A). The display device shown in Fig. 20(A) has a pixel portion 5301 having a plurality of pixels with display elements on a substrate 5300, a scanning line driving circuit 5302 for selecting each pixel, and a signal line driving circuit 5303 for controlling the input of a video signal to the selected pixels.

[0187] The pixel portion 5301 is connected to the signal line driving circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction from the signal line driving circuit 5303, and is connected to the scanning line driving circuit 5302 by a plurality of scanning lines G1 to Gn (not shown) extending in the row direction from the scanning line driving circuit 5302, and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

[0188] Also, the thin film transistors shown in Embodiments 1 to 3 are n-channel type TFTs, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to Fig. 21.

[0189] The signal line driving circuit shown in Fig. 21 includes a driver IC 5601, a switch group 5602_1 to 56 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 56 21_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M has a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

[0190] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, and the third wiring 5613 ​​​​​and connected to wirings 5621_1 to 5621_M. And each of switch groups 5602_1 to 5602_M is connected to a first wiring 5611, a second wiring 5612, a third wiring 561 3 and wirings 5621_1 to 5 621_M corresponding to each of switch groups 5602_1 to 5602_M. And each of wirings 5621_1 to 5621_M is a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film tran sistor 5603c and is connected to three signal lines. For example, the wiring 5621 _J (any one of wirings 5621_1 to 5621_M) in the J-th column is the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in switch group 5602 and is connected to signal lines Sj-1, signal line Sj, and signal line S j + 1.

[0191] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0192] Note that the driver IC 5601 is preferably formed on a single crystal substrate. Furthermore , it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_ M may be connected via an FPC or the like.

[0193] Next, the operation of the signal line driving circuit shown in FIG. 21 will be described with reference to the timing chart of FIG. 22. Note that the timing chart of FIG. 22 shows the timing chart when the scanning line Gi in the i-th row is selected. Furthermore, the selection period of the scanning line Gi in the i-th row is shown. ​​​is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driving circuit in FIG. 21 operates in the same manner as in FIG. 22 even when scanning lines of other rows are selected.

[0194] Note that the timing chart in FIG. 22 shows the case where the wiring 5621_J in the J column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c.

[0195] Note that the timing chart in FIG. 22 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J column.

[0196] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Furthermore, during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, Let the video signals input to J be Data_j-1, Data_j, and Data_j+ 1, respectively.

[0197] As shown in FIG. 22, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. In the second sub-selection period T2 , the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c.

[0198] From the above, the signal line driving circuit in FIG. 21 divides one gate selection period into three, so that a video signal can be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 21 can reduce the number of connections between the substrate on which the driver IC5601 is formed and the substrate on which the pixel portion is formed to about 1 / 3 compared to the number of signal lines. By reducing the number of connections to about 1 / 3, the signal line driving circuit in FIG. 21 can improve reliability, yield, etc.

[0199] ​ Note that, as shown in FIG. 21, if one gate selection period is divided into a plurality of sub-selection periods, and video signals are input from one wiring to each of the plurality of signal lines in each of the plurality of sub-selection periods, the arrangement, number, driving method, etc. of the thin film transistors are not limited. For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 23, in the pre-charge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the pre-charge voltage Vp input to the wiring 5621_J is applied to the first thin film transistor 5603a, the second thin film transistor

[0200] For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods. For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, wiring for controlling the thin film transistors and the thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods.

[0201] As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As another example, as shown in the timing chart of FIG. 23, one selection period may be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the timing chart of FIG. 23 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. Via the transistor 5603b and the third thin-film transistor 5603c, they are respectively input to the signal line S j-1, the signal line Sj, and the signal line Sj+1. In the first sub-selection period T1, the first thin-film transistor 5603a is turned on, and the second thin-film transistor 5603b and the third thin-film transistor 5603c are turned off. At this time, the D ata_j-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first thin-film transistor 5603a . In the second sub-selection period T2, the second thin-film transistor 5603b is turned on, and the first thin-film transistor 5603a and the third thin-film transistor 5603c are turned off. At this time, the Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin-film transistor 5603 b. In the third sub-selection period T3, the third thin-film transistor 5603c is turned on, and the first thin-film transistor 5603a and the second thin-film transistor 5603 b are turned off. At this time, the Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin-film transistor 5603c.

[0202] From the above, the signal line driving circuit of FIG. 21 to which the timing chart of FIG. 23 is applied can pre-charge the signal line by providing a pre-charge period before the sub-selection period, so that the video signal can be written to the pixel at high speed. In FIG. 23, for those similar to FIG. 22, common reference numerals are used, and detailed descriptions of the same parts or parts having the same functions are omitted.

[0203] Also, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register ​​​is provided. If necessary, the scanning line driving circuit may include a level shifter, a buffer, a switch, etc., or may be configured with only a shift register. In the scanning line driving circuit, a selection signal is generated when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The gates of the transistors of the pixels for one line are connected to the scanning line. And since the transistors of the pixels for one line must be turned on all at once, a buffer that can pass a large current is used.

[0204] A form of the shift register used in a part of the scanning line driving circuit will be described with reference to FIGS. 24 and 25.

[0205] FIG. 24 shows the circuit configuration of the shift register. The shift register shown in FIG. 24 is composed of a plurality of flip-flops 5701_1 to 5701_n. Also, a first clock signal, a second clock signal, a start pulse signal, and a reset signal are input and operate.

[0206] The connection relationship of the shift register in FIG. 24 will be described. In the shift register of FIG. 24, the i-th flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 25 connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in FIG. 25 connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in FIG. 25 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 25 connected to the fifth wiring 5715.

[0207] Also, the fourth wiring 5504 shown in FIG. 25 is connected to the second wiring 5712 in the odd-numbered flip-flops and to the third wiring 5713 in the even-numbered flip-flops, and the fifth wiring 5505 shown in FIG. 25 is connected to the fourth wiring 5714.

[0208] However, the first wiring 5501 shown in FIG. 25 of the first-stage flip-flop 5701_1 is the first wiring 5711, and the second wiring 5502 shown in FIG. 25 of the nth-stage flip-flop 5701_n is connected to the sixth wiring 5716.

[0209] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power line and the second power line, respectively.

[0210] Next, the details of the flip-flop shown in FIG. 24 are shown in FIG. 25. The flip-flop shown in FIG. 25 has a first thin-film transistor 5571, a second thin-film transistor 5572, a third thin-film transistor 5573, a fourth thin-film transistor 5574, a fifth thin-film transistor 5575, a sixth thin-film transistor 5576, a seventh thin-film transistor 5577, and an eighth thin-film transistor 5578. Note that the first thin-film transistor 5571, the second thin-film transistor 5572, the third thin-film transistor 5573, the fourth thin-film transistor 5574, the fifth thin-film transistor 5575, the sixth thin-film transistor 5576, the seventh thin-film transistor 5577, and the eighth thin-film transistor 5578 are n-channel type a transistor that becomes conductive when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vth). It is assumed that it enters a conductive state when this condition is met.

[0211] Next, the connection configuration of the flip - flop shown in FIG. 24 is described as follows.

[0212] The first electrode (either the source electrode or the drain electrode) of the first thin - film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin - film transistor 5571 is connected to the third wiring 5503.

[0213] The first electrode of the second thin - film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the second thin - film transistor 5572 is connected to the third wiring 5503.

[0214] The first electrode of the third thin - film transistor 5573 is connected to the fifth wiring 5505, and the third electrode of the third thin - film transistor 5573 is connected to the gate electrode of the second thin - film transistor 5572 and the gate electrode of the third thin - film transistor 5573 is connected to the fifth wiring 5505 as well.

[0215] The first electrode of the fourth thin - film transistor 5574 is connected to the sixth wiring 5506, and the fourth electrode of the fourth thin - film transistor 5574 is connected to the gate electrode of the second thin - film transistor 5572 and the gate electrode of the fourth thin - film transistor 5574 is connected to the gate electrode of the first thin - film transistor 5 571.

[0216] The first electrode of the fifth thin - film transistor 5575 is connected to the fifth wiring 5505, and the fifth The second electrode of the thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 Thereby.

[0217] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth The second electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0218] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh The second electrode of the thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 Thereby. The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 and the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550 1.

[0219] Note that the connection points of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 , the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 are defined as a node 5543. Further, the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the second electrode of the fourth thin film transistor 5574, The connection point of the gate electrode of the sixth thin film transistor 5576 and the second electrode of the eighth thin film transistor 5578 is defined as node 5544.

[0220] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0221] Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiments 1 to 3. Since the mobility of the n-channel type TFTs shown in Embodiments 1 to 3 is high, it is possible to increase the driving frequency of the driving circuit. Also, since the parasitic capacitance of the n-channel type TFTs shown in Embodiments 1 to 3 is reduced, the frequency characteristics (referred to as f characteristics) are high. For example, the scanning line driving circuit using the n-channel type TFTs shown in Embodiments 1 to 3 can operate at high speed, so it is possible to increase the frame frequency or realize black screen insertion.

[0222] Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or arranging a plurality of scanning line driving circuits, a higher frame frequency can be realized. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Also, a plurality of ​​​​​​​​​​​​When a signal is output to the same scanning line by the scanning line driving circuit, it is advantageous for the size reduction of the display device. It is.

[0223] Also, when manufacturing an active matrix light-emitting display device which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 20(B). When a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 20(B). When a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 20(B). 0(B).

[0224] The light-emitting display device shown in FIG. 20(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5403 for controlling the input of a video signal to the selected pixel. The light-emitting display device shown in FIG. 20(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5403 for controlling the input of a video signal to the selected pixel. The light-emitting display device shown in FIG. 20(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel, and a signal line driving circuit 5403 for controlling the input of a video signal to the selected pixel. 403.

[0225] When the video signal input to the pixel of the light-emitting display device shown in FIG. 20(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off. Therefore, gradation display can be performed using the area gradation method or the time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. When the video signal input to the pixel of the light-emitting display device shown in FIG. 20(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off. Therefore, gradation display can be performed using the area gradation method or the time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. When the video signal input to the pixel of the light-emitting display device shown in FIG. 20(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off. Therefore, gradation display can be performed using the area gradation method or the time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light.

[0226] Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time gradation method than a liquid crystal element. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel emits light in each sub-frame period. Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time gradation method than a liquid crystal element. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel emits light in each sub-frame period. Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time gradation method than a liquid crystal element. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel emits light in each sub-frame period. Turn the sub-pixels into a light-emitting or non-light-emitting state. By dividing into a plurality of sub-frame periods, the total length of the period during which a pixel actually emits light within one frame period can be controlled by a video signal, and gradation can be displayed.

[0227] In the light-emitting display device shown in FIG. 20(B), when two switching TFTs are arranged in one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. However, an example is shown where the signal input to the first scanning line and the signal input to the second scanning line may both be generated by one scanning line driving circuit. Also, for example, depending on the number of switching TFTs a pixel has, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements. In this case, the signals input to the plurality of scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of each scanning line driving circuits.

[0228] Also, in a light-emitting display device, a part of the driving circuit that can be composed of n-channel type TFTs can be formed on the same substrate as the thin film transistors in the pixel portion. Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit using only n-channel type TFTs shown in Embodiments 1 to 3.

[0229] Also, the driving circuit described above is not limited to a liquid crystal display device or a light-emitting display device, but includes a switching element and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. It is easy to read, consumes less power than other display devices, and can be made thin and light. It has advantages.

[0230] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0231] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required for the display, reducing weight.

[0232] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0233] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. If a plurality of locap capsules are arranged, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used. If a plurality of locap capsules are arranged, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules.

[0234] Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. Note that the first particles and the second particles in the microcapsules may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0235] By the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0236] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0237] (Embodiment 5) A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or the whole of the driving circuit of the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel. A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or the whole of the driving circuit of the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel. A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or the whole of the driving circuit of the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel.

[0238] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. Further, electronic ink, etc., The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. Further, electronic ink, etc., The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. Further, electronic ink, etc., A display medium whose contrast changes due to the action can also be applied.

[0239] The display device further includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted thereon. Further, regarding the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0240] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) attached module, a module provided with a printed wiring board at the tip of the TAB tape or TCP or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG (Chip On Glass) method is also included in the display device.

[0241] The appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 16. FIGS. 16(A1) and (A2) show highly reliable thin film transistors 4010, 4011, and including the oxide semiconductor layer shown in Embodiment 3 formed on the first substrate 4001 The liquid crystal element 4013 is sealed between the first substrate 4001 and the second substrate 4006 by a sealing material 400 5, and is a plan view of the panel. FIG. 16(B) corresponds to a cross-sectional view taken along M-N of FIGS. 16(A1) and (A2).

[0242] The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, the second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 16(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 16(A2) is an example in which the signal line driving circuit 4003 is mounted by the

[0243] TAB method.

[0244] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 16(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. Insulating layers 4020 and 402 are provided on the thin film transistors 4010 and 4011 ​​​​​1 is provided.

[0245] The thin film transistors 4010 and 4011 can be reliable thin film transistors including the oxide semiconductor layer shown in Embodiment 3. Also, the thin film transistors shown in Embodiment 1 or Embodiment 2 may be applied. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0246] Further, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that insulating layers 4032 and 4033 each functioning as an alignment film are provided for the pixel electrode layer 4030 and the counter electrode layer 4031, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0247] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0248] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is provided. Note that spherical spacers may be used. Also, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010 . Using a common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 4005 .

[0249] Also, a liquid crystal showing a blue phase that does not use an alignment film may be used. The blue phase is one of the liquid crystal phases and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range . A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence .

[0250] In addition to the transmissive liquid crystal display device, it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device .

[0251] Also, in the liquid crystal display device, an example is shown in which a polarizing plate is provided on the outside (viewing side) of the substrate, and a coloring layer and an electrode layer used for display elements are provided in this order on the inside. However, the polarizing plate may be provided on the inside of the substrate . Also, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. Also, a light shielding film that functions as a black matrix may be provided .

[0252] ​​ Also, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in the above embodiment is used as a protective film or a planarization insulating film, and is configured to be covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as such. Note that, the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the atmosphere, and a dense film is preferable. The protective film may be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film using a sputtering method. Although an example of forming the protective film by a sputtering method is shown, it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. Also, an insulating layer is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the second layer of the insulating layer 4020 using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT.

[0253] Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. When a silicon oxide film is used as the protective film, it is effective in preventing hillocks in the aluminum film used as the source electrode layer and the drain electrode layer.

[0254] Also, an insulating layer is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the second layer of the insulating layer 4020 using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT. When a silicon nitride film is used as the protective film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT.

[0255] Also, after forming the protective film, heat treatment (at 300 °C or lower) may be performed in a nitrogen atmosphere or in an air atmosphere. Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 4020 using a sputtering method. When a silicon oxide film is used as the protective film,

[0256] Also, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, organic materials having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials. The siloxane resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents of the siloxane resin, organic groups (for example, alkyl groups or aryl groups) or fluoro groups may be used. Further, the organic group may have a fluoro group. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 and the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc., which have translucency.

[0257]

[0258]

[0259] ​ A conductive material may be used.

[0260] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0261] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0262] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0263] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0264] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0265] In FIG. 16, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. Although an example of the installation is shown, it is not limited to this configuration. The scanning line drive circuit may be separately formed and implemented or only a part of the signal line drive circuit or a part of the scanning line drive circuit may be separately formed and implemented.

[0266] FIG. 26 shows an example of configuring a liquid crystal display module as a semiconductor device using a TFT substrate 2600 manufactured by the manufacturing method disclosed in this specification.

[0267] FIG. 26 is an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary for performing color display. In the case of the RGB method, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer.

[0268] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, etc. Alignment mode, PVA (Patterned Vertical Alig nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0269] Through the above steps, a highly reliable liquid crystal display panel can be fabricated as a semiconductor device.

[0270] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0271] (Embodiment 6) An example of an electronic paper as a semiconductor device is shown.

[0272] An electronic paper that drives electronic ink using an element electrically connected to a switching element may be used.

[0273] An electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as readability similar to paper, low power consumption compared to other display devices, and the ability to be thin and lightweight.

[0274] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the micro ​​​​​​​ Particles in the capsule are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. Here, the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle is different from that of the second particle (including colorless).

[0275] In this way, the electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0276] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having color filters or dyes.

[0277] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used.

[0278] Note that the first particle and the second particle in the microcapsule may be made of a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0279] FIG. 15 shows an active matrix type electronic paper as an example of a semiconductor device.​​​​​​​​​​​ As the thin film transistor 581 used in the device, it can be manufactured in the same manner as the thin film transistor shown in Embodiment 1, and is a highly reliable thin film transistor including an oxide semiconductor layer. Also, the thin film transistors shown in Embodiment 2 or Embodiment 3 can also be applied as the thin film transistor 5 81 of the present embodiment. 81.

[0280] The electronic paper in FIG. 15 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by disposing spherical particles painted white and black between a first electrode layer and a second electrode layer that are electrode layers using the display element, and causing a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0281] The thin film transistor 581 is a thin film transistor having a bottom gate structure and is covered with an insulating film 583 in contact with the semiconductor layer. The source electrode layer or drain electrode layer of the thin film transistor 581 is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating film 583 and the insulating layer 585. Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b, and spherical particles 589 including a cavity 594 filled with a liquid around are provided. The periphery of the spherical particles 589 is filled with a filler 595 such as resin (see FIG. 15). The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate 580 as the thin film transistor 581. Using a common connection portion, the second electrode layer 588 and the common are electrically connected through conductive particles disposed between the substrate 580 and the substrate 596. It can be electrically connected to the potential line.

[0282] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules with a diameter of about 10 μm to 20 0 μm, which encapsulate positively charged white fine particles and negatively charged black fine particles, are used. The microcapsules provided between the first electrode layer and the second electrode layer When an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required and also has low power consumption, and it is possible to recognize the display part even in a dim place. Also even when no power is supplied to the display part, it is possible to hold the image once displayed Therefore, even when the semiconductor device with a display function (simply called a display device or a semiconductor device equipped with a display device) is separated from the radio wave transmission source it is possible to save the displayed image.

[0283] Through the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0284] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0285] (Embodiment 7) An example of a light-emitting display device is shown as a semiconductor device. As the display element of the display device, here it is shown using a light-emitting element that utilizes electroluminescence. Electroluminescence​​​​ The light-emitting element that uses the light-emitting material is classified into two types according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0286] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0287] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0288] FIG. 18 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0289] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0290] The pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitive element 6403. The switching transistor 6401 has its gate connected to the scanning line 6406, and one of its first electrodes (either the source electrode or the drain electrode) is connected to the signal line 6405, and the other of its second electrodes (either the source electrode or the drain electrode) is connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode is connected to the power supply line 6407, and its

[0291] second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the

[0292] low power supply potential is a potential that satisfies < high power supply potential with respect to the high power supply potential set on the A capacitance may be formed between the gate electrode and the like.

[0293] Here, in the case of the voltage input voltage drive method, to the gate of the driving transistor 6402, a video signal is input such that the driving transistor 6402 has two states of being fully on or off. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. In addition, to the signal line 6405, a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0294] Also, when performing analog gradation driving instead of digital time gradation driving, by changing the signal input, the same pixel configuration as in FIG. 18 can be used. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 64

[0295] 04 refers to the voltage in the case of a desired luminance and includes at least the forward threshold voltage. In addition, by inputting a video signal such that the driving transistor 6402 operates in the saturation region, a current can flow through the light emitting element 6404. To operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By making the video signal analog, a current corresponding to the video signal can flow through the light emitting element 6404, and analog gradation driving can be performed.

[0296] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, a switch, a resistance element, a capacitance element, a transistor, a logic circuit, or the like may be added to the pixel shown in FIG. 18.

[0297] Next, the configuration of the light-emitting element will be described with reference to FIG. 19. Here, the case where the driving TFT is of the n-type will be taken as an example, and the cross-sectional structure of the pixel will be described. The driving TFTs TFT7001, 7011, and 7021 used in the semiconductor device shown in FIGS. 19(A), (B), and (C) can be manufactured in the same manner as the thin-film transistor shown in Embodiment 1, and are reliable thin-film transistors including an oxide semiconductor layer. Further, the thin-film transistors shown in Embodiment 2 or Embodiment 3 can also be applied as TFT7001, 7011, and 7021.

[0298] For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, there are a top emission type in which a thin-film transistor and a light-emitting element are formed on a substrate and light is extracted from the surface opposite to the substrate, a bottom emission type in which light is extracted from the surface on the substrate side, and a double-sided emission structure type in which light is extracted from both the substrate side and the surface opposite to the substrate, and the pixel configuration can be applied to any of the light-emitting elements having these emission structures.

[0299] The light-emitting element having a top emission structure will be described with reference to FIG. 19(A).

[0300] FIG. 19(A) shows a cross-sectional view of a pixel in the case where the driving TFT, TFT7001, is of the n-type and the light emitted from the light-emitting element 7002 passes through to the anode 7005 side. In FIG. 19(A), the cathode 7003 of the light-emitting element 7002 and the driving TFT, TFT7001, are electrically connected. It is provided that a light-emitting layer 7004 and an anode 7005 are sequentially laminated on a cathode 7003. The cathode 7003 can use various materials as long as it is a conductive film with a low work function and that reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7 004 may be composed of a single layer or may be configured such that a plurality of layers are laminated. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having translucency that transmits light, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or a conductive film having translucency such as indium tin oxide added with silicon oxide may be used.

[0301] The region sandwiching the light-emitting layer 7004 between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 19(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 side as indicated by the arrow.

[0302] Next, the light-emitting element with a bottom emission structure will be described with reference to FIG. 19(B). When the driving TFT 7 011 is n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side, a cross-sectional view of the pixel is shown. In FIG. 19(B), the cathode 7013 of the light-emitting element 7012 is formed on a translucent conductive film 7017 electrically connected to the driving TFT 7011. , a light-emitting layer 7014 and an anode 7015 are sequentially stacked on the cathode 7013. When the anode 7 015 has light transmittance, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as it is a conductive material with a small work function, similar to the case of FIG. 19(A). However, the film thickness should be such that light can pass through it (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or multiple stacked layers, similar to the case of FIG. 19(A). The anode 7015 does not necessarily need to transmit light, but as in FIG. 19(A), it can be formed using a conductive material with light transmittance. And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin with a black pigment added can also be used. The region between the cathode 7013 and the anode 7015 that sandwiches the light-emitting layer 7014 corresponds to the light-emitting element 7012. In the case of the pixel shown in FIG. 19(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow. Next, the light-emitting element with a double-sided emission structure will be described with reference to FIG. 19(C). In FIG. 19(C),

[0303] a cathode 7023 of a light-emitting element 7022 is formed on a conductive film 7027 with light transmittance electrically connected to the driving TFT 7021, and a light-emitting layer 7024 and an anode 7025 are sequentially stacked on the cathode 7023. The cathode 7023 is the same as in the case of FIG. 19(A) in terms of work function and can be made of various materials as long as it is a conductive material with a small work function.

[0304] On the conductive film 7027 with light transmittance electrically connected to the driving TFT 7021, a cathode 7023 of a light-emitting element 7022 is formed, and a light-emitting layer 7024 and an anode 7025 are sequentially stacked on the cathode 7023. The cathode 7023, similar to the case of FIG. 19(A), can be made of various materials as long as it is a conductive material with a small work function. Various materials can be used as long as they are conductive materials with a low work function. However, the film thickness should be such that light can pass through it. For example, Al with a film thickness of 20 nm can be used as the cathode 7023 . And the light-emitting layer 7024 can be composed of a single layer or a plurality of laminated layers, similar to Fig. 19(A). The anode 70 25 can be formed using a conductive material with light-transmitting properties, similar to Fig. 19(A).

[0305] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in Fig. 19(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side, as indicated by the arrows.

[0306] Here, although the organic EL element is described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0307] Although an example where a thin film transistor (driving TFT) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element is shown, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0308] Note that the semiconductor device is not limited to the configuration shown in Fig. 19, and various modifications based on the technical idea disclosed in this specification are possible.

[0309] Next, the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to Fig. 17(A). Fig. 17 shows a thin film formed on the first substrate. A panel in which a thin film transistor and a light emitting element are sealed with a sealing material between them and a second substrate is a plan view, and FIG. 17(B) corresponds to a cross-sectional view taken along H-I in FIG. 17(A).

[0310] A pixel portion 4502, signal line driving circuits 4503a, 450 3b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 are surrounded by a sealing material 4505 is provided. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 45 04a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506 . In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to package (encase) it with a protective film (laminated film, ultraviolet curable resin film, etc.) with little outgassing or a cover material . Also, the pixel portion 4502, signal line driving circuits 4503a, 4 503b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of thin film transistors, and in FIG. 17(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated

[0311] . The thin film transistors 4509 and 4510 can be applied with highly reliable thin film transistors including an oxide semiconductor layer shown in Embodiment 3. Also, in Embodiment 1 or Embodiment

[0312] ​​​​The thin film transistors shown in 2 may be applied. The thin film transistors 4509 and 4510 are n channel type thin film transistors.

[0313] Also, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is the pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the shown configuration. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like.

[0314] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening so as to be an inclined surface formed with a continuous curvature.

[0315] The electroluminescent layer 4512 may be configured as a single layer or as a stack of multiple layers.

[0316] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0317] Also, various signals and potentials applied to the signal line driving circuits 4503a, 4503b, the scanning line driving circuits 4504a, 4504b or the pixel portion 4502 are supplied from the FPCs 4518a, 4518 b.

[0318] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin-film transistors 4509 and 4510.

[0319] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a through the anisotropic conductive film 4519.

[0320] The second substrate 4506 located in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0321] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler.

[0322] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. A reflection preventing film may also be provided on the polarizing plate or the circular polarizing plate. For example, an anti-glare treatment that diffuses the reflected light due to the surface irregularities and can reduce the reflection can be performed.

[0323] The signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b may be implemented by driving circuits formed of a single-crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line driving circuit, or a part thereof, or only the scanning line driving circuit, or a part thereof may be separately formed and implemented, and the present invention is not limited to the configuration of FIG. 17. By the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0324]

[0325]

[0326] (Embodiment 8) The semiconductor device disclosed in this specification can be applied as an electronic paper. The electronic paper can be used in electronic devices in any field as long as it can display information. For example, the electronic paper can be used for electronic books (e-books), posters, in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIG. 27.

[0327] FIG. 27 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed about the shaft portion 2711. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0328] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 27) and An image can be displayed on the display unit 2707 in FIG.

[0329] FIG. 27 shows an example in which a housing 2701 is provided with an operation unit and the like. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0330] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0331] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television Also referred to as a receiver), monitors for computers, digital cameras, digital video cameras , digital photo frames, mobile phones (also referred to as mobile phones and mobile phone devices), portable game machines, portable information terminals, audio playback devices, large game machines such as pachinko machines, etc. are included .

[0332] Figure 28(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image . Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown .

[0333] The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or by a separate remote control unit 9610. The operation keys 9609 provided in the remote control unit 9610 can be used to operate channels and volume, and can also operate the image displayed on the display unit 9603 . Also, the remote control unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control unit 9610 .

[0334] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and can further be connected to a communication network via a modem, either wired or wirelessly , to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication .

[0335] Figure 28(B) shows an example of a digital photo frame 9700. For example, digital The photo frame 9700 has a display unit 9703 incorporated in the housing 9701. The display unit 9703 can display various images. For example, by displaying the image data captured by a digital camera or the like, it can function in the same way as a

[0336] normal photo stand. In addition, the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals and terminals connectable to various cables such as USB cables), a recording medium insertion part, and the like. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because the

[0337] design will be improved. For example, an image memory storing the image data captured by a digital camera can be inserted into the recording medium

[0338] insertion part of the digital photo frame to capture the image data and display the captured image data on the display unit 9703. Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly. Figure 29(A) shows a portable gaming machine, which is composed of two Substances, sounds, time, hardness, electric fields, currents, voltages, power, radiation, flow rates, humidity, gradients, vibrations, odors, or infrared rays (including those with a function of measuring them), microphones 9889, etc. are provided. Of course, the configuration of the portable gaming machine is not limited to the above, and any configuration with at least the semiconductor device disclosed in this specification is acceptable, and other accessory equipment can be appropriately provided. The portable gaming machine shown in Fig. 29(A) has functions such as reading the programs or data recorded on the recording medium and displaying them on the display unit, and functions of sharing information by performing wireless communication with other portable gaming machines. Note that the functions of the portable gaming machine shown in Fig. 29(A) are not limited to this, and it can have various functions. Fig. 29(B) shows an example of a large gaming machine, a slot machine 9900. The slot machine 9900 has a display unit 9903 incorporated in the housing 9901. In addition, the slot machine 9900 is provided with other operating means such as a start lever and a stop switch, a coin insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above, and any configuration with at least the semiconductor device disclosed in this specification is acceptable, and other accessory equipment can be appropriately provided. Fig. 30(A) is a perspective view showing an example of a portable computer.

[0339] The portable computer in Fig. 30(A) can be in a state where the upper housing 9301 having the display unit 9303 and the lower housing 9302 having the keyboard 9304 are overlapped with the hinge unit connecting them in a closed state, and can be carried around.

[0340]

[0341] ​​​​​​​​​is convenient, and when the user inputs using the keyboard, the hinge unit is in the open state so that the user can perform an input operation while looking at the display unit 9303.

[0342] In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. Also, if the display unit 9303 is a touch input panel, the user can perform an input operation by touching a part of the display unit. Further, the lower housing 9302 has a computing function unit such as a CPU and a hard disk. Also, the lower housing 9302 has an external connection port 9305 into which a communication cable compliant with the communication standard of another device, for example, USB, is inserted.

[0343] The upper housing 9301 further has a display unit 93 07 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. Also, the user can adjust the orientation of the screen of the storable display unit 9307. Also, if the storable display unit 9307 is a touch input panel, the user can perform an input operation by touching a part of the storable display unit.

[0344] The display unit 9303 or the storable display unit 9307 uses a video display device such as a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element.

[0345] Also, the portable computer shown in Fig. 30(A) is configured with a receiver and the like, and can receive a television broadcast and display the video on the display unit or the display units. Also, with the hinge unit connecting the upper housing 93 01 and the lower housing 9302 in the closed state, the display unit 930 7 is slid to expose the entire screen, and the screen angle is adjusted so that the user can watch the television broadcast ​This is also possible. In this case, the display unit 9303 is displayed with the hinge unit in the open state and only the circuit for displaying only the television broadcast is activated, so that the minimum power consumption and it can be achieved, which is useful for a portable computer with a limited battery capacity.

[0346] Also, FIG. 30(B) is a perspective view showing an example of a mobile phone having a form that can be worn on the user's wrist like a wristwatch.

[0347] This mobile phone includes at least a communication device having a telephone function and a main body having a battery, a band portion for wearing the main body on the wrist, an adjustment portion 9205 for adjusting the fixed state of the band portion with respect to the wrist, a display portion 9201, a speaker 9207, and a microphone 9208.

[0348] The main body also has an operation switch 9203, and in addition to a power input switch, a display switching switch, and an imaging start instruction switch, for example, a switch that starts a program for the Internet when pressed, and each function can be associated.

[0349] The input operation of this mobile phone is performed by touching the display portion 9201 with a finger or an input pen, or operating the operation switch 9203, or voice input to the microphone 9208. In FIG. 30(B), a display button 9202 displayed on the display portion 9201 is shown, and input can be performed by touching it with a finger.

[0350] The main body also has a camera portion 9206 having an imaging stage for converting a subject image formed through a photographing lens into an electronic image signal. Note that the camera portion may not be particularly provided.

[0351] ​​​​​​​​​​ The mobile phone shown in FIG. 30(B) is equipped with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0352] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 30(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0353] Although FIG. 30B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0354] (Embodiment 10) In this embodiment, an example in which some steps are different from those in the first embodiment is shown. After the formation of the source electrode layer or drain electrode layer 405a, 405b, heating for dehydration or dehydrogenation is performed. An example of the process is shown in Fig. 31. Note that the same parts as in Fig. 6 will be described using the same reference numerals.

[0355] As in the first embodiment, a gate electrode layer 401 and a gate insulator layer 402 are formed on a substrate 400 having an insulating surface. An insulating layer 402 and an oxide semiconductor layer 430 are formed (see FIG. 31A).

[0356] The source and drain electrode layers 405a and 405b are formed over the oxide semiconductor layer 430. , a part of the oxide semiconductor layer 430 is etched to form the oxide semiconductor layer 441 (see Fig. 31 (B)).

[0357] Next, heat treatment and slow cooling are performed on the oxide semiconductor layer 441 and the source electrode layer or drain electrode layer 405a, 405b in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure . By this heat treatment, the oxide semiconductor layer 441 is subjected to dehydration treatment or dehydrogenation treatment to reduce the resistance and can be made into the oxide semiconductor layer 432 with reduced resistance (see Fig. 31(C)). Note that the materials of the source electrode layer or drain electrode layer 405a , 405b are preferably materials that can withstand this heat treatment, such as tungsten, molybdenum .

[0358] Next, without exposing to the atmosphere after the above heat treatment and slow cooling, an oxide insulating film 407 is formed by sputtering or PCVD method in contact with the oxide semiconductor layer 432 . When the oxide insulating film 407 is formed by sputtering or PCVD method in contact with the oxide semiconductor layer 432 with reduced resistance , at least the region in contact with the oxide insulating film 407 in the oxide semiconductor layer 432 with reduced resistance is made to have increased resistance (the carrier concentration decreases, preferably less than 1×10 / cm 18 3 , more preferably less than or equal to 1×10 14 / cm 3 ), and can be made into a high-resistance oxide semiconductor region . Therefore, the oxide semiconductor layer 432 becomes the semiconductor layer 403 (the third oxide semiconductor layer) having a high-resistance oxide semiconductor region, and the thin film transistor 470 can be fabricated (see Fig. 31(D)).

[0359] ​​​​​By performing heat treatment for the dehydration treatment or dehydrogenation treatment, impurities (H O, H, OH, etc.) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is 2 performed. After slow cooling, an oxide insulating film or the like is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 470. Moreover, the present embodiment can be freely combined with Embodiment 1.

[0360]

[0361] (Embodiment 11) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIG. 32. The same parts or parts having similar functions, and steps as those in Embodiment 1 can be performed in the same manner as in Embodiment 1, and repeated description will be omitted.

[0362] The thin film transistor 471 shown in FIG. 32 is an example in which a conductive layer 409 is provided via an insulating film so as to overlap the channel region of the gate electrode layer 401 and the semiconductor layer 403.

[0363] FIG. 32 is a cross-sectional view of the thin film transistor 471 included in the semiconductor device. The thin film transistor 471 is a bottom gate type thin film transistor, and includes a gate electrode layer 401, a gate insulating layer 402, a semiconductor layer 403, and a source electrode layer or drain electrode layers 405a, 405b, and a conductive layer 409 on a substrate 4 00 which is a substrate having an insulating surface. The conductive layer 409 is provided on the oxide insulating film 407 so as to overlap the gate electrode layer 401.

[0364] The conductive layer 409 is connected to the gate electrode layer 401, the source electrode layer or the drain electrode layers 405a, 40 ​​​It can be formed using the same materials and methods as 5b. When providing the pixel electrode layer, it may be formed using the same materials and methods as the pixel electrode layer. In this embodiment, a titanium film, an aluminum film, and a stack of titanium films are used as the conductive layer 409. The potential of the conductive layer 409 may be the same as or different from that of the gate electrode layer 401, and it can also function as the second gate electrode layer. Further, the conductive layer 409 may be in a floating state. By providing the conductive layer 409 at a position overlapping the semiconductor layer 403, in a bias - thermal stress test (hereinafter referred to as BT test) for examining the reliability of the thin - film transistor, the change amount of the threshold voltage of the thin - film transistor 471 before and after the BT test can be reduced. In particular, the variation of the threshold voltage can be suppressed in a - BT test where the voltage applied to the gate is - 20V after raising the substrate temperature to 150°C.

[0365] It can be formed using the same materials and methods as the pixel electrode layer. In this embodiment, a titanium film, an aluminum film, and a stack of titanium films are used as the conductive layer 409. The potential of the conductive layer 409 may be the same as or different from that of the gate electrode layer 401, and it can also function as the second gate electrode layer. Further, the conductive layer 409 may be in a floating state. By providing the conductive layer 409 at a position overlapping the semiconductor layer 403, in a bias - thermal stress test (hereinafter referred to as BT test) for examining the reliability of the thin - film transistor, the change amount of the threshold voltage of the thin - film transistor 471 before and after the BT test can be reduced. In particular, the variation of the threshold voltage can be suppressed in a - BT test where the voltage applied to the gate is - 20V after raising the substrate temperature to 150°C.

[0366] This embodiment can be freely combined with Embodiment 1. (Embodiment 12) The semiconductor device and the method of manufacturing the semiconductor device will be described with reference to FIG. 33. The same parts or parts having similar functions, and processes as in Embodiment 1 can be carried out in the same manner as in Embodiment 1, and repeated explanations will be omitted. The thin - film transistor 472 shown in FIG. 33 is an example in which a conductive layer 419 is provided via an oxide insulating film 407 and an insulating layer 410 so as to overlap the channel region of the gate electrode layer 401 and the semiconductor layer 403. This embodiment can be freely combined with Embodiment 1.

[0367] This embodiment can be freely combined with Embodiment 1.

[0368] (Embodiment 12) The semiconductor device and the method of manufacturing the semiconductor device will be described with reference to FIG. 33. The same parts or parts having similar functions, and processes as in Embodiment 1 can be carried out in the same manner as in Embodiment 1, and repeated explanations will be omitted. The thin - film transistor 472 shown in FIG. 33 is an example in which a conductive layer 419 is provided via an oxide insulating film 407 and an insulating layer 410 so as to overlap the channel region of the gate electrode layer 401 and the semiconductor layer 403. This embodiment can be freely combined with Embodiment 1.

[0369] The thin - film transistor 472 shown in FIG. 33 is an example in which a conductive layer 419 is provided via an oxide insulating film 407 and an insulating layer 410 so as to overlap the channel region of the gate electrode layer 401 and the semiconductor layer 403. The thin - film transistor 472 shown in FIG. 33 is an example in which a conductive layer 419 is provided via an oxide insulating film 407 and an insulating layer 410 so as to overlap the channel region of the gate electrode layer 401 and the semiconductor layer 403. It can be formed using the same materials and methods as the pixel electrode layer. In this embodiment, a titanium film, an aluminum film, and a stack of titanium films are used as the conductive layer 409.

[0370] FIG. 33 is a cross-sectional view of a thin film transistor 472 included in a semiconductor device. The thin film transistor 472 is a bottom gate type thin film transistor, and on a substrate 400 which is a substrate having an insulating surface, a gate electrode layer 401, a gate insulating layer 402, a semiconductor layer 403, a source region or also drain regions 404a and 404b, and source electrode layers or drain electrode layers 405a and 405b, and a conductive layer 419 are included. The conductive layer 419 is provided on an oxide insulating film 407 and an insulating layer 410 so as to overlap with the gate electrode layer 401.

[0371] In this embodiment, an insulating layer 410 that functions as a planarization film is laminated on the oxide insulating film 407, and an opening reaching the source electrode layer or drain electrode layer 405b is formed in the oxide insulating film 407 and the insulating layer 410. A conductive film is formed in the opening formed in the insulating layer 410, the oxide insulating film 407, and the insulating layer 410, and etched into a desired shape to form the conductive layer 419 and the pixel electrode layer 411. In the step of forming the pixel electrode layer 411 in this way, the conductive layer 419 can be formed using the same materials and methods. In this embodiment, indium tin oxide alloy containing silicon oxide (In - Sn - O based oxide containing silicon oxide) is used for the pixel electrode layer 411 and the conductive layer 419.

[0372] Further, the conductive layer 419 may be formed using the same materials and methods as those of the gate electrode layer 401, the source electrode layer or drain electrode layer 405a, 405b.

[0373] The potential of the conductive layer 419 may be the same as that of the gate electrode layer 401 or different, and it can also function as a second gate electrode layer. Further, the conductive layer 419 may be in a floating state. ​

[0374] By providing the conductive layer 419 at a position overlapping the semiconductor layer 403, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 472 before and after the BT test can be reduced. possible.

[0375] This embodiment can be freely combined with Embodiment 1.

[0376] (Embodiment 13) In this embodiment, an example of the channel stop type thin film transistor 1430 will be described with reference to FIGS. 34(A), 34(B), and 34(C). Further, FIG. 34(C) is an example of a top view of the thin film transistor, and the cross-sectional view taken along the chain line Z1-Z2 in the figure corresponds to FIG. 34(B). Also, an example in which an oxide semiconductor material containing no gallium is used for the oxide semiconductor layer of the thin film transistor 1430 is shown. In FIG. 34(A), a gate electrode layer 1401 is provided on a substrate 1400. Next, an oxide semiconductor layer is formed on a gate insulating layer 1402 covering the gate electrode layer 1401.

[0377] In FIG. 34(A), a gate electrode layer 1401 is provided on a substrate 1400. Next, an oxide semiconductor layer is formed on a gate insulating layer 1402 covering the gate electrode layer 1401. On the gate insulating layer 1402 covering the gate electrode layer 1401, an oxide semiconductor layer is formed.

[0378] In this embodiment, an Sn-Zn-O-based oxide semiconductor using a sputtering method is used as the oxide semiconductor layer. By not using gallium in the oxide semiconductor layer, expensive targets are not required, so the cost can be reduced.

[0379] After the formation of the oxide semiconductor film or after the patterning of the oxide semiconductor layer, dehydration or dehydrogenation is performed.

[0380] ​​​​​​​For dehydration or dehydrogenation, after heat treatment is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, slow cooling is performed in an inert atmosphere. The heat treatment is carried out at 200 °C or higher and 600 °C or lower, preferably 400 °C or higher and 450 °C or lower. The oxide semiconductor layer is subjected to heat treatment and slow cooling in an inert gas atmosphere or under reduced pressure, resulting in a lower resistance (the carrier concentration increases, preferably to 1×10 / cm 18 or higher), and a low-resistance 3 oxide semiconductor layer 1403 can be obtained (see Fig. 34(A)).

[0381] Next, a channel protection layer 1418 is provided in contact with the oxide semiconductor layer 1403. By providing the channel protection layer 1418, damage (such as film loss due to plasma or etching agent during etching) to the channel formation region of the oxide semiconductor layer 1403 can be prevented. Therefore, the reliability of the thin-film transistor 1430 can be improved.

[0382] Also, after dehydration or dehydrogenation, the channel protection layer 141 8 can be formed continuously without exposure to the atmosphere. By continuously processing without exposure to the atmosphere, the interface can be formed without being contaminated by atmospheric components such as water and hydrocarbons, or impurity elements floating in the atmosphere, so that each laminated interface can be formed, reducing the variation in thin-film transistor characteristics.

[0383] Also, when a channel protection layer 1418, which is an oxide insulating film, is formed by sputtering or PCVD method in contact with the low-resistance oxide semiconductor layer 1403, the low-resistance oxide semiconductor In the layer 1403, at least the region in contact with the channel protection layer 1418 is made to have a high resistance (the carrier concentration is reduced, preferably to less than 1×10 / cm 18 / cm 3 and more preferably to less than 1×10 1 4 / cm 3 or less), and it can be made into a high-resistance oxide semiconductor region. During the manufacturing process of the semiconductor device, it is important to increase or decrease the carrier concentration of the oxide semiconductor layer by heating, slow cooling, and forming an oxide insulating film under an inert gas atmosphere (or under reduced pressure). As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography.

[0384] As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor deposition method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is processed into a shape by etching after film formation. Here, a silicon oxide film is formed by the sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography.

[0385] Next, n + layers 1406a and 1 406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In this embodiment, the n + layers 1406a and 1406b that function as the source region or the drain region are Al-Zn-O-based polycrystalline films, and are formed under film formation conditions different from those of the oxide semiconductor layer 1 403, and are oxide semiconductor layers with lower resistance. Also, the n + layers 1406a and 1406b may be Al-Zn-O-based polycrystalline films containing nitrogen, that is, Al-Zn-O-N-based polycrystalline films (also referred to as AZON films).​

[0386] Next, n + On layer 1406a, a source electrode layer 1405a, n + On layer 1406b, a drain Electrode layer 1405b is formed respectively to fabricate a thin film transistor 1430 (see Fig. 34(B ). The source electrode layer 1405a and the drain electrode layer 1405b are made of an element selected from Al, Cr, Ta , Ti, Mo, W, or an alloy containing the above-mentioned elements as components, or an alloy film formed by combining the above-mentioned Elements. Also, the source electrode layer 1405a and the drain electrode Layer 1405b may use these laminates.

[0387] n + By providing layers 1406a and 1406b, a good junction is formed between the source electrode layer 1405 a, the drain electrode layer 1405b, which are metal layers, and the oxide semiconductor layer 1403, enabling thermally stable operation compared to a Schottky junction. Also, to supply carriers to the channel (source side), or stably absorb carriers in the channel (drain side), or not to create a resistance component at the interface with the wiring, it is also effective to positively provide an n Layer. Also, due to the reduction in resistance, good mobility can be maintained even at a high drain voltage. . Or. + Providing a layer is effective . Also, due to the reduction in resistance, good mobility can be maintained even at a high drain voltage.

[0388] Also, it is not limited to the structure having the above-mentioned n + Layers 1406a and 1406b. For example, it may have a structure without providing an n + Layer.

[0389] Also, after forming the channel protection layer 1418, heat treatment (preferably 150°C or higher and lower than 350°C) is performed on the thin film transistor 1430 in a nitrogen atmosphere or in an air atmosphere (in air) . Perform. For example, perform a heat treatment at 250°C for 1 hour in a nitrogen atmosphere. When this heat treatment is performed , the oxide semiconductor layer 1403 is heated in contact with the channel protection layer 1418, and variations in the electrical characteristics of the thin film transistor 1470 can be reduced. This heat treatment (preferably 150°C or higher and less than 350°C) is not particularly limited as long as it is after the formation of the channel protection layer 1418, and can be performed without increasing the number of steps by combining it with other processes, such as heat treatment during resin film formation or heat treatment for reducing the resistance of the transparent conductive film.

[0390] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0391] (Embodiment 14) A semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIGS. 35(A) and 35(B). Parts and processes that are the same as or have similar functions to those in Embodiment 13 can be performed in the same manner as in Embodiment 13, and repeated explanations will be omitted.

[0392] The thin film transistor 1431 shown in FIG. 35(A) is an example in which a conductive layer 1409 is provided via a channel protection layer 1418 and an insulating layer 1407 so as to overlap the channel region of the gate electrode layer 1401 and the oxide semiconductor layer 1403.

[0393] FIG. 35(A) is a cross-sectional view of the thin film transistor 1431 included in the semiconductor device. The thin film transistor 1431 is a bottom gate type thin film transistor, and on a substrate 1400 having an insulating surface, a gate electrode layer 1401, a gate insulating layer 1402, an oxide semiconductor layer 1403, source regions or drain regions 1404a, 1404b, and a source electrode layer or drain electrode layer are provided. It includes drain electrode layers 1405a and 1405b, and a conductive layer 1409. The conductive layer 1409 is provided on the insulating layer 1407 so as to overlap with the gate electrode layer 1401.

[0394] The conductive layer 1409 can be formed using the same materials and methods as those of the gate electrode layer 1401, the source electrode layer, or the drain electrode layers 1405a, 1405b. In the case of providing a pixel electrode layer, it may be formed using the same materials and methods as those of the pixel electrode layer. In this embodiment, a titanium film, an aluminum film, and a stack of titanium films are used as the conductive layer 1409.

[0395] The potential of the conductive layer 1409 may be the same as or different from that of the gate electrode layer 1401, and it can also function as a second gate electrode layer. Also, the conductive layer 1409 may be in a floating state.

[0396] By providing the conductive layer 1409 at a position overlapping with the oxide semiconductor layer 1403, in a bias - thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin - film transistor, the change amount of the threshold voltage of the thin - film transistor 1431 before and after the BT test can be reduced.

[0397] Also, FIG. 35(B) shows an example partially different from FIG. 35(A). The same parts or parts having the same functions as those in FIG. 35(A), and the processes can be carried out in the same manner as in FIG. 35(A), and repeated explanations are omitted.

[0398] The thin - film transistor 1432 shown in FIG. 35(B) has a channel protection layer 1418, an insulating layer 1407, and is provided so as to overlap with the channel region of the gate electrode layer 1401 and the oxide semiconductor layer 1403. This is an example of providing the conductive layer 1409 via the insulating layer 1408.

[0399] In FIG. 35(B), an insulating layer 1408 that functions as a planarization film is laminated on the insulating layer 1407. to be.

[0400] Also, in FIG. 35(B), no source region or drain region is provided, and the oxide semiconductor layer 14 03 is in direct contact with the source electrode layer or drain electrode layer 1405a, 1405b. is.

[0401] Even in the structure of FIG. 35(B), by providing the conductive layer 1409 at a position overlapping the oxide semiconductor layer 1403, in the BT test for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 1432 before and after the BT test can be reduced. In FIG. 35(B), by providing the conductive layer 1409 at a position overlapping the oxide semiconductor layer 1403, in the BT test for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 1432 before and after the BT test can be reduced. can be. done.

[0402] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is.

[0403] (Embodiment 15) In this embodiment, an example in which the structure is partially different from that of Embodiment 1 is shown in FIG. 36. The same parts or parts having the same functions, and the processes as those in Embodiment 1 can be performed in the same manner as in Embodiment 1, and repeated explanations are omitted. The same parts or parts having the same functions, and the processes as those in Embodiment 1 can be performed in the same manner as in Embodiment 1, and repeated explanations are omitted. possible, and repeated explanations are omitted.

[0404] In this embodiment, after patterning the first oxide semiconductor layer, heat treatment is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then slow cooling is performed in an inert atmosphere. By performing heat treatment on the first oxide semiconductor layer in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed. element, or helium, neon, argon, etc.) or under reduced pressure, and then slow cooling is performed in an inert atmosphere. By performing heat treatment on the first oxide semiconductor layer in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed. After that, slow cooling is performed in an inert atmosphere. By performing heat treatment on the first oxide semiconductor layer in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed. After that, slow cooling is performed in an inert atmosphere. By performing heat treatment on the first oxide semiconductor layer in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed. 。

[0405] Next, after forming a second oxide semiconductor film to be used as a source region and a drain region ( n + layer, also referred to as a buffer layer) on the first oxide semiconductor layer, a conductive film is formed.

[0406] Next, the first oxide semiconductor layer, the second oxide semiconductor film, and the conductive film are selectively etched in an etching process to form an oxide semiconductor layer 403 and a source region or a drain region ( n + layer, also referred to as a buffer layer) 404a, 404b, and a source electrode layer or a drain electrode layer 405a, 405b. Note that only a part of the oxide semiconductor layer 403 is etched to form an oxide semiconductor layer having a groove portion (recess).

[0407] Next, a silicon oxide film by sputtering or PCVD is formed as an oxide insulating film 407 in contact with the oxide semiconductor layer 403. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and uses an inorganic insulating film that blocks these from entering from the outside - . Specifically, a silicon oxide film or a silicon oxynitride film is used.

[0408] When an oxide insulating film 407 is formed by sputtering or PCVD or the like in contact with the low-resistance oxide semiconductor layer 403, at least the region in the low-resistance oxide semiconductor layer 403 in contact with the oxide insulating film 407 is made to have a higher resistance (the carrier concentration decreases, preferably less than 1×10 18 / cm 3 18 3 14 / cm 3 ​as described below, and a high-resistance oxide semiconductor region can be formed. By forming in contact with the oxide insulating film 407, a semiconductor layer 403 having a high-resistance oxide semiconductor region is obtained, and a thin film transistor 473 can be fabricated (see Fig. 36). (See Fig. 36.)

[0409] In the structure shown in Fig. 36, an In-Ga-Zn-O-based amorphous film is used as the source region or drain region (also referred to as the n + layer or buffer layer) 404a, 404b.

[0410] Also, a source region is provided between the semiconductor layer 403 and the source electrode layer, and a drain region is provided between the semiconductor layer and the drain electrode layer. An oxide semiconductor layer showing an n-type conductivity type is used for the source region and the drain region.

[0411] Moreover, the second oxide semiconductor film used as the source region or drain region 404a, 404b of the thin film transistor 473 preferably has a thickness thinner than that of the first oxide semiconductor layer used as the channel formation region and a higher conductivity (electrical conductivity).

[0412] The first oxide semiconductor layer used as the channel formation region has an amorphous structure, and the second oxide semiconductor film used as the source region and the drain region may contain crystal grains (nanocrystals) in the amorphous structure. The crystal grains (nanocrystals) in the second oxide semiconductor film used as the source region and the drain region have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0413] Also, after forming the oxide insulating film 407, in a nitrogen atmosphere or in an air atmosphere (in air), The thin film transistor 473 is subjected to a heat treatment (preferably at 150°C or higher and lower than 350°C). This is also acceptable. For example, a heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. When performing this heat treatment the oxide semiconductor layer 403 will be heated while in contact with the oxide insulating film 407, and variations in the electrical characteristics of the thin film transistor 473 can be reduced.

[0414] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. This is possible.

[0415] Regarding the present invention having the above configuration, a more detailed explanation will be given with the following examples. This is what will be done.

Examples

[0416] Here, in the oxide semiconductor layer having a region with a high oxygen density and a region with a low oxygen density, the results of calculating the change in oxygen density before and after the heat treatment will be explained using FIGS. 42 and 43. Here, as the software for calculation, Mater ials Explorer 5.0 manufactured by Fujitsu Limited was used. This was used.

[0417] FIG. 42 shows the model of the oxide semiconductor layer used in the calculation. Here, the oxide semiconductor layer 12 01 has a structure in which a layer 1203 with a low oxygen density and a layer 1205 with a high oxygen density are laminated. This is the case.

[0418] Here, the layer 1203 with a low oxygen density has an amorphous structure composed of 15 In atoms, 15 Ga atoms, 1 5 Zn atoms, and 54 O atoms.

[0419] Also, as the layer 1205 with a high oxygen density, 15 In atoms, 15 Ga atoms, 15 It was made into an amorphous structure composed of Zn atoms and 66 O atoms.

[0420] Also, the density of the oxide semiconductor layer 1201 was set to 5.9 g / cm 3 as follows.

[0421] Next, classical MD (molecular dynamics) calculations were performed on the oxide semiconductor layer 1201 under the conditions of an NVT ensemble and a temperature of 250°C. The time step width was set to 0.2 fs, and the total calculation time was set to 20 0 ps. Also, the Born-Mayer-Huggins type was applied to the metal-oxygen bond and the oxygen-oxygen bond for the potential. Also, the movement of the atoms at the upper and lower ends of the oxide semiconductor layer 1201 was fixed.

[0422] Next, the calculation results are shown in Fig. 43. From 0 nm to 1.15 nm on the z-axis coordinate is the layer 1203 with a low oxygen density, and from 1.15 nm to 2.3 nm on the z-axis coordinate is the layer 1205 with a high oxygen density. The density distribution of oxygen before the MD calculation is shown by the solid line 1207, and the density distribution of oxygen after the MD calculation is shown by the broken line 1209.

[0423] In the solid line 1207, the oxygen density is high in the layer 1205 with a high oxygen density, from the interface between the layer 1203 with a low oxygen density and the layer 1205 with a high oxygen density. On the other hand, in the broken line 1209, it can be seen that the oxygen density is homogeneous in the layer 1203 with a low oxygen density and the layer 1205 with a high oxygen density.

[0424] From the above, it can be seen that when there is a bias in the oxygen density distribution in the laminated state of the layer 1203 with a low oxygen density and the layer 1205 with a high oxygen density, the oxygen density diffuses from the higher side to the lower side by heat treatment, and the oxygen density becomes homogeneous.

[0425] That is, as shown in Embodiment 1, an oxide insulating film 407 is formed on the oxide semiconductor layer 432. By doing so, the oxygen density is high at the interface between the oxide semiconductor layer 403 and the oxide insulating film 407. Therefore, the oxygen diffuses toward the side with a lower oxygen density in the oxide semiconductor layer 403, and the oxide semiconductor layer 403 becomes highly resistive. From the above, the reliability of the thin film transistor can be improved.

Explanation of Reference Numerals

[0426] 10 dotted line 100 substrate 101 gate electrode layer 102 gate insulating layer 103 semiconductor layer 105a source electrode layer 105b drain electrode layer 107 protective insulating layer 108 capacitor wiring 109 oxide semiconductor film 110 pixel electrode layer 121 terminal 122 terminal 125 contact hole 126 contact hole 127 contact hole 128 transparent conductive film 129 transparent conductive film 132 conductive film 133 oxide semiconductor layer 134 oxide semiconductor layer 135 semiconductor layer 150 terminal 151 terminal 152 gate insulating layer 153 connection electrode layer 154 protective insulating layer 155 transparent conductive film 156 electrode layer 170 thin film transistor 400 substrate 401 gate electrode layer 402 Gate insulating layer 403 Semiconductor layer 404a, 404b Source electrode layer or drain electrode layer 405a, 405b Source electrode layer or drain electrode layer 407 Oxide insulating film 409 Conductive layer 410 Insulating layer 411 Pixel electrode layer 419 Conductive layer 430 Oxide semiconductor layer 431 Oxide semiconductor layer 432 Oxide semiconductor layer 441 Oxide semiconductor layer 450 Substrate 451 Gate electrode layer 452 Gate insulating layer 453 Semiconductor layer 455a Drain electrode layer 457 Oxide insulating film 460 Thin film transistor 470 Thin film transistor 471 Thin film transistor 472 Thin film transistor 473 Thin film transistor 483 Oxide semiconductor layer 484 Oxide semiconductor layer 500 Substrate 501 Insulating film 502 Oxide semiconductor film 503 Electrode 510 Sample for physical property evaluation 580 Substrate 581 Thin film transistor 583 Insulating film 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a Black region 590b White region 594 Cavity 595 Filling material 596 Substrate 601 Electric furnace 602 Chamber 603 Heater 604 Substrate 605 Susceptor 606 Gas supply means 607 Exhaust means 611 Gas supply source 612 Pressure regulating valve 613 Purifier 614 Mass flow controller 615 Stop valve 701 Oxide semiconductor layer 711 Initial characteristics 712 +BT 713 -BT 721 Initial characteristics 722 +BT 723 -BT 731 Initial characteristics 732 +BT 733 -BT 1201 Oxide semiconductor layer 1203 Layer with low oxygen density 1205 Layer with high oxygen density 1207 Solid line 1209 Dashed line 1400 Substrate 1401 Gate electrode layer 1402 Gate insulating layer 1403 Oxide semiconductor layer 1404a, 1404b Source region or drain region 1405a, 1405b Source electrode layer or drain electrode layer 1406a, 1406b n+ layer 1407 Insulating layer 1408 Insulating layer 1409 Conductive layer 1418 Channel protection layer 1430 Thin film transistor 1431 Thin film transistor 1432 Thin film transistor 1470 Thin film transistor 2600 TFT Substrate 2601 Opposite substrate 2602 Sealant 2603 Pixel portion 2604 Display element 2605 Coloring layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit portion 2609 Flexible printed circuit board 2610 Cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2700 E-book 2701 Housing 2703 Housing 2705 Display portion 2707 Display portion 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel portion 4003 Signal line drive circuit 4004 Scan line drive circuit 4005 Sealant 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4501 Substrate 4502 Pixel portion 4503a, 4503b Signal line drive circuit 4504a, 4504b Scan line drive circuit Sealing material 4505 Substrate 4506 Filling material 4507 Thin film transistor 4509 Thin film transistor 4510 Light emitting element 4511 Electroluminescent layer 4512 Electrode layer 4513 Connection terminal electrode 4515 Terminal electrode 4516 Electrode layer 4517 FPC 4518a, 4518b Anisotropic conductive film 4519 Partition wall 4520 Substrate 5300 Pixel portion 5301 Scanning line drive circuit 5302 Signal line drive circuit 5303 Substrate 5400 Pixel portion 5401 Scanning line drive circuit 5402 Signal line drive circuit 5403 Scanning line drive circuit 5404 Wiring 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Node 5543 Node 5544 Thin film transistor 5571 Thin film transistor 5572 Thin film transistor 5573 Thin film transistor 5574 Thin film transistor 5575 Thin film transistor 5576 Thin film transistor 5577 Thin film transistor 5578 Driver IC 5601 Switch group 5602 Thin film transistor 5603a Thin film transistor 5603b 5603c thin film transistor 5611 wiring 5612 wiring 5613 wiring 5621 wiring 5701 flip-flop 5711 wiring 5712 wiring 5713 wiring 5714 wiring 5715 wiring 5716 wiring 5717 wiring 5721 signal 5821 signal 6400 pixel 6401 switching transistor 6402 driving transistor 6403 capacitive element 6404 light-emitting element 6405 signal line 6406 scanning line 6407 power line 6408 common electrode 7001 TFT 7002 light-emitting element 7003 cathode 7004 light-emitting layer 7005 anode 7011 driving TFT 7012 light-emitting element 7013 cathode 7014 light-emitting layer 7015 anode 7016 shielding film 7017 conductive film 7021 driving TFT 7022 light-emitting element 7023 cathode 7024 light-emitting layer 7025 anode 7027 conductive film 9201 display unit 9202 display button 9203 operation switch 9205 adjustment unit 9206 Camera unit 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display unit 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display unit 9600 Television apparatus 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Housing 9882 Display unit 9883 Display unit 9884 Speaker unit 9885 Input means (operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display unit

Claims

[Claim 1] forming a gate electrode layer; forming a gate insulating layer on the gate electrode layer; forming an oxide semiconductor layer on the gate insulating layer; dehydrating or dehydrogenating the oxide semiconductor layer; forming a source electrode layer and a drain electrode layer on the dehydrated or dehydrogenated oxide semiconductor layer; a gate insulating layer, a first insulating film, a second insulating film, and a third insulating film formed on the gate insulating layer, the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, the first insulating film being in contact with a part of the oxide semiconductor layer;

Images