Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Abstract

To provide a method of manufacturing a silicon carbide semiconductor device capable of leading a main region to be in ohmic contact with a main electrode, and further avoiding a drain-source leakage current in a trench-gate silicon carbide semiconductor device.SOLUTION: A method of manufacturing a silicon carbide semiconductor device includes the steps of: forming a base region of a second conductivity-type on a top surface side of a drift layer of a first conductivity-type including silicon carbide; forming a main region of the first conductivity-type on the top surface side of the base region; forming a trench penetrating the main region and the base region; burying a gate electrode inside the trench with the gate insulating film interposed; and forming a main electrode so as to be in contact with the main region. The step of forming the main region includes: implanting impurity ions of the first conductivity-type at a room temperature so as to form a first region including a 4H-structure; and implanting impurity ions of at least one of silicon, carbon, and argon at a room temperature so as to form a second region including a 3C-structure.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device in which an amorphous layer is formed by ion-implanting phosphorus into a hexagonal single-crystalline silicon carbide substrate, the amorphous layer is recrystallized into cubic single-crystalline n-type silicon carbide by heat treatment, and an electrode is formed by depositing nickel on the upper surface of the n-type silicon carbide.

[0003] Patent Document 2 discloses an n-type epitaxial growth layer formed on a first main surface of n-type SiC made of 4H-SiC, having an n-type source region, an n-type 3C-SiC region formed in the n-type source region, and a p-type potential fixing region, and a barrier metal film is formed in contact with the n-type 3C-SiC region and the p-type potential fixing region, and a source wiring electrode is formed on the barrier metal film. + type SiC of the first main surface formed on the n - type epitaxial growth layer within the n + type source region and n + type source region formed within the n + type 3C-SiC region and p + type potential fixing region, and n + type 3C-SiC region and p + type potential fixing region, and a semiconductor device in which a barrier metal film is formed in contact with the p-type potential fixing region, and a source wiring electrode is formed on the barrier metal film is disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a trench gate type silicon carbide semiconductor device, it has been considered to form a source region (main region) of 3C-SiC in order to make ohmic contact with a source electrode (main electrode). However, since 3C-SiC has more crystal defects and larger surface irregularities than 4H-SiC, there is a risk that a leakage current (Idss) will flow between the source and drain.

[0006] In view of the above problems, an object of the present disclosure is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device in which a main region can make ohmic contact with a main electrode and the leakage current between the source and drain can be suppressed in a trench gate type silicon carbide semiconductor device.

Means for Solving the Problems

[0007] To achieve the above object, one aspect of the present disclosure includes a step of forming a base region of a second conductivity type made of silicon carbide on the upper surface side of a drift layer of a first conductivity type made of silicon carbide, a step of forming a main region of a first conductivity type made of silicon carbide on the upper surface side of the base region, a step of forming a trench penetrating the main region and the base region, a step of forming a gate insulating film inside the trench, a step of embedding a gate electrode through the gate insulating film inside the trench, and a step of forming a main electrode in contact with the main region. The step of forming the main region includes forming a first region including a 4H structure on the upper surface side of the base region by ion implanting impurities of the first conductivity type at room temperature, and forming a second region including a 3C structure in contact with the main electrode on the upper surface side of the first region by ion implanting at least one of silicon, carbon, and argon at room temperature. The gist is that it is a method for manufacturing a silicon carbide semiconductor device.

[0008] Another aspect of the present disclosure is a silicon carbide semiconductor device including a drift layer of a first conductivity type made of silicon carbide, a base region of a second conductivity type made of silicon carbide provided on the upper surface side of the drift layer, a main region of the first conductivity type made of silicon carbide provided on the upper surface side of the base region, a gate insulating film provided inside a trench penetrating the main region and the base region, a gate electrode embedded inside the trench via the gate insulating film, and a main electrode provided in contact with the main region. The main region includes a first region including a 4H structure provided on the upper surface side of the base region, and a second region provided in contact with the main electrode on the upper surface side of the first region and having a ratio of at least the upper surface side 3C structure of 70% or more.

Effects of the Invention

[0009] According to the present disclosure, there are provided a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device in which, in a trench gate type silicon carbide semiconductor device, a main region can make ohmic contact with a main electrode and a leakage current between a source and a drain can be suppressed.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, with reference to the drawings, the first to third embodiments of the present disclosure will be described. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different even between the drawings. Further, the first to third embodiments shown below illustrate devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the material, shape, structure, arrangement, etc. of the components as follows.

[0012] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is the "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). Also, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), the "one main region" can be selected as the cathode region. The drain region of the MOSFET is the "other main region (second main region)" of a semiconductor device that can be selected as the collector region in the IGBT and the anode region in the thyristor. When simply referred to as the "main region" in this specification, it means either the first main region or the second main region that is reasonable from the common technical knowledge of those skilled in the art.

[0013] Also, the definitions of the directions such as up and down in the following description are merely for convenience of explanation and do not limit the technical idea of the present disclosure. For example, if the object is rotated by 90° and observed, the up and down are read as left and right, and if it is rotated by 180° and observed, the up and down are read in reverse. Also, the "upper surface" may be read as the "front surface", and the "lower surface" may be read as the "back surface".

[0014] In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be exemplarily described. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the + and - attached to n and p respectively mean semiconductor regions with relatively higher or lower impurity concentrations compared to the semiconductor regions without the + and - notations. However, even for semiconductor regions with the same n attached, it does not mean that the impurity concentrations of the respective semiconductor regions are exactly the same.

[0015] In addition, SiC crystals have crystal polymorphs, and the main ones are cubic 3C, and hexagonal 4H and 6H. The reported values of the bandgap at room temperature are 2.23 eV for 3C-SiC, 3.26 eV for 4H-SiC, and 3.02 eV for 6H-SiC. In the following description, the cases mainly using 4H-SiC and 3C-SiC will be exemplified.

[0016] (First Embodiment) <Structure of Silicon Carbide Semiconductor Device> As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment exemplifies the case of including a trench gate type MOSFET as an active element. In FIG. 1, a unit cell including an insulated gate electrode structure (11, 12) embedded in one trench 10 is exemplified, but actually, a large number of these unit cells are arranged periodically.

[0017] The silicon carbide semiconductor device according to the first embodiment includes a drift layer 2 of the first conductivity type (n - -type). The drift layer 2 is composed of, for example, an epitaxial growth layer made of SiC such as 4H-SiC. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less. The thickness of the drift layer 2 is, for example, 1 μm or more and 100 μm or less. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the breakdown voltage specification and the like.

[0018] On the upper surface side of the drift layer 2, a current spreading layer (CSL) 3 of the first conductivity type (n-type) with a higher impurity concentration than the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is composed of, for example, an epitaxial growth layer made of SiC such as 4H-SiC. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 1×10 18 cm -3 or less. Note that the current spreading layer 3 does not necessarily have to be provided. When the current spreading layer 3 is not provided, the drift layer 2 may be extended up to the region of the current spreading layer 3.

[0019] On the upper surface side of the current spreading layer 3, base regions 6a and 6b of the second conductivity type (p-type) are provided. The lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the current spreading layer 3. When the current spreading layer 3 is not provided, the lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the drift layer 2. The base regions 6a and 6b are composed of, for example, an epitaxial growth layer made of SiC such as 4H-SiC. The base regions 6a and 6b may be regions in which p-type impurities are ion-implanted into the current spreading layer 3. The impurity concentration of the base regions 6a and 6b is, for example, 1×10 16 cm -3 or more and 1×10 18 cm -3 or less.

[0020] On the upper surface side of the base regions 6a and 6b, first main regions (source regions) 7a and 7b of the first conductivity type (n + type) with a higher impurity concentration than the drift layer 2 are selectively provided. The source regions 7a and 7b are regions made of SiC in which n-type impurities are ion-implanted into the base regions 6a and 6b, for example.

[0021] The source region 7a is the lower layer and is an n + type source extension part (also referred to as the "first region" or "4H-SiC layer") 71a including a 4H structure (4H-SiC), and the upper layer is an n +It has a two-layer structure of a source contact portion (also referred to as the "second region" or "3C-SiC layer") 72a. The lower surface of the source extension portion 71a is in contact with the upper surface of the base region 6a. The upper surface of the source extension portion 71a is in contact with the lower surface of the source contact portion 72a. The source region 7b is the lower layer and contains a 4H structure (4H-SiC) and is n + type source extension portion (also referred to as the "first region" or "4H-SiC layer") 71b, and the upper layer is an n + type source contact portion (also referred to as the "second region" or "3C-SiC layer") 72b having a two-layer structure. The lower surface of the source extension portion 71b is in contact with the upper surface of the base region 6b. The upper surface of the source extension portion 71b is in contact with the lower surface of the source contact portion 72b. Details of the source regions 7a and 7b will be described later.

[0022] A trench 10 is provided that penetrates the source regions 7a and 7b and the base regions 6a and 6b in the normal direction (depth direction) of the upper surfaces of the source regions 7a and 7b from the upper surfaces of the source regions 7a and 7b. The lower surface of the trench 10 reaches the current diffusion layer 3. The width of the trench 10 is, for example, about 1 μm or less. The source region 7a and the base region 6a are in contact with the left side surface of the trench 10. The source region 7b and the base region 6b are in contact with the right side surface of the trench 10. The trench 10 may have a planar pattern that extends in a stripe shape in the depth direction and the front direction of the paper surface of FIG. 1, or may have a dot-shaped planar pattern.

[0023] A gate insulating film 11 is provided along the lower surface and both side surfaces of the trench 10. A gate electrode 12 is embedded inside the trench 10 via the gate insulating film 11. The gate insulating film 11 and the gate electrode 12 constitute a trench gate type insulated gate electrode structure (11, 12).

[0024] As the gate insulating film 11, in addition to a silicon oxide film (SiO 2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si 3 N 4)A film, an aluminum oxide (Al 2 O 3 ) film, a magnesium oxide (MgO) film, a yttrium oxide (Y 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, a bismuth oxide (Bi 2 O 3 ) film, any one of the single-layer films or a composite film formed by laminating a plurality of these films can be adopted. As the material of the gate electrode 12, for example, a polysilicon layer (doped polysilicon layer) doped with a p-type impurity or an n-type impurity at a high impurity concentration, or a refractory metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0025] Inside the current diffusion layer 3 and at the bottom of the trench 10, a gate bottom protection region 4b of the second conductivity type (p + -type) is provided. The upper surface of the gate bottom protection region 4b is in contact with the lower surface of the trench 10. The upper surface of the gate bottom protection region 4b does not necessarily have to be in contact with the lower surface of the trench 10. The impurity concentration of the gate bottom protection region 4b is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less.

[0026] Inside the current diffusion layer 3, first buried regions 4a and 4c of the second conductivity type (p + -type) are provided at a distance from the gate bottom protection region 4b. The first buried regions 4a and 4c are provided at approximately the same depth as the gate bottom protection region 4b. The impurity concentration of the first buried regions 4a and 4c is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3It is as follows. The first implanted regions 4a and 4c and the gate bottom protection region 4b are regions made of SiC obtained by ion-implanting p-type impurities into the current diffusion layer 3, for example. Note that on the front side or the depth side of the plane of FIG. 1, a p-type connection part connecting the first implanted regions 4a and 4c and the gate bottom protection region 4b may be selectively provided. + The p-type connection part may be selectively provided.

[0027] On the upper part of the current diffusion layer 3 and on the upper surface side of the first implanted regions 4a and 4c, second implanted regions 5a and 5b of the second conductivity type (p-type) are provided. The second implanted regions 5a and 5b electrically connect the first implanted regions 4a and 4c and the base regions 6a and 6b. The lower surface of the second implanted regions 5a and 5b is in contact with the upper surface of the first implanted regions 4a and 4c. The side surfaces of the second implanted regions 5a and 5b are in contact with the current diffusion layer 3 and the base regions 6a and 6b. The second implanted regions 5a and 5b are regions made of SiC obtained by ion-implanting p-type impurities into the current diffusion layer 3 and the base regions 6a and 6b, for example. The impurity concentration of the second implanted regions 5a and 5b may be on the same order as the impurity concentration of the first implanted regions 4a and 4c, may be lower than the impurity concentration of the first implanted regions 4a and 4c, or may be higher. The impurity concentration of the second implanted regions 5a and 5b is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less.

[0028] On the upper surface side of the second implanted regions 5a and 5b, base contact regions 8a and 8b of p-type with an impurity concentration higher than that of the second implanted regions 5a and 5b are provided. The base contact regions 8a and 8b are regions made of SiC obtained by ion-implanting p-type impurities into the base regions 6a and 6b, for example. The impurity concentration of the base contact regions 8a and 8b is, for example, 5×10 + cm 18 or more and 5×10 -3 cm 20 or less. The base contact regions 8a and 8b may be made of 3C-SiC or may be made of 4H-SiC. -3 The base contact regions 8a and 8b may be made of 3C-SiC or may be made of 4H-SiC.

[0029] The lower surface of the base contact region 8a contacts the upper surface of the second embedded region 5a, and the side surface of the base contact region 8a contacts the source extension portion 71a and the source contact portion 72a of the source region 7a. The side surface of the base contact region 8a does not necessarily contact the source contact portion 72a. For example, a part of the source extension portion 71a may be provided between the side surface of the base contact region 8a and the source contact portion 72a. The lower surface of the base contact region 8b contacts the upper surface of the second embedded region 5b, and the side surface of the base contact region 8b contacts the source extension portion 71b and the source contact portion 72b of the source region 7b. The side surface of the base contact region 8b does not necessarily contact the source contact portion 72b. For example, a part of the source extension portion 71b may be provided between the side surface of the base contact region 8b and the source contact portion 72b.

[0030] The lower surfaces of the base contact regions 8a and 8b are at about the same depth as the lower surfaces of the source extension portions 71a and 71b of the source regions 7a and 7b, but may be shallower or deeper than the lower surfaces of the source extension portions 71a and 71b of the source regions 7a and 7b. The upper surfaces of the second embedded regions 5a and 5b do not necessarily contact the lower surfaces of the p + -type base contact regions 8a and 8b. For example, base regions 6a and 6b may be provided between the second embedded regions 5a and 5b and the p + -type base contact regions 8a and 8b.

[0031] An interlayer insulating film 13 is provided on the upper surface side of the gate electrode 12. The interlayer insulating film 13 is, for example, a silicon oxide film doped with boron (B) and phosphorus (P) (BPSG film), a silicon oxide film doped with phosphorus (P) (PSG film), a non-doped silicon oxide film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film doped with boron (B) (BSG film), a silicon nitride film (Si 3 N 4 film), etc., or a single-layer film composed of these laminated films. Contact holes 13a and 13b are provided in the interlayer insulating film 13 so as to expose the upper surfaces of the source contact portions 72a and 72b and the base contact regions 8a and 8b.

[0032] An interlayer insulating film 13 and first main electrodes (source electrodes) (14, 15) are provided so as to cover the upper surfaces of source contact portions 72a, 72b and base contact regions 8a, 8b exposed from contact holes 13a, 13b of the interlayer insulating film 13. The source electrodes (14, 15) include a lower barrier metal layer 14 and an upper source wiring electrode 15. For example, the barrier metal layer 14 is made of a metal such as titanium nitride (TiN), titanium (Ti), or a laminated structure of TiN / Ti with Ti as the lower layer. The barrier metal layer 14 is in direct contact with the source contact portions 72a, 72b and the base contact regions 8a, 8b, and has an ohmic contact with low resistance to the source contact portions 72a, 72b and the base contact regions 8a, 8b.

[0033] The source wiring electrode 15 is electrically connected to the source regions 7a, 7b and the base contact regions 8a, 8b via the barrier metal layer 14. The source wiring electrode 15 is provided separately from a gate wiring electrode (not shown) electrically connected to the gate electrode 12. The source wiring electrode 15 is made of a metal such as aluminum (Al), copper (Cu), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or aluminum-silicon-copper (Al-Si-Cu).

[0034] On the lower surface side of the drift layer 2, a second main region (drain region) 1 of the first conductivity type (n + type) with an impurity concentration higher than that of the drift layer 2 is provided. The drain region 1 is composed of, for example, a semiconductor substrate (SiC substrate) made of 4H-SiC. The impurity concentration of the drain region 1 is, for example, 1×10 19 cm -3 or more and 3×10 20 cm -3 or less. The thickness of the drain region 1 is, for example, 30 μm or more and 500 μm or less. Note that a dislocation conversion layer or a recombination promotion layer, which is an n-type buffer layer having an impurity concentration higher than that of the drift layer 2 and lower than that of the drain region 1, may be provided between the drift layer 2 and the drain region 1.

[0035] On the lower surface side of the drain region 1, a second main electrode (drain electrode) 16 is provided. As the drain electrode 16, for example, a single-layer film made of gold (Au) or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used. Further, a metal film such as molybdenum (Mo) or tungsten (W) may be laminated on the lowermost layer thereof. Also, a drain contact layer such as a nickel silicide (NiSi x ) film or the like may be provided between the drain region 1 and the drain electrode 16 for ohmic contact.

[0036] An enlarged cross-section of the broken-line region A including the source extension portion 71a, the source contact portion 72a of the source region 7a shown in FIG. 1, the gate insulating film 11, and the gate electrode 12 is shown in FIG. 2. With reference to FIG. 2, the configuration of the source extension portion 71a and the source contact portion 72a and the positional relationship between the source extension portion 71a and the source contact portion 72a and the gate electrode 12 will be described.

[0037] The source extension portion 71a is a region with fewer crystal defects than the source contact portion 72a and does not inherit the crystal defects of the source contact portion 72a. The source extension portion 71a is mainly composed of 4H-SiC. The proportion of 4H-SiC contained in the source extension portion 71a is, for example, about 90% or more and 100% or less. In addition to 4H-SiC, the source extension portion 71a may slightly contain an amorphous structure, 3C-SiC, or the like. As a method for measuring (observing) the crystal structure of the source extension portion 71a and the source contact portion 72a, for example, the area ratio of the crystal structure on the surface can be measured by a field emission scanning electron microscope (FE-SEM) and electron backscatter diffraction (EBSD).

[0038] The depth d1 from the upper surface of the source contact portion 72a to the lower surface of the source extension portion 71a is, for example, about 200 nm or more and 450 nm or less. The thickness of the source extension portion 71a is, for example, about 150 nm or more and 400 nm or less. The impurity concentration of the source extension portion 71a is lower than the impurity concentration of the source contact portion 72a. The impurity concentration of the source extension portion 71a is, for example, 1×10 16 / cm 3 or more and 1×10 19 / cm 3 or less. The source extension portion 71a contains, for example, phosphorus (P), nitrogen (N), or arsenic (As) as an n-type impurity. When the source contact portion 72a contains argon (Ar) which is an inert element, the source extension portion 71a may contain Ar on its upper surface side.

[0039] The source contact portion 72a is a region containing 3C-SiC. The source contact portion 72a may be a mixed crystal of 3C-SiC and 4H-SiC. In addition to 3C-SiC, the source contact portion 72a may contain an amorphous structure, 4H-SiC, etc. Since 3C-SiC has a narrower bandgap than 4H-SiC, when the source contact portion 72a contains 3C-SiC, an ohmic contact with low resistance can be achieved with the source electrodes (14, 15).

[0040] The ratio of 3C-SiC contained in the source contact portion 72a is, for example, about 10% or more and 100% or less, may be about 70% or more and 100% or less, and may be about 85% or more and 100% or less at least on the upper surface side of the source contact portion 72a. In order to achieve a good ohmic contact with the source electrodes (14, 15), the ratio of 3C-SiC contained in the source contact portion 72a is preferably 70% or more, and more preferably 85% or more.

[0041] The depth from the upper surface to the lower surface of the source contact portion 72a (the thickness of the source contact portion 72a) d2 is, for example, about 30 nm or more and 100 nm or less. The impurity concentration of the source contact portion 72a is higher than that of the source extension portion 71a. The impurity concentration of the source contact portion 72a is, for example, 1×10 18 / cm 3 or more and 5×10 19 / cm 3 or less. The source contact portion 72a contains the same n-type impurity as the source extension portion 71a. The source contact portion 72a contains, as the n-type impurity, for example, phosphorus (P), nitrogen (N), or arsenic (As). The source contact portion 72a may further contain argon (Ar), which is an inert element, in addition to the n-type impurity.

[0042] The differentiation of the crystal structures of the source extension portion 71a and the source contact portion 72a can be achieved by changing the element to be ion-implanted, the temperature during ion implantation, the dose amount (impurity concentration), the activation temperature, etc. for each of the source extension portion 71a and the source contact portion 72a.

[0043] As a method for forming the source extension portion 71a of the silicon carbide semiconductor device according to the first embodiment, for 4H-SiC, at room temperature, by ion-implanting an n-type impurity at a concentration that does not break the structure of 4H-SiC, the source extension portion 71a can be formed while maintaining 4H-SiC.

[0044] As a method for forming the source contact portion 72a of the silicon carbide semiconductor device according to the first embodiment, for 4H-SiC, at room temperature, instead of an n-type impurity, argon (Ar), which is a noble gas, or silicon (Si) or carbon (C), which is a Group 4 element, is ion-implanted to break 4H-SiC using the damage of ion implantation to form an amorphous structure. Then, by performing activation annealing, when the amorphous structure recrystallizes to become 3C-SiC, the source contact portion 72a containing 3C-SiC can be formed.

[0045] As shown in FIG. 2, the upper surface (upper end) 12a of the position of the end portion of the gate electrode 12 in contact with the gate insulating film 11 is deeper than the lower surface (lower end) 72x of the position of the source contact portion 72a in contact with the gate insulating film 11, and shallower than the lower surface (lower end) 71x of the position of the source extension portion 71a in contact with the gate insulating film 11. Note that the source contact portion 72a may be separated from the gate insulating film 11, and a part of the source extension portion 71a may be provided between the source contact portion 72a and the gate insulating film 11. In that case, the upper surface (upper end) 12a of the position of the end portion of the gate electrode 12 in contact with the gate insulating film 11 may be shallower than the lower surface (lower end) 72x on the gate insulating film 11 side of the source contact portion 72a.

[0046] The upper surface 12a of the position of the gate electrode 12 in contact with the gate insulating film 11 may be the uppermost surface of the gate electrode 12. For example, when the entire upper surface of the gate electrode 12 is a downwardly convex curved surface, the upper surface of the central portion of the gate electrode 12 may be deeper than the upper surface 12a of the end portion of the gate electrode 12.

[0047] The gate electrode 12 and the source extension portion 71a face each other with the gate insulating film 11 interposed therebetween. The gate electrode 12 and the source contact portion 72a do not face each other with the gate insulating film 11 interposed therebetween. The source contact portion 72a faces the interlayer insulating film 13 with the gate insulating film 11 interposed therebetween. The amount of depression d0 from the upper surface of the source contact portion 72a of the gate electrode 12 is, for example, about 100 nm or more and 300 nm or less. The amount of depression d0 of the gate electrode 12 and the position of the upper surface 12a of the position of the gate electrode 12 in contact with the gate insulating film 11 can be controlled, for example, by adjusting the etching conditions of the gate electrode 12.

[0048] Since the source extension portion 71b and the source contact portion 72b of the source region 7b shown in FIG. 1 have the same configurations as the source extension portion 71a and the source contact portion 72a of the source region 7a, respectively, duplicate descriptions are omitted. Also, since the positional relationship between the source extension portion 71b and the source contact portion 72b of the source region 7b and the gate electrode 12 is the same as the positional relationship between the source extension portion 71a and the source contact portion 72a of the source region 7a and the gate electrode 12, duplicate descriptions are omitted.

[0049] During the operation of the silicon carbide semiconductor device according to the first embodiment, when a positive voltage is applied to the drain electrode 16 with the source electrodes (14, 15) at the ground potential and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 12, an inversion layer (channel) is formed on the side surface of the trench 10 in the base regions 6a, 6b, and the device is in the on state. In the on state, current flows from the drain electrode 16 through the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layers in the base regions 6a, 6b, and the source regions 7a, 7b to the source electrodes (14, 15). On the other hand, when the voltage applied to the gate electrode 12 is less than the threshold value, no inversion layer is formed in the base regions 6a, 6b, so the device is in the off state and no current flows from the drain electrode 16 to the source electrodes (14, 15).

[0050] According to the silicon carbide semiconductor device according to the first embodiment, by forming the source region 7a into a two-layer structure of the source extension portion 71a and the source contact portion 72a and including 3C-SiC in the upper source extension portion 71a in contact with the source electrodes (14, 15), the source contact portion 72a can form an ohmic contact with the source electrodes (14, 15) with low resistance without forming a silicide layer such as nickel (Ni) silicide. Therefore, problems such as peeling of the silicide layer can be suppressed as compared with the case where a silicide layer is formed.

[0051] Also, as shown in FIG. 3, consider a case where a source region 7x containing 3C-SiC is formed in a single-layer structure and the source region 7x faces the gate electrode 12 via the gate insulating film 11. In this case, since the source region 7x contains 3C-SiC, the source region 7x can make ohmic contact with the source electrodes (14, 15). However, since 3C-SiC has more crystal defects and larger surface irregularities compared to 4H-SiC, there is a risk that a leakage current I1 will flow between the gate electrode 12 and the source region 7x.

[0052] On the other hand, according to the silicon carbide semiconductor device according to the first embodiment, as shown in FIG. 2, the upper surface 12a of the gate electrode 12 is made deeper than the lower surface 72x of the source contact portion 72a and shallower than the lower surface 71x of the source extension portion 71a. As a result, the source extension portion 71a with fewer crystal defects in the source region 7a faces the gate electrode 12 via the gate insulating film 11, and the source contact portion 72a with more crystal defects in the source region 7a does not face the gate electrode 12 via the gate insulating film 11. Therefore, it is possible to suppress the generation of leakage current between the source region 7a and the gate electrode 12.

[0053] <Method for manufacturing a silicon carbide semiconductor device> Next, an example of a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described. Note that the method for manufacturing a silicon carbide semiconductor device described below is an example, and it goes without saying that it can be realized by various other manufacturing methods including this modification within the scope of the gist described in the claims. FIG. 4 is a flowchart of some procedures of the method for manufacturing a silicon carbide semiconductor device according to the first embodiment, and in the following description, FIG. 4 will be referred to as appropriate.

[0054] First, a semiconductor substrate (SiC substrate) 1 (see FIG. 1) made of n-type 4H-SiC doped with an n-type impurity such as nitrogen (N) is prepared. The upper surface of the SiC substrate 1 has an off-angle of, for example, 3 degrees or more and 8 degrees or less from the {0001} plane. An n-type impurity such as N is added to the upper surface of the SiC substrate 1, and the n-type impurity has a lower impurity concentration than the SiC substrate 1. + type 4H-SiC doped with an n-type impurity such as nitrogen (N) is added to the upper surface of the SiC substrate 1, and the n-type impurity has a lower impurity concentration than the SiC substrate 1. -A drift layer 2 made of a 4H-SiC of a type (see FIG. 1) is epitaxially grown. Next, as shown in FIG. 5, an n-type impurity such as N is added to the upper surface of the drift layer 2, and an n-type layer 3a made of 4H-SiC of an n-type with a higher impurity concentration than the drift layer 2 is epitaxially grown. Note that the n-type layer 3a may be formed by ion-implanting an n-type impurity such as nitrogen (N) on the upper part of the drift layer 2.

[0055] Next, an oxide film is deposited on the upper surface of the n-type layer 3a by a chemical vapor deposition (CVD) technique or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned using a photolithography technique, a dry etching technique, or the like. Using the patterned oxide film as a mask for ion implantation, a p-type impurity such as aluminum (Al) is selectively ion-implanted. Note that instead of the oxide film, a photoresist film may be used as a mask for ion implantation. Thereafter, the oxide film used as a mask for ion implantation is removed. As a result, as shown in FIG. 6, p-type first embedded regions 4a and 4c and a p-type gate bottom protection region 4b are selectively formed on the upper part of the n-type layer 3a. + type, and + type gate bottom protection region 4b are selectively formed.

[0056] Next, an n-type layer 3b (see FIG. 7) made of 4H-SiC of an n-type is epitaxially grown on the upper surfaces of the n-type layer 3a, the first embedded regions 4a and 4c, and the gate bottom protection region 4b. As a result, a current diffusion layer 3 composed of the n-type layer 3a and the n-type layer 3b is formed. Next, as shown in FIG. 7, a base region 6 made of 4H-SiC of a p-type is epitaxially grown on the upper surface of the current diffusion layer 3. The n-type layer 3b and the base region 6 may be formed by ion implantation instead of epitaxial growth.

[0057] Next, an oxide film is deposited on the upper surface of the base region 6 by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film, and the oxide film is patterned by photolithography technology, dry etching technology or the like. Using the patterned oxide film as an ion implantation mask, p-type impurities such as aluminum (Al) are selectively ion-implanted. Note that a photoresist film may be used as the ion implantation mask instead of the oxide film. Thereafter, the oxide film used as the ion implantation mask is removed. As a result, as shown in FIG. 8, p-type second buried regions 5a, 5b are selectively formed on the upper surface side of the first buried regions 4a, 4c.

[0058] Next, n in step S11 of FIG. + The source extension part forming process is carried out. + In the step of forming a type source extension, an oxide film 21 (see FIG. 9) is deposited on the upper surface of the base region 6 by CVD or the like. A photoresist film is applied to the upper surface of the oxide film 21, and the oxide film 21 is patterned by photolithography, dry etching, or the like. Using the patterned oxide film 21 as a mask for ion implantation, as shown in FIG. 9, n-type impurities such as phosphorus (P), nitrogen (N) or arsenic (As) are ion-implanted at room temperature (RT) without heating. The room temperature is, for example, about 1° C. or higher and 40° C. or lower, and may be about 15° C. or higher and 30° C. or lower. Note that a photoresist film may be used as the ion implantation mask instead of the oxide film 21. As a result, n-type impurities such as phosphorus (P), nitrogen (N) or arsenic (As) are ion-implanted on the upper portion of the base region 6. + A source extension 71 of the mold is formed.

[0059] In order to cause less damage during ion implantation to form source extension portion 71 compared to ion implantation of source contact portion 72 described later, as the n-type impurity, P (atomic number 15), which has a relatively small atomic weight, is preferable to As (atomic number 33), which has a relatively large atomic weight, and N (atomic number 7), which has a relatively small atomic weight, is more preferable.

[0060] Ion implantation for forming the source extension portion 71 may be performed in one step. When the P ion implantation is in one step, the acceleration energy may be, for example, about 100 keV or more and 140 keV or less, and more preferably, about 110 keV or more and 130 keV or less. When the ion implantation is in one step, the dose amount may be, for example, 1×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, and more preferably, 3×10 13 / cm 2 or more and 5×10 13 / cm 2 or less.

[0061] Ion implantation for forming the source extension portion 71 may also be performed in two or more multiple steps. For example, as the first ion implantation, an n-type impurity such as P, N, or As is ion implanted in a state of not heating at room temperature. Next, as the second ion implantation, an n-type impurity such as P, N, or As is ion implanted in a state of not heating at room temperature with an acceleration energy and a dose amount smaller than those of the first ion implantation. In the first ion implantation and the second ion implantation, the same n-type impurity may be implanted into each other, or different n-type impurities may be implanted into each other. Note that the order of the first ion implantation and the second ion implantation may be interchanged, and the first ion implantation may be performed after the second ion implantation.

[0062] The acceleration energy of the first ion implantation may be, for example, about 150 keV or more and 250 keV or less, and more preferably, about 180 keV or more and 220 keV or less. The dose amount of the first ion implantation may be, for example, 1×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, and more preferably, 2×10 13 / cm 2 or more and 4×10 13 / cm 2 or less.

[0063] The acceleration energy of the second ion implantation is, for example, about 50 keV or more and 120 keV or less, and more preferably, it may be about 60 keV or more and 100 keV or less. The dose of the second ion implantation is, for example, 1×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, and more preferably, it may be about 2×10 13 / cm 2 or more and 4×10 13 / cm 2 or less.

[0064] By performing ion implantation for forming the source extension portion 71 in two or more stages (multiple stages), the surface concentration of the source contact portion 72 can be increased and the contact resistance can be reduced as compared with the case where ion implantation for forming the source extension portion 71 is performed in one stage. On the other hand, by performing ion implantation for forming the source extension portion 71 in one stage, the manufacturing cost can be reduced as compared with the case where ion implantation for forming the source extension portion 71 is performed in two or more stages (multiple stages).

[0065] By ion implantation of n-type impurities for forming the source extension portion 71, for example, an impurity concentration of 1×10 17 cm -3 or more and 1×10 19 cm -3 or less can be obtained from a depth of 350 nm or more and 400 nm or less from the upper surface of the source extension portion 71, and it can be used as a current path.

[0066] Next, the n + -type source contact portion forming step of step S12 in FIG. 4 is performed. This n +In the p-type source contact portion forming step, as shown in FIG. 10, subsequently, using the oxide film 21 as a mask for ion implantation, at room temperature without heating, at least one of Ar, Si, or C is ion implanted instead of the n-type impurity. The room temperature is, for example, about 1°C or higher and 40°C or lower, and may be about 15°C or higher and 30°C or lower. The room temperature during ion implantation may be the same as or different from the room temperature during ion implantation for forming the source extension portion 71. Note that, instead of the oxide film 21, a photoresist film may be used as a mask for ion implantation. As a result, an n + type source contact portion 72 is formed on the upper surface side of the source extension portion 71.

[0067] By ion implantation for forming the source contact portion 72, the structure of 4H-SiC on the upper surface side of the source extension portion 71 is disrupted to form an amorphous structure. In order to achieve a higher damage compared to the ion implantation of the source extension portion 71 described above, Si (atomic number 14) having a relatively larger atomic weight is preferable to C (atomic number 6) having a relatively smaller atomic weight, and Ar (atomic number 18) having a relatively even larger atomic weight is more preferable.

[0068] The acceleration energy of the ion implantation for forming the source contact portion 72 is, for example, about 50 keV or higher and 100 keV or lower when Ar is ion implanted, and more preferably about 60 keV or higher and 80 keV or lower. When Si is ion implanted, it is, for example, about 60 keV or higher and 120 keV or lower, and more preferably about 70 keV or higher and 100 keV or lower. When C is ion implanted, it is, for example, about 20 keV or higher and 60 keV or lower, and more preferably about 25 keV or higher and 40 keV or lower.

[0069] The dose amount of the ion implantation for forming the source contact portion 72 is, for example, 2×10 14 / cm 2 or more and 2×10 15 / cm 2 or less when Ar is ion implanted, and more preferably 2×10 14 / cm2 Above, it may be on the order of 1×10 15 / cm 2 or less. When ion-implanting Si, for example, it may be on the order of 2×10 14 / cm 2 or more and 2×10 16 / cm 2 or less, and more preferably, it may be on the order of 2×10 14 / cm 2 or more and 1×10 15 / cm 2 or less. When ion-implanting C, for example, it may be on the order of 1×10 15 / cm 2 or more and 5×10 15 / cm 2 or less, and more preferably, it may be on the order of 1×10 15 / cm 2 or more and 3×10 15 / cm 2 or less. The higher the dose amount during ion implantation, the more the ratio of 3C contained in the source contact portion 72 can be increased.

[0070] Next, perform the p + -type contact region formation step of step S13 in FIG. 4. In this p + -type contact region formation step, a oxide film 22 is deposited on the upper surface of the base region 6 by CVD technology or the like. A photoresist film is applied on the upper surface of this oxide film 22, and the oxide film 22 is patterned using photolithography technology, dry etching technology, etc. Using the patterned oxide film 22 as an ion implantation mask, as shown in FIG. 11, p-type impurities such as aluminum (Al) and boron (B) are ion-implanted. Note that instead of the oxide film 22, a photoresist film may be used as the ion implantation mask. As a result, p + -type base contact regions 8a, 8b are selectively formed on the upper surface side of the second embedded regions 5a, 5b. Thereafter, the oxide film 22 used as the ion implantation mask is removed.

[0071] Note that the order of ion implantation for forming the base region 6, ion implantation for forming the source extension portion 71, ion implantation for forming the source contact portion 72, ion implantation for forming the second embedded regions 5a and 5b, and ion implantation for forming the base contact regions 8a and 8b is not limited to this, and the order may be changed.

[0072] Next, the activation annealing (heat treatment) step of step S14 in FIG. 4 is performed. In this activation annealing step, for example, activation annealing is performed at about 1600°C or higher and 1900°C or lower, whereby the p-type impurities or n-type impurities ion-implanted into the first embedded regions 4a and 4c, the gate bottom protection region 4b, the second embedded regions 5a and 5b, the source extension portion 71, the source contact portion 72, and the base contact regions 8a and 8b are activated all at once. At this time, the amorphous structure of the source contact portion 72 is recrystallized to become 3C-SiC, thereby forming the source contact portion 72 containing 3C-SiC.

[0073] Note that here, the case where activation annealing is performed once collectively after all the ion implantation steps is illustrated, but multiple activation annealings may be performed individually after each ion implantation step. Further, before the activation annealing, a cap film made of carbon (C) may be formed, the activation annealing may be performed in a state covered with the cap film, and the cap film may be removed after the activation annealing.

[0074] Next, the trench formation process of step S15 in FIG. 4 is performed. In this trench formation process, an oxide film 23 (see FIG. 12) is deposited on the upper surfaces of the base contact regions 8a and 8b and the source contact portion 72 by means of CVD technology or the like. A photoresist film is applied on the upper surface of the oxide film 23, and the oxide film is patterned using photolithography technology, dry etching technology, or the like. Using the patterned oxide film 23 as an etching mask, a trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72 as shown in FIG. 12 by means of dry etching technology such as reactive ion etching (RIE). Note that, instead of the oxide film 23, a photoresist film may be used as an etching mask.

[0075] The trench 10 penetrates through the source extension portions 71, the source contact portion 72, and the base region 6, further digs into the upper part of the current diffusion layer 3, and reaches the gate bottom protection region 4b. The source extension portion 71 is divided into source extension portions 71a and 71b, the source contact portion 72 is divided into source contact portions 72a and 72b, and the base region 6 is divided into base regions 6a and 6b. Source regions 7a and 7b are formed by the source extension portions 71a and 71b and the source contact portions 72a and 72b. Thereafter, the oxide film 23 used as the etching mask is removed. The trench 10 does not have to reach the gate bottom protection region 4b as long as it reaches the current diffusion layer 3.

[0076] Next, the gate insulating film / gate electrode formation process of step S16 in FIG. 4 is performed. In this gate insulating film / gate electrode formation process, a gate insulating film 11 (see FIG. 13) is formed on the lower surface and side surfaces of the trench 10 and on the upper surfaces of the source contact portions 72a and 72b and the base contact regions 8a and 8b by means of CVD technology, high-temperature oxidation (HTO) method, thermal oxidation method, or the like. When forming the gate insulating film 11, heat treatment (PDA: Post Deposition Annealing) is performed, for example, at a temperature of 900°C or higher and 1350°C or lower.

[0077] Next, by means of CVD technology or the like, a polysilicon layer (doped polysilicon layer) with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited so as to fill the inside of the trench 10. Thereafter, a part of the polysilicon layer is selectively removed by photolithography technology and dry etching. As a result, as shown in FIG. 13, an insulated gate electrode structure (11, 12) composed of a gate insulating film 11 and a gate electrode 12 is formed. At this time, as shown in FIG. 2, the falling amount d0 of the gate electrode 12 is adjusted so that the upper surface 12a of the position where the gate electrode 12 contacts the gate insulating film 11 is deeper than the lower surface (lower end) 72x of the source contact portion 72a and shallower than the lower surface (lower end) 71x of the source extension portion 71a.

[0078] Next, by means of CVD technology or the like, an interlayer insulating film 13 (see FIG. 14) is deposited on the upper surface of the insulated gate electrode structure (11, 12). By photolithography technology, dry etching technology or the like, a part of the interlayer insulating film 13 and the gate insulating film 11 is selectively removed, and contact holes 13a, 13b that expose the upper surfaces of the source contact portions 72a, 72b and the base contact regions 8a, 8b are opened in the interlayer insulating film 13 as shown in FIG. 14. Thereafter, a heat treatment (reflow) for planarizing the interlayer insulating film 13 may be performed.

[0079] Next, by means of sputtering technology, vapor deposition method or the like, as shown in FIG. 15, a barrier metal layer 14 and a source wiring electrode 15 are sequentially formed so as to cover the upper surface and the side surface of the interlayer insulating film 13 and the upper surfaces of the source contact portions 72a, 72b and the base contact regions 8a, 8b, and a source electrode (14, 15) is formed. The barrier metal layer 14 makes an ohmic contact with low resistance with the source contact portions 72a, 72b of the source regions 7a, 7b and the base contact regions 8a, 8b.

[0080] Next, the SiC substrate 1 is thinned from the lower surface side by grinding or chemical mechanical polishing (CMP) or the like to adjust the thickness, thereby forming the drain region 1. Next, a drain electrode 16 (see FIG. 1) made of gold (Au) or the like is formed on the entire lower surface of the drain region 1 by a sputtering method, a vapor deposition method, or the like. In this way, the silicon carbide semiconductor device shown in FIG. 1 is completed.

[0081] According to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, the source region 7a has a two-layer structure of the 4H-SiC source extension portion 71a and the 3C-SiC source contact portion 72a, and the source region 7b has a two-layer structure of the 4H-SiC source extension portion 71b and the 3C-SiC source contact portion 72b. Thus, a trench gate type silicon carbide semiconductor device can be realized in which the source contact portions 72a and 72b can be in ohmic contact with the source electrodes (14, 15) with low resistance without forming a silicide layer such as nickel (Ni) silicide.

[0082] Furthermore, according to the silicon carbide semiconductor device according to the first embodiment, as shown in FIG. 2, the upper surface 12a of the gate electrode 12 is made deeper than the lower surface 72x of the source contact portion 72a and shallower than the lower surface 71x of the source extension portion 71a. As a result, the source extension portion 71a with fewer crystal defects in the source region 7a faces the gate electrode 12 via the gate insulating film 11, and the source contact portion 72a with more crystal defects in the source region 7a does not face the gate electrode 12 via the gate insulating film 11. Therefore, it is possible to suppress the generation of leakage current between the source region 7a and the gate electrode 12.

[0083] Furthermore, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, when performing ion implantation to form the source contact portion 72, Si, C, or Ar is ion-implanted at room temperature instead of an n-type impurity. As a result, since the dose amount of the n-type impurity for ion implantation to form the source extension portion 71 and the source contact portion 72 can be set low, the formation of crystal defects can be suppressed when the crystal structure changes to 3C, and the leakage current between the source and drain can be suppressed. Furthermore, since the dose amount of the n-type impurity for ion implantation to form the source extension portion 71 and the source contact portion 72 can be set low, heating during ion implantation of the n-type impurity for forming the source extension portion 71 becomes unnecessary, and the n-type impurity can be ion-implanted at room temperature. Therefore, the manufacturing cost can be reduced as compared with the case where ion implantation of the n-type impurity for forming the source extension portion 71 is performed at a high temperature (for example, about 200°C or higher and 600°C or lower).

[0084] Furthermore, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, by ion-implanting Si or C during ion implantation for forming the source contact portion 72, compared with the case of ion-implanting Ar, since the crystal structure is more easily repaired by heating, the leakage current between the source and drain can be suppressed to a lower level. Furthermore, when an upper limit is set for the leakage current between the source and drain, the injectable dose amount of Si or C is higher than the dose amount of Ar. Therefore, by increasing the dose amount of Si or C, the ratio of 3C formation can be increased, and the contact resistance can be further reduced. Furthermore, since the impurity concentration on the surface side of the source contact portion 72 can be set low, it becomes easier to reduce the number of implantation steps.

[0085] Furthermore, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, when performing ion implantation to form the source contact portion 72, by ion-implanting Ar, compared with the case of ion-implanting Si or C, since the atomic weight of Ar is small, damage is easily introduced and the dose amount can be reduced.

[0086] Next, with reference to Table 1 below, the first to sixth embodiments and the comparative example will be described.

[0087]

Table 1

[0088] <First Embodiment> As the first embodiment, at room temperature, P + was ion-implanted in two steps: a first ion implantation with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 and a second ion implantation with an acceleration energy of 85 keV and a dose of 3×10 + cm 13 at room temperature. Then, at room temperature, Ar -2 was ion-implanted with an acceleration energy of 70 keV and a dose of 2×10 + cm 14 to manufacture a silicon carbide semiconductor device with a breakdown voltage of 1200 V. -2 Regarding the silicon carbide semiconductor device of the first embodiment, the SiC surface was analyzed by EBSD, and when the ratio of the crystal phase was calculated, the ratio of 3C was 70%. Also, regarding the silicon carbide semiconductor device of the first embodiment, when the leakage current (Idss) between the source and drain was measured, it was 5×10

[0089] A. -6

[0090] <Second Embodiment> As the second embodiment, similar to the first embodiment, at room temperature, P + was ion-implanted in two steps: a first ion implantation with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 and a second ion implantation with an acceleration energy of 85 keV and a dose of 3×10 + cm 13 at room temperature. Then, the dose was changed to be higher than that of the first embodiment, and at room temperature, Ar -2 + ​​at an acceleration energy of 70 keV and a dose of 1×10 15 cm -2 and ion implantation was performed. Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0091] Regarding the silicon carbide semiconductor device of the second embodiment, the SiC surface was analyzed by EBSD, and when the ratio of the crystal phase was calculated, the ratio of 3C was 85%. Therefore, it can be seen that the ratio of 3C increased by increasing the dose of Ar + compared with the first embodiment.

[0092] <Third Embodiment> As a third embodiment, in the same manner as in the first embodiment, at room temperature, P + was ion-implanted in two steps: a first ion implantation at an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 and a second ion implantation at room temperature with P + at an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 Then, the ion species was changed from that in the first embodiment, and at room temperature, Si + was ion-implanted at an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0093] Regarding the silicon carbide semiconductor device of the third embodiment, the SiC surface was analyzed by EBSD, and when the ratio of the crystal phase was calculated, the ratio of 3C was 70%. Therefore, it can be seen that when Si + was ion-implanted instead of Ar + the ratio of 3C was equivalent.

[0094] <Fourth Embodiment> As a fourth embodiment, in the same manner as in the first embodiment, at room temperature, P + was ion-implanted at an acceleration energy of 200 keV and a dose of 4×10 13 cm-2 The first ion implantation with ion implantation at [temperature] and, at room temperature, P + was ion implanted in two steps: the second ion implantation with ion implantation at an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 . Then, the implanted element was changed compared to the first embodiment, and the dose was made higher than that of the first embodiment. At room temperature, Si + was ion implanted at an acceleration energy of 70 keV and a dose of 1×10 15 cm -2 . Other manufacturing conditions were the same as those of the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0095] Regarding the silicon carbide semiconductor device of the fourth embodiment, the SiC surface was analyzed by EBSD, and when the ratio of the crystal phase was calculated, the ratio of 3C was 85%. Therefore, it can be seen that increasing the dose of Si + increased the ratio of 3C compared to the third embodiment.

[0096] <Fifth Embodiment> As a fifth embodiment, in the same manner as in the first embodiment, at room temperature, P + was ion implanted in two steps: the first ion implantation with ion implantation at an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 , and the second ion implantation with ion implantation at an acceleration energy of 85 keV and a dose of 3×10 + cm 13 . Then, the ion species was changed compared to the first embodiment, and at room temperature, carbon ions (C -2 ) were ion implanted at an acceleration energy of 70 keV and a dose of 1×10 + cm 15 . Other manufacturing conditions were the same as those of the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured. -2

[0097] Regarding the silicon carbide semiconductor device of the fifth embodiment, the SiC surface was analyzed by EBSD, and when the ratio of the crystal phase was calculated, the ratio of 3C was 70%. Therefore, compared to the first embodiment, Ar +Instead of C + When ion implantation is performed on + , it can be seen that the ratio of 3C is the same.

[0098] <Sixth Embodiment> As a sixth embodiment, similar to the first embodiment, at room temperature, P + was ion-implanted in two steps: a first ion implantation with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 and a second ion implantation with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 Then, the implanted element was changed from that of the first embodiment, and the dose was increased compared to the first embodiment. At room temperature, C + was ion-implanted with an acceleration energy of 70 keV and a dose of 3×10 15 cm -2 Other manufacturing conditions were the same as those of the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0099] Regarding the silicon carbide semiconductor device of the sixth embodiment, the SiC surface was analyzed by EBSD, and the ratio of the crystal phase was calculated. The ratio of 3C was 85%. Therefore, it can be seen that increasing the dose of C + increased the ratio of 3C compared to the fifth embodiment.

[0100] <Comparative Example> As a comparative example, similar to the first embodiment, at room temperature, P + was ion-implanted in two steps: a first ion implantation with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 and a second ion implantation with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 Then, the ion species was changed from that of the first embodiment, and at room temperature, P, which is an n-type impurity + was ion-implanted with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2Ion implantation was performed. Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0101] Regarding the silicon carbide semiconductor device of the comparative example, when measuring the leakage current (Idss) between the source and drain, it became 1×10 -5 A. Therefore, it can be seen that when P + was ion-implanted instead of Ar + , the leakage current increased.

[0102] Next, the seventh to ninth embodiments will be described with reference to Table 2 below.

[0103]

Table 2

[0104] <Seventh Embodiment> As the seventh embodiment, the number of stages, acceleration energy, and dose amount were changed from those in the first embodiment, and at room temperature, P + was ion-implanted in one stage with an acceleration energy of 120 keV and a dose amount of 5×10 13 cm -2 . Then, in the same manner as in the first embodiment, at room temperature, Ar + was ion-implanted with an acceleration energy of 70 keV and a dose amount of 2×10 14 cm -2 . Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0105] Regarding the silicon carbide semiconductor device of the seventh embodiment, when measuring the leakage current (Idss) between the source and drain, it became 5×10 -6 A. Therefore, it can be seen that the leakage current is equivalent to that in the first embodiment, and the leakage current can be suppressed more than in the comparative example.

[0106] <Eighth Embodiment> As the eighth embodiment, in the same manner as in the seventh embodiment, at room temperature, P + was ion-implanted with an acceleration energy of 120 keV and a dose amount of 5×1013 cm -2 was ion-implanted in one step. Then, the ion species were changed from those in the seventh embodiment, and at room temperature, Si + was ion-implanted at an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 . Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0107] When measuring the leakage current (Idss) between the source and the drain of the silicon carbide semiconductor device of the eighth embodiment, it was 1×10 -6 A. Therefore, it can be seen that when Si + was ion-implanted instead of Ar + , the leakage current can be further suppressed. From this, it can be inferred that when Si + is ion-implanted, the formation of crystal defects is suppressed when the crystal structure changes to 3C more than when Ar + is ion-implanted.

[0108] <Ninth Embodiment> As the ninth embodiment, in the same manner as in the seventh embodiment, at room temperature, P + was ion-implanted in one step at an acceleration energy of 120 keV and a dose of 5×10 13 cm -2 . Then, the ion species, acceleration energy, and dose were changed from those in the seventh embodiment, and at room temperature, C + was ion-implanted at an acceleration energy of 30 keV and a dose of 1×10 15 cm -2 . Other manufacturing conditions were the same as those in the first embodiment, and a silicon carbide semiconductor device with a breakdown voltage of 1200 V was manufactured.

[0109] When measuring the leakage current (Idss) between the source and the drain of the silicon carbide semiconductor device of the ninth embodiment, it was 1×10 -6 A. Therefore, it can be seen that when C + was ion-implanted instead of Ar + , the leakage current can be further suppressed. From this, C +When ion implantation is performed, Ar + It can be presumed that the formation of crystal defects is suppressed when the crystal structure changes to 3C as compared with the case of ion implantation.

[0110] (Second Embodiment) The silicon carbide semiconductor device according to the second embodiment has the same configuration as the silicon carbide semiconductor device according to the first embodiment shown in FIG. 1. As shown in FIG. 16, the manufacturing method of the silicon carbide semiconductor device according to the second embodiment is different from the manufacturing method of the silicon carbide semiconductor device according to the first embodiment in that the activation annealing process for the ion implantation region other than the source contact portion 72 in step S23 and the activation annealing process for the source contact portion 72 in step S25 are performed separately.

[0111] The procedure before the n + type source extension portion forming step in step S21 of FIG. 16 is substantially the same as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so redundant descriptions are omitted. The n + type source extension portion forming step in step S21 of FIG. 16 is the same as the n + type source extension portion forming step in step S11 of FIG. 4. As shown in FIG. 9, at room temperature, an n-type impurity such as P is ion implanted to form an n + type source extension portion 71.

[0112] The p + type contact region forming step in step S22 of FIG. 16 is the same as the p + type contact region forming step in step S13 of FIG. 4. As shown in FIG. 11, p-type impurities are ion implanted to form p + type base contact regions 8a, 8b. At this time, the n + type source contact portion 72 is not formed.

[0113] The activation annealing process of step S23 in FIG. 16 is the same as the activation annealing process of step S14 in FIG. 4. For example, by performing activation annealing at about 1600 °C or higher and 1900 °C or lower, the p-type impurities or n-type impurities ion-implanted into the first implanted regions 4a, 4c, the gate bottom protection region 4b, the second implanted regions 5a, 5b, the source extension portion 71, the base contact regions 8a, 8b, etc. are simultaneously activated. At this time, the n + -type source contact portion 72 is not formed.

[0114] The n + -type source contact portion forming process of step S24 in FIG. 16 is the same as the n + -type source contact portion forming process of step S12 in FIG. 4. As shown in FIG. 10, at room temperature, by ion-implanting Ar, Si, or C, the n + -type source contact portion 72 is formed. Due to the damage caused by ion implantation, the 4H-SiC contained in the source contact portion 72 is broken down, and an amorphous structure is formed.

[0115] The activation annealing process of step S25 in FIG. 16 is performed at a temperature lower than that of the activation annealing process of step S23 in FIG. 16, for example, at about 1300 °C or higher and 1500 °C or lower, to activate the n-type impurities ion-implanted into the source contact portion 72. At this time, the amorphous structure of the source contact portion 72 is recrystallized to become 3C-SiC, thereby forming the source contact portion 72 containing 3C-SiC.

[0116] The trench forming process of step S26 in FIG. 16 is the same as the trench forming process of step S15 in FIG. 4. As shown in FIG. 12, the trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72 by dry etching technology or the like.

[0117] The gate insulating film / gate electrode formation step S27 in FIG. 16 is the same as the gate insulating film / gate electrode formation step S16 in FIG. 4. As shown in FIG. 13, an insulating gate type electrode structure (11, 12) composed of a gate insulating film 11 and a gate electrode 12 is embedded inside the trench 10. The procedures after the gate insulating film / gate electrode formation step S27 in FIG. 16 are substantially the same as those in the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so duplicate explanations are omitted.

[0118] According to the manufacturing method of the silicon carbide semiconductor device according to the second embodiment, similar to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, the source regions 7a and 7b can be in ohmic contact with the source electrodes (14, 15), and a trench gate type silicon carbide semiconductor device capable of suppressing the leakage current between the source and drain can be realized.

[0119] Furthermore, according to the manufacturing method of the silicon carbide semiconductor device according to the second embodiment, the activation annealing step for the ion implantation regions other than the source contact portion 72 in step S23 and the activation annealing step for the source contact portion 72 in step S25 are performed separately. The crystal defects of 3C-SiC in the source contact portion 72 occur when the amorphous structure recrystallizes during activation annealing. Since the activation annealing step in step S25 is performed at a lower temperature than the activation annealing step in step S23, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed.

[0120] (Third Embodiment) The silicon carbide semiconductor device according to the third embodiment has the same configuration as the silicon carbide semiconductor device according to the first embodiment shown in FIG. 1. The manufacturing method of the silicon carbide semiconductor device according to the third embodiment is different from the manufacturing method of the silicon carbide semiconductor device according to the first embodiment in that the heat treatment (PDA) in the gate insulating film / gate electrode formation step S36 in FIG. 17 also serves as the activation annealing of the source contact portion 72, as shown in FIG. 17.

[0121] The n in step S31 of FIG. 17+ The steps before the p-type source extension portion forming step are substantially the same as those in the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so duplicate descriptions are omitted. In step S31 of FIG. 17, n + The p-type source extension portion forming step is the same as the p-type source extension portion forming step in step S11 of FIG. 4. As shown in FIG. 9, at room temperature, by ion-implanting an n-type impurity such as P, n + a p-type source extension portion 71 is formed. +

[0122] In step S32 of FIG. 17, the p + type contact region forming step is the same as the p-type contact region forming step in step S13 of FIG. 4. As shown in FIG. 11, by ion-implanting a p-type impurity, p + type base contact regions 8a and 8b are formed. At this time, n + type source contact portion 72 is not formed. +

[0123] In step S33 of FIG. 17, the activation annealing step is the same as the activation annealing step in step S14 of FIG. 4. For example, by performing activation annealing at about 1600 °C or higher and 1900 °C or lower, the p-type impurities or n-type impurities ion-implanted into the first embedded regions 4a and 4c, the gate bottom protection region 4b, the second embedded regions 5a and 5b, the source extension portion 71, and the base contact regions 8a and 8b are simultaneously activated. At this time, n + type source contact portion 72 is not formed.

[0124] In step S34 of FIG. 17, the n + type source contact portion forming step is the same as the n-type source contact portion forming step in step S12 of FIG. 4. As shown in FIG. 10, at room temperature, by ion-implanting Ar, Si, or C, n + a type source contact portion 72 is formed. Due to the ion implantation damage, the 4H-SiC contained in the source contact portion 72 is broken down, and an amorphous structure is formed. +

[0125] The trench formation step S35 in FIG. 17 is the same as the trench formation step S15 in FIG. 4. As shown in FIG. 12, the trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72 by a dry etching technique or the like.

[0126] The gate insulating film / gate electrode formation step S36 in FIG. 17 is the same as the gate insulating film / gate electrode formation step S16 in FIG. 4. As shown in FIG. 13, the gate insulating film 11 is formed inside the trench 10. When forming the gate insulating film 11, a heat treatment is performed at a temperature lower than that of the activation annealing step S33 in FIG. 17, for example, about 900°C or higher and 1350°C or lower. By this heat treatment, the n-type impurities ion-implanted into the source contact portion 72 are activated. At this time, the amorphous structure of the source contact portion 72 is recrystallized to become 3C-SiC, and thus the source contact portion 72 containing 3C-SiC is formed. Then, the gate electrode 12 is embedded inside the trench 10, and an insulated gate type electrode structure (11, 12) composed of the gate insulating film 11 and the gate electrode 12 is formed.

[0127] The procedure after the gate insulating film / gate electrode formation step S36 in FIG. 17 is substantially the same as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, and thus the overlapping description is omitted.

[0128] According to the manufacturing method of the silicon carbide semiconductor device according to the third embodiment, similar to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, the source regions 7a and 7b can be ohmic - contacted with the source electrodes (14, 15), and a trench gate type silicon carbide semiconductor device capable of suppressing the leakage current between the source and the drain can be realized.

[0129] Furthermore, according to the method for manufacturing a silicon carbide semiconductor device according to the third embodiment, the crystal defects of 3C-SiC in the source contact portion 72 are generated when the amorphous structure recrystallizes during activation annealing. However, since the heat treatment in the gate insulating film / gate electrode formation step of step S36 is performed at a lower temperature than the activation annealing step of step S33, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed. Furthermore, since the heat treatment in the gate insulating film / gate electrode formation step of step S36 also serves as the activation annealing of the source contact portion 72, an increase in man-hours can be suppressed.

[0130] (Other Embodiments) As described above, although the first to third embodiments of the present disclosure have been described, the discussions and drawings that form a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0131] For example, although a MOSFET has been exemplified as the semiconductor device according to the first to third embodiments, an insulated gate bipolar transistor (IGBT) having a configuration in which a p-type collector region is provided instead of the n-type drain region 1 is also applicable. In addition to a single IGBT, it is also applicable to a reverse-conducting IGBT (RC-IGBT) and a reverse-blocking insulated gate bipolar transistor (RB-IGBT). + type collector region provided instead of the + type drain region 1 is also applicable. In addition to a single IGBT, it is also applicable to a reverse-conducting IGBT (RC-IGBT) and a reverse-blocking insulated gate bipolar transistor (RB-IGBT).

[0132] In addition, the configurations disclosed in the first to third embodiments can be appropriately combined within a range where no contradiction occurs. Thus, the present disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention-specific matters according to the appropriate claims based on the above description.

Description of Reference Numerals

[0133] 1... Drain region (SiC substrate) 2... Drift layer 3... Current diffusion layer 3a, 3b…n-type layer 4a, 4c…first buried region 4b…gate bottom protection region 5a, 5b…second buried region 6, 6a, 6b…base region 7a, 7b, 7x…source region 8a, 8b…base contact region 10…trench 11…gate insulating film 12…gate electrode 12a…upper surface 13…interlayer insulating film 13a, 13b…contact hole 14…barrier metal layer 15…source wiring electrode 16…drain electrode 21~23…oxide film 71, 71a, 71b…source extension 71x…lower surface 72, 72a, 72b…source contact portion 72x…lower surface

Claims

1. A step of forming a second conductivity type base region made of silicon carbide on the upper surface side of a first conductivity type drift layer made of silicon carbide; A step of forming a first conductivity type main region made of silicon carbide on the upper surface side of the base region; A step of forming a trench penetrating the main region and the base region; A step of forming a gate insulating film inside the trench; A step of embedding a gate electrode through the gate insulating film inside the trench; A step of forming a main electrode in contact with the main region; comprising The step of forming the main region is By ion implanting a first conductivity type impurity at room temperature, a first region including a 4H structure is formed on the upper surface side of the base region, By ion implanting at least one of silicon, carbon, and argon at room temperature, a second region including a 3C structure is formed on the upper surface side of the first region so as to be in contact with the main electrode including this, a method for manufacturing a silicon carbide semiconductor device.

2. The first conductivity type impurity is phosphorus or nitrogen The method for manufacturing a silicon carbide semiconductor device according to Claim 1.

3. The dose amount of ion implantation of the impurity of the first conductivity type is 5×10 １３ cm －２ or less The method for manufacturing a silicon carbide semiconductor device according to Claim 1 or 2.

4. By ion implanting silicon or carbon, the second region is formed The method for manufacturing a silicon carbide semiconductor device according to Claim 1 or 2.

5. By ion implanting argon, the second region is formed The method for manufacturing a silicon carbide semiconductor device according to Claim 1 or 2.

6. The upper surface of the position of the gate electrode in contact with the gate insulating film is deeper than the lower surface of the second region and shallower than the lower surface of the first region The method for manufacturing a silicon carbide semiconductor device according to Claim 1 or 2.

7. A first conductivity type drift layer made of silicon carbide; A second conductivity type base region made of silicon carbide provided on the upper surface side of the drift layer; A first conductivity type main region made of silicon carbide provided on the upper surface side of the base region; A gate insulating film provided inside a trench penetrating the main region and the base region; A gate electrode embedded through the gate insulating film inside the trench; A main electrode provided in contact with the main region; comprising The main region is A first region including a 4H structure provided on the upper surface side of the base region; A second region provided in contact with the main electrode on the upper surface side of the first region, and having a ratio of at least the upper surface side 3C structure of 70% or more; comprising A silicon carbide semiconductor device.

8. The second region contains argon The silicon carbide semiconductor device according to claim 7 **Claim 9** The ratio of the 3C structure on at least the upper surface side of the second region is 85% or more The silicon carbide semiconductor device according to claim 7 or 8

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