Digital protection control system and digital protection control method

Abstract

To solve the problem in which: in a protection control system in which a MU and an IED are separated from each other, when a sampling period of the MU and the period of processing executed by the IED are different from each other, desired characteristics as the IED may not be obtained.SOLUTION: A digital protection control system has a first digital filter, a second digital filter, and a protection control operation unit. Upon input of first data obtained by sampling a measured value of an electric power system with a first sampling frequency, the first digital filter removes a folding component at the first sampling frequency from the first data and outputs second data obtained by sampling the measured value with a second sampling frequency. Upon input of the second data, the second digital filter removes a low-order harmonic component of the electric power system included in the input second data. The protection control operation unit performs protection control processing on the electric power system on the basis of the second data from which the low-order harmonic component is removed, and outputs a result of the processing.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a digital protection control system, and more particularly to a digital protection control system suitable for converting data of analog input amounts sampled at different sampling rates into data of a desired sampling rate and performing protection control calculations.

Background Art

[0002] For removing faults such as short circuits and ground faults occurring in transmission lines, buses, transformers, and generators constituting a power system, protection devices installed for each element operate on faults occurring within their protection ranges, and the section of the power system including the fault point is disconnected by a circuit breaker.

[0003] In a protection device, voltage and current signals indicating the state of the system are captured, converted into digital values, and then a system accident is discriminated by software processing using a digital arithmetic function.

[0004] In current digital protection control systems, conversion from analog signals to digital data is performed at an electrical angle of 3.75°. After removing low-order harmonic signal components unnecessary for protection control calculations using a digital filter, data for protection control calculations is generated every 30° of electrical angle, and protection and sequence processing are generally performed. Since accurate protection control processing can be performed by these calculations, they are applied to many substations and contribute to the stable operation of the power system.

[0005] On the other hand, as a digital protection control system utilizing digital communication technology, it has evolved into a system configuration for a digital substation that divides into an analog input section called a merging unit (hereinafter referred to as MU) and a protection control calculation section (hereinafter referred to as IED), and connects them by digital communication called a process bus, and standardization for wiring reduction and digitization is progressing.

[0006] In this digital substation, as described above, since the functions are separated between the MU and the IED, and connections may be made between products of different vendors, the interface between them becomes an important item when constructing the system.

[0007] Regarding the communication interface between this MU and the IED, particularly in the part that generates analog sample values (hereinafter referred to as SV) within the MU, what sampling frequency (sampling rate) to adopt becomes an important specification item among vendors. In Japan, sampling at an electrical angle of 3.75° is common and unified among vendors, but in MUs manufactured according to international standards such as IEC61850 and IEC61869, a sampling frequency of 4.5° electrical angle is defined as the standard.

[0008] Therefore, when simply combined with an MU that sends data with a sampling rate different from the domestic specification, there arises a problem that the desired characteristics cannot be satisfied. Also, in order to match the sampling rate to the international standard, it is necessary to change the protection control operation algorithm based on an electrical angle of 30°. Against this background, a configuration has been proposed to correct and process data to the sampling rate required by the existing operation algorithm from the SV values received within the IED.

[0009] In International Publication No. 2018 / 042587 (Patent Document 1), in an IED, after receiving SV data from an MU, an up-conversion unit for increasing the sampling rate is provided, the SV data is made into a high sampling rate and interpolated (previous value interpolation), and then, by periodically extracting data points at arbitrary sample times that can be changed from the time-series data, a method for generating time-series data with a low sampling rate for performing protection relay operations has been proposed.

[0010] In the 71st Volume, No. 1 of the Electrical Joint Research (Non-Patent Document 1), it is shown that when adapting the algorithm of the protection relay to the 4.5° sampling that is mainstream among overseas manufacturers, a huge amount of labor is required for redesigning and re-verifying the relay algorithm.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Non-Patent Documents

[0012]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0013] In domestic protection control systems, as described above, it is common to perform operations at an electrical angle of 3.75°. However, when combined with a MU compliant with international standards such as IEC61850 and IEC61869, problems occur where timing coordination cannot be achieved, correct SV data cannot be recognized, and desired characteristics as an IED cannot be obtained.

[0014] Although it is possible to make the corresponding adjustments by reviewing the processing on the IED side for an electrical angle of 4.5°, since the conventional protection control operation algorithms based on SV data with an electrical angle of 3.75° cannot be directly applied, it is necessary to review all related protection control operation algorithms, which requires a huge amount of working time and verification time and has a large impact.

[0015] In Patent Document 1, as described above, a method of providing an up-conversion unit to convert the sampling rate is disclosed as a method that can be utilized even when the sampling frequencies of MUs are different.

[0016] However, in this Patent Document 1, for the conversion of the sampling rate, it is necessary to provide an up-conversion unit for once increasing the sampling rate, so the circuit scale becomes large, and since it is necessary to perform the sampling rate conversion process at the speed of upsampling, it is necessary to complete this process in a short time, so there is a problem of a limitation in the number of received channels of the SV data that can be processed.

[0017] Also, in Non-Patent Document 1, when adapting the algorithm of the protection relay to the mainstream 4.5° sampling by overseas manufacturers, it is shown that a huge amount of labor is required for redesigning and re-verifying the relay algorithm, and although it is described that it is necessary to consider making it possible to easily apply existing software assets in the study, no information has been disclosed up to the specific method.

Means for Solving the Problems

[0018] In order to solve at least one of the above problems, the present invention is a digital protection control system, which includes a first digital filter, a second digital filter, and a protection control arithmetic unit. When the first digital filter receives first data obtained by sampling measurement values of a power system at a first sampling frequency, it removes the aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency. When the second digital filter receives the second data, it removes the low-order harmonic components of the power system included in the input second data. The protection control arithmetic unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed and outputs the result.

Effects of the Invention

[0019] According to one aspect of the present invention, without converting the SV data to a high sampling rate associated with resampling within the IED, the sampling rate can be converted at a 3.75° period. Therefore, since there is no need to provide high-speed conversion operation means for the conversion, miniaturization and low power consumption of the conversion means of the IED can be achieved. As a result, since software assets that perform existing protection control operations based on an electrical angle of 3.75° can be reused, proven protection control operation processing can be applied as it is, so there is an effect that cost reduction can be achieved while maintaining reliability. In addition, since a system configuration combined with MUs having different sampling rates can be constructed, there is an effect that the flexibility of system construction can be improved.

[0020] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of Drawings

[0021]

Figure 1

Figure 2

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Figure 10

Figure 11

Figure 12

Mode for Carrying Out the Invention

[0022] First, an overview of the embodiments of the present invention will be described.

[0023] In the first embodiment (Example 1) of the present invention, the above-described problems are solved. Without performing an upsampling operation to increase the sampling rate by using SV data sampled at an electrical angle of 4.5° from the MU as an input, the filter coefficients that determine the characteristics of a band-limiting filter provided as a first digital filter for removing aliasing (hereinafter referred to as aliasing) are switched so as to perform an operation equivalent to upsampling.

[0024] Even if upsampling is performed and 0 data is interpolated, since the operation result becomes 0 in the digital filter operation, the band-limiting filter, which is the first digital filter, is configured so as not to perform this operation, and it is made to operate in a configuration decomposed into multiple phases (referred to as polyphase).

[0025] In this way, before performing the protection control operation using the electrical angle 3.75° data, generation of data to be upsampled at a period shorter than 3.75° is eliminated.

[0026] In the system of the present disclosure, a grand master clock (hereinafter referred to as GMC) is provided in a LAN of the same domain, and a plurality of MUs that send out SV data with an electrical angle of 4.5° and an IED that resamples this SV data to 3.75° and performs protection control calculation are synchronized in sampling for the entire system. By doing so, stable resampling can be performed so as to eliminate unnecessary timing deviations when resampling with the above-described configuration.

[0027] Further, in the second embodiment (Example 2) of the present invention, based on the above-described Example 1, by replacing the first digital filter for removing aliasing with the digital filter for harmonic removal executed by the protection control calculation unit, the function of this digital filter is also used, and aliasing can also be removed, and the delay of the digital filter for removing aliasing is eliminated.

[0028] Next, the embodiments of the present invention will be described in detail with appropriate reference to the drawings.

Example

[0029] FIG. 1 shows a processing block configuration example of the entire protection control function system according to the first embodiment of the present invention. The function of the overall processing will be described with reference to FIG. 1.

[0030] In FIG. 1, the substation protection control system S1 is composed of a plurality of merging units (MUs) 101a, 101b, 101c and a protection control unit (IED) 100. The merging units (MUs) 101a, 101b, 101c take in analog voltage and current signals L100a, L100b, L100c from substation equipment such as circuit breakers, and send out data (SV data) of analog instantaneous values after A / D conversion toward the process bus L100. The protection control unit (IED) 100 performs protection control calculation and issues an operation command signal to the MU for the operation of substation equipment such as circuit breakers.

[0031] In the above-described configuration, a plurality of MUs such as MU101a and the IED100 exchange time synchronization packets with a grandmaster clock (GMC) 102 for achieving time synchronization of the entire substation, and operate to achieve a predetermined synchronization accuracy in reflection of sampling synchronization control.

[0032] In order to perform synchronization in accordance with a standardized procedure such as the international standard IEC61588, the GMC 102 exchanges synchronization packets with slave MUs MU101a, 101b, 101c and the IED100 serving as synchronization masters, for example, at a fixed period of 1 second. By adjusting their own clock timings for time synchronization between the MUs MU101a, 101b, 101c and the IED100, the start points of data are aligned in units of the least common multiple (22.5°×n: n is an integer) for the MUs MU101a, 101b, 101c operating at 4.5° and the IED100 operating at 3.75°.

[0033] The IED100 is composed of an input means 1, a synchronization control means 2, a first digital filter (DF1) 3, a filter coefficient transmission means 4, a data buffer means 8, a second digital filter means (DF2) 9, a protection control calculation / SEQ processing means 10, and an output means 11.

[0034] The input means 1 receives the SV data obtained by A / D converting the analog input signals L100a to L100c captured by each MU from the master device. The synchronization control means 2 extracts a synchronization control packet from the signal L101 received and processed by the input means 1 and performs synchronization control. The first digital filter 3 removes the aliasing component. The filter coefficient sending means 4 sends out the filter coefficient L105 necessary for the filter operation performed by the first digital filter 3. The data buffer means 8 accumulates the filter operation output data L106 of the first digital filter 3 and sends out the data L107 after accumulation. The second digital filter means 9 sends out a signal L108 obtained by removing the low-order harmonic signal component of the power system included in the data L107. The protection control calculation and SEQ processing means 10 performs protection control calculation and sequence processing using the data from which the low-order harmonic component has been removed. The output means 11 sends out an operation command signal to the power equipment associated with the processing result to the MU101a, etc.

[0035] In the IED100, the consistent processing functions from the input means 1 to the data buffer 8 are configured by hardware such as a field programmable gate array (hereinafter referred to as FPGA).

[0036] Therefore, the synchronization control means 2 synchronizes with the GMC102 by a time synchronization control method defined in, for example, IEC61588, and gives a timing control signal L103 to the first digital filter 3 and a timing control signal L104 to the filter coefficient sending means 4, so that the hardware circuits of the first digital filter 3 and the filter coefficient sending means 4 operate in conjunction.

[0037] The filter coefficient transmission means 4 implemented in the IED 100 is composed of a filter coefficient group 5, a selection means 6, and a phase calculation means 7. The filter coefficient group 5 stores filter coefficients by determining a combined configuration of filter coefficients in advance. The phase calculation means 7 detects the phase at the current timing based on the timing control signal L104. The selection means 6 selects one from the filter coefficient group 5 based on the phase detected by the phase calculation means 7 and gives it to the filter means 3. These series of operations also operate based on a time-synchronized signal.

[0038] Also, although not shown in FIG. 1, a series of operations from the second digital filter means (DF2) 9 to the output means 11 are realized by the software of the CPU. The configuration as these hardware will be described later with reference to the drawings (see FIG. 5).

[0039] FIG. 12 shows the correspondence relationship between the sampling timing, the input data, and the filter coefficients in the embodiment of the present invention.

[0040] Specifically, FIG. 12 is a diagram for explaining the operation of an interpolation filter for area aliasing removal installed after upsampling, which is generally known.

[0041] Generally, this interpolation filter is composed of a FIR (Finite Impulse Response) type low-pass filter (LPF) without a feedback loop.

[0042] The data passing through this filter enters from the left and exits to the right as shown in FIG. 12. The direction from top to bottom in the figure is described as indicating the flow of time. In the figure, Xn represents the input data, n of Xn represents the order of the input data, negative represents the input data before X0, X-1 is the input data one before X0, and X-7 is the input data seven before X0. hn (h0~h47) represents the filter coefficients of the interpolation filter.

[0043] In this example, when L = 6, that is, an example of 6-fold upsampling is shown.

[0044] The function for upsampling (referred to as an upsampler here) inserts zero data between each of the input data X0, X1, X2... Xn. In this example, five zero data are inserted. Here, the FIR-type LPF, which is an interpolation filter, performs the following operations. As examples, the cases of an electrical angle of 0° and 3.75° are shown by the following equations.

[0045] (Equation 1) For the case of an electrical angle of 0°: Yn = h0·(X0)+h6·(X-1)+h12·(X-2)+h18·(X-3)+ h24·(X-4)+h30·(X-5)+h36·(X-6)+h42·(X-7) For the case of an electrical angle of 3.75°: Yn = h5·(X0)+h11·(X-1)+h17·(X-2)+h23·(X-3)+ h29·(X-4)+h35·(X-5)+h41·(X-6)+h47·(X-7)

[0046] Here, as shown in the figure, in order to insert zero data between each of the input data, the filter operation during this period becomes filter coefficient · zero data, and the operation result becomes zero.

[0047] Therefore, it is only necessary to perform the operation only on the part where the input data exists. Also, although the filter operation with a short period interpolated by zero data can be obtained as an operation result, the time interval of the data for converting the sampling rate may be an electrical angle of 3.75°, and an operation result with a finer granularity is not necessary.

[0048] For example, when configuring an aliasing removal filter for a 48-tap FIR-type LPF, there are 48 filter coefficients from h0 to h47. To obtain the calculation results every 3.75° of electrical angle, at 0° of electrical angle, it is only necessary to perform the calculation when using the coefficients of h0, h6, h12, h18, h24, h30, h36, and h42, and there is no need to perform the calculation using other coefficients.

[0049] Similarly, to obtain the calculation result after 3.75° of electrical angle has elapsed, it is only necessary to perform the calculation when using the coefficients of h5, h11, h17, h23, h29, h35, h41, and h47.

[0050] By performing this calculation while changing the filter coefficients every 3.75° of electrical angle, it becomes unnecessary to insert zero data and perform upsampling processing, and there is no need to shorten the calculation cycle. That is, the operation of upsampling with zero data can be eliminated.

[0051] Next, the filter operation of aliasing removal will be described with reference to FIGS. 1 and 2.

[0052] FIG. 2 shows a configuration example of a digital filter that removes aliasing in resampling according to Embodiment 1 of the present invention.

[0053] First, the details of the filter coefficient sending means 4 in FIG. 1 are shown in FIG. 2(a).

[0054] In FIG. 2(a), the filter coefficient group 20 is composed of a combination of six sets of filter coefficients 200 to 205. This corresponds to the filter coefficient group 5 in FIG. 1. The filter coefficient selection circuit 21 corresponds to the selection means 6 in FIG. 1, and based on the result of the phase calculation by the phase calculation means 7 in FIG. 1, it selects the necessary coefficient group from a plurality of (in this embodiment, six-element) filter coefficient groups and sets it in the filter coefficient storage register 22.

[0055] Note that the least common multiple of the sampling period of the input data of the first digital filter (DF1) 3 (electrical angle 4.5° in this embodiment) and the sampling period of the output data (electrical angle 3.75° in this embodiment) (electrical angle 22.5° in this embodiment) needs to be divided by the latter period, and the same number of filter coefficient groups as the resulting value (6 in this embodiment) need to be prepared.

[0056] This setting operation is performed at a constant period (cyclic) every 3.75° of electrical angle.

[0057] Figure 2(b) shows the configuration of the FIR type LPF for performing aliasing removal. This FIR type LPF corresponds to the first digital filter (DF1) 3 shown in Figure 1.

[0058] In Figure 2(b), the FIR type LPF is composed of delay elements 23a to 23d that delay the input data every one operation cycle, multipliers 24a to 24e that multiply the input data and the data obtained by delaying the input data by filter coefficients, and an addition circuit 25 that adds the operation results of each multiplier. The addition result becomes the output Y(n) of the aliasing removal filter.

[0059] Here, when the number of taps of the FIR type LPF is 48 taps, the total number of filter coefficients is 48, namely h0 to h47. The combinations of the filter coefficients of each filter coefficient group are as follows, and the filter operation is divided for each phase. That is, the filter for aliasing removal is polyphased.

[0060] Coefficients Gr1…h0, h6, h12, h18, h24, h30, h36, h42 Coefficients Gr2…h1, h7, h13, h19, h25, h31, h37, h43 Coefficients Gr3…h2, h8, h14, h20, h26, h32, h38, h44 Coefficients Gr4…h3, h9, h15, h21, h27, h33, h39, h45 Coefficients Gr5…h4, h10, h16, h22, h28, h34, h40, h46 Coefficients Gr6…h5, h11, h17, h23, h29, h35, h41, h47

[0061] The hardware that executes the calculation has the configuration shown in Fig. 2(b), and takes in and calculates a group of filter coefficients selected at each time corresponding to the phase.

[0062] The filter coefficients are pre-designed for the frequency-gain characteristics for aliasing removal, and the coefficients for each tap from h0 to h47 are obtained and stored in the storage area for the coefficient group.

[0063] Fig. 3 shows an example of the operation timing of a digital filter that removes the folding component of resampling according to Embodiment 1 of the present invention.

[0064] Referring to Fig. 3, an example of the operation timing of the aliasing removal filter shown in Fig. 2 will be described. Fig. 3(a) shows the sampling timing of an electrical angle of 4.5°, and data is taken out at intervals of T1 which is a 4.5° period.

[0065] Fig. 3(b) shows an example of the data update timing of an electrical angle of 4.5°. Here, an example of Data(t0) to Data(t4) is shown, and the data is updated according to the timing of Fig. 3(a).

[0066] Fig. 3(c) shows the data update timing of an electrical angle of 3.75°, and Fig. 3(d) shows the timing for performing the calculation of the aliasing removal filter every 3.75° of electrical angle. These series of operations are cyclically repeated.

[0067] At the timing of t0 in Fig. 3(d), the coefficient of coefficient Gr1_200 is taken in from the group of filter coefficients at the start of the process, and the filter calculation shown in Fig. 2(b) is performed.

[0068] The combinations of eight data items taken into the filter operations at each time for the aliasing removal filter are shown below. What is described as X-7 to X5 of DF(t0) to DF(t7) represents the SV data sampled at the timing of an electrical angle of 4.5°. That is, each SV data is updated every 4.5° of electrical angle. Note that Fig. 3 shows DF(t0) to DF(t5) and X0 to X-4, and the others are omitted.

[0069] For example, X-7 represents the data acquired 7 samples before the X0 time point, DF(t1) represents the operation using the data of X0 to X-7 at an electrical angle of 4.5°, and DF(t2) represents the operation using the data from the data X1 to X-6 at an electrical angle of 4.5°. For example, DF(t2) represents 1 sample after DF(t1) at an electrical angle of 3.75°.

[0070] DF(t0)…X0,X-1,X-2,X-3,X-4,X-5,X-6,X-7 DF(t1)…X0,X-1,X-2,X-3,X-4,X-5,X-6,X-7 DF(t2)…X1,X0,X-1,X-2,X-3,X-4,X-5,X-6 DF(t3)…X2,X1,X0,X-1,X-2,X-3,X-4,X-5 DF(t4)…X3,X2,X1,X0,X-1,X-2,X-3,X-4 DF(t5)…X4,X3,X2,X1,X0,X-1,X-2,X-3 DF(t6)…X5,X4,X3,X2,X1,X0,X-1,X-2 DF(t7)…X5,X4,X3,X2,X1,X0,X-1,X-2

[0071] In the aliasing removal filter, the filter operation is repeated using the plurality of SV data shown above. However, due to the relationship between the periods of the electrical angles of 4.5° and 3.75°, 5 data items of 4.5° of electrical angle and 6 data items of 3.75° of electrical angle can be obtained within the least common multiple electrical angle of 22.5°.

[0072] Therefore, in the above example, like DF(t0) and DF(t1), and DF(t6) and DF(t7), out of the six operation patterns of the electrical angle of 3.75°, two operations will be performed using the SV data of the same electrical angle of 4.5°. However, the filter coefficients used for the filter operation of alias removal are updated and calculated every 3.75° of the electrical angle.

[0073] When the synchronization between the electrical angles of 4.5° and 3.75° cannot be achieved, that is, when the timing of data update slips, the operations in the above timing relationship cannot be performed, so the desired characteristics cannot be obtained. Therefore, it is essential to synchronize the MU on the data transmission side and the IED on the reception side. That is, it is necessary to perform synchronization control so that the synchronization points match at the timing of the electrical angle of 22.5°, which is the least common multiple of the electrical angles of 4.5° and 3.75°.

[0074] Although it is also possible to achieve this by performing synchronization control at the timing of the electrical angle of 22.5°, it can be addressed by controlling at a fixed period (for example, a 1s period, etc.) using a general time synchronization protocol due to the frequency deviation of the clock oscillators implemented in the MU and IED.

[0075] Next, the time synchronization method will be described with reference to FIG. 4.

[0076] FIG. 4 shows an example of the timing of time synchronization according to Embodiment 1 of the present invention.

[0077] FIG. 4(a) describes the time synchronization of a two-terminal configuration of a master station and a slave station.

[0078] Here, the master station corresponds to the GMC102 shown in FIG. 1. On the other hand, the slave stations correspond to the MU101a to 101c and the IED100 shown in FIG. 1.

[0079] This time synchronization method is the one specified by IEEE1588 or IEC61588, and it is meaningful to apply this method to stably perform the conversion of the sampling rate. The description of the operation will be limited to an outline. Also, the following method is an example, and other methods may be adopted as long as the time synchronization can be realized with high precision.

[0080] First, the master station transmits a transmission packet (SYNC) L401 for synchronizing control to the slave station.

[0081] Next, the master station transmits the time data t1 at the time when the above SYNC signal is sent to the slave station in the next transmission packet (Follow - UP) L402.

[0082] On the other hand, the slave station extracts the time t0 when the first transmission packet (SYNC) L401 is received and the transmission time data t1 in the next transmission packet (Follow - UP) L402.

[0083] Next, the slave station transmits a transmission packet (DELAY REQUEST) L403 to the master station for synchronizing control. At this time, the slave station obtains the transmission time t2.

[0084] Next, the master station transmits the time t3 when the packet (DELAY REQUEST) L404 is received to the slave station on the next packet (DELAY RESPONSE) L404.

[0085] The slave station obtains the time t3 from the above packet (DELAY RESPONSE) L404.

[0086] Through this series of operations, the slave station can obtain the time data from t0 to t3. Then, the slave station can obtain the delay time tdx and the offset time toff, which are data for correcting the deviation of the sampling timing between the master station and the slave station, by performing the calculation shown in the following formula from this time data.

[0087] (Equation 3) tdx = ((t1 - t0) + (t3 - t2)) / 2

[0088] (Equation 4) toff = (t2 - t1) - tdx

[0089] From the above Equation 3 and Equation 4, by controlling to make toff approach 0, the slave station can be controlled so that the sampling times are the same with respect to the master station.

[0090] In this way, it is possible by transmitting and receiving packets that periodically measure the communication delay time, but sampling synchronization control is also possible even if it is carried out irregularly.

[0091] Generally, the control period of this time synchronization is carried out at a period of 1 second in the following IEEE standard PowerProfile (IEEE Standard Profile for Use of IEEE 1588 Precision Time Protocol in Power System Applications IEEE1588 PowerProfile).

[0092] By achieving time synchronization between the MU and the IED in this way, the electrical angles of 4.5° and 3.75° of the timing serving as the reference for both can be synchronized at a period of 1 second. In order to synchronize at intervals of 1 second, the electrical angles of 4.5° and 3.75° each run freely for 1 second, but generally, due to the initial value deviation of the clock, there will be no synchronization deviation of more than 1 sample per second. It is possible to cope by selecting components with clock accuracy that do not cause synchronization deviation in advance.

[0093] Figure 4(b) shows a circuit example in which, taking the case where the slave station is IED100 as an example, the start signals of the electrical angle of 3.75° and the electrical angle of 30° are controlled by time synchronization.

[0094] In FIG. 4(b), the synchronization control circuit includes a clock generator 40, frequency dividers 41 and 42, a register 43 for storing an offset value for controlling the synchronization timing of the slave station, and a signal generation circuit (combinational circuit) 44.

[0095] The offset values obtained by Equations 3 and 4 are stored in register 43. By setting a set value corresponding to the offset in the set value of the counter, the operation period until the time-up of the counter can be controlled. As a result, the electrical angle 3.75° start signal and the electrical angle 30° interrupt signal of the signal generation circuit are controlled.

[0096] FIG. 4(c) shows a timing example of the synchronization control circuit.

[0097] FIG. 4(c) shows the cycle timing 45 of the synchronization control (1pps) of GMC102, a timing example 46 in IED100, and an interrupt signal 47 of the electrical angle 30° in IED100.

[0098] In the cycle timing 45 of the synchronization control (1pps) of GMC, as described above, the normal cycle T4 is 1 second.

[0099] The timing example 46 in IED100 shows that a start signal is generated every 3.75° of the electrical angle, and is synchronized with the above-described 1pps timing.

[0100] The interrupt signal 47 of the electrical angle 30° in IED100 is also synchronized with the 1pps timing.

[0101] FIG. 5 shows a hardware block configuration example of IED100 for realizing the protection control function according to Embodiment 1 of the present invention.

[0102] In FIG. 5, the hardware of the IED is composed of communication means 50a and 50b, SERDES means (Serializer / Deserializer) 51a and 51b, PCS (Physical Coding Sublayer) means 52a and 52c, reception FIFO means 53a and transmission FIFO means 53b, digital filter (DF1) 55, filter coefficient memory means 56, timing control means 57, arithmetic means (CPU) 59, memory means 58, program memory 60, and CPU bus 500.

[0103] Communication means 50a and 50b communicate with MU101a to 101c. SERDES means 51a and 51b convert a serial signal into a parallel signal or convert a parallel signal into a serial signal. PCS means 52a and 52c perform frame encoding. Reception FIFO means 53a and transmission FIFO means 53b have a hardware timestamp function, set and enter reception and transmission data. Digital filter (DF1) 55 is configured as an anti-aliasing filter. Filter coefficient memory means 56 stores the filter coefficients of digital filter 55. Timing control means 57 performs timing control for operating the above circuit means. CPU 59 performs various operations. Memory means 58 stores information for operating CPU 59. Program memory 60 stores a program for CPU 59.

[0104] As described with reference to FIG. 1, the operations of the second digital filter means (DF2) 9, protection control operation SEQ processing means 10, and output means 11 shown in FIG. 1 are realized by the CPU 59 executing the program stored in the program memory 60. Also, digital filter 55 corresponds to the first digital filter (DF1) 3 shown in FIG. 1, and filter coefficient memory 56 is included in the filter coefficient sending means 4 shown in FIG. 1.

[0105] Note that the filter coefficient memory 56 shown in FIG. 5 incorporates a filter coefficient group 5 that stores filter coefficients by determining a combined configuration of filter coefficients in advance as shown in FIG. 1, and a selection means 6 that selects one from the filter coefficient group 5 based on the phase calculated by the phase calculation means 7 and supplies it to the filter means 3.

[0106] Also, the timing control means 57 supplies timing signals to each part based on the synchronization information of the time synchronization means (for example, high-precision time synchronization means based on the IEEE 1588 standard) 54. Since this time synchronization means 54 exchanges synchronization packets with the GMC102 shown in FIG. 1 to perform synchronization control, the MU101a to 101c shown in FIG. 1 are also in a state of highly accurate synchronization.

[0107] FIG. 6 shows an example of the processing flow of signal processing according to Embodiment 1 of the present invention.

[0108] FIG. 6(a) shows the response from signal reception to anti-aliasing filter operation, and FIG. 6(b) shows the response of protection control and sequence processing including a low-order harmonic removal digital filter.

[0109] In FIG. 6(a), the IED100 waits for activation at an electrical angle of 3.75° in step S001, and after activation, performs the operations in subsequent steps S002 to S006. All of these processes are implemented in hardware. The IED100 reads input data at an electrical angle of 4.5° from the reception FIFO 53a in step S002, performs phase calculation for coefficient selection in step S003, selects a filter coefficient group based on the phase calculation result in step S004, and sets the selected filter coefficient group in the coefficient register of the anti-aliasing removal LPF.

[0110] After that, the IED100 performs the operation of the anti-aliasing removal LPF in step S005 and stores the operation result of the anti-aliasing removal LPF at a cycle of 3.5° in step S006. These series of operations are cyclically repeated every 3.75° of electrical angle.

[0111] Figure 6(b) shows the operation starting when the CPU shown at 59 in Figure 5 receives an interrupt signal for starting the electrical angle 30° processing, and shows this operation flow.

[0112] In Figure 6(b), the IED100 reads out eight input data (SV data) resampled to an electrical angle of 3.75° in step S007. In step S008, a digital filter operation (DF2) is performed to remove low-order harmonic components unnecessary for the protection control operation. In step S009, the operation result is stored in the memory, in step S010, the protection control operation is performed, and the sequence process of step S011 is performed using the result. In step S012, output related to display is performed, and in step S013, data output such as a trip signal is performed to the MU (GOOSE communication). These series of processes are cyclically performed every 30° of electrical angle.

[0113] Figure 7 shows a characteristic example of the digital filter for removing the aliasing component according to the first embodiment of the present invention.

[0114] As described above, the first digital filter (DF1) 3 of this embodiment is constituted by an FIR type LPF. As shown by the characteristics (gain - frequency characteristics) 70 of this filter, it has a characteristic of removing frequency components higher than the Nyquist frequency of the electrical angle 4.5° sampling data with a low frequency before and after resampling, and eliminating the influence of the aliasing error component that enters the signal band.

[0115] The cut-off frequency of the LPF is set to fc1, the start frequency of the stop band is set to fst, and the attenuation amount gs necessary for removing the aliasing component is ensured.

[0116] fB0 represents the pass band, fB1 represents the transition region from the pass band to the stop band, and fB2 represents each frequency band of the stop band. The start frequency of the stop band is set to be half the frequency of the lower side of the sampling frequency for sampling rate conversion, so as to eliminate the influence of aliasing.

[0117] For example, assuming that the system frequency is 60 Hz, 2400 Hz, which is half of the first sampling frequency of 4800 Hz, is set as the start frequency fst of the stop band.

[0118] FIG. 8 shows an example of the characteristics of a digital filter for removing low-order harmonic components according to Embodiment 1 of the present invention.

[0119] Specifically, FIG. 8 shows filter characteristics 80 for removing low-order harmonic signal components generated during a system accident that are required for protection control calculation in accordance with the filter characteristics 70 for aliasing removal shown in FIG. 7.

[0120] These filter characteristics 80 are within the pass band fB0 of the filter characteristics 70, with the fundamental wave f0, which is the system frequency, as the center frequency, the frequency between the low-frequency side fBP1 and the high-frequency side fBP2 as the pass band 81, and is an example of a band-pass filter that removes frequencies lower than fBP1 and frequencies higher than fBP2 (in the stop band 81).

[0121] When a system accident occurs, low-order harmonics (such as the third harmonic, fifth harmonic, seventh harmonic, etc.) of the fundamental wave f0 are generated by the capacitance component C to ground and the reactance component L. Since these harmonic components are unnecessary for the protection control calculation based on the fundamental wave, they are removed by this filter.

[0122] In this example, an example of band-pass filter characteristics has been described, but it is not limited to a band-pass filter, and it can also be configured with a low-pass filter or a low-pass notch filter, etc.

[0123] FIG. 9 shows an example of the waveform of signal processing according to Embodiment 1 of the present invention.

[0124] Specifically, FIG. 9 shows examples of signal waveforms of each part in the configuration of FIG. 1 on the time axis. FIG. 9(a) shows the input signal L100a, etc., FIG. 9(b) shows the output signal L106 of the digital filter for aliasing removal, and FIG. 9(c) shows an example of the output signal when it is taken as the electrical angle 30° data for application to the protection control calculation after passing through the low-order harmonic digital filter.

[0125] The time interval of the input signal in FIG. 9(a) is the electrical angle 4.5° of the signal period T90. The time interval of the output signal of the digital filter for aliasing removal in FIG. 9(b) is the electrical angle 3.75° of the period T91. When the digital filter for aliasing removal is configured as an FIR type LPF, a delay time T92 occurs according to the number of taps of the filter.

[0126] The signal for application to the protection control calculation in FIG. 9(c) is output every electrical angle 30° of the period T93, and a delay time T94 of the low-order harmonic removal filter occurs. Thus, although a delay time occurs due to the digital filter for aliasing removal configured for sampling rate conversion that has not existed conventionally, sampling rate conversion is achievable.

[0127] In addition, in the first embodiment, as described above, the filter for aliasing removal (that is, the first digital filter (DF1) 3) and the filter for low-order harmonic removal (that is, the second digital filter (DF2) 9) are separated. For this reason, regardless of the characteristics of the former filter, a filter with arbitrary characteristics can be adopted as the latter filter. For example, a filter with a configuration different from that of the former filter, such as an IIR (Infinite Impulse Response) type filter, can be adopted as the latter filter, and characteristics other than the band-pass filter can also be set. For this reason, in the first embodiment, the degree of freedom in designing the second digital filter (DF2) 9 is high, and a filter with arbitrary characteristics suitable for the use of the IED100 can be implemented.

Example

[0128] Next, referring to FIGS. 10 and 11, Example 2 of the present invention will be described. The configuration of the system according to Example 2 is the same as that of the system according to Example 1 shown in FIGS. 1 to 9 except for the differences described below, and thus the description thereof will be omitted.

[0129] FIG. 10 shows an example of the processing block configuration of the entire system of the protection control function according to Example 2 of the present invention.

[0130] When compared with the IED100 of Example 1 shown in FIG. 1, in the IED100 of Example 2 shown in FIG. 10, a digital filter (DF1) 3, which is a digital filter for aliasing removal for sampling rate conversion, is replaced by a digital filter (DF2) 9 provided for removing low-order harmonics. Example 2 is characterized in that this digital filter (DF2) 9 has both a function of removing aliasing components and a function of removing low-order harmonic components unnecessary for protection control operations.

[0131] Except for the differences in the configurations described above, since the configuration of the system of Example 2 is the same as that shown in FIG. 1, the description of each functional block will be omitted.

[0132] According to the configuration of FIG. 10, since it is possible to concurrently remove aliasing components and low-order harmonic components unnecessary for protection control operations, the delay due to the filter response of the first digital filter (DF1) 3 in FIG. 1 is eliminated, and the response time can be shortened. Therefore, it is suitable for a protection control system that requires high-speed response.

[0133] The digital filter (DF2) 9 of Example 2 can be configured by the same FIR type filter as the first digital filter (DF1) 3 of Example 1. However, its characteristics are changed to filter characteristics 80 instead of filter characteristics 70 of the filter gain-frequency characteristic example shown in FIG. 8. That is, the filter coefficient group 5 is calculated in advance so as to obtain the filter characteristics 80 and is held by the filter coefficient transmission means 4.

[0134] As a digital filter for aliasing removal, it is ideal to pass almost all of the frequencies below 1 / 2 of the resampled signal frequency (Nyquist frequency or below). However, for protection control, since it is implemented with an arithmetic algorithm based on the fundamental wave, there is no need to make the characteristics flat below the Nyquist frequency in order to attenuate the low-order harmonic signal components other than the fundamental wave.

[0135] Also, although the aliasing removal filter of this embodiment was described with an example of 48 taps similar to that of Embodiment 1, the number of taps is not limited to 48 as long as the necessary attenuation characteristics can be satisfied.

[0136] FIG. 11 shows an example of the waveform of signal processing according to Embodiment 2 of the present invention.

[0137] Specifically, FIG. 11 shows examples of the signal waveforms of each part in the configuration of Embodiment 2 represented on the time axis. FIG. 11(a) shows the input signal L100a, etc., and FIG. 11(b) shows an example of the output signal when the signal after passing through the low-order harmonic digital filter is used as the electrical angle 30° data for application to the protection control operation.

[0138] As shown in FIG. 11, a delay time due to the filter characteristics for low-order harmonic removal also occurs in Embodiment 2. However, in Embodiment 2, since there is no function of the digital filter for aliasing removal alone, the delay time in this filter can be omitted, and the response speed of the signal can be made faster than that of Embodiment 1.

[0139] The fact that the response speed can be increased means that it can be said to be effective for the device finishing time of the protection control system, and it is possible to realize resampling support for a protection control system for an extra-high voltage system with strict operating time, and there is an effect of expanding the applicable range.

[0140] In any of the above-described Example 1 and Example 2, when SV data with a sampling rate of 4.5° electrical angle is input, the sampling rate can be converted to 3.75° electrical angle. Therefore, for the post-conversion processing, a protection control algorithm with proven performance can be applied.

[0141] In this embodiment, the sampling rate conversion from 4.5° electrical angle to 3.75° electrical angle has been described. However, not limited to 4.5° electrical angle, for any predetermined sampling rate, the sampling rate can be converted by the same method without upsampling.

[0142] Also, the system of the embodiment of the present invention may be configured as follows.

[0143] (1) A digital protection control system (for example, IED100 or a protection control system S1 including the same), having a first digital filter (for example, the first digital filter (DF1) 3 and the filter coefficient transmission means 4 in FIG. 1), a second digital filter (for example, the second digital filter (DF2) 9), and a protection control calculation unit (for example, the protection control calculation SEQ processing unit 10). When the first digital filter receives first data sampled at a first sampling frequency (for example, a frequency corresponding to 4.5° electrical angle) of a power system, the first digital filter removes the aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency (for example, a frequency corresponding to 3.75° electrical angle). When the second digital filter receives the second data, the second digital filter removes the low-order harmonic components of the power system included in the input second data. The protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed and outputs the result.

[0144] As a result, it is possible to convert the sampling rate at a 3.75° cycle without converting the SV data to a high sampling rate by resampling within the IED. Therefore, there is no need to provide high-speed conversion arithmetic means for the conversion, and thus the conversion means of the IED can be miniaturized and the power consumption can be reduced. As a result, since software assets that perform existing protection control arithmetic based on an electrical angle of 3.75° can be reused, proven protection control arithmetic processing can be applied as it is, and thus there is an effect that cost can be reduced while maintaining reliability. In addition, since a system configuration combined with MUs having different sampling rates can be constructed, the flexibility of system construction can be improved.

[0145] (2) The digital protection control system according to (1) above, wherein the first digital filter is constituted by a non-recursive digital filter (for example, the FIR filter shown in Fig. 2(b)) having a function of switching filter coefficients according to the processing timing.

[0146] As a result, it is possible to convert the sampling rate at a 3.75° cycle without converting the SV data to a high sampling rate by resampling within the IED.

[0147] (3) The digital protection control system according to (2) above, wherein the first digital filter includes a plurality of delay means (for example, delay elements 23a to 23d), a plurality of multiplication means (for example, multipliers 24a to 24e), addition means (for example, addition circuit 25), and a filter coefficient memory (for example, filter coefficient memory 56 constituting filter coefficient sending means 4). The plurality of delay means are connected in series (for example, the arrangement of delay elements 23a to 23d shown in FIG. 2(b)), and the first data is input thereto. Each of the plurality of multiplication means performs multiplication on the data input to the plurality of delay means and the data output from each of the plurality of delay means (for example, the processing of multipliers 24a to 24e shown in FIG. 2(b)). The addition means adds the outputs of the plurality of multiplication means (for example, the processing of addition circuit 25 shown in FIG. 2(b)). The filter coefficient memory holds a plurality of groups of filter coefficients (for example, coefficient groups Gr1 to Gr6), and each of the plurality of groups of filter coefficients includes a plurality of coefficients to be multiplied by the plurality of multiplication means. The first digital filter selects the group of filter coefficients to be applied to the plurality of multiplication means according to the phase of the input data (for example, the selection of the group of filter coefficients shown in FIG. 3(d)).

[0148] As a result, it is possible to convert the sampling rate at a 3.75° period without converting the SV data to a high sampling rate by resampling within the IED.

[0149] (4) The digital protection control system according to (3) above, wherein the delay amount of each of the plurality of delay means is a period of the first sampling frequency, and the filter coefficient memory holds, as the plurality of filter coefficient groups, the same number of filter coefficient groups (for example, coefficient groups Gr1 to Gr6) as the value obtained by dividing the least common multiple (for example, electrical angle 22.5°) of the period of the first sampling frequency (for example, electrical angle 4.5°) and the period of the second sampling frequency (for example, electrical angle 3.75°) by the period of the second sampling frequency. Each filter coefficient of the plurality of filter coefficient groups is determined such that the first digital filter operates as a low-pass filter having a stop band of a frequency band equal to or higher than the lower Nyquist frequency (for example, fst in FIG. 7) among the first sampling frequency and the second sampling frequency. The first digital filter switches the filter coefficient group to be applied to the plurality of multiplication means among the plurality of filter coefficient groups for each period of the second sampling frequency.

[0150] As a result, it is possible to convert the sampling rate at a 3.75° period without converting the SV data to a high sampling rate by resampling within the IED.

[0151] (5) The digital protection control system according to (4) above, further comprising a communication means (for example, communication IF 50a), a serial / parallel conversion means (for example, SERDES 51a), a coding means (for example, PCS 52a), a synchronization control means (for example, synchronization control means 2 and 54), a processor (for example, CPU 59), a program memory (for example, program memory 60), and a work memory (for example, memory 58), wherein the communication means samples at the first sampling frequency and receives, as a serial signal, data of the measured values of the power system that has been digitally converted, via a network connected to the communication means, the serial / parallel conversion means converts the serial signal into a parallel signal, the coding means converts the parallel signal with a predetermined code, the synchronization control means synchronizes with a master clock connected to the network and transmits control signals to each part within the digital protection control system, data converted by the coding means is input as the first data to the first digital filter, the first digital filter switches a group of filter coefficients to be applied to the multiplication means according to the timing of the control signal received from the synchronization control means, and the second digital filter and the protection control arithmetic unit are realized by the processor executing a program stored in the program memory.

[0152] Thus, a protection control system can be configured by an appropriate combination of hardware and software.

[0153] (6) The digital protection control system according to (1) above, wherein the second digital filter is a band-pass filter, a low-pass filter, or a low-pass notch filter that passes a predetermined frequency band (for example, the pass band 81 in FIG. 8) including the frequency of the power system.

[0154] Thus, since software assets for performing existing protection control operations can be reused, proven protection control operation processing can be applied as it is.

[0155] (7) The digital protection control system according to (1) above, comprising a protection control unit (for example, IED100) having the first digital filter, the second digital filter, and the protection control arithmetic unit; a plurality of merging units (for example, MU101a to 101c) connected to the protection control unit via a network; and a grand master clock (for example, GMC102) connected to the network. Each merging unit samples the measured values of the power system at the first sampling frequency, digitally converts them, and transmits them to the protection control unit via the network. The merging units and the protection control unit control the sampling and the operation of the first digital filter based on the synchronized time by exchanging synchronization information with the grand master clock.

[0156] In this way, the MU on the data transmission side and the IED on the reception side can be surely time-synchronized, and the conversion of the sampling rate can be stably performed.

[0157] (8) A digital protection control system, comprising a digital filter (for example, the second digital filter (DF2) 9 in FIG. 10) and a protection control arithmetic unit. When the first data obtained by sampling the measured values of the power system at the first sampling frequency is input to the digital filter, the digital filter removes the aliasing component at the first sampling frequency and the low-order harmonic component of the power system included in the first data, and outputs the second data sampled at the second sampling frequency. The protection control arithmetic unit performs protection control processing on the power system based on the second data and outputs the result.

[0158] In this way, the delay time caused by separately providing a digital filter for alias removal can be saved, and the response speed of the signal can be increased.

[0159] Note that the present invention is not limited to the above-described embodiments, and various modifications are included. For example, the above-described embodiments have been described in detail for better understanding of the present invention, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible.

[0160] In addition, each of the above configurations, functions, processing units, processing means, etc. may be realized in hardware by designing a part or all of them, for example, by using an integrated circuit. Also, each of the above configurations, functions, etc. may be realized in software by a processor interpreting and executing a program for realizing each function. Information such as a program, table, file, etc. for realizing each function can be stored in a storage device such as a non-volatile semiconductor memory, a hard disk drive, an SSD (Solid State Drive), or a computer-readable non-transitory data storage medium such as an IC card, an SD card, or a DVD.

[0161] Also, the control lines and information lines show those considered necessary for explanation, and not necessarily all the control lines and information lines are shown on the product. In fact, it may be considered that almost all the components are interconnected.

Explanation of Reference Numerals

[0162] S1 Protection control system 1 Reception input means 2 Synchronization control means 3 Digital filter for aliasing removal 4 Digital filter coefficient means for aliasing removal 5 Filter coefficient 6 Filter coefficient selection 7 Phase calculation means 8 Data buffer 9 Filter for removing low-order harmonics 10 Protection control operation SEQ processing means 11 Output means 20 Filter coefficient group of the aliasing removal filter 200 - 205 Filter coefficient group divided into multiple phases 21 Filter coefficient selection circuit 22 Filter coefficient storage register 22 Multiplier 23a - 23d 1 - sample delay element 24a - 24e Multiplier 25 Adder 40 Clock generator 41 Counter 42 Signal generation circuit 43 Offset storage register 45 1PPS synchronization signal 46 Electrical angle 3.75° start timing 47 Electrical angle 30° start timing 50a, 50b Communication interface 51a, 51b Serializer / deserializer means 52a, 52b PCS 53a, 53b Receive FIFO memory 54 Synchronization control circuit 55 Aliasing removal filter 56 Filter coefficient memory 57 Timing control circuit 58 Work memory 59 CPU 60 Program memory 500 CPU bus 70 Gain - frequency characteristic example of the aliasing removal digital filter 80 Gain - frequency characteristic example of the low - order harmonic removal filter 81 Passband of the low - order harmonic removal filter 82 Stopband of the low - order harmonic removal filter 120 Operation of the interpolation filter

Claims

1. A digital protection control system, comprising: a first digital filter, a second digital filter, and a protection control calculation unit; when first data obtained by sampling measurement values of a power system at a first sampling frequency is input to the first digital filter, the first digital filter removes an aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency; when the second data is input to the second digital filter, the second digital filter removes low-order harmonic components of the power system included in the input second data; the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs a result thereof. A digital protection control system characterized by the above.

2. The digital protection control system according to claim 1, wherein the first digital filter is configured by a non-recursive digital filter having a function of switching filter coefficients according to processing timing. A digital protection control system characterized by the above.

3. The digital protection control system according to claim 2, wherein the first digital filter includes a plurality of delay means, a plurality of multiplication means, an addition means, and a filter coefficient memory; the plurality of delay means are connected in series, and the first data is input thereto; each of the plurality of multiplication means performs multiplication on data input to the plurality of delay means and data output from each of the plurality of delay means; the addition means adds the outputs of the plurality of multiplication means; the filter coefficient memory holds a plurality of filter coefficient groups; each of the plurality of filter coefficient groups includes a plurality of coefficients to be multiplied by the plurality of multiplication means; the first digital filter selects a filter coefficient group to be applied to the plurality of multiplication means according to the phase of the input data. A digital protection control system characterized by the above.

4. The digital protection control system according to claim 3, wherein a delay amount of each of the plurality of delay means is a period of the first sampling frequency. The filter coefficient memory holds, as the plurality of filter coefficient groups, the same number of filter coefficient groups as the value obtained by dividing the least common multiple of the periods of the first sampling frequency and the period of the second sampling frequency by the period of the second sampling frequency. Each filter coefficient of the plurality of filter coefficient groups is determined such that the first digital filter operates as a low-pass filter having a stop band for a band equal to or higher than the lower Nyquist frequency of the first sampling frequency and the second sampling frequency. The first digital filter is characterized in that, for each period of the second sampling frequency, it switches the filter coefficient group to be applied to the plurality of multiplying means among the plurality of filter coefficient groups. A digital protection control system.

5. The digital protection control system according to claim 4, further comprising communication means, serial / parallel conversion means, coding means, synchronization control means, a processor, a program memory, and a work memory. The communication means samples at the first sampling frequency and receives, as a serial signal, data of the measured values of the power system that has been digitally converted, via a network connected to the communication means. The serial / parallel conversion means converts the serial signal into a parallel signal. The coding means converts the parallel signal with a predetermined code. The synchronization control means synchronizes with a master clock connected to the network and transmits control signals to each part within the digital protection control system. Data converted by the coding means is input as the first data to the first digital filter. The first digital filter switches the filter coefficient group to be applied to the multiplying means according to the timing of the control signal received from the synchronization control means. The second digital filter and the protection control calculation unit are realized by the processor executing a program stored in the program memory. A digital protection control system.

6. The digital protection control system according to claim 1, The digital protection control system is characterized in that the second digital filter is a band-pass filter, a low-pass filter, or a low-pass notch filter that passes a predetermined frequency band including the frequency of the power system.

7. The digital protection control system according to claim 1, a protection control unit having the first digital filter, the second digital filter, and the protection control arithmetic unit; a plurality of merging units connected to the protection control unit via a network; a grand master clock connected to the network, and each merging unit samples the measured value of the power system at the first sampling frequency, digitally converts it, and transmits it to the protection control unit via the network. The digital protection control system is characterized in that each of the merging units and the protection control unit controls the sampling and the operation of the first digital filter based on the synchronized time by exchanging synchronization information with the grand master clock.

8. A digital protection control system, having a digital filter and a protection control arithmetic unit, wherein when the first data obtained by sampling the measured value of the power system at the first sampling frequency is input to the digital filter, the digital filter removes the aliasing component at the first sampling frequency and the low-order harmonic component of the power system included in the first data, and outputs second data sampled at a second sampling frequency. The protection control arithmetic unit performs protection control processing of the power system based on the second data and outputs the result. The digital protection control system is characterized by this.

9. A digital protection control method executed by a digital protection control system, wherein the digital protection control system has a first digital filter, a second digital filter, and a protection control arithmetic unit, and the digital protection control method includes: a procedure in which when the first digital filter is input with first data obtained by sampling the measured value of the power system at the first sampling frequency, the first digital filter removes the aliasing component at the first sampling frequency from the first data and outputs second data sampled at a second sampling frequency. When the second digital filter receives the second data, a procedure for removing low-order harmonic components of the power system included in the input second data; A procedure in which the protection control calculation unit performs protection control processing of the power system based on the second data from which the low-order harmonic components have been removed, and outputs the result, wherein the digital protection control method is characterized by including the procedure.

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