Doherty amplifier circuit and semiconductor device

Abstract

To provide a Doherty amplifier circuit capable of suppressing deterioration in characteristics.SOLUTION: A Doherty amplifier circuit includes: a distributor 16 that distributes a received input signal into a first signal, a second signal and a third signal; a main amplifier 10 that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier 12 that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier 14 that amplifies the third signal and outputs the amplified signal as a sixth signal; a combiner 18 that combines the fourth signal, the fifth signal and the sixth signal and outputs the combined signal to an output terminal as an output signal; and a semiconductor chip 20 on which the main amplifier, the first peak amplifier and the second peak amplifier are mounted. Input power of the input signal at which the second peak amplifier is turned on is larger than input power at which the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are adjacent to each other.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device.

Background Art

[0002] An N (N is 3 or more)-way Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2). It is known to provide a main amplifier and a peak amplifier on the same semiconductor chip (for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] If there is a large difference in characteristics such as parasitic capacitance between the main amplifier and the plurality of peak amplifiers, the phase between each amplifier will deviate from the desired difference, and characteristics such as gain will deteriorate. In an N (N is 3 or more)-way Doherty amplifier circuit, it is not known how to arrange the main amplifier and the plurality of peak amplifiers to improve the characteristics.

[0005] The present disclosure aims to suppress deterioration of characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal; and the same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted. The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are adjacent Doherty amplifier circuits.

[0007] One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal; a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; and a second semiconductor chip on which the second peak amplifier is mounted and is different from the first semiconductor chip. The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on, and it is a Doherty amplifier circuit.

[0008] One embodiment of the present disclosure includes a main amplifier that amplifies a first signal to which an input signal is distributed and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies a second signal to which the input signal is distributed and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies a third signal to which the input signal is distributed and outputs the amplified signal as a sixth signal, and the same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted. The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are semiconductor devices for a Doherty amplifier circuit that are adjacent to each other.

[0009] One embodiment of the present disclosure includes a main amplifier that amplifies a first signal to which an input signal is distributed and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies a second signal to which the input signal is distributed and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies a third signal to which the input signal is distributed and outputs the amplified signal as a sixth signal, a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted, and a second semiconductor chip on which the second peak amplifier is mounted and which is different from the first semiconductor chip. The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on, and it is a semiconductor device for a Doherty amplifier circuit.

Advantages of the Invention

[0010] According to the present disclosure, deterioration of characteristics can be suppressed.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0012] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal, and the same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted. The input power of the input signal when the second peak amplifier is turned on is greater than the input power when the first peak amplifier is turned on, and the main amplifier and the first peak amplifier are a Doherty amplifier circuit adjacent to each other. Thereby, the difference in parasitic capacitance and the like between the main amplifier and the first peak amplifier can be reduced. Therefore, since the phases of the fourth signal and the fifth signal can be matched, deterioration of characteristics can be suppressed. (2) In the above (1), the first peak amplifier may be provided between the main amplifier and the second peak amplifier. Thereby, deterioration of characteristics can be further suppressed. (3) In the above (1) or (2), the main amplifier and the first peak amplifier are adjacent in the first direction, and the distance between the main amplifier and the first peak amplifier may be smaller than either the width of the main amplifier in the first direction or the width of the first peak amplifier in the first direction. Thereby, deterioration of characteristics can be further suppressed. (4) In any one of the above (1) to (3), a first input pad provided on the semiconductor chip and electrically connected to the input terminal of the main amplifier, a second input pad provided on the semiconductor chip and electrically connected to the input terminal of the first peak amplifier, a third input pad provided on the semiconductor chip and electrically connected to the input terminal of the second peak amplifier, a first output pad provided on the semiconductor chip and electrically connected to the output terminal of the main amplifier, a second output pad provided on the semiconductor chip and electrically connected to the output terminal of the first peak amplifier, and a third output pad provided on the semiconductor chip and electrically connected to the output terminal of the second peak amplifier may be provided. Thereby, the main amplifier, the first peak amplifier, and the second peak amplifier can be electrically connected to the outside. (5) In the above (4), the main amplifier, the first peak amplifier, and the second peak amplifier are arranged in the first direction, the first input pad and the first output pad sandwich the main amplifier in a second direction intersecting the first direction, the second input pad and the second output pad sandwich the first peak amplifier in the second direction, and the third input pad and the third output pad may sandwich the second peak amplifier in the second direction. Thereby, the main amplifier and the first peak amplifier can be made adjacent. (6) In any one of the above (1) to (5), passive elements may not be provided on the semiconductor chip. Thereby, the main amplifier and the first peak amplifier can be made adjacent, and the first peak amplifier and the second peak amplifier can be made adjacent. (7) An embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal, a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted, and a second semiconductor chip on which the second peak amplifier is mounted and is different from the first semiconductor chip. The Doherty amplifier circuit is such that the input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on. Thereby, deterioration of characteristics can be suppressed and the yield can be improved. (8) An embodiment of the present disclosure includes a main amplifier that amplifies a first signal into which an input signal is distributed and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies a second signal into which the input signal is distributed and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies a third signal into which the input signal is distributed and outputs the amplified signal as a sixth signal, and the same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted. The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on. The semiconductor device for a Doherty amplifier circuit is such that the main amplifier and the first peak amplifier are adjacent to each other. Thereby, deterioration of characteristics can be suppressed. (9) One embodiment of the present disclosure includes a main amplifier that amplifies a first signal to which an input signal is distributed and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies a second signal to which the input signal is distributed and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies a third signal to which the input signal is distributed and outputs the amplified signal as a sixth signal, a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted, and a second semiconductor chip on which the second peak amplifier is mounted and is different from the first semiconductor chip. The input power of the input signal when the second peak amplifier is turned on is greater than the input power when the first peak amplifier is turned on, and it is a semiconductor device for a Doherty amplifier circuit. Thereby, deterioration of characteristics can be suppressed and the yield can be improved.

[0013] [Details of Embodiments of the Present Disclosure] Specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0014] [Example 1] As a Doherty amplifier circuit, a high-power high-frequency amplifier circuit used in a base station for mobile communication will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. FIG. 1 is a block diagram of the Doherty amplifier circuit according to Example 1.

[0015] As shown in FIG. 1, in the Doherty amplifier circuit 100, a main amplifier 10, peak amplifiers 12 (first peak amplifier) and 14 (second peak amplifier) are connected in parallel between a distributor 16 and a combiner 18. In this way, the Doherty amplifier circuit 100 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having three or more peak amplifiers.

[0016] A high-frequency signal is input as an input signal Sin to an input terminal Tin. A distributor 16 distributes the input signal Sin input to the input terminal Tin into signals S1 (first signal), S2 (second signal), and S3 (third signal). The distributor 16 is, for example, a Wilkinson-type distributor.

[0017] The path through which the signal S1 is input includes a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path through which the signal S2 is input includes a matching circuit 31, a bias circuit 37, a peak amplifier 12, and a matching circuit 34. The path through which the signal S3 is input includes a matching circuit 32, a bias circuit 38, a peak amplifier 14, and a matching circuit 35.

[0018] The matching circuits 30 to 32 match the impedances seen from the matching circuits 30 to 32 to the distributor 16 to the impedances seen from the matching circuits 30 to 32 to the main amplifier 10, the peak amplifiers 12, and 14, respectively. The bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of the main amplifier 10, the peak amplifiers 12, and 14, respectively, to suppress leakage of the signals S1 to S3 to the bias terminals.

[0019] The main amplifier 10, the peak amplifiers 12, and 14 amplify the signals S1, S2, and S3, respectively, and output the amplified signals S4 (fourth signal), S5 (fifth signal), and S6 (sixth signal), respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, the peak amplifiers 12, and 14 to suppress leakage of the signal S4 to the bias terminal. The matching circuits 33 to 35 match the impedances seen from the matching circuits 33 to 35 to the main amplifier 10, the peak amplifiers 12, and 14 to the impedances seen from the matching circuits 33 to 35 to a synthesizer 18, respectively. The synthesizer 18 synthesizes the signals S4 to S6 and outputs the synthesized signal as an output signal Sout to an output terminal Tout.

[0020] The main amplifier 10, peak amplifiers 12 and 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOS (Laterally Diffused Metal Oxide Semiconductor). The sources S of the transistors Q1 to Q3 are grounded, signals S1 to S3 are respectively input to the gates G, and signals S4 to S6 are respectively output from the drains D. The transistors Q1 to Q3 are mounted on one semiconductor chip 20. The matching circuits 30 to 33 and the semiconductor chip 20 are mounted in the package 50.

[0021] FIG. 2 is a plan view of the semiconductor device in the first embodiment. In FIG. 2, the lid of the package 50 is not shown. The thickness direction of the base 51 of the package 50 is the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is the Y direction (the first direction).

[0022] As shown in FIG. 2, in the semiconductor device 102, the package 50 has a base 51 at least the upper surface of which is conductive. The base 51 is a conductor substrate such as a laminated substrate of copper and molybdenum, for example. A reference potential such as a ground potential is supplied to the base 51. The semiconductor chip 20 and the capacitive components 24a to 24c are mounted on the base 51.

[0023] On one side of the base 51 in the X direction, leads 27a to 27c are provided with an insulating layer (not shown) interposed therebetween. On the + side of the base 51 in the X direction, leads 28a to 28c are provided with an insulating layer (not shown) interposed therebetween. The leads 27a to 27c and 28a to 28c are metal layers or metal plates such as copper, for example. Signals S1 to S3 are respectively input to the leads 27a to 27c, and signals S4 to S6 are respectively output from the leads 28a to 28c.

[0024] The semiconductor chip 20 includes a substrate 21, transistors Q1 to Q3, pads 22a to 22c and 23a to 23c provided on the upper surface of the substrate 21, and electrodes (not shown) provided on the lower surface of the substrate 21. The pad 22a (first input pad), 23a (first output pad), and the lower surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q1, respectively. The pad 22b (second input pad), 23b (second output pad), and the lower surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q2, respectively. The pad 22c (third input pad), 23c (third output pad), and the lower surface electrode are electrically connected to the gate G (input terminal), drain D (output terminal), and source S of the transistor Q3, respectively.

[0025] The substrate 21 is a semiconductor substrate. When the transistors Q1 to Q3 are GaN HEMTs, the substrate 21 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOS, the substrate 21 is, for example, a silicon (Si) substrate. The pads 22a to 22c, 23a to 23c, and the lower surface electrodes are metal layers such as gold layers, for example. The transistor Q1 is shown smaller than the transistors Q2 and Q3 (for example, having a smaller gate width and a smaller saturation power when the gate bias voltage and the drain bias voltage are the same), but the transistor Q1 may be the same as the transistors Q2 and Q3 (for example, having the same gate width and the same saturation power when the gate bias voltage and the drain bias voltage are the same).

[0026] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode (not shown) provided on the lower surface of the dielectric substrate 25. The electrode 26 and the lower surface electrode sandwiching the dielectric substrate 25 form a capacitor. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is a metal layer such as a gold layer, for example.

[0027] Bonding wire 46 electrically connects the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c respectively. Bonding wire 47 electrically connects the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c respectively. Bonding wire 48 electrically connects the pads 23a to 23c and the leads 28a to 28c respectively. The bonding wires 46 to 48 are metal wires such as, for example, gold wires or aluminum wires.

[0028] Bonding wires 46 and 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bonding wires 46, 47 and the capacitive components 24a to 24c correspond to at least a part of the matching circuits 30 to 32 of the T-type LCL circuit.

[0029] FIG. 3 is a cross-sectional view of the semiconductor chip in Example 1. As shown in FIG. 3, the substrate 21 includes a substrate 40a and a semiconductor layer 40b provided on the substrate 40a. The regions where a part of the semiconductor layer 40b is inactivated by ion implantation or the like are the inactive regions 44, 44a and 44b. The regions where the semiconductor layer 40b is not inactivated are the active regions 45a to 45c. Transistors Q1 to Q3 are respectively provided on the active regions 45a to 45c. An inactive region 44a is between the transistors Q1 and Q2, and an inactive region 44b is between the transistors Q2 and Q3.

[0030] Transistor Q1 includes a source electrode 41a, a gate electrode 42a, and a drain electrode 43a arranged in the Y direction. Transistor Q2 includes a source electrode 41b, a gate electrode 42b, and a drain electrode 43b arranged in the Y direction. Transistor Q3 includes a source electrode 41c, a gate electrode 42c, and a drain electrode 43c arranged in the Y direction. An insulating layer 49 is provided on the substrate 21 so as to cover transistors Q1 to Q3. The insulating layer 49 is an organic insulating layer such as, for example, a polyimide layer or a BCB (Benzocycbutene) layer. At least a part of the insulating layer 49 may be an inorganic insulating layer.

[0031] When transistors Q1 to Q3 are GaN HEMTs, the substrate 40a is, for example, a silicon carbide substrate, and the semiconductor layer 40b includes a gallium nitride running layer and an aluminum gallium nitride barrier layer. The source electrodes 41a to 41c and the drain electrodes 43a to 43c are metal films, for example, a titanium film and an aluminum film from the side of the semiconductor layer 40b. The gate electrodes 42a to 42c are metal films, for example, a nickel film and a gold film from the side of the semiconductor layer 40b.

[0032] In transistors Q1 to Q3, the thicknesses of the respective layers of the semiconductor layer 40b are substantially the same. For example, in transistors Q1 to Q3, the thicknesses of the gallium nitride running layers are the same as each other, and the thicknesses of the aluminum gallium nitride barrier layers are the same as each other. Also, in transistors Q1 to Q3, the dimensions of the source electrodes 41a to 41c are the same as each other, the dimensions of the gate electrodes 42a to 42c are the same as each other, and the dimensions of the drain electrodes 43a to 43c are the same as each other.

[0033] Therefore, the characteristics per unit gate width of transistors Q1 to Q3 are substantially the same as each other. For example, in transistors Q1 to Q3, the gate-source capacitances per unit gate width are substantially the same as each other, the drain-source capacitances per unit gate width are substantially the same, and the gate-drain capacitances per unit gate width are substantially the same.

[0034] FIG. 4 is a schematic diagram showing the probability with respect to Pout in Example 1, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin.

[0035] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifiers 12 and 14. Each gain is the power gain of each of the main amplifier 10, the peak amplifiers 12 and 14. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. Note that Pin and Pout are in dB display. The gain of the main amplifier 10 with an input power Pin below the power P1 is greater than the gain of the peak amplifier 12 with a power above P1 and below P2. That is, the slope of Pout with respect to the input power Pin in the main amplifier 10 below the power P1 is greater than the slope of Pout with respect to the input power Pin in the peak amplifier 12 with a power above P1 and below P2. However, FIG. 4 is a schematic diagram, and shows the slope of Pout with respect to the input power Pin in the main amplifier 10 below the power P1 to be smaller than the slope of Pout with respect to the input power Pin in the peak amplifier 12 with a power above P1 and below P2.

[0036] As shown in FIG. 4, when the output power Pout is the power P0, the probability of the modulation wave is the highest. That is, when outputting the signal of the modulation wave, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A or AB amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin at which the peak amplifier 12 turns on is larger than the input power Pin at which the main amplifier 10 turns on, and the input power Pin at which the peak amplifier 14 turns on is larger than the input power Pin at which the peak amplifier 12 turns on. In order to operate in this way, it can be realized by making the gate bias voltage VG2 of the transistor Q2 more negative and larger than the gate bias voltage VG1 of the transistor Q1, and making the gate bias voltage VG3 of the transistor Q3 more negative and larger than the gate bias voltage VG2 of the transistor Q2.

[0037] As the input power Pin of the input signal Sin increases, when the input power Pin exceeds the power P0 and reaches the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is below the power P1, as the input power Pin increases, the output power Pout of the main amplifier 10 increases linearly. Therefore, when the input power Pin is below the power P0, each gain and the overall gain are almost constant.

[0038] When the input power Pin is equal to or greater than the power P1 and equal to or less than the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. Along with this, the overall gain also decreases. Since the peak amplifier 12 operates in class C, the gain of the peak amplifier 12 between the power P1 and P2 is lower than the gain of the main amplifier 10 below the power P1. Also, the saturation power of the peak amplifier 12 is smaller than the saturation power of the main amplifier 10.

[0039] When the input power Pin is equal to or greater than power P2 and equal to or less than power P3, all of the main amplifier 10, peak amplifiers 12 and 14 operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 saturates. Therefore, the gain of the peak amplifier 12 decreases. Along with this, the overall gain also decreases. Since the operating point of the peak amplifier 14 is more negative than that of the peak amplifier 12, the gain of the peak amplifier 14 between the powers P2 and P3 is lower than the gain of the peak amplifier 12 between the powers P1 and P2. Also, the saturation power of the peak amplifier 14 is smaller than the saturation power of the peak amplifier 12.

[0040] When the input power Pin is equal to or greater than power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 saturates. Therefore, the gain of the peak amplifier 14 decreases. Along with this, the overall gain also decreases.

[0041] The product of the probability and the overall gain corresponds to the gain of the modulated wave. In order to improve the gain of the modulated wave, the overall gain at a high probability Pout is improved.

[0042] [Comparative Example 1] FIG. 5 is a plan view of the semiconductor device in Comparative Example 1. As shown in FIG. 5, in the semiconductor device 110 of Comparative Example 1, the transistors Q1 to Q3 are mounted on different semiconductor chips 20a to 20c, respectively. The semiconductor chips 20a to 20c each include substrates 21a to 21c. When the semiconductor chips 20a to 20c are different, the parasitic capacitances (for example, gate-source capacitance, drain-source capacitance, and gate-drain capacitance) between the transistors Q1 to Q3 vary due to manufacturing variations and the like. For example, when the wafers from which the semiconductor chips 20a to 20c are obtained are different from each other, the parasitic capacitances of the transistors Q1 to Q3 with respect to each other are likely to be different. Even when the semiconductor chips 20a to 20c are obtained from the same wafer, if the positions within the wafer from which the semiconductor chips 20a to 20c are obtained are different from each other, the parasitic capacitances of the transistors Q1 to Q3 with respect to each other are likely to be different. Therefore, it is difficult to align the phases of the main amplifier 10, the peak amplifiers 12 and 14. If the phases of the signals S4 to S6 deviate from the desired relationship, the gain of the output signal Sout decreases.

[0043] [Description of Example 1] According to Example 1, as shown in FIG. 2, the main amplifier 10, the peak amplifiers 12 and 14 are mounted on the same semiconductor chip 20. The difference in parasitic capacitance and the like between the transistors Q1 to Q3 provided in adjacent regions within the semiconductor chip 20 is small. Therefore, the phases of the signals S4 to S6 output from the main amplifier 10, the peak amplifiers 12 and 14 can be aligned. For this reason, a decrease in characteristics such as the gain of the output signal Sout can be suppressed.

[0044] As shown in Fig. 4, when the input power Pin at which the main amplifier 10 and the peak amplifier 12 operate is between the powers P1 and P2, the probability of the modulation wave is high. Therefore, by setting the phases of the main amplifier 10 and the peak amplifier 12 within a desired range, the gain of the modulation wave can be improved. Thus, as shown in Fig. 2, the main amplifier 10 and the peak amplifier 12 are adjacent in the Y direction. Since the transistors Q1 and Q2 are adjacent, the difference in parasitic capacitance and the like between the transistors Q1 and Q2 becomes small. As a result, the phase difference between the main amplifier 10 and the peak amplifier 12 can be reduced. Therefore, deterioration of characteristics such as the gain of the modulation wave can be suppressed. Note that the fact that the main amplifier 10 and the peak amplifier 12 are adjacent means that no other transistors, passive elements, or wirings are provided between the main amplifier 10 and the peak amplifier 12.

[0045] As shown in Fig. 4, when the input power Pin at which the main amplifier 10, the peak amplifiers 12 and 14 operate is equal to or higher than the power P2, the probability of the modulation wave is low. For this reason, the peak amplifier 14 does not affect the gain of the modulation wave as much as the peak amplifier 12. Therefore, the peak amplifier 12 may be provided between the main amplifier 10 and the peak amplifier 14.

[0046] As shown in Fig. 3, let the respective widths in the Y direction of the main amplifier 10, the peak amplifiers 12 and 14 (i.e., the transistors Q1 to Q3) be W1, W2 and W3. Let the distance between the main amplifier 10 and the peak amplifier 12 be D1, and the distance between the peak amplifiers 12 and 14 be D2. When the distance D1 becomes smaller, the difference in parasitic capacitance and the like between the transistors Q1 and Q2 becomes smaller. Therefore, deterioration of characteristics can be suppressed. From this viewpoint, the distance D1 can be made equal to or less than the width W1 and equal to or less than the width W2, can be made 0.5 times or less of the widths W1 and W2, and can be made 0.2 times or less. From the viewpoint of reducing the variation in parasitic capacitance and the like between the transistors Q2 and Q3, the distance D2 can be made equal to or less than the width W2 and equal to or less than the width W3, can be made 0.5 times or less of the widths W2 and W3, and can be made 0.2 times or less.

[0047] As shown in FIG. 2, pads 22a and 23a electrically connected to the input terminal and the output terminal of the main amplifier 10, respectively, are provided on the semiconductor chip 20. Pads 22b and 23b electrically connected to the input terminal and the output terminal of the peak amplifier 12, respectively, are provided on the semiconductor chip 20. Pads 22c and 23c electrically connected to the input terminal and the output terminal of the peak amplifier 14, respectively, are provided on the semiconductor chip 20. Thereby, the main amplifier 10, the peak amplifiers 12 and 14 can be electrically connected to external circuits such as the matching circuits 30 to 35.

[0048] The main amplifier 10, the peak amplifiers 12 and 14 are arranged in the Y direction. The pads 22a and 23a sandwich the main amplifier 10 in the X direction. The pads 22b and 23b sandwich the peak amplifier 12 in the X direction. The pads 22c and 23c sandwich the peak amplifier 14 in the X direction. Thereby, no pads 22a to 22c and 23a to 23c are provided between the main amplifier 10 and the peak amplifier 12, and between the peak amplifiers 12 and 14. Therefore, the main amplifier 10 and the peak amplifier 12 can be adjacent to each other, and the peak amplifiers 12 and 14 can be adjacent to each other.

[0049] No passive elements such as inductors or capacitors are provided on the semiconductor chip 20. Thereby, no passive elements are provided between the main amplifier 10 and the peak amplifier 12, and between the peak amplifiers 12 and 14. Therefore, the main amplifier 10 and the peak amplifier 12 can be adjacent to each other, and the peak amplifiers 12 and 14 can be adjacent to each other.

[0050] [Embodiment 2] FIG. 6 is a plan view of the semiconductor device in Example 2. As shown in FIG. 6, in the semiconductor device 104 of Example 2, transistors Q1 and Q2 are mounted on the semiconductor chip 20a, and transistor Q3 is mounted on the semiconductor chip 20c. The semiconductor chips 20a and 20c each include substrates 21a and 21c. Transistors Q1 and Q2 are provided adjacent to each other on the substrate 21a. Other configurations are the same as those in Example 1, and the description thereof is omitted.

[0051] In order to improve the gain of the modulated wave, it is effective to reduce the phase difference between the main amplifier 10 and the peak amplifier 12. Therefore, the semiconductor chip 20a (first semiconductor chip) mounts the main amplifier 10 and the peak amplifier 12. Thereby, the phase difference between the main amplifier 10 and the peak amplifier 12 can be suppressed, and the gain of the modulated wave can be improved. On the other hand, as in Example 1, when three amplifiers are provided on the same semiconductor chip 20, the semiconductor chip 20 becomes a good product when all three amplifiers are good products. For this reason, the yield of the semiconductor chip 20 decreases. Therefore, the peak amplifier 14, which does not affect the gain of the modulated wave as much as the peak amplifier 12, is mounted on a semiconductor chip 20c (second semiconductor chip) different from the semiconductor chip 20a. Thereby, the yields of the semiconductor chips 20a and 20c can be improved.

[0052] On the semiconductor chip 20a, the main amplifier 10 and the peak amplifier 12 are adjacent to each other. Thereby, the difference in parasitic capacitance between transistors Q1 and Q2 is reduced. Therefore, deterioration of characteristics can be suppressed. Referring to FIG. 3, also in Modification 1 of Example 1, the distance D1 in the Y direction between the main amplifier 10 and the peak amplifier 12 can be made equal to or less than the width W1 in the Y direction of the main amplifier 10 and equal to or less than the width W2 in the Y direction of the peak amplifier 12, and can be made equal to or less than 0.5 times the widths W1 and W2, and can be made equal to or less than 0.2 times.

[0053] Although the 3-way Doherty amplifier circuit has been described as an example of Example 1 and its modifications, in the case of an N-way Doherty amplifier circuit, N - 1 peak amplifiers may be provided.

[0054] The embodiments disclosed this time should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Description of Reference Numerals

[0055] 10 Main amplifier 12 (First peak amplifier), 14 (Second peak amplifier) Peak amplifier 16 Distributor 18 Combiner 20, 20a (First semiconductor chip), 20b, 20c (Second semiconductor chip) Semiconductor chip 21, 21a, 21b, 21c Substrate 22a (First input pad), 22b (Second input pad), 22c (Third input pad), 23a (First output pad), 23b (Second output pad), 23c (Third output pad) Pad 24a, 24b, 24c Capacitive component 25 Dielectric substrate 26 Electrode 27a, 27b, 27c, 28a, 28b, 28c Lead 30, 31, 32, 33, 34, 35 Integrated circuit 36, 37, 38, 39 Bias circuit 40a Substrate 40b Semiconductor layer 41a, 41b, 41c Source electrode 42a, 42b, 42c Gate electrode 43a, 43b, 43c Drain electrode 44, 44a, 44b Inactive region 45a, 45b, 45c Active region 46, 47, 48 Bonding wire 49 Insulating layer 50 Package 51 Base 100 Doherty amplifier circuit 102, 104, 110 semiconductor devices S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal) signals Sin input signal Sout output signal Tin input terminal Tout output terminal G (input terminal) gate D (output terminal) drain

Claims

1. A distributor that distributes an inputted input signal into a first signal, a second signal, and a third signal; A main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; A first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; A second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; A synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal; The same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted; Comprising The input power of the input signal at which the second peak amplifier turns on is greater than the input power of the input signal at which the first peak amplifier turns on; A Doherty amplifier circuit in which the main amplifier and the first peak amplifier are adjacent.

2. The Doherty amplifier circuit according to claim 1, wherein the first peak amplifier is provided between the main amplifier and the second peak amplifier.

3. The main amplifier and the first peak amplifier are adjacent in a first direction, and the distance between the main amplifier and the first peak amplifier is smaller than either the width of the main amplifier in the first direction or the width of the first peak amplifier in the first direction. The Doherty amplifier circuit according to claim 1 or claim 2.

4. A first input pad provided on the semiconductor chip and electrically connected to the input terminal of the main amplifier; A second input pad provided on the semiconductor chip and electrically connected to the input terminal of the first peak amplifier; A third input pad provided on the semiconductor chip and electrically connected to the input terminal of the second peak amplifier; A first output pad provided on the semiconductor chip and electrically connected to the output terminal of the main amplifier; A second output pad provided on the semiconductor chip and electrically connected to the output terminal of the first peak amplifier; A third output pad provided on the semiconductor chip and electrically connected to the output terminal of the second peak amplifier; The Doherty amplifier circuit according to claim 1 or claim 2, comprising

5. The main amplifier, the first peak amplifier, and the second peak amplifier are arranged in a first direction; The first input pad and the first output pad sandwich the main amplifier in a second direction that intersects the first direction. The second input pad and the second output pad sandwich the first peak amplifier in the second direction, The third input pad and the third output pad sandwich the second peak amplifier in the second direction. The Doherty amplifier circuit according to claim 4. **Claim 6** The Doherty amplifier circuit according to claim 1 or claim 2, wherein no passive element is provided on the semiconductor chip. **Claim 7** A distributor that distributes an input input signal into a first signal, a second signal, and a third signal, A main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, A first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, A second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, A synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal, A first semiconductor chip on which the main amplifier and the first peak amplifier are mounted, A second semiconductor chip on which the second peak amplifier is mounted and is different from the first semiconductor chip, Comprising: A Doherty amplifier circuit in which the input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on. **Claim 8** A main amplifier that amplifies the first signal into which the input signal is distributed and outputs the amplified signal as a fourth signal, A first peak amplifier that amplifies the second signal into which the input signal is distributed and outputs the amplified signal as a fifth signal, A second peak amplifier that amplifies the third signal into which the input signal is distributed and outputs the amplified signal as a sixth signal, The same semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted, Comprising: The input power of the input signal when the second peak amplifier is turned on is greater than the input power of the input signal when the first peak amplifier is turned on, A semiconductor device for a Doherty amplifier circuit in which the main amplifier and the first peak amplifier are adjacent to each other. **Claim 9** A main amplifier that amplifies the first signal into which the input signal is distributed and outputs the amplified signal as a fourth signal, A first peak amplifier that amplifies the second signal into which the input signal is distributed and outputs the amplified signal as a fifth signal, A second peak amplifier that amplifies the third signal into which the input signal is distributed and outputs the amplified signal as a sixth signal, A first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; A second semiconductor chip on which the second peak amplifier is mounted and which is different from the first semiconductor chip; Comprising: A semiconductor device for a Doherty amplifier circuit in which the input power of the input signal when the second peak amplifier is turned on is greater than the input power when the first peak amplifier is turned on.

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