Doherty amplifier circuit

Abstract

To provide a Doherty amplifier circuit capable of improving characteristics.SOLUTION: A Doherty amplifier circuit includes: a distributor that distributes a received input signal into a first signal, a second signal and a third signal, and causes power of the second signal being distributed to be larger than power of the third signal; a main amplifier 10 that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier 12 that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier 14 that amplifies the third signal and outputs the amplified signal as a sixth signal; and a combiner that combines the fourth signal, the fifth signal and the sixth signal and outputs the combined signal to an output terminal as an output signal. Input power of the input signal at which the first peak amplifier is turned on is smaller than the input power at which the second peak amplifier is turned on.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit.

Background Art

[0002] An N (N is 3 or more)-way Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a Doherty amplifier circuit, it is required to improve the gain of the modulated wave to be amplified.

[0005] The present disclosure aims to improve characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a Doherty amplifier circuit including a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, and distributes the power of the second signal to be greater than the power of the third signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, and a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal, wherein an input power of the input signal when the first peak amplifier is turned on is smaller than an input power of the input signal when the second peak amplifier is turned on.

Advantages of the Invention

[0007] According to the present disclosure, characteristics can be improved.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Best Mode for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal, a second signal, and a third signal, and distributes the power of the second signal to be greater than the power of the third signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, and a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal. The Doherty amplifier circuit is such that the input power of the input signal when the first peak amplifier is turned on is smaller than the input power when the second peak amplifier is turned on. Thereby, in the range of power with a high probability of modulated waves, the overall gain increases. Therefore, the gain of the modulated wave can be improved and the characteristics can be improved. (2) In the above (1), when the main amplifier and the first peak amplifier are operating and the second peak amplifier is not operating, the first position on the Smith chart of the impedance at the center frequency of the operating band seen from the first peak amplifier to the synthesizer, and the second position on the Smith chart of the impedance at the center frequency seen from the first peak amplifier to the synthesizer where the gain of the first peak amplifier is maximum, the first distance between them may be shorter than the second distance between the position on the Smith chart of the impedance at the center frequency seen from the main amplifier to the synthesizer and the position on the Smith chart of the impedance at the center frequency seen from the main amplifier to the synthesizer where the gain of the main amplifier is maximum. Thereby, the characteristics can be further improved. (3) In the above (2), the first position on the Smith chart may be located within a circle having a diameter equal to the distance between the third position on the Smith chart of the impedance at the center frequency, as seen from the synthesizer to the first peak amplifier, where the efficiency of the first peak amplifier is maximized, with the second position as the center. Thereby, the characteristics can be further improved. (4) In the above (2) or (3), when the main amplifier, the first peak amplifier, and the second peak amplifier operate, the third distance between the fourth position on the Smith chart of the impedance at the center frequency, as seen from the first peak amplifier to the synthesizer, and the second position may be equal to or less than the first distance. Thereby, the characteristics can be further improved. (5) In any of the above (1) to (4), when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier may be greater than the saturation power of the second peak amplifier. Thereby, amplifiers having the same structure can be used. (6) In any of the above (1) to (4), when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier and the saturation power of the second peak amplifier may be equal. Thereby, the characteristics can be further improved.

[0010] [Details of Embodiments of the Present Disclosure] A specific example of a Doherty amplifier circuit according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is intended to cover all modifications within the meaning and scope equivalent to the claims, as indicated by the claims.

[0011] As a Doherty amplifier circuit, a high-output high-frequency amplifier circuit used in a base station for mobile communication will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or higher and 10 GHz or lower. FIG. 1 is a block diagram of a Doherty amplifier circuit according to Example 1.

[0012] As shown in FIG. 1, in Doherty amplifier circuit 100, main amplifier 10, peak amplifier 12 (first peak amplifier), and 14 (second peak amplifier) are connected in parallel between distributor 16 and combiner 18. In this way, Doherty amplifier circuit 100 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having three or more peak amplifiers.

[0013] A high-frequency signal is input as input signal Sin to input terminal Tin. Distributor 16 distributes input signal Sin input to input terminal Tin into signal S1 (first signal), S2 (second signal), and S3 (third signal). Distributor 16 is, for example, a Wilkinson type distributor.

[0014] The path through which signal S1 is input includes matching circuit 30, bias circuit 36, main amplifier 10, bias circuit 39, and matching circuit 33. The path through which signal S2 is input includes matching circuit 31, bias circuit 37, peak amplifier 12, and matching circuit 34. The path through which signal S3 is input includes matching circuit 32, bias circuit 38, peak amplifier 14, and matching circuit 35.

[0015] Matching circuits 30 to 32 match the impedance seen from distributor 16 to matching circuits 30 to 32 with the impedance seen from matching circuits 30 to 32 to main amplifier 10, peak amplifiers 12 and 14, respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to gates G of main amplifier 10, peak amplifiers 12 and 14, respectively, and suppress leakage of signals S1 to S3 to the bias terminals.

[0016] The main amplifier 10, peak amplifiers 12 and 14 amplify signals S1, S2 and S3 respectively, and output amplified signals S4 (the fourth signal), S5 (the fifth signal) and S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, peak amplifiers 12 and 14, and suppresses leakage of the signal S4 to the bias terminal. The matching circuits 33 to 35 match the impedances seen from the main amplifier 10, peak amplifiers 12 and 14 to the impedances seen from the matching circuits 33 to 35 to the synthesizer 18 respectively. The synthesizer 18 synthesizes the signals S4 to S6 and outputs the synthesized signal as the output signal Sout to the output terminal Tout.

[0017] The main amplifier 10, peak amplifiers 12 and 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, signals S1 to S3 are input to the gates G respectively, and signals S4 to S6 are output from the drains D respectively.

[0018] FIG. 2 is a plan view of the semiconductor device in the first embodiment. In FIG. 2, the lid of the package 50 is not shown. The thickness direction of the base 51 of the package 50 is the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is the Y direction (the first direction).

[0019] As shown in FIG. 2, in the semiconductor device 102, the package 50 has a base 51 whose at least upper surface is conductive. The base 51 is a conductor substrate such as a laminated substrate of copper and molybdenum, for example. A reference potential such as a ground potential is supplied to the base 51. On the base 51, semiconductor chips 20a to 20c and capacitive components 24a to 24c are mounted.

[0020] On one side of the base 51 in the X direction, lead-in leads 27a to 27c sandwiching an insulating layer (not shown) are provided. On the + side of the base 51 in the X direction, lead-out leads 28a to 28c sandwiching an insulating layer (not shown) are provided. The leads 27a to 27c and 28a to 28c are metal layers or metal plates such as copper, for example. Signals S1 to S3 are respectively input to the leads 27a to 27c, and signals S4 to S6 are respectively output from the leads 28a to 28c.

[0021] The semiconductor chip 20a includes a substrate 21a, a transistor Q1, pads 22a and 23a provided on the upper surface of the substrate 21a, and an electrode (not shown) provided on the lower surface of the substrate 21a. The pads 22a, 23a, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q1, respectively. The semiconductor chip 20b includes a substrate 21b, a transistor Q2, pads 22b and 23b provided on the upper surface of the substrate 21b, and an electrode provided on the lower surface of the substrate 21b. The pads 22b, 23b, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q2, respectively. The semiconductor chip 20c includes a substrate 21c, a transistor Q3, pads 22c and 23c provided on the upper surface of the substrate 21c, and an electrode provided on the lower surface of the substrate 21c. The pads 22c, 23c, and the lower surface electrode are electrically connected to the gate G, drain D, and source S of the transistor Q3, respectively.

[0022] The substrates 21a to 21c are semiconductor substrates. When the transistors Q1 to Q3 are GaN HEMTs, the substrates 21a to 21c are, for example, silicon carbide (SiC) substrates, sapphire substrates or gallium nitride (GaN) substrates. When the transistors Q1 to Q3 are LDMOS, the substrates 21a to 21c are, for example, silicon (Si) substrates. The pads 22a to 22c, 23a to 23c and the bottom electrodes are metal layers such as gold layers, for example. The sizes of the transistors Q1 to Q3 are the same (for example, when the gate widths are the same and the saturation power is the same when the gate bias voltage and the drain bias voltage are the same).

[0023] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode provided on the lower surface of the dielectric substrate 25. The electrode 26 and the bottom electrode sandwiching the dielectric substrate 25 form a capacitor. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is a metal layer such as a gold layer, for example.

[0024] The bonding wires 46 electrically connect the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c, respectively. The bonding wires 47 electrically connect the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c, respectively. The bonding wires 48 electrically connect the pads 23a to 23c and the leads 28a to 28c, respectively. The bonding wires 46 to 48 are metal wires such as gold wires or aluminum wires, for example.

[0025] The bonding wires 46 and 47 function as inductors, and the capacitive components 24a to 24c function as capacitors. The bonding wires 46, 47 and the capacitive components 24a to 24c correspond to the matching circuits 30 to 32 of the T-type LCL circuit.

[0026] FIG. 3 is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Example 1 and Comparative Example 1.

[0027] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifiers 12 and 14. Each gain is the power gain of each of the main amplifier 10, the peak amplifiers 12 and 14. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. Note that Pin and Pout are in dB display. The gain of the main amplifier 10 with an input power Pin of power P1 or less is greater than the gain of the peak amplifier 12 with a power of P1 or more and P2 or less. That is, the slope of Pout with respect to the input power Pin at an input power Pin of power P1 or less of the main amplifier 10 is greater than the slope of Pout with respect to the input power Pin at an input power Pin of power P1 or more and P2 or less of the peak amplifier 12. However, FIG. 4 is a schematic diagram, and shows that the slope of Pout with respect to the input power Pin at an input power Pin of power P1 or less of the main amplifier 10 is smaller than the slope of Pout with respect to the input power Pin at an input power Pin of power P1 or more and P2 or less of the peak amplifier 12. The dashed line indicates Comparative Example 1, and the solid line indicates Example 1.

[0028] [Description of Comparative Example 1] In Comparative Example 1, the distribution ratios of the distributor 16 are the same for signals S2 and S3. As shown in FIG. 3, in Comparative Example 1, when the output power Pout is the power P0, the probability of the modulated wave is the highest. That is, when outputting a signal of the modulated wave, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is an A-class or AB-class amplifier, and the peak amplifiers 12 and 14 are C-class amplifiers. The input power Pin at which the peak amplifier 12 turns on is greater than the input power Pin at which the main amplifier 10 turns on, and the input power Pin at which the peak amplifier 14 turns on is greater than the input power Pin at which the peak amplifier 12 turns on. To operate in this way, it can be realized by making the gate bias voltage VG2 of the transistor Q2 more negative and greater than the gate bias voltage VG1 of the transistor Q1, and making the gate bias voltage VG3 of the transistor Q3 more negative and greater than the gate bias voltage VG2 of the transistor Q2.

[0029] As the input power Pin of the input signal Sin increases, and when the input power Pin exceeds the power P0 and reaches the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not operate. When the input power Pin is less than or equal to the power P1, as the input power Pin increases, the output power Pout of the main amplifier 10 increases linearly. Therefore, when the input power Pin is less than or equal to the power P1, each gain and the overall gain are almost constant.

[0030] When the input power Pin is greater than or equal to the power P1 and less than or equal to the power P2b, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not operate. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. Along with this, the overall gain also decreases. Since the peak amplifier 12 operates in a C-class mode, the gain of the peak amplifier 12 between the powers P1 and P2 is lower than the gain of the main amplifier 10 below the power P1. Also, the saturation power of the peak amplifier 12 is smaller than the saturation power of the main amplifier 10.

[0031] When the input power Pin is equal to or greater than P2b and equal to or less than P3b, all of the main amplifier 10, peak amplifiers 12 and 14 operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 saturates. For this reason, the gain of the peak amplifier 12 decreases. Along with this, the overall gain also decreases. Since the operating point of the peak amplifier 14 is more negative than that of the peak amplifier 12, the gain of the peak amplifier 14 between the powers P2 and P3 is lower than the gain of the peak amplifier 12 between the powers P1 and P2. Also, the saturation power of the peak amplifier 14 is smaller than the saturation power of the peak amplifier 12.

[0032] When the input power Pin is equal to or greater than P3b, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 saturates. For this reason, the gain of the peak amplifier 14 decreases. Along with this, the overall gain also decreases.

[0033] The product of the probability and the overall gain corresponds to the gain of the modulated wave. In order to improve the gain of the modulated wave, the overall gain at a high probability Pout is improved.

[0034] [Description of Example 1] In Example 1, the signal S2 is distributed more greatly than the signal S3. That is, assuming that the power amplitude of the signal S2 is A2 (expressed in W) and the power amplitude of the signal S3 is A3 (expressed in W), A2 > A3. For example, it is set such that A2:A3 = 2:1.

[0035] As shown in FIG. 3, when the input power Pin is equal to or less than P1, each Pout, each gain, and the overall gain are the same as in Comparative Example 1. When the input power Pin is equal to or greater than P1, in addition to the main amplifier 10, the peak amplifier 12 operates. Since the distribution ratio A2 / A3 of the signal S2 of the distributor 16 is greater than 1, the Pout of the peak amplifier 12 rises steeply compared to Comparative Example 1. The gain of the input signal Sin of the peak amplifier 12 with respect to the input power Pin is greater than that of Comparative Example 1. For this reason, the overall gain is greater than that of Comparative Example 1. The peak amplifier 12 saturates when the input power Pin reaches the power P2a. The power P2a is smaller than the power P2b of Comparative Example 1.

[0036] When the input power Pin becomes equal to or greater than the power P2a, all of the main amplifier 10, peak amplifiers 12 and 14 operate. Since the peak amplifier 12 saturates and the gain of the peak amplifier 12 decreases, the overall gain also decreases. Since the distribution ratio A3 / A2 of the signal S3 of the distributor 16 is less than 1, the Pout of the peak amplifier 14 rises more slowly compared to Comparative Example 1. The gain of the input signal Sin of the peak amplifier 14 with respect to the input power Pin becomes smaller than that of Comparative Example 1. For this reason, the overall gain becomes smaller than that of Comparative Example 1. The peak amplifier 14 saturates at the input power Pin at the power P3a. The power P3a is greater than the power P3b of Comparative Example 1.

[0037] As described above, in Example 1 compared to Comparative Example 1, when the input power Pin is between the powers P1 and P2a (or P2b), the overall gain becomes larger, and when the input power Pin is equal to or greater than the power P2a (or P2b), the overall gain becomes smaller.

[0038] The gain of the modulated wave is the product of the probability of the modulated wave and the overall gain. In Example 1, the distributor 16 distributes the power of the signal S2 to be greater than the power of the signal S3. Thereby, in the range of the powers P1 to P2a with a high probability, the overall gain becomes larger than that of Comparative Example 1. Therefore, the gain of the modulated wave can be improved compared to Comparative Example 1, and the characteristics are improved.

[0039] From the viewpoint of improving the gain of the modulated wave, the ratio A2 / A3 of the amplitude A2 of the power of the signal S2 to the amplitude A3 of the power of the signal S3 can be 1.2 or more, can be 1.5 or more, and can be 2 or more. If the amplitude A3 of the signal S3 is too small, the gain when the input power Pin is large will decrease. From this viewpoint, the ratio A2 / A3 can be 10 or less and can be 5 or less.

[0040] FIG. 4 is a Smith chart showing the load impedance in Example 1. The upper half of the Smith chart is illustrated. Note that each load impedance is a virtual value for explaining the load impedance of each amplifier. The load impedances Z10, Z12, and Z14 of the main amplifier 10, the peak amplifiers 12 and 14 are the impedances when viewed from the main amplifier 10, the peak amplifiers 12 and 14 to the matching circuits 33 to 35 (i.e., the synthesizer 18) in FIG. 1, respectively.

[0041] In FIG. 4, the gain matching impedance 52 is the impedance at which the gain (power gain) is maximized at the center frequency of the operating band when the main amplifier 10, the peak amplifiers 12 and 14 are subjected to load-pull measurement. The efficiency matching impedance 54 is the impedance at which the drain efficiency is maximized at the center frequency of the operating band when the main amplifier 10, the peak amplifiers 12 and 14 are subjected to load-pull measurement.

[0042] Note that in FIG. 4, the gain matching impedances 52 of the main amplifier 10, the peak amplifiers 12 and 14 coincide with each other, but they may be different from each other. The efficiency matching impedances 54 of the main amplifier 10, the peak amplifiers 12 and 14 coincide with each other, but they may be different from each other.

[0043] The load impedances Z10a, Z10b, and Z10c are the load impedances at the center frequency of the operating band when the input power Pin in the main amplifier 10 is the power P1, P2, and P3, respectively. The load impedances Z12b and Z12c are the load impedances at the center frequency of the operating band when the input power Pin in the peak amplifier 12 is the power P2 and P3, respectively. The load impedance Z14c is the load impedance at the center frequency of the operating band when the input power Pin in the peak amplifier 12 is the power P3.

[0044] When the input power Pin is the power P1, the load impedance Z10a is near the impedance 54 for efficiency matching. When the input power Pin is the power P2, the load impedances Z10b and Z12b are located between the impedance 54 for efficiency matching and the impedance 52 for gain matching. When the input power Pin is the power P3, the load impedances Z10c, Z12c, and Z14c are located near the load impedance 52 for gain matching. Thereby, at the power P1, the efficiency of the Doherty amplifier circuit 100 can be increased. The power P2 can moderately adjust the efficiency and gain of the Doherty amplifier circuit 100. At the power P3, the gain of the Doherty amplifier circuit 100 can be increased.

[0045] [Modification Example 1 of Embodiment 1] FIG. 5 is a Smith chart showing the load impedance in Modification Example 1 of Embodiment 1. As shown in FIG. 5, in Modification Example 1 of Embodiment 1, when the input power Pin of the peak amplifier 12 is the power P2, the load impedance Z12b is closer to the impedance 52 for gain matching than in Embodiment 1. Other configurations are the same as those in Embodiment 1 and the description thereof is omitted.

[0046] In Modification Example 1 of Embodiment 1, when the input power Pin is the power P2 (that is, when the main amplifier 10 and the peak amplifier 12 operate and the peak amplifier 14 does not operate), the first distance D1 is defined as the distance between the first position of the load impedance Z12b on the Smith chart and the second position of the impedance 52 for gain matching on the Smith chart. The second distance D2 is defined as the distance between the position of the load impedance Z10b on the Smith chart and the position of the impedance 52 for gain matching on the Smith chart. At this time, the distance D1 is shorter than the distance D2. Thereby, the gain of the peak amplifier 12 at the power P2 is improved, and the overall gain at the power P2a in FIG. 3 is improved. Therefore, the gain of the modulated wave can be improved, and the characteristics are further improved.

[0047] From the viewpoint of improving the gain of the peak amplifier 12 at the power P2, the distance D1 can be 0.8 times or less, 0.6 times or less, and 0.4 times or less of the distance D2.

[0048] In the power P2, let the distance between the position of the impedance 52 for gain matching of the peak amplifier 12 on the Smith chart and the third position of the impedance 54 for efficiency matching of the peak amplifier 12 on the Smith chart be D4. On the Smith chart, draw a circle 56 with the impedance 52 as the center and a diameter D5 equal to the distance D4. At this time, the load impedance Z12b is located within the circle 56. Thereby, in the power P2, the gain of the peak amplifier 12 can be improved, and the characteristics are further improved.

[0049] From the viewpoint of improving the gain of the peak amplifier 12 at the power P2, the diameter D5 of the circle 56 can be 0.8 times or less of the distance D4, can be 0.6 times or less of the distance D4, and can be 0.4 times or less of the distance D4.

[0050] When the input power Pin is the power P3 (that is, when the main amplifier 10, the peak amplifiers 12 and 14 are operating), let the third distance D3 (substantially 0 in FIG. 5) be the distance between the fourth position of the load impedance Z12c of the peak amplifier 12 on the Smith chart and the second position of the impedance 52 for gain matching on the Smith chart. At this time, the third distance is equal to or less than the first distance D1. Thereby, at the powers P2 and P3, the gain of the peak amplifier 12 can be improved, and the characteristics can be further improved.

[0051] From the viewpoint of improving the gain of the peak amplifier 12 at the power P3, the third distance D3 can be 0.8 times or less of the first distance D1, can be 0.6 times or less of the first distance D1, and can be 0.4 times or less of the first distance D1.

[0052] As in Example 1 and its Modification 1, when the same bias voltages (gate bias voltage and drain bias voltage) are supplied to the peak amplifier 12 and the peak amplifier 14, the saturation power of the peak amplifier 12 and the saturation power of the peak amplifier 14 may be equal. Thereby, as the peak amplifiers 12 and 14, amplifiers (for example, semiconductor chips) having the same structure can be used. Note that the equality (or approximate equality) of the saturation power of the peak amplifier 12 and the saturation power of the peak amplifier 14 allows for a difference on the order of manufacturing error. For example, the difference between the saturation power of the peak amplifier 12 and the saturation power of the peak amplifier 14 can be set to 1 dBm or less, and can be set to 0.5 dBm or less. Note that the saturation power does not have to be the power at which the output power is completely saturated, and the saturation power may be, for example, about 1 dBm to 3 dBm lower than the power at which the output power is completely saturated. When comparing the saturation powers of different amplifiers, the comparison may be made using the power that is lower by a certain value from the power at which the output power is completely saturated.

[0053] [Example 2] FIG. 6 is a plan view of the semiconductor device in Example 2. As shown in FIG. 6, in the semiconductor device 104 of Example 2, the transistor Q2 is larger than the transistor Q3. That is, the transistor Q2 is larger than the transistor Q3 (for example, has a larger gate width and has a larger saturation power when the gate bias voltage and the drain bias voltage are the same).

[0054] FIG. 7 is a schematic diagram showing the probability with respect to Pout, Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Example 2 and Example 1. The broken line indicates Example 1, and the solid line indicates Example 2.

[0055] When the same gate bias voltage and drain bias voltage are supplied to transistors Q2 and Q3, let the saturation powers of transistors Q2 and Q3 be Ps2 and Ps3 (in W), respectively. At this time, assume that the ratio Ps2 / Ps3 of Ps2 (in W) to Ps3 is approximately equal to the ratio A2 / A3. At this time, when the input power Pin becomes larger than the power P1, the gain of the peak amplifier 12 is almost the same between Example 2 and Example 1. The peak amplifier 12 of Example 1 saturates at a power smaller than the power P2 (the power P2a in FIG. 3), while the peak amplifier 12 of Example 2 does not saturate up to the power P2 (the power P2b in FIG. 3). Therefore, the gain of the peak amplifier 12 does not decrease up to the power P2. The overall gain of Example 2 does not decrease up to a larger input power Pin than that of Example 1 in the vicinity of the power P2.

[0056] When the input power Pin becomes larger than the power P2, the gain of the peak amplifier 14 is almost the same between Example 2 and Example 1. The peak amplifier 14 of Example 1 saturates at a power larger than the power P3, while the peak amplifier 14 of Example 2 saturates at the power P3. Therefore, the gain of the peak amplifier 14 decreases at a power P3 smaller than that of Example 1. The overall gain of Example 2 is smaller than that of Example 1 in the vicinity of the power P3.

[0057] In Example 2, when the same bias voltage (gate bias voltage and drain bias voltage) is supplied to the peak amplifier 12 and the peak amplifier 14, the saturation power of the peak amplifier 12 is made larger than the saturation power of the peak amplifier 14. Thereby, in the vicinity of P2 where the probability of the modulated wave is high, the overall gain becomes larger than that of Example 1. Therefore, the gain of the modulated wave can be improved compared to Example 1, and the characteristics can be further improved.

[0058] From the viewpoint of improving the gain of the modulated wave, the saturation power Ps2 (in W) of the peak amplifier 12 can be 1.2 times or more, 1.5 times or more, and 2 times or more that of the saturation power Ps3 (in W) of the peak amplifier 14. If the saturation power Ps3 of the peak amplifier 14 is too small, the gain when the input power Pin is large will decrease. From this viewpoint, the ratio Ps2 can be 10 times or less, and 5 times or less that of Ps3. The ratio of the saturation powers Ps2 / Ps3 can be 0.5 times or more and 2 times or less, and 0.8 times or more and 1.25 times or less the ratio of the distribution A2 / A3 of the distributor 16.

[0059] Although the 3-way Doherty amplifier circuit has been described as an example, in the case of an N-way Doherty amplifier circuit, N-1 peak amplifiers may be provided. In FIG. 4, when the same gate bias voltage and drain bias voltage are supplied to the main amplifier 10, the peak amplifiers 12 and 14, the saturation powers of the main amplifier 10, the peak amplifiers 12 and 14 have been described as being the same, but the saturation powers of the main amplifier 10, the peak amplifiers 12 and 14 may be different.

[0060] It should be considered that all aspects of the embodiments disclosed this time are illustrative and not restrictive. The scope of the present disclosure is shown not by the above meaning, but by the scope of the claims, and all modifications within the meaning and scope equivalent to the scope of the claims are intended to be included.

Explanation of reference numerals

[0061] 10 Main amplifier 12 (First peak amplifier), 14 (Second peak amplifier) Peak amplifier 16 Distributor 18 Combiner 20a, 20b, 20c Semiconductor chips 21a, 21b, 21c Substrates 22a, 22b, 22c, 23a, 23b, 23c Pads 24a, 24b, 24c Capacitive components 25 Dielectric substrate 26 electrodes 27a, 27b, 27c, 28a, 28b, 28c leads 30, 31, 32, 33, 34, 35 integrated circuits 36, 37, 38, 39 bias circuits 46, 47, 48 bonding wires 50 package 51 base 52, 54 impedance 56 circle 100 Doherty amplifier circuit S1 (first signal), S2 (second signal), S3 (third signal), S4 (fourth signal), S5 (fifth signal), S6 (sixth signal) signals Sin input signal Sout output signal Tin input terminal Tout output terminal D1 (first distance), D2 (second distance), D4 distances D5 diameter

Claims

1. A distributor that distributes an inputted input signal into a first signal, a second signal, and a third signal, and distributes the power of the second signal to be greater than the power of the third signal; A main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; A first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; A second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; A synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal to an output terminal as an output signal; Comprising; A Doherty amplifier circuit in which the input power of the input signal when the first peak amplifier is turned on is smaller than the input power when the second peak amplifier is turned on.

2. When the main amplifier and the first peak amplifier are operating and the second peak amplifier is not operating, A first distance between a first position on a Smith chart of an impedance at a center frequency of an operating band seen from the first peak amplifier to the synthesizer and a second position on the Smith chart of the impedance at the center frequency seen from the first peak amplifier to the synthesizer where the gain of the first peak amplifier is maximum is Shorter than a second distance between a position on the Smith chart of the impedance at the center frequency seen from the main amplifier to the synthesizer and a position on the Smith chart of the impedance at the center frequency seen from the main amplifier to the synthesizer where the gain of the main amplifier is maximum. The Doherty amplifier circuit according to Claim 1.

3. The Doherty amplifier circuit according to Claim 2, wherein the first position on the Smith chart is centered on the second position, and a distance between the first position and a third position on the Smith chart of the impedance at the center frequency seen from the first peak amplifier to the synthesizer where the efficiency of the first peak amplifier is maximum is located within a circle having the distance as a diameter.

4. When the main amplifier, the first peak amplifier, and the second peak amplifier are operating, A third distance between a fourth position on the Smith chart of the impedance at the center frequency seen from the first peak amplifier to the synthesizer and the second position is less than or equal to the first distance. The Doherty amplifier circuit according to Claim 2 or Claim 3.

5. The Doherty amplifier circuit according to any one of claims 1 to 3, wherein when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is greater than the saturation power of the second peak amplifier.

6. The Doherty amplifier circuit according to any one of claims 1 to 3, wherein when the same bias voltage is supplied to the first peak amplifier and the second peak amplifier, the saturation power of the first peak amplifier is equal to the saturation power of the second peak amplifier.

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