Semiconductor device and semiconductor system

Abstract

To provide a semiconductor device and a semiconductor system in which the deterioration of a circuit can be suppressed.SOLUTION: A semiconductor device includes one or a plurality of first circuits that output a first output voltage, a second circuit that outputs a second output voltage different from the first output voltage and used to drive a liquid crystal display, a pad, which is a terminal, that supplies at least one of the first output voltage and the second output voltage to a driving circuit for the liquid crystal display and shared by the first circuit and the second circuit, a P-type transistor included in the first circuit and connected to the pad, a comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal with a high-level or low-level potential corresponding to the comparison result, and a switching circuit that switches the potential to be applied to the gate of the P-type transistor to the first output voltage or the second output voltage in accordance with the level of the comparison result signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a semiconductor system.

Background Art

[0002] Patent Document 1 discloses an analog switch circuit that suppresses current flow through a power supply terminal when the voltage of a signal input to a terminal becomes equal to or higher than the power supply voltage input to the power supply terminal. The analog switch circuit of Patent Document 1 continues to maintain an off state even when the VA voltage input to the terminal becomes equal to or higher than the power supply voltage input to the power supply terminal D. Thereby, even when the VA voltage input to terminal A is higher than the VDD voltage input to the power supply terminal D, current flow through the power supply terminal is suppressed.

[0003] On the other hand, in the case of a semiconductor device including a PAD which is a terminal that shares an input / output port which is a general-purpose port for outputting a power supply voltage VDD or the like, and an LCD port for outputting a voltage VL supplied to an LCD driver, when the voltage VL becomes higher than the power supply voltage VDD (VL > VDD), current may flow through a transistor (for example, a P-type MOS transistor) connected to the PAD to which the voltage VL is applied.

[0004] A power supply voltage VDD and a voltage generated at the PAD (PAD voltage) can be applied to the NWELL region of the transistor by a voltage selection circuit. The NWELL region of the transistor may include wiring connected to the transistor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the circuit disclosed in Patent Document 1, when VDD >> PAD voltage, the diode between VDD and PAD is in an on state (the PMOS is also in an on state due to the voltage), and VDD and the NWELL region are connected with low resistance. The same applies when VDD << PAD voltage. The diode may be interpreted as a parasitic diode formed in the P-type MOS transistor constituting the voltage selection circuit.

[0007] However, when the voltage difference between VDD and the PAD voltage is small, that is, when VDD is almost equal to the PAD voltage, the P-type MOS transistor constituting the voltage selection circuit becomes high resistance. Specifically, the diode included in the P-type MOS transistor constituting the voltage selection circuit is not turned on, and the PMOS transistor is also not turned on. Therefore, the resistance between the NWELL region and the PAD becomes high, and the resistance between the NWELL region and VDD may also become high. For this reason, when the output level of the input / output port changes from L to H, and when the input level of the input / output port changes from L to H, the voltage of the PAD changes from 0V to VDD, and through the parasitic capacitance of the PMOS connected to the PAD, the voltage of the NWELL region temporarily increases. As a result, the deterioration of the PMOS may progress.

[0008] As described above, in the prior art, there is room for improvement in suppressing the deterioration of the circuit (such as PMOS) of the semiconductor device having a terminal which is a PAD sharing the input / output port and the LCD port.

[0009] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a semiconductor system capable of suppressing the deterioration of a circuit.

Means for Solving the Problem

[0010] To solve the above problems, a semiconductor device according to the present disclosure includes one or more first circuits that output a first output voltage, a second circuit that outputs a second output voltage for driving a liquid crystal display, which is different from the first output voltage, a pad that supplies at least one of the first output voltage and the second output voltage to a driving circuit of the liquid crystal display, and is a terminal shared by the first circuit and the second circuit, a P-type transistor included in the first circuit and connected to the pad, a comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal of a high-level or low-level potential corresponding to the comparison result, and a switching circuit that switches the potential applied to the gate of the P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are given to the same functions and configurations, and the description thereof will be omitted as appropriate.

[0013] (First Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device 100-1 may be interpreted as a circuit 200 that supplies a specific voltage to a liquid crystal display (LCD). The specific voltage may include a voltage VP and a voltage VN.

[0014] Here, both the voltage VP and the voltage VN are voltages obtained by dividing a voltage VL described later. Note that in the present embodiment, it is described that VP>VN, but it is not limited thereto. The voltage VL may be interpreted as a voltage output by a booster circuit (not shown) provided in the second circuit 20.

[0015] Furthermore, the range of the voltage VL may be 2.85 [V] to 5.175 [V]. When the power supply voltage VDD is within the voltage range described later, the voltage VL may be set within this range. When the power supply voltage VDD is lower than a specific value, the voltage VL may be a value higher than the power supply voltage VDD. Specifically, when the power supply voltage VDD is 3 [V], the voltage VL may be 5 [V].

[0016] The semiconductor device 100-1 may include one or more first circuits 10, a second circuit 20, a pad 30, a P-type transistor 40, and a switching circuit 60.

[0017] (First Circuit 10) The first circuit 10 may be interpreted as an input / output port that outputs a first output voltage. The first output voltage may be interpreted as the power supply voltage VDD or the voltage VSS. Hereinafter, the power supply voltage VDD may be simply referred to as VDD, and the voltage VSS may be simply referred to as VSS. Here, the power supply voltage VDD may be applied from a power supply circuit (not shown) provided outside the first circuit 10. Also, the range of VDD may be 1.8 [V] to 5.5 [V]. The input / output port may be interpreted as a port input / output circuit, a port input / output terminal, or a general-purpose port.

[0018] The first circuit 10 may include a P-type transistor 40, a control circuit 11, an NMOS transistor 12, a PMOS transistor 13, and a PMOS transistor 14.

[0019] (P-type transistor 40) The P-type transistor 40 may be included in the first circuit 10. The P-type transistor 40 may be interpreted as a PMOS transistor connected to the pad 30. VDD is applied to the drain of the P-type transistor 40. The drain of the P-type transistor 40 may be connected to the gate of the PMOS transistor 14 and the gate of the NMOS transistor 12.

[0020] The gate of the P-type transistor 40 may be connected to the drain of the PMOS transistor 14. The gate of the P-type transistor 40 may be connected to the drain of the NMOS transistor 12. The gate of the P-type transistor 40 may be connected to the source of the PMOS transistor 13.

[0021] The source of the P-type transistor 40 may be connected to the source of the PMOS transistor 14, the gate of the PMOS transistor 13, and the pad 30.

[0022] (NMOS transistor 12 and PMOS transistor 13) The NMOS transistor 12 and the PMOS transistor 13 may be interpreted as an analog switch circuit.

[0023] VDD is applied to the gate of the NMOS transistor 12. The drain of the NMOS transistor 12 may be connected to the gate of the P-type transistor 40 and the source of the PMOS transistor 13.

[0024] The source of the NMOS transistor 12 may be connected to the control circuit 11 and the drain of the PMOS transistor 13.

[0025] The gate of the PMOS transistor 13 may be connected to the gate of the PMOS transistor 14, the gate of the P-type transistor 40, and the pad 30. The drain of the PMOS transistor 13 may be connected to the control circuit 11.

[0026] (Second circuit 20) The second circuit 20 may be interpreted as an LCD output port that outputs a second output voltage for driving an LCD, which is different from the first output voltage. The second output voltage may be interpreted as the voltage VP or the voltage VN. Hereinafter, the voltage VP may simply be referred to as VP, and the voltage VN may simply be referred to as VN. The LCD output port may be interpreted as an LCD output circuit or an LCD output terminal.

[0027] The second circuit 20 may include a control circuit 21, a PMOS transistor 22, and an NMOS transistor 23.

[0028] The gate of the PMOS transistor 22 may be connected to the control circuit 21. The power supply voltage VP is applied to the drain of the PMOS transistor 22. The source of the PMOS transistor 22 may be connected to the drain of the NMOS transistor 23 and the pad 30.

[0029] The gate of the NMOS transistor 23 may be connected to the control circuit 21. The drain of the NMOS transistor 23 may be connected to the source of the PMOS transistor 22 and the pad 30. The voltage VN is applied to the source of the NMOS transistor 23.

[0030] (Pad 30) The pad 30 may supply the second output voltage to a driving circuit of an LCD (not shown) and may be interpreted as a terminal shared by the first circuit 10 and the second circuit 20. The pad 30 may be interpreted as a metal portion for wire bonding to the semiconductor device 100-1.

[0031] The first circuit 10 and the second circuit 20 may be connected to the pad 30. The VDD or VSS output from the first circuit 10 may be applied to the pad 30. The VP or VN output from the second circuit 20 may be applied to the pad 30.

[0032] Specifically, when the first circuit 10 is operating, the VDD may be applied to the pad 30. This VDD may be interpreted as the VDD output from the first circuit 10.

[0033] When the second circuit 20 is operating and VL is greater than VDD (VL > VDD), VP or VN may be applied to the pad 30. This VP and VN may be interpreted as the VP and VN output from the second circuit 20.

[0034] When the second circuit 20 is operating and VDD is greater than VL (VDD > VL), VP or VN may be applied to the pad 30. This VP and VN may be interpreted as the VP and VN output from the second circuit 20.

[0035] (Comparison Circuit) The comparison circuit 50 may be interpreted as a circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal, which is a signal of a high level (H) or a low level (L) potential corresponding to the comparison result.

[0036] Specifically, the comparison circuit 50 compares the respective values of VL and VDD. When VL > VDD, the comparison circuit 50 becomes a high level (H). When VDD > VL, the comparison circuit 50 becomes a low level (L).

[0037] The output of the comparison circuit 50 is input to the level shift circuit 1, the inverter circuit 2, and the first switch 61 of the switching circuit 60.

[0038] The level shift circuit 1 may be interpreted as a circuit that outputs a voltage having a value different from the input voltage with the same waveform as the input voltage. Specifically, the level shift circuit 1 may convert VDD to VL and output it. The output of the level shift circuit 1 is input to the first switch 61 and the inverter circuit 3.

[0039] The inverter circuit 3 may invert the value of the input voltage and input it to the second switch 62. The inverter circuit 2 may invert the value of the input voltage and input it to the second switch 62.

[0040] (Switching Circuit 60) The switching circuit 60 may be interpreted as a circuit that switches the potential applied to the gate of the P-type transistor 40 to the first output voltage or the second output voltage according to the level of the comparison result signal. The switching circuit 60 may include a first switch 61 and a second switch 62.

[0041] (The first switch 61) The first switch 61 may include two PMOS transistors. Among the two PMOS transistors, the first transistor inputs the voltage from the level shift circuit 1, and the second transistor inputs the voltage from the comparison circuit 50.

[0042] When VL > VDD, that is, when the second output voltage is higher than the first output voltage, the first switch 61 turns off, so that the VDD which is the first output voltage is not applied to the gate of the P-type transistor 40.

[0043] When VDD > VL, that is, when the first output voltage is higher than the second output voltage, the first switch 61 turns on, so that the VDD which is the first output voltage may be applied to the gate of the P-type transistor 40.

[0044] Specifically, when VDD > VL, the first switch 61 may input the level of the comparison result signal without inverting it and apply the VDD which is the first output voltage to the gate of the P-type transistor 40. The level of the comparison result signal may be interpreted as the output voltage level of the comparison circuit 50.

[0045] (The second switch 62) The second switch 62 may include two PMOS transistors. Among the two PMOS transistors, the first transistor inputs the voltage from the inverter circuit 2, and the second transistor inputs the voltage from the inverter circuit 3.

[0046] When VL > VDD, the second switch 62 may invert the level of the comparison result signal and input it, and apply VL, which is the second output voltage, to the gate of the P-type transistor 40. Specifically, when VL > VDD, that is, when the second output voltage is higher than the first output voltage, the second switch 62 may be turned on to apply VL, which is the second output voltage, to the gate of the P-type transistor 40.

[0047] When VDD > VL, that is, when the first output voltage is higher than the second output voltage, the second switch 62 turns off, so that the second output voltage is not applied to the gate of the P-type transistor 40.

[0048] (Operation of the semiconductor device 100-1) Next, the operation of the semiconductor device 100-1 will be described with reference to FIGS. 2 and 3. FIGS. 2 and 3 are timing charts for explaining the operation of the semiconductor device according to the first embodiment. FIG. 2 shows the voltage when VDD > VL. FIG. 3 shows the voltage when VL > VDD.

[0049] FIGS. 2 and 3 show the pad 30, the voltage applied to the NWELL region of the P-type MOS transistor 40, and the like. N1 is the voltage between the PMOS transistor 13 and the NMOS transistor 12 and the control circuit 11. N2 is the voltage between the PMOS transistor 13 and the NMOS transistor 12 and the P-type transistor 40. N3 is the voltage between the NMOS transistor 12 connected to the source of the P-type transistor 40 and the control circuit 11. N4 is the voltage between the PMOS transistor 22 and the control circuit 21. N5 is the voltage between the NMOS transistor 23 and the control circuit 21.

[0050] (When using the port input / output circuit) When using the port input / output circuit, that is, when using the first circuit 10, since the input of the comparison circuit 50 is VDD > VL, the output level of the comparison circuit 50 becomes L. As a result, the first switch 61 turns on and the second switch 62 turns off. Therefore, the first output voltage, VDD, is applied to the gate of the P-type transistor 40 and the NWELL region of the P-type MOS transistor 40.

[0051] When using the port input / output circuit, since the second circuit 20, which is the LCD circuit, is not operating, the respective values of VL, VP, and VN can be specific voltages from 0 [V] to VDD.

[0052] That the first switch 61 is on can be interpreted as the gate potential of the two PMOS transistors included in the first switch 61 being L, that is, 0 [V], or it can be interpreted as the two PMOS transistors included in the first switch 61 being in the on state.

[0053] That the second switch 62 is off can be interpreted as VDD being applied to the gate of the first transistor and VL being applied to the gate of the second transistor among the two PMOS transistors included in the second switch 62, so that the two PMOS transistors are in complementary on or off states. With this configuration, regardless of the magnitude relationship between VL and VDD, one of the two PMOS transistors turns off and the second switch 62 turns off.

[0054] (Example 1 when using the LCD circuit) When using the LCD circuit, that is, when using the second circuit 20, as shown in FIG. 3, when the input of the comparison circuit 50 is VL > VDD, the output level of the comparison circuit 50 becomes H. As a result, the first switch 61 turns off and the second switch 62 turns on. Therefore, the second output voltage, VL, is applied to the gate of the P-type transistor 40 and the NWELL region of the P-type transistor 40.

[0055] (Example 2 when using the second circuit 20) When using the LCD circuit, as shown in FIG. 2, when the input of the comparison circuit 50 is VDD > VL, the output level of the comparison circuit 50 becomes L. As a result, the first switch 61 turns on and the second switch 62 turns off. Therefore, the first output voltage VDD is applied to the gate of the P-type transistor 40 and the NWELL region of the P-type transistor 40.

[0056] (Comparative Example) FIG. 4 is a diagram showing the configuration of a semiconductor device according to a comparative example. The semiconductor device 100A according to the comparative example includes a first circuit 10 provided with a voltage selection circuit 15. The semiconductor device 100A does not include the comparison circuit and the switching circuit 60 shown in FIG. 1.

[0057] The voltage selection circuit 15 includes a PMOS transistor 15a and a PMOS transistor 15b.

[0058] The gate of the PMOS transistor 15a may be connected to the source of the P-type transistor 40, the source of the PMOS transistor 15b, and the pad 30.

[0059] The source of the PMOS transistor 15a may be connected to the drain of the PMOS transistor 15b, the gate of the P-type transistor 40, the gate of the PMOS transistor 13, and the gate of the PMOS transistor 14.

[0060] VDD is applied to the drain of the PMOS transistor 15a. The drain of the PMOS transistor 15a may be connected to the gate of the PMOS transistor 15a and the gate of the PMOS transistor 15b.

[0061] The drain of the PMOS transistor 15b may be connected to the source of the PMOS transistor 15a, the gate of the P-type transistor 40, the gate of the PMOS transistor 13, and the gate of the PMOS transistor 14.

[0062] The source of PMOS transistor 15b may be connected to the gate of PMOS transistor 13, the source of PMOS transistor 14, and pad 30.

[0063] To the NWELL region of P-type MOS transistor 40, the power supply voltage VDD and the voltage generated at pad 30 (PAD voltage) may be applied by voltage selection circuit 15. The NWELL region of P-type MOS transistor 40 may include wiring connected to the transistor.

[0064] (Operation of the semiconductor device according to the comparative example) Next, with reference to FIG. 5, the operation of semiconductor device 100A according to the comparative example will be described. FIG. 5 is a timing chart for explaining the operation of the semiconductor device according to the comparative example.

[0065] FIG. 5 shows pad 30, the voltage applied to the NWELL region of P-type MOS transistor 40, etc. N1 is the voltage between PMOS transistor 13 and NMOS transistor 12 and control circuit 11. N2 is the voltage between PMOS transistor 13 and NMOS transistor 12 and P-type transistor 40. N3 is the voltage between the NMOS transistor connected to the source of P-type transistor 40 and control circuit 11. N4 is the voltage between PMOS transistor 22 and control circuit 21. N5 is the voltage between NMOS transistor 23 and control circuit 21.

[0066] As shown in FIG. 4, in semiconductor device 100A having pad 30 shared by first circuit 10 and second circuit 20, when VL is higher than VDD (VL > VDD), current may flow through P-type transistor 40 connected to pad 30.

[0067] Specifically, when VDD is higher than the PAD voltage, the diode is in an on state, and VDD and the NWELL region are connected with low resistance. The diode may be interpreted as parasitic diodes formed in PMOS transistor 15a and PMOS transistor 15b. Specifically, the diode may be interpreted as a unidirectional element connected between the drains and sources of PMOS transistor 15a and PMOS transistor 15a respectively.

[0068] This is the same when the PAD voltage is higher than VDD. Depending on the voltage value, PMOS transistor 15a and PMOS transistor 15b may also be in an on state.

[0069] However, when VDD is approximately equal to the PAD voltage, that is, when the voltage difference between VDD and the PAD voltage is small, PMOS transistor 15a and PMOS transistor 15b that make up the voltage selection circuit 15 become high resistance.

[0070] Specifically, when the voltage difference between VDD and the PAD voltage is small, the aforementioned diode does not turn on, that is, PMOS (PMOS transistor 15a and PMOS transistor 15b) does not turn on. For this reason, the resistance between the NWELL region of P-type transistor 40 and pad 30 can become high. Also, the resistance between the NWELL region of P-type transistor 40 and VDD can become high.

[0071] Therefore, when the output level of the input / output port changes from L to H, and when the input level of the input / output port changes from L to H, the PAD voltage changes from 0 [V] to VDD.

[0072] When the output level of the input / output port changes from L to H, it may be interpreted as when NMOS transistor 12 changes from an on state to PMOS transistor 13 being in an on state.

[0073] When the output level of the input / output port changes from L to H, it may be interpreted as when the NMOS transistor 12 changes from the state of outputting a voltage of level L to the state of outputting a voltage of level H.

[0074] When the input level of the input / output port changes from L to H, it may be interpreted as when the level of the digital signal changes from L to H. The digital signal may be interpreted as a signal transmitted from an external circuit connected to the pad 30.

[0075] As a result, the voltage of the NWELL region temporarily increases through the parasitic capacitance of the P-type transistor 40 connected to the pad 30. Specifically, as shown in part A of FIG. 5, a voltage exceeding VDD temporarily occurs in the NWELL region of the P-type transistor 40. This may cause the deterioration of the P-type transistor 40 to progress.

[0076] (Operation and Effect) In the semiconductor device 100-1 of the present disclosure, the NWELL region of the P-type transistor 40 can be connected to VDD or VL with low resistance by the first switch 61 or the second switch 62.

[0077] Specifically, depending on the magnitude relationship between the voltages of VDD and VL, one of the first switch 61 and the second switch 62 is turned on, so that the NWELL region can be connected to VDD or VL with low resistance.

[0078] By reducing the voltage of the NWELL region, which is a factor causing the deterioration of circuits such as the P-type transistor 40, it is possible to suppress the voltage fluctuation of the NWELL region, that is, to suppress the increase in the voltage of the NWELL region.

[0079] (Second Embodiment) FIG. 6 is a diagram showing the configuration of a semiconductor device and a semiconductor system according to the second embodiment of the present disclosure. The difference from the semiconductor device 100-1 shown in FIG. 1 is that the semiconductor device 100-2 according to the second embodiment includes a logical product circuit 300 in addition to the circuit 200.

[0080] The semiconductor system 400 shown in FIG. 6 may include a plurality of circuits 200 included in the semiconductor device 100-2. Among the plurality of circuits 200, an AND circuit 300 is provided. The comparison result signal of one comparison circuit 50 is input to the AND circuits 300 provided in each of the plurality of circuits 200. That is, the output signal of the comparison circuit 50 branches and is input to the plurality of circuits 200.

[0081] The AND circuit 300 may be connected to the output side of the comparison circuit 50. The AND circuit 300 may input the comparison result signal and a control signal lcd_en for controlling the operation of the second circuit 20. The AND circuit 300 may output a signal at a level corresponding to the logical product result of the comparison result signal and the control signal.

[0082] The signal at the level corresponding to the logical product result may be interpreted as a signal including a low-level (L) or high-level (H) voltage.

[0083] For example, when the first circuit 10 is in use, by setting the control signal lcd_en = L, the output of the AND circuit 300 is always L. Therefore, regardless of the state of the output signal of the comparison circuit 50, the voltage of the NWELL region becomes VDD.

[0084] When the second circuit 20 is in use, by setting the control signal lcd_en = H, the states of the first switch 61 and the second switch 62 are switched according to the output signal of the comparison circuit 50. Therefore, the semiconductor device 100-2 can realize the same operation as in the first embodiment.

[0085] (Operation of the semiconductor device 100-2) When the level of the control signal is L, the AND circuit 300 outputs an L signal to the switching circuit 60. Thereby, regardless of the level of the signal at the H or L potential corresponding to the comparison result, the switching circuit 60 is operated so that the potential applied to the gate of the P-type MOS transistor 40 is maintained at the first output voltage.

[0086] The AND circuit 300 outputs a high signal to the switching circuit 60 when the level of the comparison result signal is high and the level of the control signal is high. Thereby, according to the level of the comparison result signal, the switching circuit 60 is operated so as to switch the potential applied to the gate of the P-type MOS transistor 40 to the first output voltage or the second output voltage.

[0087] As described above, according to the present disclosure, it is possible to provide a semiconductor device and a semiconductor system capable of suppressing circuit degradation.

[0088] In addition, the following supplementary notes are further disclosed regarding the above description.

[0089] (Supplementary Note 1) One or more first circuits that output a first output voltage, A second circuit that outputs a second output voltage for driving a liquid crystal display, different from the first output voltage, A pad that supplies at least one of the first output voltage and the second output voltage to a drive circuit of the liquid crystal display and is a terminal shared by the first circuit and the second circuit, A P-type transistor included in the first circuit and connected to the pad, A comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal of a high level or a low level potential corresponding to the comparison result, A switching circuit that switches the potential applied to the gate of the P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal, A semiconductor device comprising: (Supplementary Note 2) The switching circuit is: A first switch that, when the second output voltage is higher than the first output voltage, turns off so as not to apply the first output voltage to the gate, and when the first output voltage is higher than the second output voltage, turns on so as to apply the first output voltage to the gate, When the second output voltage is higher than the first output voltage, by turning on, the second output voltage is applied to the gate. When the first output voltage is higher than the second output voltage, by turning off, the second output voltage is not applied to the gate. A second switch; The semiconductor device according to appended claim 1, comprising the same. (Appended claim 3) The first switch inputs the level of the comparison result signal without inverting it, and applies the first output voltage to the gate. The second switch inputs the level of the comparison result signal after inverting it, and applies the second output voltage to the gate. The semiconductor device according to appended claim 2. (Appended claim 4) An AND circuit that inputs the comparison result signal and a control signal for controlling the operation of the second circuit, and outputs a signal having a level corresponding to the logical product result of the comparison result signal and the control signal. The AND circuit When the level of the control signal is a low level, by outputting a low-level signal to the switching circuit, regardless of the level of the signal having a high level or low level potential corresponding to the comparison result, the potential applied to the gate is maintained at the first output voltage. The switching circuit is operated so as to be maintained. When the level of the comparison result signal is a high level and the level of the control signal is a high level, by outputting a high-level signal to the switching circuit, the potential applied to the gate is set to the first output voltage or the second output voltage according to the level of the comparison result signal. The switching circuit is operated so as to be switched. The semiconductor device according to appended claim 1. (Appended claim 5) A semiconductor system including a plurality of semiconductor devices according to claim 1, The plurality of semiconductor devices are provided with the AND circuit, A comparison result signal of one of the comparison circuits is input to the AND circuits provided in each of the plurality of semiconductor devices. A semiconductor system.

Explanation of reference numerals

[0090] 1 Level Shift Circuit 2 Inverter Circuit 3 Inverter Circuit 10 First Circuit 11 Control Circuit 12 NMOS Transistor 13 PMOS Transistor 14 PMOS Transistor 15 Voltage Selection Circuit 15a PMOS Transistor 15b PMOS Transistor 20 Second Circuit 21 Control Circuit 22 PMOS Transistor 23 NMOS Transistor 30 Pad 40 P-Type Transistor 50 Comparison Circuit 60 Switching Circuit 61 First Switch 62 Second Switch 100-1 Semiconductor Device 100-2 Semiconductor Device 100A Semiconductor Device 200 Circuit 300 AND Circuit 400 Semiconductor System

Claims

1. One or more first circuits that output a first output voltage, A second circuit that outputs a second output voltage for driving a liquid crystal display, which is different from the first output voltage, A pad that supplies at least one of the first output voltage and the second output voltage to a driving circuit of the liquid crystal display and is a terminal shared by the first circuit and the second circuit, A P-type transistor included in the first circuit and connected to the pad, A comparison circuit that compares the first output voltage and the second output voltage and outputs a comparison result signal that is a signal of a high-level or low-level potential corresponding to the comparison result, A switching circuit that switches the potential applied to the gate of the P-type transistor to the first output voltage or the second output voltage according to the level of the comparison result signal, A semiconductor device comprising the above.

2. The switching circuit is, When the second output voltage is higher than the first output voltage, it turns off, so that the first output voltage is not applied to the gate. When the first output voltage is higher than the second output voltage, it turns on, so that the first output voltage is applied to the gate. A first switch, When the second output voltage is higher than the first output voltage, it turns on, so that the second output voltage is applied to the gate. When the first output voltage is higher than the second output voltage, it turns off, so that the second output voltage is not applied to the gate. A second switch, The semiconductor device according to claim 1, comprising the above.

3. The first switch inputs the level of the comparison result signal without inverting it and applies the first output voltage to the gate, The second switch inputs the level of the comparison result signal after inverting it and applies the second output voltage to the gate. The semiconductor device according to claim 2.

4. Comprising a logical product circuit that inputs the comparison result signal and a control signal for controlling the operation of the second circuit and outputs a signal of a level corresponding to the logical product result of the comparison result signal and the control signal, The logical product circuit is, When the level of the control signal is low, it outputs a low-level signal to the switching circuit, so that regardless of the level of the signal of the high-level or low-level potential corresponding to the comparison result, the potential applied to the gate is maintained at the first output voltage, and the switching circuit is operated. When the level of the comparison result signal is high and the level of the control signal is high, a high-level signal is output to the switching circuit, and the switching circuit is operated so that the potential applied to the gate is switched between the first output voltage and the second output voltage according to the level of the comparison result signal. The semiconductor device according to claim 1.

5. A semiconductor system including a plurality of semiconductor devices according to claim 4, wherein the plurality of semiconductor devices are provided with the AND circuit, A semiconductor system in which a comparison result signal of one of the comparison circuits is input to the AND circuits provided in each of the plurality of semiconductor devices.

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