LSI device and failure detection method

Abstract

To detect leak current by a failure with high accuracy during an IDDQ test.SOLUTION: An LSI device 100 includes a logic circuit 11 in which a plurality of function blocks having a different highest operation frequency are connected, a test control part 12 for inputting a plurality of test patterns prepared in advance in each block reset pattern being a pattern for resetting a function block other than an object function block to be a measurement main object of a stationary time current in the lock circuit 11 according to terminal control information from an LSI tester 18, and a reset control part 13 for resetting the function block other than the object function block in each of the plurality of test patterns on the basis of the block reset pattern. The LSI tester 18 performs failure determination of an LSI 10 on the basis of difference of a current measurement value in each test pattern in the LSI 10 acquired about each of the plurality of test patterns.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an LSI device and a fault detection method.

Background Art

[0002] For example, Patent Document 1 describes an IDDQ test circuit for a semiconductor integrated circuit incorporating a circuit through which a through-current several times that in a steady state flows. The IDDQ test circuit includes means for blocking an output value output from the semiconductor integrated circuit by an inspection execution instruction signal and supplying an output of a pattern automatic generation circuit to a static circuit which is a circuit under measurement, and blocking means for temporarily blocking a power supply supplied to a through-current path or setting it to a standby state where no current flows. During the blocking by the blocking means, a direct current flowing through the semiconductor integrated circuit is detected using an external current detection means, and means for determining the quality of the semiconductor integrated circuit is provided.

[0003] The above IDDQ (IDD Quiescent) test is known as a method for detecting defects generated in the manufacturing process of a CMOS (Complementary Metal Oxide Semiconductor) circuit. An ideal CMOS circuit uses a method utilizing the property that no power supply current (Idd) flows during a stationary state, measures a leakage current while switching the logic inside an IC (Integrated Circuit), and performs fault detection.

[0004] Also, as a method for ensuring the measurement accuracy of a leakage current, delta IDDQ is generally used. In delta IDDQ, an abnormal current is determined based on a differential current value obtained as a plurality of IDDQ measurement results with different test patterns.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, as the process is miniaturized, even with the conventional IDDQ test, the leakage current due to a fault is masked by the variation in the leakage current during normal operation. In particular, in an LSI with a high maximum operating frequency, the leakage current during normal operation tends to be large, so it may be difficult to accurately detect the leakage current due to a fault.

[0007] The present invention has been made in view of the above circumstances, and an object thereof is to provide an LSI device and a fault detection method capable of accurately detecting a leakage current due to a fault during an IDDQ test.

Means for Solving the Problems

[0008] In order to solve the above problems, an LSI device according to the present invention includes an LSI and an LSI tester. The LSI includes a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, and a test control unit that inputs, according to terminal control information from the LSI tester, a plurality of test patterns prepared in advance for each block reset pattern that is a pattern for resetting functional blocks other than a target functional block, which is a functional block that is a main target of fault detection by measuring the quiescent current, with respect to the logic circuit. The LSI also includes a reset control unit that resets functional blocks other than the target functional block based on the block reset pattern for each of the plurality of test patterns. The LSI tester performs a fault determination of the LSI based on the difference in the current measurement value for each test pattern in the LSI obtained for each of the plurality of test patterns.

[0009] Furthermore, in order to solve the above problems, the LSI device according to the present invention includes an LSI and an LSI tester. The LSI includes a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, and for each block reset pattern, which is a pattern for resetting functional blocks other than the target functional block, which is the main target of failure detection by measuring the quiescent current, with respect to the logic circuit, a reset control unit that resets the functional blocks other than the target functional block, and a test control unit that inputs single or multiple test patterns to the logic circuit according to terminal control information from the LSI tester and inputs the block reset pattern to the reset control unit. The LSI tester performs a failure determination of the LSI based on a difference in current measurement values in the LSI obtained for each block reset pattern for the single or multiple test patterns.

[0010] Furthermore, in order to solve the above problems, a failure detection method according to the present invention inputs, according to terminal control information from an LSI tester, a plurality of test patterns prepared in advance for each block reset pattern, which is a pattern for resetting functional blocks other than the target functional block, which is the main target of failure detection by measuring the quiescent current, with respect to a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected. For each of the plurality of test patterns, based on the block reset pattern, it is an LSI failure detection method for resetting functional blocks other than the target functional block, wherein the LSI tester performs a failure determination of the LSI based on a difference in current measurement values for each test pattern in the LSI obtained for each of the plurality of test patterns.

Advantages of the Invention

[0011] According to the present invention, there is an effect that a leakage current due to a failure can be accurately detected during an IDDQ test.

Brief Description of the Drawings

[0012]

Figure 1

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Figure 8

[0013] Hereinafter, with reference to the drawings, an example of an embodiment for carrying out the technology of the present invention will be described in detail. Note that components and processes that perform the same functions, operations, and functions are given the same reference numerals throughout the drawings, and redundant descriptions may be omitted as appropriate. Each drawing is only schematically shown to the extent that the technology of the present invention can be sufficiently understood. Therefore, the technology of the present invention is not limited to only the illustrated examples. Also, in this embodiment, descriptions of configurations that are not directly related to the present invention and well-known configurations may be omitted.

[0014] [First Embodiment] FIG. 1 is a block diagram showing an example of the configuration of the LSI device 100 according to the first embodiment. The LSI device 100 includes an LSI (Large Scale Integration) 10 and an LSI tester 18 provided outside the LSI 10.

[0015] As shown in FIG. 1, the LSI 10 according to the present embodiment includes a logic circuit 11, a test control unit 12, a reset control unit 13, a block reset terminal 14, an overall reset terminal 15, a power supply terminal 16, and an input terminal 17. The logic circuit 11 includes a plurality of flip-flop (FF) circuits, and the plurality of flip-flop circuits are connected in a scan chain. The logic circuit 11 includes a plurality of functional blocks A, C, and D having different maximum operating frequencies during normal operation. The logic circuit 11 also includes a functional block B having the same maximum operating frequency as the functional block A during normal operation. The functional blocks A and B are blocks having approximately the same circuit scale. As an example, the maximum operating frequencies of the functional blocks A and B are 300 MHz, the maximum operating frequency of the functional block C is 120 MHz, and the maximum operating frequency of the functional block D is 32 MHz.

[0016] When an active is input to the power supply terminal 16, the power supply voltage vdd is supplied to each of the logic circuit 11, the test control unit 12, and the reset control unit 13.

[0017] The LSI tester 18 controls each terminal of the LSI 10 and measures current and determines whether the LSI 10 is faulty. The input terminal 17 inputs terminal control information including a test clock and a test pattern necessary for the IDDQ test from the LSI tester 18.

[0018] The test control unit 12 executes the IDDQ test according to the terminal control from the LSI tester 18. The test control unit 12 processes the terminal control information input to the input terminal 17 from the LSI tester 18, and inputs test patterns and supplies clocks to each of the logic circuit 11 and the reset control unit 13. The test control unit 12 inputs a plurality of test patterns prepared in advance for each block reset pattern to the logic circuit 11. The block reset pattern is a pattern for resetting function blocks other than the target function block. The target function block is the main target of failure detection by measuring the quiescent current (IDDQ). The test pattern is a pattern for switching the data holding state (on (or High) and off (or Low)) of each element including flip-flop circuits and other AND gates, OR gates, etc.

[0019] In addition to flip-flop circuits, a large number of logic elements such as AND gates and OR gates are distributed at multiple points in the logic circuit 11, and these logic elements such as AND gates and OR gates are connected to each flip-flop circuit. When the SCAN input data propagates from the flip-flop circuit, the states of the logic elements connected to each flip-flop circuit also change.

[0020] Since the leakage currents of the transistors constituting these circuits vary during manufacturing, differences in measured values occur between chips when the leakage currents are measured.

[0021] FIG. 2 is a diagram showing an example of a test pattern according to this embodiment.

[0022] The test patterns shown in FIG. 2 are prepared in advance for each block reset pattern. The example of FIG. 2 shows the test pattern when the target functional block is functional block A. In this example, the functional blocks B, C, and D other than the functional block A are reset. Similarly, in the test pattern with the target functional block being functional block B, the functional blocks A, C, and D other than the functional block B are reset. In the test pattern with the target functional block being functional block C, the functional blocks A, B, and D other than the functional block C are reset. In the test pattern with the target functional block being functional block D, the functional blocks A, B, and C other than the functional block D are reset.

[0023] The reset control unit 13 includes SCAN-FFs in which a plurality of flip-flop circuits are connected in a scan chain, and is configured to propagate the input of the test pattern and set the output (sout) of the logic circuit 11 to the input (si) of the reset control unit 13.

[0024] The reset control unit 13 resets the functional blocks other than the target functional block based on the block reset pattern for each of the plurality of test patterns (see FIG. 2). The reset control unit 13 includes flip-flop (FF) circuits and logic circuits (AND, OR) corresponding to the functional blocks A to D of the logic circuit 11.

[0025] When an active is input to the block reset terminal 14, the reset control unit 13 executes a reset process on the functional blocks other than the target functional block according to the input test pattern. Also, when an active is input to the overall reset terminal 15, the reset control unit 13 executes a reset process on all the functional blocks.

[0026] The LSI tester 18 determines whether the LSI 10 is faulty based on the differences in the current measurement values for each test pattern in the LSI 10 obtained for each of a plurality of test patterns (see FIG. 2). In the example of FIG. 1, it shows that a leakage current due to a fault has occurred in the functional block D. Specifically, the test control unit 12 calculates, for each test pattern of the target functional block, the difference (hereinafter referred to as the "measurement difference") between each current measurement value corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits in the target functional block. The test control unit 12 determines that the LSI 10 is faulty when the absolute value of the obtained measurement difference exceeds the threshold value. Note that the measurement difference represents the difference between the current measurement value corresponding to a specific measurement point among the N measurement points and the current measurement values corresponding to the measurement points other than the specific measurement point. An appropriate value is determined for the threshold value considering the variations between chips.

[0027] Specifically, in the example of FIG. 1, the LSI tester 18 determines whether the absolute value of the measurement difference between each current measurement value corresponding to the first to Nth measurement points of the functional block A is less than or equal to the threshold value A. At this time, the functional blocks B, C, and D other than the functional block A are set to the reset state. Similarly, the LSI tester 18 determines whether the absolute value of the measurement difference between each current measurement value corresponding to the first to Nth measurement points of the functional block B is less than or equal to the threshold value B. At this time, the functional blocks A, C, and D other than the functional block B are set to the reset state. The LSI tester 18 determines whether the absolute value of the measurement difference between each current measurement value corresponding to the first to Nth measurement points of the functional block C is less than or equal to the threshold value C. At this time, the functional blocks A, B, and D other than the functional block C are set to the reset state. The LSI tester 18 determines whether the absolute value of the measurement difference between each current measurement value corresponding to the first to Nth measurement points of the functional block D is less than or equal to the threshold value D. At this time, the functional blocks A, B, and C other than the functional block D are set to the reset state. Note that appropriate values for these threshold values A to D are determined considering the variations between chips as described above.

[0028] Note that it may be possible to select a functional block to be reset. For example, functional blocks A and B may be targets for measuring the static current (IDDQ), and functional blocks C and D may be reset, or functional blocks A, B, and C may be targets for measuring the static current (IDDQ), and functional block D may be reset. By making it possible to select a functional block to be reset in this way, appropriate measurement conditions can be set according to the test time vs. effect.

[0029] Next, with reference to FIG. 3, the operation of the LSI device 100 according to the first embodiment will be described.

[0030] FIG. 3 is a flowchart showing an example of the flow of the IDDQ test process by the LSI device 100 according to the first embodiment. The LSI tester 18 executes the IDDQ test process via the test control unit 12 and the reset control unit 13 provided in the LSI 10 by controlling the terminals of the LSI 10.

[0031] In step S101 of FIG. 3, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 sets the test mode.

[0032] In step S102, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 inputs, as an example, the test pattern of the target functional block that is the measurement target of the static current (IDDQ) among the plurality of test patterns shown in FIG. 2 above to the logic circuit 11.

[0033] In step S103, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 performs a shift operation (that is, an operation to switch the data holding state) according to the test pattern of the target functional block, and stops the shift operation at the n-th (1 ≦ n ≦ N, n ← 1) measurement point set as the IDDQ measurement circuit state.

[0034] In step S104, the reset control unit 13 resets function blocks other than the target function block in response to an active input to the block reset terminal 14.

[0035] In step S105, the LSI tester 18 measures the quiescent current (IDDQ) at the power supply terminal 16.

[0036] In step S106, the LSI tester 18 determines whether the measurement of the quiescent current (IDDQ) has been performed the measurement number (N times). If it is determined that the measurement of the quiescent current (IDDQ) has been performed the measurement number (N times) (in the case of an affirmative determination), the process proceeds to step S107. If it is determined that the measurement of the quiescent current (IDDQ) has not been performed the measurement number (N times) (in the case of a negative determination), n is incremented by 1, and the process returns to step S102 to repeat the process.

[0037] In step S107, for each test pattern of the target function block, the LSI tester 18 obtains the measurement difference between each current measurement value corresponding to the first to Nth measurement points, and determines whether the absolute value of the measurement difference is less than or equal to the threshold value. If it is determined that the absolute value of the measurement difference is less than or equal to the threshold value (in the case of an affirmative determination), the process proceeds to step S108. If it is determined that the absolute value of the measurement difference exceeds the threshold value (in the case of a negative determination), the process proceeds to step S110.

[0038] In step S108, the LSI tester 18 determines whether the measurement of the quiescent current (IDDQ) has been performed for all measurement conditions. If it is determined that the measurement of the quiescent current (IDDQ) has been performed for all measurement conditions (in the case of an affirmative determination), the process proceeds to step S109. If it is determined that the measurement of the quiescent current (IDDQ) has not been performed for all measurement conditions (in the case of a negative determination), the process returns to step S102, inputs the next test pattern, and repeats the process.

[0039] In step S109, the LSI tester 18 determines that the LSI 10 is a non-defective product and ends the IDDQ test process.

[0040] On the other hand, in step S110, the LSI tester 18 determines that the LSI 10 is a defective product and ends the IDDQ test process.

[0041] As described above, according to this embodiment, by simply adding a reset control unit, the circuit to be tested in the IDDQ test can be narrowed down, and the variation in the measurement of the leakage current can be minimized. Therefore, during the IDDQ test, the leakage current due to a fault can be accurately detected.

[0042] Here, due to the miniaturization of the process and the increase in circuits, the leakage current tends to increase. Also, in the case of circuits corresponding to high-speed operations, the leakage current also tends to increase. Therefore, for example, it is considered that there is a difference in the leakage current values between blocks for a circuit block with a high maximum operating frequency and a low-speed circuit block.

[0043] The conventionally used delta IDDQ assumes that the current difference depending on the measurement point is small, but even in this difference, it is affected by the leakage current due to the miniaturization of the process. Therefore, with the conventional method of measuring the entire logic circuit of the same power supply, it is difficult to accurately detect the leakage current due to a fault.

[0044] In contrast, according to this embodiment, during delta IDDQ, it is possible to limit the circuit blocks whose measurement states change for each test pattern by using reset control. That is, the current difference for each measurement of the leakage current can be reduced according to the test pattern, and delta IDDQ can be executed more effectively than the conventional method with a smaller circuit increment.

[0045] [Second Embodiment] In the second embodiment, in addition to the measurement differences between the current measurement values corresponding to the first to Nth measurement points of the target functional block, a form of detecting a fault using the difference between the measurement differences for two functional blocks having the same maximum operating frequency will be described.

[0046] Since the configuration of the LSI device 100A according to the second embodiment is the same as the configuration of the LSI device 100 according to the first embodiment described above, the configuration of the LSI device 100A according to the second embodiment will be described with reference to FIG. 1 above.

[0047] The LSI tester 18 obtains a first difference between each current measurement value corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of a plurality of flip-flop circuits in the target functional block for each test pattern of the target functional block. Further, the LSI tester 18 obtains a second difference between the first differences for two functional blocks having the same maximum operating frequency among the plurality of functional blocks. In the present embodiment, the first difference is referred to as a measurement difference, and the second difference is referred to as a difference between measurement differences. Note that the difference between measurement differences may be the difference between the corresponding measurement differences of each functional block or the difference between the representative values of the measurement differences of each functional block. This representative value may be, for example, an average value or a total value. Then, when the absolute value of the measurement difference exceeds the first threshold value or the absolute value of the difference between measurement differences exceeds the second threshold value, the LSI 10 is determined to be faulty. Appropriate values are determined for the first threshold value and the second threshold value in consideration of the variations between chips.

[0048] Specifically, in the example of FIG. 1, the functional block A and the functional block B have the same maximum operating frequency (=300 MHz). Here, the term "the same" may be interpreted as being the same including a predetermined error. Since the functional block A and the functional block B are high-speed, high-leakage, and blocks of the same scale, it is expected that the differences in current measurement values are close. Therefore, the difference between the measurement differences between each current measurement value corresponding to each measurement point of the functional block A and the measurement differences between each current measurement value corresponding to each measurement point of the functional block B is used as the difference between measurement differences, and it is complementarily determined whether the absolute value of the difference between measurement differences exceeds the second threshold value.

[0049] Next, with reference to FIG. 4, the operation of the LSI device 100A according to the second embodiment will be described.

[0050] FIG. 4 is a flowchart showing an example of the flow of IDDQ test processing by the LSI device 100A according to the second embodiment. The LSI tester 18 executes IDDQ test processing by controlling the terminals of the LSI 10 via the test control unit 12 and the reset control unit 13 provided in the LSI 10.

[0051] Since steps S111 to S116, S119, S120, and S121 in FIG. 4 are the same processes as steps S101 to S106, S108, S109, and S110 in FIG. 3 described above, repeated description thereof is omitted.

[0052] In step S117 of FIG. 4, the LSI tester 18 obtains the measurement difference between each current measurement value corresponding to each measurement point from the first to the Nth for each test pattern of the target functional block, and determines whether the absolute value of the measurement difference is less than or equal to the first threshold. When it is determined that the absolute value of the measurement difference is less than or equal to the first threshold (in the case of an affirmative determination), the process proceeds to step S118, and when it is determined that the absolute value of the measurement difference exceeds the first threshold (in the case of a negative determination), the process proceeds to step S121.

[0053] In step S118, the LSI tester 18 obtains the difference between measurement differences, which is the difference between the measurement differences for two functional blocks having the same maximum operating frequency among the plurality of functional blocks, and determines whether the absolute value of the difference between measurement differences is less than or equal to the second threshold. When it is determined that the absolute value of the difference between measurement differences is less than or equal to the second threshold (in the case of an affirmative determination), the process proceeds to step S119, and when it is determined that the absolute value of the difference between measurement differences exceeds the second threshold (in the case of a negative determination), the process proceeds to step S121.

[0054] Thus, according to the present embodiment, in addition to the measurement difference, by using the difference between measurement differences complementarily, it is possible to detect a leakage current due to a failure with higher accuracy.

[0055] [Third Embodiment] In the third embodiment, in addition to the measurement differences between the current measurement values corresponding to the first to Nth measurement points of the target functional block, a form of detecting a failure using the current measurement values corresponding to the first to Nth measurement points of the entire logic circuit will be described.

[0056] Since the configuration of the LSI device 100B according to the third embodiment is the same as the configuration of the LSI device 100 according to the first embodiment, the configuration of the LSI device 100B according to the third embodiment will be described with reference to FIG. 1 above.

[0057] The test control unit 12 further inputs another test pattern (hereinafter referred to as the "entire test pattern") for measuring the quiescent current (IDDQ) of the entire logic circuit 11 to the logic circuit 11 according to the terminal control information input from the LSI tester 18. The entire test pattern is a pattern for switching the data holding states of a plurality of flip-flop circuits included in the logic circuit 11.

[0058] The LSI tester 18 obtains the current measurement values of the logic circuit 11 corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the logic circuit 11 for the entire test pattern of the logic circuit 11. Further, the LSI tester 18 obtains the measurement differences, which are the differences between the current measurement values corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block for each of the test patterns of the target functional block. Then, the LSI tester 18 determines that the LSI 10 has failed when the current measurement value of the logic circuit 11 exceeds the first threshold value or when the absolute value of the measurement difference exceeds the second threshold value. Appropriate values are determined for the first threshold value and the second threshold value in consideration of the variations between chips.

[0059] Next, with reference to FIG. 5, the operation of the LSI device 100B according to the third embodiment will be described.

[0060] FIG. 5 is a flowchart showing an example of the flow of IDDQ test processing by the LSI device 100B according to the third embodiment. The LSI tester 18 executes IDDQ test processing by controlling the terminals of the LSI 10 via the test control unit 12 and the reset control unit 13 provided in the LSI 10.

[0061] Note that steps S131 to S136, S139, S140, and S141 in FIG. 5 are the same processes as steps S101 to S106, S108, S109, and S110 in FIG. 3 described above, so the repeated description thereof is omitted. However, in this embodiment, in step S132, in addition to the test pattern shown in FIG. 2 described above, the overall test pattern is input.

[0062] In step S137 of FIG. 5, the LSI tester 18 determines whether each current measurement value corresponding to each measurement point from the first to the Nth times is less than or equal to the first threshold value with respect to the overall test pattern of the LSI 10. When it is determined that each current measurement value is less than or equal to the first threshold value (in the case of an affirmative determination), the process proceeds to step S138, and when it is determined that each current measurement value exceeds the first threshold value (in the case of a negative determination), the process proceeds to step S141.

[0063] In step S138, the LSI tester 18 obtains the measurement difference between each current measurement value corresponding to each measurement point from the first to the Nth times for each of the test patterns of the target functional block, and determines whether the absolute value of the measurement difference is less than or equal to the second threshold value. When it is determined that the absolute value of the measurement difference is less than or equal to the second threshold value (in the case of an affirmative determination), the process proceeds to step S139, and when it is determined that the absolute value of the measurement difference exceeds the second threshold value (in the case of a negative determination), the process proceeds to step S141.

[0064] Thus, according to this embodiment, in addition to the measurement difference, by complementarily using each current measurement value of the logic circuit, it is possible to detect the leakage current due to a failure with higher accuracy.

[0065] [Fourth Embodiment] In the fourth embodiment, in addition to the measurement differences between the respective current measurement values corresponding to the first to Nth measurement points of the target functional block, a form of detecting a failure using the differences between the measurement differences and the respective current measurement values of the LSI will be described.

[0066] Since the configuration of the LSI device 100C according to the fourth embodiment is the same as the configuration of the LSI device 100 according to the first embodiment described above, the configuration of the LSI device 100C according to the fourth embodiment will be described with reference to FIG. 1 above.

[0067] The test control unit 12 further inputs an overall test pattern for making the entire logic circuit 11 a measurement target of the quiescent current (IDDQ) to the logic circuit 11 in accordance with the terminal control information input from the LSI tester 18. As described above, the overall test pattern is a pattern for switching the data holding states of a plurality of flip-flop circuits included in the logic circuit 11.

[0068] The LSI tester 18 obtains the respective current measurement values of the logic circuit 11 corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the logic circuit 11 for the overall test pattern of the logic circuit 11. Further, the LSI tester 18 obtains a first difference between the respective current measurement values corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block for each of the test patterns of the target functional block. Further, the LSI tester 18 obtains a second difference between the first differences for two functional blocks having the same maximum operating frequency among the plurality of functional blocks. In the present embodiment, the first difference is referred to as a measurement difference, and the second difference is referred to as a difference between measurement differences. Then, the LSI tester 18 determines that the LSI 10 has failed when each current measurement value of the LSI 10 exceeds a first threshold value, when the absolute value of the measurement difference exceeds a second threshold value, or when the absolute value of the difference between the measurement differences exceeds a third threshold value. Appropriate values are determined for the first threshold value, the second threshold value, and the third threshold value in consideration of the variations between chips.

[0069] Next, with reference to FIG. 6, the operation of the LSI device 100C according to the fourth embodiment will be described.

[0070] FIG. 6 is a flowchart showing an example of the flow of the IDDQ test process by the LSI device 100C according to the fourth embodiment. The LSI tester 18 executes the IDDQ test process via the test control unit 12 and the reset control unit 13 provided in the LSI 10 by controlling the terminals of the LSI 10.

[0071] Note that steps S151 to S156, S160, S161, and S162 in FIG. 6 are the same processes as steps S101 to S106, S108, S109, and S110 in FIG. 3 described above, so the repeated description thereof will be omitted. However, in the present embodiment, in step S152, in addition to the test pattern shown in FIG. 2 described above, the overall test pattern is input.

[0072] In step S157 of FIG. 6, the LSI tester 18 determines whether or not each current measurement value corresponding to each measurement point from the first to the Nth times is less than or equal to the first threshold value for the overall test pattern of the logic circuit 11. When it is determined that each current measurement value is less than or equal to the first threshold value (in the case of an affirmative determination), the process proceeds to step S158, and when it is determined that each current measurement value exceeds the first threshold value (in the case of a negative determination), the process proceeds to step S162.

[0073] In step S158, the LSI tester 18 obtains the measurement difference between each current measurement value corresponding to each measurement point from the first to the Nth times for each of the test patterns of the target functional block, and determines whether or not the absolute value of the measurement difference is less than or equal to the second threshold value. When it is determined that the absolute value of the measurement difference is less than or equal to the second threshold value (in the case of an affirmative determination), the process proceeds to step S159, and when it is determined that the absolute value of the measurement difference exceeds the second threshold value (in the case of a negative determination), the process proceeds to step S162.

[0074] In step S159, the LSI tester 18 obtains the difference between measurement differences, which is the difference between the measurement differences for two functional blocks having the same maximum operating frequency among the plurality of functional blocks, and determines whether the absolute value of the difference between the measurement differences is less than or equal to a third threshold value. When it is determined that the absolute value of the difference between the measurement differences is less than or equal to the third threshold value (in the case of an affirmative determination), the process proceeds to step S160, and when it is determined that the absolute value of the difference between the measurement differences exceeds the third threshold value (in the case of a negative determination), the process proceeds to step S162.

[0075] Thus, according to the present embodiment, in addition to the measurement difference, by complementarily using the difference between the measurement differences and each current measurement value of the logic circuit, it is possible to detect a leakage current due to a failure with higher accuracy.

[0076] [Fifth Embodiment] In the fifth embodiment, an independent control mode will be described in which the reset control unit is separated from the SCAN chain and the block reset is controlled by a test mode setting from the test control unit.

[0077] FIG. 7 is a block diagram showing an example of the configuration of the LSI device 100D according to the fifth embodiment.

[0078] As shown in FIG. 7, the LSI device 100D according to the present embodiment includes an LSI 10 and an LSI tester 18. The LSI 10 according to the present embodiment includes a logic circuit 11, a test control unit 12, a reset control unit 13, a block reset terminal 14, an overall reset terminal 15, a power supply terminal 16, and an input terminal 17.

[0079] The reset control unit 13 resets functional blocks other than the target functional block for each block reset pattern with respect to the logic circuit 11.

[0080] The test control unit 12 inputs single or multiple test patterns to the logic circuit 11 and inputs a block reset pattern to the reset control unit 13 in accordance with the terminal control information input from the LSI tester 18. The LSI tester 18 performs a failure determination of the LSI 10 based on the difference in the current measurement values in the logic circuit 11 obtained for each block reset pattern for single or multiple test patterns.

[0081] When the block reset is in an independent control form, the block reset pattern for each block reset and single or multiple test patterns are independently controlled. That is, the test control unit 12 inputs single or multiple test patterns to the logic circuit 11 regardless of the block reset in accordance with the terminal control from the LSI tester 18, and inputs a block reset pattern for each block reset to the reset control unit 13. In the example of FIG. 7, a form in which the block reset pattern is directly input from the test control unit 12 to the reset control unit 13 is shown. Note that the block reset terminals 14 may be provided in accordance with the number of blocks. In the example of FIG. 7, four block reset terminals 14 are provided.

[0082] Next, with reference to FIG. 8, the operation of the LSI device 100D according to the fifth embodiment will be described.

[0083] FIG. 8 is a flowchart showing an example of the flow of the IDDQ test process by the LSI device 100D according to the fifth embodiment. The LSI tester 18 executes the IDDQ test process via the test control unit 12 and the reset control unit 13 provided in the LSI 10 by controlling the terminals of the LSI 10.

[0084] In step S171 of FIG. 8, the test control unit 12 sets the test mode in accordance with the terminal control information of the LSI 10 input from the LSI tester 18.

[0085] In step S172, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 inputs a block reset pattern for resetting function blocks other than the target function block to the reset control unit 13.

[0086] In step S173, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 inputs one or more test patterns to the logic circuit 11.

[0087] In step S174, according to the terminal control information of the LSI 10 input from the LSI tester 18, the test control unit 12 performs a shift operation (i.e., an operation to switch the data holding state of the flip-flop) according to one or more test patterns of the target function block, and stops the shift operation at the nth (1 ≤ n ≤ N, n ← 1) measurement point set as the IDDQ measurement circuit state.

[0088] In step S175, according to the terminal control information of the LSI 10 input from the LSI tester 18, the reset control unit 13 performs a reset process on function blocks other than the target function block in response to an active input to the block reset terminal 14.

[0089] In step S176, the LSI tester 18 measures the quiescent current (IDDQ) at the power supply terminal 16.

[0090] In step S177, the LSI tester 18 determines whether the measurement of the quiescent current (IDDQ) has been performed the measurement number (N times). If it is determined that the measurement of the quiescent current (IDDQ) has been performed the measurement number (N times) (in the case of an affirmative determination), the process proceeds to step S178. If it is determined that the measurement of the quiescent current (IDDQ) has not been performed the measurement number (N times) (in the case of a negative determination), n is incremented by one, and the process returns to step S173 to repeat the process.

[0091] In step S178, the LSI tester 18 obtains the measurement differences between the respective current measurement values corresponding to the first to Nth measurement points for each of the block reset patterns for a single or a plurality of test patterns of the target functional block, and determines whether the absolute value of the measurement difference is less than or equal to a threshold value. If it is determined that the absolute value of the measurement difference is less than or equal to the threshold value (in the case of an affirmative determination), the process proceeds to step S179. If it is determined that the absolute value of the measurement difference exceeds the threshold value (in the case of a negative determination), the process proceeds to step S181.

[0092] In step S179, the LSI tester 18 determines whether the measurement of the quiescent current (IDDQ) has been performed for all measurement conditions. If it is determined that the measurement of the quiescent current (IDDQ) has been performed for all measurement conditions (in the case of an affirmative determination), the process proceeds to step S180. If it is determined that the measurement of the quiescent current (IDDQ) has not been performed for all measurement conditions (in the case of a negative determination), the process returns to step S172, inputs the next block reset pattern, and repeats the process.

[0093] In step S180, the LSI tester 18 determines that the LSI 10 is a non-defective product and ends the IDDQ test process.

[0094] On the other hand, in step S181, the LSI tester 18 determines that the LSI 10 is a defective product and ends the IDDQ test process.

[0095] Note that in this embodiment, the case where the independent control form of block reset is applied to the first embodiment has been described. However, the independent control form of block reset can be similarly applied to the second to fourth embodiments.

[0096] As described above, according to this embodiment, even when the block reset is in the independent control form, it is possible to detect the leakage current due to a failure with higher accuracy, similar to the first to fourth embodiments.

[0097] Note that the configurations of the LSI device and the fault detection method described in each of the above embodiments are merely examples, and it goes without saying that the configurations may be changed without departing from the gist of the embodiments.

[0098] Regarding the above embodiments, the following additional remarks are disclosed.

[0099] (Supplementary Note 1) An LSI, an LSI tester, and the LSI includes a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, a test control unit that inputs, in accordance with terminal control information from the LSI tester, a plurality of test patterns prepared in advance for each block reset pattern, which is a pattern for resetting functional blocks other than the target functional block, which is the main target of fault detection by measuring the quiescent current, with respect to the logic circuit, a reset control unit that resets functional blocks other than the target functional block based on the block reset pattern for each of the plurality of test patterns, and the LSI tester performs a fault determination of the LSI based on the difference in the current measurement value for each test pattern in the LSI obtained for each of the plurality of test patterns. LSI device. (Supplementary Note 2) Each of the plurality of functional blocks includes a plurality of flip-flop circuits, the test pattern is a pattern for switching the data holding states of the plurality of flip-flop circuits, The LSI device according to Supplementary Note 1. (Supplementary Note 3) The LSI tester For each of the test patterns of the target functional block, obtain the difference between each current measurement value corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block. When the absolute value of the difference exceeds a threshold value, determine that the LSI has a fault. The LSI device according to Supplementary Note 2. (Supplementary Note 4) The LSI tester For each of the test patterns of the target functional block, obtain the first difference between each current measurement value corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block. For two functional blocks having the same maximum operating frequency among the plurality of functional blocks, obtain the second difference between the first differences for the two functional blocks. When the absolute value of the first difference exceeds a first threshold value, or when the absolute value of the second difference exceeds a second threshold value, determine that the LSI has a fault. The LSI device according to Supplementary Note 2. (Supplementary Note 5) The test control unit In accordance with the terminal control information from the LSI tester, input to the logic circuit another test pattern for measuring the quiescent current of the entire logic circuit, which is a test pattern for switching the data holding states of the plurality of flip-flop circuits included in the logic circuit. The LSI tester For the other test pattern of the logic circuit, obtain each current measurement value of the logic circuit corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the logic circuit. For each of the test patterns of the target functional block, a difference between each current measurement value corresponding to the first to Nth (N≧2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block is obtained. When each current measurement value of the logic circuit exceeds a first threshold value, or when the absolute value of the difference exceeds a second threshold value, the LSI is determined to be faulty. The LSI device according to Supplementary Note 2. (Supplementary Note 6) The test control unit According to the terminal control information from the LSI tester, another test pattern for measuring the quiescent current of the entire logic circuit is input to the logic circuit, and this another test pattern is for switching the data holding states of the plurality of flip-flop circuits included in the logic circuit. The LSI tester For the another test pattern of the logic circuit, each current measurement value of the logic circuit corresponding to the first to Nth (N≧2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the logic circuit is obtained. For each of the test patterns of the target functional block, a first difference between each current measurement value corresponding to the first to Nth (N≧2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits of the target functional block is obtained. For two functional blocks having the same highest operating frequency among the plurality of functional blocks, a second difference between the first differences for the two functional blocks is obtained. When each current measurement value of the logic circuit exceeds a first threshold value, when the absolute value of the first difference exceeds a second threshold value, or when the absolute value of the second difference exceeds a third threshold value, the LSI is determined to be faulty. The LSI device according to Supplementary Note 2. (Supplementary Note 7) An LSI An LSI tester and The LSI is a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, a reset control unit that resets functional blocks other than a target functional block, which is a functional block that is the main target of failure detection by measuring the quiescent current, for each block reset pattern, which is a pattern for resetting the functional blocks other than the target functional block with respect to the logic circuit, a test control unit that inputs single or a plurality of test patterns to the logic circuit according to terminal control information from the LSI tester and inputs the block reset pattern to the reset control unit, and includes the LSI tester performs a failure determination of the LSI based on a difference in current measurement values in the LSI obtained for each block reset pattern for the single or plurality of test patterns. LSI device. (Appendix 8) A method for detecting a failure of an LSI, in which a plurality of test patterns prepared in advance for each block reset pattern, which is a pattern for resetting functional blocks other than a target functional block, which is a functional block that is the main target of failure detection by measuring the quiescent current, for a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, are input according to terminal control information from an LSI tester, and for each of the plurality of test patterns, based on the block reset pattern, functional blocks other than the target functional block are reset, the LSI tester performs a failure determination of the LSI based on a difference in current measurement values for each test pattern in the LSI obtained for each of the plurality of test patterns. Failure detection method.

Description of Signs

[0100] 10 LSI 11 Logic circuit 12 Test control unit 13 Reset control unit 14 Block reset terminal 15 All reset terminal 16 Power supply terminal 17 Input terminal 18 LSI tester 100, 100A~100D LSI device

Claims

1. An LSI, an LSI tester, and comprising: wherein the LSI is a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, and a test control unit that inputs, according to terminal control information from the LSI tester, a plurality of test patterns prepared in advance for each block reset pattern which is a pattern for resetting functional blocks other than a target functional block which is a functional block to be mainly subjected to failure detection by measuring a quiescent current with respect to the logic circuit, and a reset control unit that resets functional blocks other than the target functional block based on the block reset pattern for each of the plurality of test patterns, and comprising: wherein the LSI tester performs a failure determination of the LSI based on a difference between current measurement values for each test pattern in the LSI obtained for each of the plurality of test patterns. An LSI device.

2. each of the plurality of functional blocks includes a plurality of flip-flop circuits, and the test pattern is a pattern for switching a data holding state of the plurality of flip-flop circuits. The LSI device according to claim 1.

3. wherein the LSI tester for each of the test patterns of the target functional block, obtains a difference between each current measurement value corresponding to each measurement point from the first time to the Nth time (N≥2) set according to the switching of the data holding state of the plurality of flip-flop circuits of the target functional block, and determines that the LSI has failed when an absolute value of the difference exceeds a threshold value. The LSI device according to claim 2.

4. wherein the LSI tester for each of the test patterns of the target functional block, obtains a first difference between each current measurement value corresponding to each measurement point from the first time to the Nth time (N≥2) set according to the switching of the data holding state of the plurality of flip-flop circuits of the target functional block, obtains a second difference between the first differences for the two functional blocks having the same maximum operating frequency among the plurality of functional blocks, and determines that the LSI has failed when an absolute value of the first difference exceeds a first threshold value or when an absolute value of the second difference exceeds a second threshold value. The LSI device according to claim 2.

5. wherein the test control unit In accordance with the terminal control information from the LSI tester, another test pattern for measuring the quiescent current of the entire logic circuit is input to the logic circuit, and the data holding states of a plurality of flip-flop circuits included in the logic circuit are switched. The LSI tester For each of the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits in the logic circuit with respect to the another test pattern of the logic circuit, the current measurement values of the logic circuit corresponding to each of the measurement points are obtained. For each of the test patterns of the target functional block, the difference between the current measurement values corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits in the target functional block is obtained. When each of the current measurement values of the logic circuit exceeds a first threshold value, or when the absolute value of the difference exceeds a second threshold value, the LSI is determined to be faulty. The LSI device according to claim 2.

6. The test control unit In accordance with the terminal control information from the LSI tester, another test pattern for measuring the quiescent current of the entire logic circuit is input to the logic circuit, and the data holding states of a plurality of flip-flop circuits included in the logic circuit are switched. The LSI tester For each of the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits in the logic circuit with respect to the another test pattern of the logic circuit, the current measurement values of the logic circuit corresponding to each of the measurement points are obtained. For each of the test patterns of the target functional block, the first difference between the current measurement values corresponding to the first to Nth (N≥2) measurement points set according to the switching of the data holding states of the plurality of flip-flop circuits in the target functional block is obtained. For two functional blocks having the same highest operating frequency among the plurality of functional blocks, the second difference between the first differences for the two functional blocks is obtained. When each current measurement value of the logic circuit exceeds a first threshold value, when the absolute value of the first difference exceeds a second threshold value, or when the absolute value of the second difference exceeds a third threshold value, the LSI is determined to be faulty. The LSI device according to claim 2.

7. An LSI, An LSI tester, Comprising, The LSI is A logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, For each block reset pattern, which is a pattern for resetting functional blocks other than the target functional block, which is the main target of failure detection by measuring the quiescent current, for the logic circuit, a reset control unit for resetting functional blocks other than the target functional block, A test control unit that inputs single or a plurality of test patterns to the logic circuit according to terminal control information from the LSI tester and inputs the block reset pattern to the reset control unit, Comprising, The LSI tester performs a failure determination of the LSI based on the difference in the current measurement values in the LSI obtained for each block reset pattern for the single or plurality of test patterns. LSI device.

8. For each block reset pattern, which is a pattern for resetting functional blocks other than the target functional block, which is the main target of failure detection by measuring the quiescent current, for a logic circuit to which a plurality of functional blocks having different maximum operating frequencies are connected, a plurality of test patterns prepared in advance are input according to terminal control information from an LSI tester, and for each of the plurality of test patterns, based on the block reset pattern, a method for detecting a failure of an LSI for resetting functional blocks other than the target functional block, The LSI tester performs a failure determination of the LSI based on the difference in the current measurement values for each test pattern in the LSI obtained for each of the plurality of test patterns. Failure detection method.

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