Semiconductor device and operation method using the same
The semiconductor device architecture allows for concurrent operations across memory blocks, addressing the speed limitations of non-volatile memory devices by utilizing separate source line driving circuits for efficient operation management.
Patent Information
- Application Number
- JP2024152051
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-30
- Filing Date
- 2024-09-04
- Publication Date
- 2025-06-11
AI Technical Summary
Existing non-volatile memory devices face challenges in improving data processing speed, particularly in shortening the time required for program, erase, and verification operations.
A semiconductor device architecture that allows at least one memory block to perform a different operation while another memory block is performing a specific operation, utilizing separate source line driving circuits to manage operations across multiple memory blocks.
This approach enables simultaneous performance of different operations across memory blocks, enhancing the operating speed of the memory device and optimizing resource utilization.
Smart Images
Figure 2025088708000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor device and an operating method using the same.
Background Art
[0002] Recently, with the miniaturization, low power consumption, high performance, and diversification of electronic devices, semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices have been required. Semiconductor devices are broadly classified into a volatile memory device and a non-volatile memory device. The volatile memory device has a high data processing speed, but has a disadvantage in that power must be continuously supplied to hold the stored data. The non-volatile memory device has a disadvantage in that the data processing speed is slow, while power does not need to be continuously supplied to hold the stored data.
[0003] The non-volatile memory device performs a program operation to store data and an erase operation to erase the stored data. At the same time, the non-volatile memory device performs an operation of verifying whether the data is normally programmed or erased during the program operation or the erase operation.
[0004] Therefore, in order to improve the data processing speed of the non-volatile memory device, not only research for shortening the time for the program or erase operation but also research for shortening the time consumed for verification of each operation has been advanced.
Summary of the Invention
Problems to be Solved by the Invention
[0005] An embodiment of the present invention provides a semiconductor device in which at least one other memory block can perform an operation different from a specific operation when a part of a memory block sharing a page buffer is performing the specific operation.
Means for Solving the Problems
[0006] A semiconductor device according to an embodiment of the present invention can include a first source line driving circuit that drives a first source line, a second source line driving circuit that drives a second source line, a first memory block including a plurality of first memory strings connected between the first source line and a plurality of bit lines, and a second memory block including a plurality of second memory strings connected between the second source line and the plurality of bit lines.
[0007] A method of operating a semiconductor device according to an embodiment of the present invention can include driving a first source line at a level of an erase voltage, driving a second source line at a level of a ground voltage or an external power supply voltage, causing an erase operation to be performed on a first memory block connected to the first source line, and causing a read operation or a program operation to be performed on a second memory block connected to the second source line.
[0008] A semiconductor device according to another embodiment of the present invention includes a first source line, a second source line, a plurality of bit lines, a first memory block including a plurality of first memory strings respectively connected between the first source line and the plurality of bit lines, a second memory block including a plurality of second memory strings respectively connected between the second source line and the plurality of bit lines, a control circuit that causes an erase operation to be performed on the first memory block and simultaneously causes a read or program operation to be performed on the second memory block, a first source driving circuit that drives the first source line with an erase voltage, and a second source driving circuit that drives the second source line with a ground voltage lower than the erase voltage.
Advantages of the Invention
[0009] Embodiments of the present invention enable each of the memory blocks to perform different operations together, and can improve the operating speed of the memory device.
Brief Description of the Drawings
[0010]
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Embodiments for Carrying Out the Invention
[0011] Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the accompanying drawings.
[0012] FIG. 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention.
[0013] Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention can include a control circuit 100, a line drive circuit 200, a page buffer group 300, a cell array 400, a first source line drive circuit 510 (SD1), and a second source line drive circuit 520 (SD2).
[0014] The control circuit 100 can control the line drive circuit 200 and the page buffer group 300. For example, the control circuit 100 can control the line drive circuit 200 and the page buffer group 300 based on the command signal CMD and the address signal ADD. Here, the control circuit 100 can generate a drive address signal ADD_d based on the command signal CMD and the address signal ADD. The control circuit 100 can provide the drive address signal ADD_d to the line drive circuit 200 to control the line drive circuit 200. Also, the control circuit 100 can generate a page buffer control signal PB_ctrl based on the command signal CMD and the address signal ADD. The control circuit 100 can provide the page buffer control signal PB_ctrl to the page buffer group 300 to control the page buffer group 300.
[0015] The line drive circuit 200 can receive the drive address signal ADD_d from the control circuit 100. The line drive circuit 200 can drive each of the drain select line DSL, the word line WL, and the source select line SSL at at least one voltage level of a plurality of voltages based on the drive address signal ADD_d. For example, the plurality of voltages may be voltages provided from inside or outside the semiconductor device, or each of the plurality of voltages may have different voltage levels from each other. The plurality of voltages can include pass voltages, read voltages, program voltages, etc. having different voltage levels from each other.
[0016] The page buffer group 300 can include a plurality of page buffers PB1, PB2, …, PBn. Each of the plurality of page buffers PB1, PB2, …, PBn can be connected to each of the plurality of bit lines BL1, BL2, …, BLn. During a read operation, each of the plurality of page buffers PB1, PB2, …, PBn can sense, under the control of the page buffer control signal PB_ctrl, the data value stored in the memory cell via the bit line and output the sensed value as data DATA. Also, during a verification operation, each of the plurality of page buffers PB1, PB2, …, PBn can output, under the control of the page buffer control signal PB_ctrl, the threshold voltage of the memory cell sensed via the bit line as a verification result. At the same time, during a program operation, each of the plurality of page buffers PB1, PB2, …, PBn can adjust the voltage level of the bit line under the control of the page buffer control signal PB_ctrl.
[0017] The cell array 400 can include a plurality of memory blocks BK1, BK2. For example, the plurality of memory blocks BK1, BK2 can include the first and second memory blocks BK1, BK2. Each of the first and second memory blocks BK1, BK2 may be selected by a word line WL. Among the first and second memory blocks BK1, BK2, the memory string of one selected memory block can be connected to a plurality of page buffers PB1, PB2, …, PBn via a plurality of bit lines BL1, BL2, …, BLn. Also, each of the first and second memory blocks BK1, BK2 can include a plurality of memory strings in which a plurality of memory cells are connected in series. Each of the plurality of memory strings can include first and second selection transistors (e.g., drain selection transistors, source selection transistors) in addition to the plurality of memory cells connected in series. The first selection transistor is configured to be turned on or off by a drain selection line DSL, and the second selection transistor may be configured to be turned on or off by a source selection line SSL. At the same time, the plurality of memory strings included in the first memory block BK1 can be connected between the first source line SL1 and the plurality of bit lines BL1, BL2, …, BLn. On the other hand, the plurality of memory strings included in the second memory block BK2 can be connected between the second source line SL2 and the plurality of bit lines BL1, BL2, …, BLn.
[0018] The first source line driving circuit 510 can drive the first source line SL1. For example, the first source line driving circuit 510 can drive the first source line SL1 at a first voltage level during a read operation or a program operation. On the other hand, the first source line driving circuit 510 can drive the first source line SL1 at a second voltage level during an erase operation.
[0019] The second source line driving circuit 520 can drive the second source line SL2. For example, during a read operation or a program operation, the second source line driving circuit 520 can drive the second source line SL2 at a first voltage level. On the other hand, during an erase operation, the second source line driving circuit 520 can drive the second source line SL2 at a second voltage level. At this time, the first voltage level may be the level of the ground voltage, and the second voltage level may be an erase voltage at a voltage level higher than the level of the ground voltage.
[0020] In the semiconductor device according to the embodiment of the present invention configured as described above, when one of the first and second memory blocks BK1 and BK2 performs a read or program operation using the electrically separated first and second source lines SL1 and SL2, the remaining memory block can perform an erase operation. For example, when a first voltage is provided to the first source line SL1 and a second voltage is provided to the second source line SL2, a read or program operation may be performed on the selected memory string of the first memory block BK1 by the word line WL, the drain selection line DSL, and the source selection line SSL. At the same time, while a read or program operation is being performed on the first memory block BK1, an erase operation may be performed on all the memory strings of the second memory block BK2.
[0021] The semiconductor device according to the embodiment of the present invention includes source lines that are electrically separated from each other for each memory block that shares a plurality of bit lines, and a source line driving circuit that drives each source line. When a read or write operation is performed on one of the memory blocks, at least one other memory block can be made to perform an erase operation. Also, in the semiconductor device according to the embodiment of the present invention, since the memory blocks share a plurality of bit lines, after a read or write operation is performed, an erase verification operation can be performed on at least one memory block on which an erase operation has been performed.
[0022] FIG. 2 is a diagram for explaining a semiconductor device according to another embodiment of the present invention. At this time, since other configurations except for the cell array 400 in FIG. 2 are the same as those in FIG. 1, only the configuration of the cell array 400 will be described below.
[0023] Referring to FIG. 2, the cell array 400 can include a plurality of memory blocks BK1-1 to BK1-i, BK2-1 to BK2-j. For example, the plurality of memory blocks BK1-1 to BK1-i, BK2-1 to BK2-j can include a first memory block BK1-1 to BK1-i and a second memory block BK2-1 to BK2-j. Each of the first and second memory blocks BK1-1 to BK1-i, BK2-1 to BK2-j may be selected by a word line WL. Among the first and second memory blocks BK1-1 to BK1-i, BK2-1 to BK2-j, the memory string of one selected memory block can be connected to a plurality of page buffers PB1, PB2,..., PBn via a plurality of bit lines BL1, BL2,..., BLn. Also, each of the first and second memory blocks BK1-1 to BK1-i, BK2-1 to BK2-j can include a plurality of memory strings in which a plurality of memory cells are connected in series. Each of the plurality of memory strings can include first and second selection transistors (for example, a drain selection transistor, a source selection transistor) in addition to a plurality of memory cells connected in series. The first selection transistor is configured to be turned on or off by a drain selection line DSL, and the second selection transistor may be configured to be turned on or off by a source selection line SSL. At the same time, the plurality of memory strings included in the first memory block BK1-1 to BK1-i can be connected between a first source line SL1 and a plurality of bit lines BL1, BL2,..., BLn. On the other hand, the plurality of memory strings included in the second memory block BK2-1 to BK2-j can be connected between a second source line SL2 and a plurality of bit lines BL1, BL2,..., BLn.
[0024] At the same time, the first memory blocks BK-1 to BK-i can be connected to a first source line SL1 driven by a first source line driving circuit SD1. On the other hand, the second memory blocks BK2-1 to BK2-j can be connected to a second source line SL2 driven by a second source line driving circuit SD2. Hereinafter, the configuration and operation of the semiconductor device according to an embodiment of the present invention will be described in detail.
[0025] FIGS. 3 and 4 are diagrams for explaining the memory blocks of the semiconductor device according to an embodiment of the present invention. Here, the drain selection line DSL can include at least one first drain selection line DSLA (FIG. 3) and at least one second drain selection line DSLB (FIG. 4). The word line WL can include a plurality of first word lines WL1A to WLnA (FIG. 3) and a plurality of second word lines WL1B to WLnB (FIG. 4). Further, the source selection line SSL can include at least one first source selection line SSLA (FIG. 3) and at least one second source selection line SSLB (FIG. 4).
[0026] First, referring to FIG. 3, the first memory block BK1 will be described as follows.
[0027] The first memory block BK1 can include a plurality of first memory strings St_1A to St_nA connected between each of the plurality of bit lines BL1, BL2,..., BLn and the first source line SL1. The plurality of bit lines BL1, BL2,..., BLn can include first to nth bit lines BL1, BL2,..., BLn. For example, a first memory string St_1A can be connected between the first bit line BL1 and the first source line SL1. A first memory string St_2A can be connected between the second bit line BL2 and the first source line SL1. A first memory string St_nA can be connected between the nth bit line BLn and the first source line SL1.
[0028] Each of the plurality of first memory strings St_1A to St_nA can include a first drain selection transistor DSTA connected in series, a plurality of first memory cells MC1A to MCnA, and a first source selection transistor SSTA. The first drain selection transistor DSTA can be configured to receive control of a first drain selection line DSLA, and the first source selection transistor SSTA can be configured to receive control of a first source selection line SSLA. Also, each of the plurality of first memory cells MC1A to MCnA can be configured to receive control of each of the plurality of first word lines WL1A to WLnA.
[0029] The operation of the first memory block BK1 of the semiconductor device according to the embodiment of the present invention configured as described above will be described as follows.
[0030] For example, during a program operation, the first source line SL1 can be driven at the level of an external power supply voltage by a first source line driving circuit 510. Among the first to nth bit lines BL1, BL2,..., BLn, a ground voltage may be provided to at least one selected bit line, and an external power supply voltage may be provided to the unselected bit lines. Also, among the plurality of first word lines WL1A to WLnA, a program voltage may be provided to the selected word line, and a pass voltage may be provided to the remaining word lines. At the same time, the first drain selection transistor DSTA may be turned on, and the first source selection transistor SSTA may be turned off.
[0031] At this time, among the memory cells of the memory string connected to the selected bit line, that is, the bit line receiving a voltage higher than the ground voltage, the memory cell receiving the program voltage via the selected word line can be programmed.
[0032] More specifically, taking an example for explanation, it is as follows.
[0033] When the program is operating, assume that among the first to nth bit lines BL1, BL2, …, BLn, the first bit line BL1 is selected, and among the multiple first word lines WL1A to WL1n, the first first word line WL1A is selected.
[0034] In this case, the first memory cell MC1A connected to the first first word line WL1A among the first memory cells MC1A to MCnA of the first memory string St_1A connected to the selected first bit line BL1, that is, the first bit line receiving the ground voltage, can be programmed.
[0035] On the other hand, during the read operation, the first source line SL1 can be driven at the level of the ground voltage by the first source line drive circuit 510. Among the first to nth bit lines BL1, BL2, …, BLn, a voltage higher than the ground voltage may be provided to at least one selected bit line. Also, a read voltage may be provided to the selected word line among the multiple first word lines WL1A to WL1n, and a pass voltage may be provided to the remaining word lines. At the same time, the first drain selection transistor DSTA and the first source selection transistor SSTA may be turned on so that current can flow through the memory string connected to the selected bit line.
[0036] Among the plurality of first memory strings St_1A to St_nA, at least one memory string connected to at least one selected bit line can conduct current from the bit line to the first source line SL1. At this time, according to the data stored in the memory cells included in at least one memory string that receive a read voltage via the selected word line, the amount of current flowing from the bit line to the first source line SL1 can be adjusted. At this time, the page buffer connected to the selected bit line can detect the voltage level of the selected bit line or the amount of current flowing through the bit line, sense and store the data stored in the memory cell that receives the read voltage. By outputting the data stored in the page buffer, the read operation can be completed.
[0037] During the erase operation, the first source line SL1 can be driven at an erase voltage level higher than the level of the ground voltage by the first source line driving circuit 510. The first drain selection transistor DSTA may be turned off, and the first source selection transistor SSTA may be turned on. The plurality of first word lines WL1A to WLnA can receive the ground voltage. At this time, an erase operation may be performed on the memory cells included in the plurality of first memory strings St_1A to St_nA connected to the first source line SL1.
[0038] On the other hand, after the program operation or the erase operation is performed, a verification operation can be performed using a plurality of page buffers PB connected to the first to nth bit lines BL1, BL2,..., BLn via the first drain selection transistor DSTA.
[0039] In this way, since the first memory block BK1 performs read, program, and verification operations with the first drain selection transistor DSTA turned on, each of the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 can be electrically connected to each of the plurality of bit lines BL1, BL2, …, BLn during read, program, and verification operations.
[0040] Also, since the first memory block BK1 performs an erase operation with the first drain selection transistor DSTA turned off, each of the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 can be electrically separated from each of the plurality of bit lines BL1, BL2, …, BLn during the erase operation.
[0041] Next, referring to FIG. 4, the second memory block BK2 will be described as follows.
[0042] The second memory block BK2 can include a plurality of second memory strings St_1B to St_nB connected between each of the plurality of bit lines BL1, BL2, …, BLn and the second source line SL2. The plurality of bit lines BL1, BL2, …, BLn can include the first to nth bit lines BL1, BL2, …, BLn. For example, at least one second memory string St_1B can be connected between the first bit line BL1 and the second source line SL2. At least one second memory string St_2B can be connected between the second bit line BL2 and the second source line SL2. At least one second memory string St_nB can be connected between the nth bit line BLn and the second source line SL2.
[0043] Each of the plurality of second memory strings St_1B to St_nB can include a second drain selection transistor DSTB, a plurality of second memory cells MC1B to MCnB, and a second source selection transistor SSTB connected in series. The second drain selection transistor DSTB may be configured to receive control of a second drain selection line DSLB, and the second source selection transistor SSTB may be configured to receive control of a second source selection line SSLB. Also, each of the plurality of second memory cells MC1B to MCnB may be configured to receive control of each of the plurality of second word lines WL1B to WLnB.
[0044] The operation of the second memory block BK2 of the semiconductor device according to the embodiment of the present invention configured as described above will be described as follows.
[0045] During the program operation, the second source line SL2 can be driven at the level of an external power supply voltage by the second source line driving circuit 520. Among the first to nth bit lines BL1, BL2,..., BLn, a ground voltage may be provided to at least one selected bit line, and an external power supply voltage may be provided to the unselected bit lines. Also, among the plurality of second word lines WL1B to WLnB, a program voltage may be provided to the selected word line, and a pass voltage may be provided to the remaining word lines. At the same time, the second drain selection transistor DSTA may be turned on, and the second source selection transistor SSTA may be turned off.
[0046] At this time, among the memory cells of the memory string connected to the selected bit line, that is, the bit line receiving the ground voltage, the memory cells receiving the program voltage via the selected word line can be programmed.
[0047] During the read operation, the second source line SL2 can be driven at the level of the ground voltage by the second source line driving circuit 520. Among the first to nth bit lines BL1, BL2, …, BLn, a voltage higher than the ground voltage may be provided to at least one selected bit line. Also, among the plurality of second word lines WL1B to WLnB, a read voltage may be provided to the selected word line and a pass voltage may be provided to the remaining word lines. At the same time, the second drain selection transistor DSTB and the second source selection transistor SSTB may be turned on so that current can flow through the memory string connected to the selected bit line.
[0048] Among the plurality of second memory strings St_1B to St_nB, at least one memory string connected to at least one selected bit line can conduct current from the bit line to the second source line SL2. At this time, according to the data stored in the memory cell that receives the read voltage via the selected word line among the memory cells included in at least one memory string, the amount of current flowing from the bit line to the second source line SL2 can be adjusted. At this time, the page buffer connected to the selected bit line can detect the voltage level of the selected bit line or the amount of current flowing through the bit line, sense and store the data stored in the memory cell that receives the read voltage. By outputting the data stored in the page buffer, the read operation can be completed.
[0049] On the other hand, during the erase operation, the second source line SL2 can be driven at an erase voltage level higher than the ground voltage level by the second source line driving circuit 520. The second drain selection transistor DSTB may be turned off and the second source selection transistor SSTB may be turned on. The plurality of second word lines WL1B to WLnB can receive the ground voltage. At this time, an erase operation may be performed on the memory cells included in the plurality of second memory strings St_1B to St_nB connected to the second source line SL2.
[0050] On the other hand, after a program operation or an erase operation is performed, a verification operation can be performed using a plurality of page buffers PB connected to the first to nth bit lines BL1, BL2, …, BLn via the second drain selection transistor DSTB.
[0051] Thus, since the second memory block BK2 performs a read operation, a program operation, and a verification operation with the second drain selection transistor DSTB turned on, each of the plurality of second memory strings St_1A to St_nA included in the second memory block BK2 can be electrically connected to each of the plurality of bit lines BL1, BL2, …, BLn during the read operation, the program operation, and the verification operation.
[0052] In addition, since the second memory block BK2 performs an erase operation with the second drain selection transistor DSTB turned off, each of the plurality of second memory strings St_1B to St_nB included in the second memory block BK2 can be electrically separated from each of the plurality of bit lines BL1, BL2, …, BLn during the erase operation.
[0053] Ultimately, the semiconductor device according to the embodiment of the present invention includes each source line for each of the plurality of memory blocks sharing a plurality of bit lines, and the memory block performing the program operation, the read operation, and the verification operation is connected to the plurality of bit lines, and the memory block performing the erase operation is electrically separated from the plurality of bit lines. A ground voltage is provided to the source line of the memory block performing the program operation, the read operation, and the verification operation, and an erase voltage having a voltage level higher than the ground voltage can be provided to the source line of the memory block performing the erase operation, respectively. Therefore, the semiconductor device according to the embodiment of the present invention can cause some of the plurality of memory blocks to perform a program operation, a read operation, and a verification operation while simultaneously causing other memory blocks to perform an erase operation.
[0054] FIG. 5 is a diagram for explaining a page buffer of a semiconductor device according to an embodiment of the present invention.
[0055] The page buffer PB of the semiconductor device according to the embodiment of the present invention shown in FIG. 5 may show the configurations of the plurality of page buffers PB1, PB2, …, PBn shown in FIG. 1.
[0056] Referring to FIG. 5, the page buffer PB can include a plurality of latches Latch1, Latch2, Latch3, Latch4, Latch5 and a first switch SW1. At this time, the description taking the plurality of latches Latch1, Latch2, Latch3, Latch4, Latch5 including the first to fifth latches Latch1, Latch2, Latch3, Latch4, Latch5 and the first switch SW1 as an example is only for illustration, and does not limit the number of latches.
[0057] The first switch SW1 can electrically connect or disconnect the bit line BL and the common node Node_SO based on the first page buffer selection signal PBSelA. The first switch SW1 can include a transistor TR. The first page buffer selection signal PBSelA is input to the gate of the transistor TR, and the bit line BL and the common node Node_SO may be respectively connected to both ends (drain and source) of the transistor TR.
[0058] Each of the first to fifth latches Latch1, Latch2, Latch3, Latch4, Latch5 can be connected to the common node Node_SO. At this time, the first latch Latch1 may be arranged closest to the bit line BL, or the fifth latch Latch5 may be arranged farthest from the bit line BL. Also, the second to fourth latches Latch2, Latch3, Latch4 may be arranged between the first latch Latch1 and the fifth latch Latch5.
[0059] The first latch, Latch1, may be a sensing latch. The first latch, Latch1, can sense the voltage level or current amount of the bit line BL and store data according to the sensed value. Therefore, the first latch, Latch1, can be controlled to be activated during a read operation or a verification operation.
[0060] The fifth latch, Latch5, may be a cache latch. The fifth latch, Latch5, can receive and store data DATA from outside the page buffer PB during a program operation, or output data DATA to the outside of the page buffer PB during a read operation. Therefore, the fifth latch, Latch5, can be controlled to be activated during a program operation or a read operation.
[0061] The second to fourth latches, Latch2, Latch3, and Latch4, may be data storage latches. The reason for explaining the data storage latch with three latches, Latch2, Latch3, and Latch4, in FIG. 5 is that the memory cell can store 3-bit (LSB, CSB, MSB) data. Therefore, the second to fourth latches, Latch2, Latch3, and Latch4, can store the 3-bit (LSB, CSB, MSB) data transmitted from the fifth latch, Latch5, during a program operation. Also, the second to fourth latches, Latch2, Latch3, and Latch4, can store the 3-bit (LSB, CSB, MSB) data transmitted from the first latch, Latch1, during a read operation. Therefore, the second to fourth latches, Latch2, Latch3, and Latch4, can be controlled to be activated during a read operation or a program operation. The number of data storage latches may be different according to the number of data bits that the memory cell can store.
[0062] FIGS. 6 and 7 are diagrams for explaining the operation of a semiconductor device according to an embodiment of the present invention.
[0063] As shown in FIG. 6, the semiconductor device according to an embodiment of the present invention can perform an erasing operation in an ISPE (Incremental Step Pulse Erase) method that gradually increases the level of the erasing voltage provided to the first source line SL1 or the second source line SL2, or the first and second source lines SL1 and SL2.
[0064] That is, each of the memory blocks BK1 and BK2 included in the semiconductor device according to an embodiment of the present invention can perform an erasing operation in the ISPE method. In FIG. 6, the erasing operation of each memory block BK1 and BK2 by the ISPE method will be described. At this time, in FIG. 6, the source lines SL1 and SL2 and the word lines WL1A to WL1n and WL1B to WLnB of each memory block BK1 and BK2 are shown as SL and WL for convenience of explanation.
[0065] Referring to FIG. 6, with the word line WL at the ground voltage level, the first erasing pulse (1 st Pulse) of the erasing voltage level may be provided to the source line SL to perform the first erasing operation.
[0066] After the first erasing operation is completed, the source line SL may be driven at the ground voltage level, and the read voltage Vread may be provided to the word line WL to perform the first erasing verification operation. At this time, if it is determined that the first erasing operation fails in the first erasing verification operation, the second erasing operation may be performed.
[0067] The second erasing operation may be performed by driving the word line WL at the ground voltage level again and providing the second erasing pulse (2 nd Pulse) to the source line SL. At this time, the voltage level of the second erasing pulse (2 nd Pulse) may be a voltage level higher than the voltage level of the first erasing pulse (1 st Pulse). That is, during the second erasing operation, the erasing voltage provided to the source line SL is a preset voltage level V higher than that during the first erasing operation. STEPIt may be only the erasing voltage of a high voltage level.
[0068] After the second erasing operation is completed, the source line SL can be driven at the level of the ground voltage, and a read voltage Vread can be provided to the word line WL to perform the second erasing verification operation. At this time, if it is determined that the second erasing operation is successful (Pass) in the second erasing verification operation, the erasing operation of the memory block can be terminated.
[0069] If it is determined that the second erasing operation fails (Fail) again, a third erasing operation can be performed, and the level of the erasing voltage provided to the source line SL in the third erasing operation may be higher than the level of the erasing voltage during the second erasing operation.
[0070] Thus, the semiconductor device according to the embodiment of the present invention can perform an erasing operation in the ISPE method and can provide a source voltage whose voltage level gradually increases to the electrically separated source lines. For example, each of the first and second source line driving circuits 510 and 520 shown in FIG. 1 may be configured to provide an erasing voltage by the ISPE method during the erasing operation.
[0071] FIG. 7 may show that a part of the memory blocks BK1 and BK2 included in the semiconductor device according to the embodiment of the present invention, the memory block BK1 is performing an erasing operation, and the remaining memory block BK2 is performing a read operation or a program operation. At this time, for convenience of explanation, it is assumed that the first memory block BK1 performs an erasing operation and the second memory block BK2 performs a read operation.
[0072] Referring to FIGS. 3 and 4, the first memory block BK1 that performs an erasing operation and the second memory block BK2 that performs a read or program operation will be described.
[0073] Each of the plurality of first memory strings St_1A to St_nA included in the first memory block BK1 may be in a state electrically separated from the plurality of bit lines BL1, BL2, …, BLn and an erase operation may be performed. At this time, the first source line SL1 can be driven at the level of the erase voltage by the first source line driving circuit 510.
[0074] Each of the plurality of second memory strings St_1B to St_nB included in the second memory block BK1 may be in a state electrically connected to the plurality of bit lines BL1, BL2, …, BLn and a read or program operation may be performed. At this time, the second source line SL2 may be driven at the level of the ground voltage during a read operation and at the level of the external power supply voltage during a program operation by the second source line driving circuit 520.
[0075] If the first memory block BK1 performs a read or program operation and the second memory block BK2 performs an erase operation, as described above, the first memory block BK1 may be electrically connected to the plurality of bit lines BL1, BL2, …, BLn, and the second memory block BK2 may be electrically separated from the plurality of bit lines BL1, BL2, …, BLn. Also, the first source line SL1 may be driven at the level of the ground voltage or the external power supply voltage by the first source line driving circuit 510, and the second source line SL2 may be driven at the level of the erase voltage by the second source line driving circuit 520.
[0076] Thereafter, the memory block that has performed the erase operation can be electrically connected to the plurality of bit lines BL1, BL2, …, BLn and perform a verification operation for the erase operation via the plurality of page buffers PB1, BP2, …, PBn after another memory block has completed a read or program operation.
[0077] Ultimately, the semiconductor device according to the embodiment of the present invention is configured to include source lines for each of a plurality of memory blocks, and can be controlled such that while some of the plurality of memory blocks are performing read or program operations, some other memory blocks are performing erase operations. Therefore, the semiconductor device according to the embodiment of the present invention can perform erase operations and other operations simultaneously, and can perform more operations required by the host than a general semiconductor device that performs erase operations and other operations separately.
[0078] As described above, embodiments according to the technical idea of the present invention have been described with reference to the accompanying drawings. However, this is merely for explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the above embodiments. Within the scope not departing from the technical idea of the present invention described in the claims, various forms of substitution, modification, and change to the embodiments are possible by those with ordinary knowledge in the technical field to which the present invention pertains, and these also belong to the scope of the present invention.
Description of Reference Numerals
[0079] 100: Control Circuit, 200: Line Driving Circuit 300: Page Buffer Group, 400: Cell Array 510, 520: Source Line Driving Circuit
Claims
1. a first source line driving circuit for driving the first source line; a second source line driving circuit for driving the second source line; a first memory block including a plurality of first memory strings respectively connected between the first source line and a plurality of bit lines; a second memory block including a plurality of second memory strings respectively connected between the second source line and the plurality of bit lines. Semiconductor device.
2. Each of the first source line driving circuit and the second source line driving circuit comprises: driving the first source line and the second source line at different voltage levels; The semiconductor device according to claim 1 .
3. The first source line driving circuit includes: When a read operation or a program operation is performed on the first memory block, the first source line is driven to a ground voltage level or a power supply voltage level; When an erase operation is performed on the first memory block, the first source line is driven at an erase voltage level higher than the ground voltage level. The semiconductor device according to claim 2 .
4. The second source line driving circuit includes: driving the second source line to a level of the ground voltage or a level of a power supply voltage when the read operation or the program operation is performed on the second memory block; driving the second source line at a level of the erase voltage when the erase operation is performed on the second memory block; The semiconductor device according to claim 3 .
5. a plurality of page buffers coupled to each of the plurality of bit lines, The semiconductor device according to claim 4.
6. The plurality of page buffers include a plurality of bit lines electrically connected to a selected memory block that performs the read operation or the program operation among the first and second memory blocks, and performing the read operation or a verify operation for the program operation; The semiconductor device according to claim 5 .
7. The plurality of page buffers include Among the first and second memory blocks, a memory block which is subjected to the erase operation is electrically isolated. The semiconductor device according to claim 6.
8. The plurality of page buffers include When the erase operation is completed, a verify operation for the erase operation is performed by electrically connecting the erased memory block to the memory block. The semiconductor device according to claim 7.
9. Each of the first and second plurality of memory strings comprises: a plurality of drain select transistors respectively connected to the plurality of bit lines; a plurality of source selection transistors connected to the first source line or the second source line; a plurality of memory cells serially coupled between each of the plurality of drain select transistors and each of the plurality of source select transistors; The semiconductor device according to claim 1 .
10. Each of the first and second plurality of memory strings comprises: the drain selection transistors are turned on and off to be electrically connected to or isolated from the bit lines, respectively; The semiconductor device according to claim 9.
11. Each of the first and second plurality of memory strings comprises: the plurality of source select transistors are turned on and off to be electrically connected to or isolated from the first and second source lines, respectively; The semiconductor device according to claim 10.
12. driving a first source line at an erase voltage level; driving the second source line at one of a ground voltage and a power supply voltage; performing an erase operation on a first memory block connected to the first source line; and causing a second memory block connected to the second source line to perform a read operation or a program operation. A method of operating a semiconductor device.
13. The step of causing the first memory block to perform an erase operation includes: electrically isolating a plurality of first memory strings and a plurality of bit lines included in the first memory block; electrically connecting the first source line to the first plurality of memory strings. A method for operating the semiconductor device according to claim 12.
14. The step of causing the first memory block to perform an erase operation includes: driving a plurality of first word lines coupled to the plurality of first memory strings at a level of the ground voltage. A method for operating the semiconductor device according to claim 13.
15. The step of causing the second memory block to perform a read operation or a program operation includes: electrically connecting a plurality of second memory strings included in the second memory block to the plurality of bit lines; electrically connecting the second source line and the second memory strings during the read operation, and electrically isolating the second source line and the second memory strings during the program operation. A method for operating the semiconductor device according to claim 13.
16. A first source line; A second source line; A plurality of bit lines; a first memory block including a plurality of first memory strings respectively connected between the first source line and the plurality of bit lines; a second memory block including a plurality of second memory strings respectively connected between the second source line and the plurality of bit lines; a control circuit for causing the first memory block to perform an erase operation and for causing the second memory block to perform a read or program operation at the same time; a first source driving circuit for driving the first source line with an erase voltage; a second source driving circuit for driving the second source line with a ground voltage lower than the erase voltage. Semiconductor device.
17. a plurality of page buffers respectively connected to the plurality of bit lines; The semiconductor device according to claim 16.
18. Each of the first and second plurality of memory strings comprises: a plurality of drain select transistors respectively connected to the plurality of bit lines; a plurality of source selection transistors connected to the first source line or the second source line; a plurality of memory cells connected in series between the plurality of drain select transistors and the plurality of source select transistors; The semiconductor device according to claim 16.
19. Each of the first and second plurality of memory strings comprises: the drain selection transistors are turned on and off to be electrically connected to or isolated from the bit lines; The semiconductor device according to claim 18.
20. Each of the first and second plurality of memory strings comprises: the first and second source lines are electrically connected to or separated from each other by turning on and off the plurality of source transistors; 20. The semiconductor device according to claim 19.