Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device and a semiconductor module capable of preventing the outflow of defective chips.SOLUTION: On the front surface of a semiconductor chip 10, a source pad 11, a gate pad 12, and a measurement pad 13 are exposed at different openings 26d, 26b, and 26e of a passivation film 26, respectively. A measurement pad 13 is disposed in a position relatively close to the source pad 11 and the gate pad 12, and a part 11a of the source pad 11 is interposed between the gate pad 12 and the measurement pad 13. When the gate pad 12 and the measurement pad 13 are short-circuited by solder material that has flowed out from above the gate pad 12 onto the surface of the passivation film 26 during soldering of the external lead-out wiring to the gate pad 12 during assembly of the semiconductor module, the gate pad 12 and the source pad 11 are short-circuited, making it possible to detect the short-circuit between the gate pad 12 and the measurement pad 13.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a semiconductor module.

Background Art

[0002] Patent Document 1 describes a technique for measuring the resistance value of a gate resistance determined by the internal resistance of a gate polysilicon (poly-Si) layer connected in series between a gate pad and a measurement pad by an electrode pad for measuring the gate resistance value (hereinafter referred to as a measurement pad). Patent Document 2 describes a technique of providing a plating film for bringing a probe needle of an inspection device into contact only with a part on a source pad and a measurement pad.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Documents 1 and 2 above, when a wiring for external extraction such as a wire is soldered to a gate pad in the assembly process of a semiconductor module, the gate pad and the measurement pad may be short-circuited by the spread solder, and the resistance value of the gate resistance may fluctuate. Since there is no means for detecting a semiconductor chip (hereinafter referred to as a defective chip) in which the gate pad and the measurement pad are at the same potential, the product (semiconductor module) with the defective chip mounted may flow out.

[0005] An object of this disclosure is to provide a semiconductor device and a semiconductor module capable of preventing the outflow of defective chips.

Means for Solving the Problems

[0006] A semiconductor module according to one aspect of this disclosure is as follows. The semiconductor element is provided on a semiconductor substrate and includes an insulating gate having a three-layer structure of a metal film - oxide film - semiconductor. The main electrode pad is provided on the first main surface of the semiconductor substrate to conduct the semiconductor element. A first external member is metal-bonded to the main electrode pad. The gate pad is provided on the first main surface of the semiconductor substrate via an insulating film. The gate runner is provided on the first main surface of the semiconductor substrate via the insulating film.

[0007] The gate electrode, which is the metal film of the insulating gate, is electrically connected to the gate runner. The gate resistor is provided on the first main surface of the semiconductor substrate via the insulating film and electrically connects the gate pad and the gate runner. The measurement pad is provided on the first main surface of the semiconductor substrate via the insulating film and is electrically connected to the gate runner. The measurement pad is used for measuring the resistance value of the gate resistor. A part of the main electrode pad is interposed between the gate pad and the measurement pad in a plan view.

Advantages of the Invention

[0008] According to the semiconductor device and the semiconductor module according to the present disclosure, there is an effect that the outflow of defective chips can be prevented.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Embodiments for Carrying Out the Invention

[0010] <Summary of Embodiments of the Present Disclosure> (1) A semiconductor device according to one aspect of this disclosure is as follows. The semiconductor element is provided on a semiconductor substrate and includes an insulating gate having a three-layer structure of a metal film - an oxide film - a semiconductor. The main electrode pad is provided on the first main surface of the semiconductor substrate to conduct the semiconductor element. A first external member is metal-bonded to the main electrode pad. The gate pad is provided on the first main surface of the semiconductor substrate via an insulating film. The gate runner is provided on the first main surface of the semiconductor substrate via the insulating film.

[0011] The gate electrode, which is the metal film of the insulating gate, is electrically connected to the gate runner. The gate resistor is provided on the first main surface of the semiconductor substrate via the insulating film and electrically connects the gate pad and the gate runner. The measurement pad is provided on the first main surface of the semiconductor substrate via the insulating film and is electrically connected to the gate runner. The measurement pad is used for measuring the resistance value of the gate resistor. A part of the main electrode pad is interposed between the gate pad and the measurement pad in a plan view.

[0012] According to the above disclosure, even if the gate pad and the measurement pad are short-circuited due to the adhesion of conductive foreign matter, the adhesion causes the gate pad and the main electrode pad to be short-circuited, and it becomes possible to detect the short-circuit between the gate pad and the measurement pad.

[0013] (2) Further, in the semiconductor device according to this disclosure, in the above-described (1), a second external member may be metal-bonded to the gate pad.

[0014] According to the above disclosure, even if the gate pad and the measurement pad are short-circuited when the second external member is bonded to the gate pad, the bonding material of the second external member causes the gate pad and the main electrode pad to be short-circuited, and it becomes possible to detect the short-circuit between the gate pad and the measurement pad.

[0015] (3) Further, in the semiconductor device according to this disclosure, in the above-described (1) or (2), the surface area of the first metal bonding layer that bonds the main electrode pad and the first external member in a plan view may be larger than the surface area of the opening of the main electrode pad.

[0016] According to the above disclosure, it is possible to induce a short circuit between the gate pad and the main electrode pad when conductive foreign matter adheres or when metal bonding is performed to the gate pad.

[0017] (4) Further, in the semiconductor device according to this disclosure, in any one of the above-described (1) to (3), the passivation film covers the first main surface of the semiconductor substrate. The main electrode pad is exposed in the first opening of the passivation film. The first metal bonding layer that bonds the main electrode pad and the first external member may be filled in the first opening and extend on the surface of the passivation film.

[0018] According to the above disclosure, it is possible to induce a short circuit between the gate pad and the main electrode pad when conductive foreign matter adheres or when metal bonding is performed to the gate pad.

[0019] (5) Further, in any one of (1) to (4) described above, in the semiconductor device according to this disclosure, the surface area of the second metal bonding layer that bonds the gate pad and the second external member in plan view may be larger than the opening surface area of the gate pad.

[0020] According to the above-described disclosure, a short circuit between the gate pad and the main electrode pad can be induced when the second external member is bonded to the gate pad.

[0021] (6) Further, in any one of (1) to (5) described above, in the semiconductor device according to this disclosure, the passivation film covers the first main surface of the semiconductor substrate. The gate pad is exposed in the second opening of the passivation film. The second metal bonding layer that bonds the gate pad and the second external member may be filled in the second opening and extend on the surface of the passivation film.

[0022] According to the above-described disclosure, a short circuit between the gate pad and the main electrode pad can be induced when the second external member is bonded to the gate pad.

[0023] (7) Further, in any one of (1) to (6) described above, in the semiconductor device according to this disclosure, the first metal bonding layer may be formed of a solder material or a metal sintered material.

[0024] According to the above-described disclosure, a short circuit between the gate pad and the main electrode pad can be induced when a conductive foreign object adheres or when the metal is bonded to the gate pad.

[0025] (8) Further, in any one of (1) to (7) described above, in the semiconductor device according to this disclosure, the second metal bonding layer may be formed of a solder material or a metal sintered material.

[0026] According to the above-described disclosure, a short circuit between the gate pad and the main electrode pad can be induced when the second external member is bonded to the gate pad.

[0027] (9) Further, in any one of (1) to (8) described above, in the semiconductor device according to this disclosure, the first metal bonding layer is made of a solder material. The main electrode pad may be bonded to the first metal bonding layer via a plating film.

[0028] According to the above-described disclosure, the wettability of the first metal bonding layer can be improved.

[0029] (10) Further, in any one of (1) to (9) described above, in the semiconductor device according to this disclosure, the second metal bonding layer is made of a solder material. The gate pad may be bonded to the second metal bonding layer via a plating film.

[0030] According to the above-described disclosure, the wettability of the second metal bonding layer can be improved.

[0031] (11) A semiconductor module according to one aspect of this disclosure is a semiconductor module equipped with any one of the semiconductor devices of (1) to (10) described above, and is as follows. A plurality of the semiconductor elements are mounted. The plurality of semiconductor elements are connected in parallel to each other. The first external member is metal-bonded to the main electrode pads of the plurality of semiconductor elements, respectively.

[0032] According to the above-described disclosure, it becomes possible to detect a semiconductor element in which the gate pad and the measurement pad are short-circuited from a plurality of semiconductor elements connected in parallel.

[0033] <Knowledge underlying the present disclosure> First, the semiconductor module of the reference example will be described. FIGS. 6 and 7 are plan views showing layout examples of semiconductor chips mounted on the semiconductor module of the reference example as viewed from the front side. FIG. 6 is FIG. 7 of Patent Document 1 described above. FIGS. 8 and 9 are cross-sectional views showing cross-sectional structures taken along the cutting line AA-AA' of FIGS. 6 and 7. FIGS. 8 and 9 show the normal state (good chip 110a) and the abnormal state (defective chip 110b) after the external lead wire 132 is soldered to the gate pad 112 of the semiconductor chip 110 mounted on the semiconductor module 130 (see FIG. 10) of the reference example. FIG. 10 is a circuit diagram showing an equivalent circuit of the semiconductor module of the reference example.

[0034] The semiconductor device 120-1 shown in FIG. 6 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor, a MOS type field effect transistor having an insulated gate composed of a three-layer structure of a metal film - an oxide film - a semiconductor) 120 provided with a source pad 111, a gate pad 112, and a measurement pad 113 on the front surface of the semiconductor chip 110 in the active region 101, and is mounted on the semiconductor module 130 of the reference example shown in FIG. 10. The active region 101 has a substantially rectangular planar shape and is disposed substantially at the center of the semiconductor chip 110. The region between the active region 101 and the end of the semiconductor chip 110 is the edge termination region 102. The edge termination region 102 surrounds the periphery of the active region 101.

[0035] The source electrode of the MOSFET 120 is provided on the front surface of the semiconductor chip 110. The portion of the source electrode that is exposed in the substantially rectangular planar opening 124a of the passivation film 124 functions as the source pad 111. The source pad 111, the gate pad 112, and the measurement pad 113 are respectively exposed in different openings 124a to 124c of the passivation film 124. The gate pad 112 has a substantially rectangular planar shape and is disposed near the boundary between the active region 101 and the edge termination region 102. The measurement pad 113 has a substantially rectangular planar shape and is disposed away from the source pad 111 and the gate pad 112 at a corner portion of the four corner portions (vertices) of the active region 101 that is close to the gate pad 112.

[0036] The measurement pad 113 is connected to the gate runner 114. The gate runner 114 is provided on the front surface of the semiconductor chip 110 in the edge termination region 102 via the field oxide film 123 and surrounds the periphery of the active region 101 in a substantially rectangular shape. The gate runner 114 is electrically connected to the gate pad 112 via the gate resistor 115. All the gate electrodes 125 (see FIG. 10) of the cells (functional units of the elements) of the MOSFET 120 disposed in the active region 101 are connected to the gate runner 114. By the gate runner 114, the built-in resistance Rg2 by the gate resistor 115 made of polysilicon and the parasitic resistance Rg1 by the gate electrode 125 made of polysilicon are connected in series.

[0037] The combined resistance of the built-in resistance Rg2 by the gate resistor 115 and the parasitic resistance Rg1 by the gate electrode 125 is the overall gate resistance Rg3 of the MOSFET 120. The resistance value of the built-in resistance Rg2 by the gate resistor 115 is set higher than the resistance value of the parasitic resistance Rg1 by the gate electrode 125 so that the resistance value of the overall gate resistance Rg3 of the MOSFET 120 is determined by the resistance value of the built-in resistance Rg2 by the gate resistor 115. By connecting the measurement pad 113 to the gate runner 114, the built-in resistance Rg2 by the gate resistor 115 is connected in series between the gate pad 112 and the measurement pad 113, and the resistance value of the built-in resistance Rg2 can be measured by the measurement pad 113.

[0038] However, the longer the distance between the measurement pad 113 and the gate pad 112, the longer the gate polysilicon wiring layer constituting the gate runner 114 is routed between the measurement pad 113 and the gate pad 112. For this reason, the resistance value of the gate polysilicon wiring layer constituting the gate runner 114 cannot be ignored and is added to the resistance value measured by the measurement pad 113, increasing the resistance value of the overall gate resistance Rg3 of the MOSFET 120. Also, when the MOSFET 120 is switched, the potential of the field oxide film 123 directly under the gate runner 114 (on the n + type drain region side) of the semiconductor chip 110 is raised by the displacement current flowing through the semiconductor chip 110, and there is a risk of dielectric breakdown occurring at this location.

[0039] The longer the gate runner 114 is routed between the measurement pad 113 and the gate pad 112, the longer the path of the displacement current flowing directly under the gate runner 114, making it easier for dielectric breakdown to occur directly under the gate runner 114. Also, the displacement current is between the front surface of the semiconductor chip 110 and the n -It flows through the p-type region 122 between the type drift region 121 and is drawn out to the source electrode. When silicon carbide (SiC) is used as the semiconductor material of the semiconductor chip 110, since the sheet resistance of p-type SiC is high, the potential of the field oxide film 123 directly under the gate runner 114 is likely to rise due to the displacement current flowing through the p-type region 122 directly under the gate runner 114, and it is particularly prominent in a low-temperature environment.

[0040] When the MOSFET 120 is switched at high speed, a high voltage (= the current value of the displacement current flowing through the p-type region 122 × the sheet resistance value of the p-type region 122) is applied to the semiconductor chip 110 at a steep dV / dt (rate of change of voltage with time), so breakdown is likely to occur directly under the gate runner 114. The semiconductor device 120-2 shown in FIG. 7 is different from the semiconductor device 120-1 shown in FIG. 6 in that the distance between the gate pad 112 and the measurement pad 113 is shortened to suppress breakdown directly under the gate runner 114. The measurement pad 113 of the semiconductor device 120-2 is arranged between the source pad 111 and the gate pad 112, away from the source pad 111 and the gate pad 112, and at a position relatively close to the gate pad 112.

[0041] The semiconductor module 130 shown in FIG. 10 is a MOSFET module in which MOSFETs 120 respectively fabricated on a plurality of semiconductor chips 110 having the same structure shown in FIG. 6 or FIG. 7 are connected in parallel. The gate pads 112 of each semiconductor chip 110 are connected in parallel by an external lead wiring 132 (see FIGS. 8 and 9), and are electrically connected to the PG (Protective Ground) 133 of the semiconductor module 130 via the chip resistance Rg4 of the semiconductor chip 110 itself. In each semiconductor chip 110, a parasitic resistance Rg1 due to the gate electrode 125 and a built-in resistance Rg2 due to the gate resistor 115 are connected in series between the PG 133 and the gate electrode 125 of the MOSFET 120.

[0042] In each semiconductor chip 110, there is a large variation in the parasitic resistance Rg1 due to the gate electrode 125. Therefore, by adjusting the resistance value of the built-in resistor Rg2 by the gate resistor 115 added to the semiconductor chip 110, the resistance value of the gate resistor Rg3 of the semiconductor chip 110 determined by the resistance value of the built-in resistor Rg2 is controlled. The semiconductor chips 110 are sorted based on the resistance value of the built-in resistor Rg2 by the gate resistor 115 measured using the measurement pads 113, and only the semiconductor chips 110 in which the resistance value of the gate resistor Rg3 is within a predetermined range are mounted on the semiconductor module 130. In this way, the switching variation of the plurality of semiconductor chips 110 connected in parallel within the semiconductor module 130 is reduced.

[0043] However, when assembling the semiconductor module 130, the measurement pads 113 of each semiconductor chip 110 are in an exposed state. Therefore, if the distance between the gate pad 112 and the measurement pad 113 is shortened as in the semiconductor device 120-2 of FIG. 7, when soldering an external lead wiring 132 such as a wire to the gate pad 112, the solder spreads wet from the gate pad 112 to the measurement pad 113, and there is a risk that the gate pad 112 and the measurement pad 113 are short-circuited via the solder layer 131 (FIG. 9). Even if the distance between the gate pad 112 and the measurement pad 113 is sufficiently increased as in the semiconductor device 120-1 of FIG. 6, there is a risk that the gate pad 112 and the measurement pad 113 are short-circuited due to the adhesion of conductive foreign matter (not shown).

[0044] When the gate pad 112 and the measurement pad 113 are short-circuited, the resistance value of the internal resistance Rg2 by the gate resistor 115 becomes zero, the resistance value of the gate resistor Rg3 fluctuates, and it becomes a defective chip 110b that turns on (malfunctions) earlier than other semiconductor chips 110 (good chip 110a: FIG. 8) in the semiconductor module 130. Since there is no means to detect the defective chip 110b in which the gate pad 112 and the measurement pad 113 are at the same potential, the product (semiconductor module 130) with the defective chip 110b mounted will leak out. On the other hand, if the distance between the gate pad 112 and the measurement pad 113 is increased to prevent short-circuiting, as described above, an increase in the resistance value of the gate resistor Rg3 and dielectric breakdown due to displacement current will occur.

[0045] An issue to be solved in the present embodiment is to prevent the leakage of defective chips.

[0046] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the semiconductor device and the semiconductor module according to this disclosure will be described in detail. In this specification and the accompanying drawings, for a layer or region preceded by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0047] (Details of Embodiment 1) The semiconductor device and semiconductor module according to Embodiment 1 for solving the above-described problems will be described below. FIG. 1 is a plan view showing a layout example of a semiconductor chip mounted on the semiconductor module according to Embodiment 1 as viewed from the front side. FIGS. 2 and 3 are cross-sectional views showing the cross-sectional structure taken along the cutting line A-A' in FIG. 1. FIGS. 2 and 3 show the states of the measurement pads 13 in the normal state (good chip 10a) and the abnormal state (defective chip 10b) after the external lead wiring 32 is soldered to the gate pad 12 of the semiconductor chip 10 mounted on the semiconductor module 30 (see FIG. 4). FIG. 4 is a circuit diagram showing an equivalent circuit of the semiconductor module according to Embodiment 1.

[0048] The semiconductor device 20-1 according to Embodiment 1 shown in FIGS. 1 to 3 is a vertical MOSFET (semiconductor element) 20 provided with a source pad (main electrode pad) 11, a gate pad 12, and a measurement pad 13 on the front surface of the semiconductor chip 10 in the active region 1, and is mounted on the semiconductor module 30 according to Embodiment 1 shown in FIG. 4. The active region 1 has a substantially rectangular planar shape and is disposed substantially at the center of the semiconductor chip 10. The effective region of the active region 1 (hereinafter referred to as the active effective region) is a region through which the main current flows when the MOSFET 20 is in the on state, and occupies most of the active region 1. A plurality of cells (functional units of the element) having the same structure of the MOSFET 20 are arranged adjacent to each other in the active effective region.

[0049] The region between the active region 1 and the end of the semiconductor chip 10 is the edge termination region 2. The edge termination region 2 surrounds the periphery of the active region 1. The edge termination region 2 has a function of relaxing the electric field on the front surface side of the semiconductor chip 10 and maintaining the breakdown voltage. The breakdown voltage is the limit voltage at which the element does not malfunction or break. A predetermined breakdown voltage structure (not shown), such as a junction termination extension (JTE) structure or a field limiting ring (FLR) structure, is disposed in the edge termination region 2.

[0050] The source electrode 59 of the MOSFET 20 (see FIGS. 2 and 3) is provided on the front surface of the semiconductor chip 10 and covers substantially the entire active region. The portion of the source electrode 59 that is exposed at the opening (first opening) 26a of the passivation film 26 functions as the source pad 11. The source pad 11, the gate pad 12, and the measurement pad 13 are respectively exposed at different openings 26a to 26c of the passivation film 26 and are arranged apart from each other. The source pad 11 is electrically insulated from the gate pad 12 and the measurement pad 13 by the interlayer insulating film 25 and the passivation film 26.

[0051] As shown in FIG. 1, the source pad 11 has a substantially rectangular planar shape with a part recessed so as to surround the measurement pad 13, and surrounds substantially the entire circumference around the measurement pad 13 in a substantially rectangular shape with an opening 11b. Among the active regions 1, directly below the gate pad 12, the measurement pad 13, and the gate resistor 15 are inactive regions (regions excluding the active region) that do not function as the MOSFET 20, and cells of the MOSFET 20 are not arranged. The gate pad 12 has a substantially rectangular planar shape and is arranged near the outer periphery of the active region 1. The measurement pad 13 has a substantially rectangular planar shape and is arranged between the source pad 11 and the gate pad 12.

[0052] Substantially the entire circumference around the measurement pad 13 faces the source pad 11 only through the passivation film 26 in a direction parallel to the front surface of the semiconductor chip 10. A part 11a of the source pad 11 is interposed between the gate pad 12 and the measurement pad 13 except for the opened part 11b of the source pad 11. The measurement pad 13 faces the gate pad 12 through the passivation film 26 in a direction parallel to the front surface of the semiconductor chip 10 at the opened part 11b of the source pad 11. The measurement pad 13 is electrically connected to the gate polysilicon (poly-Si) wiring layer that constitutes the gate runner 14 at a portion not shown in the figure.

[0053] That is, the source pad 11 is arranged so as to overlap on a straight path from the gate pad 12 toward the measurement pad 13 when viewed from the front side of the semiconductor chip 10 (in plan view). The gate pad 12 has a relatively small area, and it is difficult to adjust the amount of solder applied onto the gate pad 12 during soldering of the external lead wiring 32b (see FIGS. 2 and 3) to the gate pad 12. Since there is a risk that the solder material applied onto the gate pad 12 may flow out onto the surface of the passivation film 26 and spread wetly toward the measurement pad 13 side, a part of the source pad 11 may be arranged on the path along which the solder material spreads wetly from the gate pad 12 toward the measurement pad 13 side.

[0054] The gate runner 14 is provided on the front surface of the semiconductor chip 10 via the field oxide film 24 in the edge termination region 2. The gate runner 14 is formed by laminating a gate polysilicon wiring layer and a gate metal wiring layer in this order. The gate polysilicon wiring layer constituting the gate runner 14 is provided in the same layer as the gate resistor 15 and the gate polysilicon layers 16 and 17 (see FIGS. 2 and 3) described later, and surrounds the periphery of the active region 1 in a substantially rectangular shape. Further, the gate polysilicon wiring layer constituting the gate runner 14 is electrically connected to the gate pad 12 via the gate resistor 15.

[0055] The gate electrodes 56 of all cells of the MOSFET 20 are connected to the gate polysilicon wiring layer constituting the gate runner 14. By the gate runner 14, the built-in resistance Rg2 by the gate resistor 15 made of polysilicon and the parasitic resistance Rg1 by the gate electrode 56 made of polysilicon are connected in series. Further, the gate polysilicon wiring layer constituting the gate runner 14 is routed into the active region 1, extends toward the measurement pad 13 side through the opened portion 11b of the source pad 11 (not shown), and is connected to the measurement pad 13 and the gate polysilicon layer 17 directly below the measurement pad 13.

[0056] The gate polysilicon wiring layer constituting the gate runner 14 is covered with the interlayer insulating film 25. The gate metal wiring layer constituting the gate runner 14 is provided in the same layer as the source pad 11, the gate pad 12, and the measurement pad 13, surrounds the periphery of the active region 1 in a substantially rectangular shape, and is connected to the gate polysilicon wiring layer directly below through the contact hole of the interlayer insulating film 25. The gate resistor 15 is a gate polysilicon layer provided on the front surface of the semiconductor chip 10 via the field oxide film 24 in the active non-active region, and is disposed between the gate pad 12 and the gate runner 14.

[0057] One end of the gate resistor 15 is connected to the gate polysilicon layer 16 directly below the gate pad 12. The other end of the gate resistor 15 is connected to the gate polysilicon wiring layer constituting the gate runner 14. The combined resistance of the built-in resistance Rg2 by the gate resistor 15 and the parasitic resistance Rg1 by the gate electrode 56 is the overall gate resistance Rg3 of the MOSFET 20. The resistance value of the built-in resistance Rg2 by the gate resistor 15 is set higher than the resistance value of the parasitic resistance Rg1 by the gate electrode 56 so that the resistance value of the overall gate resistance Rg3 of the MOSFET 20 is determined by the resistance value of the built-in resistance Rg2 by the gate resistor 15.

[0058] By connecting the measurement pad 13 to the gate runner 14, the built-in resistance Rg2 by the gate resistor 15 is connected in series between the gate pad 12 and the measurement pad 13, and the resistance value of the built-in resistance Rg2 can be measured by the measurement pad 13. Since the distance between the gate pad 12 and the measurement pad 13 is relatively short, the length of the gate runner 14 (gate polysilicon wiring layer) routed between the gate pad 12 and the measurement pad 13 becomes relatively short. Therefore, the resistance value of the gate polysilicon wiring layer constituting the gate runner 14 can be ignored and is not added to the resistance value measured by the measurement pad 13.

[0059] Regarding the cross-sectional structure of the semiconductor device 20-1, the case where the semiconductor material of the semiconductor chip 10 is SiC will be described as an example. As shown in FIGS. 2 and 3, the semiconductor chip 10 is, for example, an n + -type starting substrate 41 on the front surface of the n - -type drift region 21 and a p-type base region 51 are semiconductor substrates formed by laminating epitaxial layers 42 and 43 in this order. The n + -type starting substrate 41 becomes the n + -type drain region 27. The semiconductor chip 10 has the first main surface on the p-type epitaxial layer 43 side as the front surface and the second main surface on the n + -type starting substrate 41 side as the back surface.

[0060] In the active effective region, an element structure (here, a trench gate structure) of the MOSFET 20 is provided on the front surface side of the semiconductor chip 10. The trench gate structure is composed of a p-type base region 51, an n + -type source region 52, a p ++ -type contact region 53, a trench 54, a gate insulating film 55, and a gate electrode 56. The portion of the p-type epitaxial layer 43 excluding the n + -type source region 52, the p ++ -type contact region 53, the p + -type outer peripheral region 22 to be described later, and the p ++ -type outer peripheral region 23 to be described later is the p-type base region 51. The p-type base region 51 is provided between the front surface of the semiconductor chip 10 and the n - -type drift region 21.

[0061] The n + -type source region 52 and the p ++ -type contact region 53 are diffusion regions formed in the p-type epitaxial layer 43 by ion implantation. The n + -type source region 52 and the p ++ -type contact region 53 are selectively provided in contact with the p-type base region 51 between the front surface of the semiconductor chip 10 and the p-type base region 51, respectively. The n + -type source region 52 and the p ++The p-type contact region 53 contacts the source electrode 59 on the front surface of the semiconductor chip 10. p ++ The p-type contact region 53 may not be provided. In this case, p ++ Instead of the p-type contact region 53, the p-type base region 51 reaches the front surface of the semiconductor chip 10.

[0062] The trench 54 penetrates the n-type source region 52 and the p-type base region 51 in the depth direction and terminates inside the n-type current diffusion region 58 described later. The trenches 54 are arranged in a plurality adjacent to each other in a stripe shape parallel to the front surface of the semiconductor chip 10, for example. The trench 54 on the most inactive region side penetrates the p + -type outer peripheral region 23 and the p ++ -type outer peripheral region 22 and terminates inside the p + -type outer peripheral region 22. A gate electrode 56 is provided inside the trench 54 via a gate insulating film 55. +

[0063] Between the p-type base region 51 and the n - -type drift region 21, at a position deeper than the bottom surface of the trench 54 on the n + -type drain region 27 side, a p + -type region 57 and an n-type current diffusion region 58 are selectively provided, respectively. p + -type region 57 and the n-type current diffusion region 58 are diffusion regions formed by ion implantation in the n - -type epitaxial layer 42. The portion of the n - -type epitaxial layer 42 excluding the p + -type region 57, the n-type current diffusion region 58, and the p + -type outer peripheral region 22 described later is the n - -type drift region 21. The p + -type region 57 is fixed to the potential of the source electrode 59 at a portion not shown in the figure.

[0064] p +The p-type region 57 has a function of relaxing the electric field near the bottom surface of the trench 54 by being depleted when the MOSFET 20 is turned off (or by depleting the n-type current diffusion region 58 or both). + The p-type region 57 is provided apart from the p-type base region 51 and faces the bottom surface of the trench 54 in the depth direction. + The p-type region 57 may be in contact with the gate insulating film 55 at the bottom surface of the trench 54 or may be separated from the trench 54. + The p-type region 57 has a lower surface (the surface on the n + -type drain region 27 side) and may be in contact with the n - -type drift region 21 or may be surrounded by the n-type current diffusion region 58.

[0065] The n-type current diffusion region 58 is a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the spreading resistance of carriers. The n-type current diffusion region 58 is adjacent to the p + -type region 57 and the trench 54 in a direction parallel to the front surface of the semiconductor chip 10, has an upper surface (the surface on the n + -type source region 52 side) in contact with the p-type base region 51, and has a lower surface in contact with the n - -type drift region 21. The n-type current diffusion region 58 may not be provided. In this case, instead of the n-type current diffusion region 58, the n - -type drift region 21 reaches the p-type base region 51 and reaches the trench 54 between the p-type base region 51 and the p + -type region 57.

[0066] The interlayer insulating film 25 is provided on the entire front surface of the semiconductor chip 10 and covers all the gate electrodes 56. The source electrode 59 makes an ohmic contact with the front surface of the semiconductor chip 10 through the contact hole of the interlayer insulating film 25 and is electrically connected to the p-type base region 51, the n + -type source region 52, and the p ++ -type contact region 53. The drain electrode 18 is provided on the entire back surface of the back surface of the semiconductor chip 10 (the back surface of the n + -type starting substrate 41). The drain electrode 18 makes an ohmic contact with the back surface of the semiconductor chip 10 and is n+ type drain region 27(n + type starting substrate 41) is electrically connected.

[0067] In the active non-effective region, on the entire area between the front surface of the semiconductor chip 10 and the n - type drift region 21, n - type drift region 21 in contact with a p + type outer peripheral region 22 is provided. p + type outer peripheral region 22 is a diffusion region formed by ion implantation in the epitaxial layers 42, 43. p + type outer peripheral region 22 surrounds the active effective region. p + type outer peripheral region 22 extends toward the active effective region side and reaches the side wall of the trench 54 on the most active non-effective region side, and may be in contact with the p + type region 57 directly below the trench 54 on the most active non-effective region side. p + The depth position of the lower surface of the p + type outer peripheral region 22 may be substantially the same as the depth position of the lower surface of the p

[0068] Between the front surface of the semiconductor chip 10 and the p + type outer peripheral region 22, on the entire area, p + type outer peripheral region 22 in contact with a p ++ type outer peripheral region 23 is provided. p ++ type outer peripheral region 23 is a diffusion region formed by ion implantation in the p-type epitaxial layer 43. p ++ type outer peripheral region 23 is covered by the field oxide film 24. p ++ type outer peripheral region 23 surrounds the active effective region. p ++ type outer peripheral region 23, p ++ type contact region 53 may be formed simultaneously. p ++ type outer peripheral region 23 may not be provided. In this case, p ++ instead of the p + type outer peripheral region 23, the p

[0069] p + type outer peripheral regions 22 and p ++The p-type outer peripheral region 23 is electrically connected to the source electrode 59 at a portion not shown in the figure, and has a function of drawing out holes accumulated in the n-type drift region 21 in the edge termination region 2 to the source electrode 59 when the MOSFET 20 is turned off. In the active non-active region, the entire front surface of the semiconductor chip 10 is covered with an insulating layer formed by laminating a field oxide film 24 and an interlayer insulating film 25 in this order. A gate resistor 15 (see FIG. 1) and gate polysilicon layers 16 and 17 are provided between the field oxide film 24 and the interlayer insulating film 25. - The gate polysilicon layers 16 and 17 are arranged apart from each other and are exposed to different contact holes of the interlayer insulating film 25, respectively. The gate polysilicon layers 16 and 17 may be partially connected. The gate pad 12 and the measurement pad 13 are provided on the gate polysilicon layers 16 and 17 at the respective contact holes of the interlayer insulating film 25. The gate pad 12 and the measurement pad 13 are provided in the same layer as the source electrode 59 (source pad 11). The source pad 11, the gate pad 12, and the measurement pad 13 are terminated on the interlayer insulating film 25 while being separated from each other.

[0070] The passivation film 26 is a surface protection film that covers substantially the entire front surface of the semiconductor chip 10 (that is, the surface of the interlayer insulating film 25) to protect the front surface of the semiconductor chip 10. The source pad 11 (source electrode 59), the gate pad 12, and the measurement pad 13 are exposed to the openings 26a to 26c of the passivation film 26, respectively. The entire surfaces of the gate pad 12, the measurement pad 13, the gate runner 14, the gate resistor 15, and the gate polysilicon layers 16 and 17 face the p-type outer peripheral region 23 and the p-type outer peripheral region 22 through the field oxide film 24 in the depth direction.

[0071] ++ type outer peripheral region 23 and p + type outer peripheral region 22.

[0072] ​Among the source pads 11, the portion 11a intervening between the gate pad 12 and the measurement pad 13 is short-circuited with the gate pad 12 when the gate pad 12 and the measurement pad 13 are short-circuited, enabling detection of a short circuit between the gate pad 12 and the measurement pad 13 even when the MOSFETs 20 of the plurality of semiconductor chips 10 are connected in parallel. The source pad 11 has a relatively large surface area, and a solder material is applied to a location relatively distant from the gate pad 12 and the measurement pad 13, and an external lead wiring (first external member) 32a described later is soldered thereto. Therefore, the possibility of the solder material spreading wetly from the source pad 11 toward the gate pad 12 side and the measurement pad 13 side is low.

[0073] Between the gate pad 12 and the measurement pad 13, it is preferable that the distance d1 between the gate pad 12 and the source pad 11 and the distance d2 between the measurement pad 13 and the source pad 11 are substantially the same. When the gate pad 12, the source pad 11, and the measurement pad 13 are arranged at substantially equal intervals between the gate pad 12 and the measurement pad 13, there are no electrical change points, making it easier to detect abnormal points other than a short circuit between the gate pad 12 and the measurement pad 13. The distance d1 between the gate pad 12 and the source pad 11 may be shorter than the distance d2 between the measurement pad 13 and the source pad 11.

[0074] When the distance d1 between the gate pad 12 and the source pad 11 becomes shorter, a short circuit between the gate pad 12 and the source pad 11 can be induced by the solder material flowing out onto the surface of the passivation film 26 from the gate pad 12 during soldering of the external lead wiring (second external member) 32b to the gate pad 12. Therefore, the detection accuracy of the semiconductor chip 10 in which the gate pad 12 and the measurement pad 13 are short-circuited (hereinafter referred to as the defective chip 10b) is improved. Also, when the distance d2 between the measurement pad 13 and the source pad 11 becomes longer, it becomes difficult for the source pad 11 and the measurement pad 13 to be short-circuited.

[0075] The measurement pad 13 is separated from the gate pad 12 by a distance corresponding to the resistance value of the built-in resistor Rg2 set in the gate resistor 15 connected in series between the gate pad 12 and the measurement pad 13. Also, the measurement pad 13 is preferably separated from the gate pad 12 by a distance of 1 / 2 or less of the width of one side of the semiconductor chip 10. That is, when the gate pad 12 is disposed near the center of a predetermined one side of the outer periphery of the semiconductor chip 10, the measurement pad 13 is disposed between the center of the predetermined one side where the gate pad 12 of the outer periphery of the semiconductor chip 10 is disposed and both end portions of the one side (corner portions (vertices) of the semiconductor chip 10).

[0076] Specifically, the measurement pad 13 is preferably separated from the gate pad 12, for example, within a range of about 50 μm or more and 300 μm or less. Since the distance between the gate pad 12 and the measurement pad 13 is relatively short, it is possible to suppress the rise in the potential of the field oxide film 24 due to the displacement current flowing through the semiconductor chip 10 directly below the gate runner 14 during the switching of the MOSFET 20. Also, the measurement pad 13 is preferably separated from the gate pad 12 by a distance of at least the thicknesses t1, t2 (about 100 μm) of the solder layers 31 described later. Thereby, it becomes difficult for the gate pad 12 and the measurement pad 13 to be short-circuited.

[0077] Before the assembly of the semiconductor module 30 (see FIG. 4), the gate pad 12 and the measurement pad 13 are contacted by a probe needle (not shown), which is a metal contact of an inspection device, in the state of the semiconductor chip 10 as it is during the inspection of the semiconductor chip 10. Examples of the inspection of the semiconductor chip 10 using the gate pad 12 and the measurement pad 13 include measurement of the resistance value of the built-in resistor Rg2 by the gate resistor 15. Since the measurement pad 13 is not used in the product (semiconductor module 30), it may be covered with an insulator after the inspection process of the semiconductor chip 10, but it is preferable to leave the measurement pad 13 exposed to reduce the number of manufacturing processes.

[0078] At the source pad 11 and the gate pad 12, when assembling the semiconductor module 30 (see FIG. 4), one end of the external lead wiring 32 (32a, 32b) is joined via different solder layers 31 (31a, 31b), respectively. The other ends of the external lead wirings 32 (32a, 32b) are exposed outside the case (not shown) of the semiconductor module 30. The external lead wiring 32 is a metal terminal such as a wire or a terminal pin. The external lead wirings 32a, 32b each have a function of taking out the potentials of the source pad 11 and the gate pad 12 to the outside. The external lead wiring 32a is connected to an external ground potential (lowest potential).

[0079] It is preferable that a plating film (not shown) such as nickel (Ni) with high solder wettability is provided over the entire surfaces of the source pad 11 and the gate pad 12 within the openings (first and second openings) 26a, 26b of the passivation film 26. By the plating film, the wetting spread (solder wettability) of the solder layer 31 during solder reflow is improved. The solder layers (first and second metal bonding layers) 31a, 31b are filled within the openings 26a, 26b of the passivation film 26 on the surfaces of the source pad 11 and the gate pad 12, respectively. The surface of the solder layer 31 reaches a position higher than the surface of the passivation film 26. The solder layers 31a, 31b extend onto the surface of the passivation film 26.

[0080] In a semiconductor chip 10 (hereinafter referred to as a good chip 10a) in which the gate pad 12 and the measurement pad 13 do not short-circuit during soldering of the external lead wiring 32b to the gate pad 12, the solder layers 31a and 31b are separated from each other and terminate on the surface of the passivation film 26 (Fig. 2). In this case, the surface areas of the solder layers 31a and 31b are respectively approximately the same as the opening surface areas of the openings 26a and 26b of the passivation film 26, or larger than the opening surface areas of the openings 26a and 26b of the passivation film 26. No external lead wiring is joined to the measurement pad 13. The measurement pad 13 may remain exposed. The portion of the source pad 11 that is exposed inward from the portion where the opening 26a of the passivation film 26 contacts the source pad 11 is defined as the opening surface area of the source pad 11. Similarly, the portion of the gate pad 12 that is exposed inward from the portion where the opening 26b of the passivation film 26 contacts the gate pad 12 is defined as the opening surface area of the gate pad 12. Similarly, the portion of the measurement pad 13 that is exposed inward from the portion where the opening 26c of the passivation film 26 contacts the measurement pad 13 is defined as the opening surface area of the measurement pad 13.

[0081] In a defective chip 10b in which the gate pad 12 and the measurement pad 13 short-circuit during soldering of the external lead wiring 32b to the gate pad 12, the solder layer 31b that has spread wet from above the gate pad 12 to above the measurement pad 13 connects the solder layer 31b on the gate pad 12 and the solder layer 31a on the source pad 11 between the gate pad 12 and the measurement pad 13. In this case, the solder layer 31b terminates on the measurement pad 13 (Fig. 3), or is also filled in the opening 26c of the passivation film 26. The solder layer 31b causes the gate pad 12 and the source pad 11 to short-circuit.

[0082] The semiconductor module 30 shown in FIG. 4 is a MOSFET module in which a plurality of semiconductor chips 10 (see FIGS. 1 to 3) having the same structure are mounted, and MOSFETs 20 respectively fabricated (manufactured) on each semiconductor chip 10 are connected in parallel. The gate pads 12 of each semiconductor chip 10 are connected in parallel by an external lead wiring 32 (see FIGS. 2 and 3), and are electrically connected to the PG (protective ground) 33 of the semiconductor module 30 via the chip resistance Rg4 of the semiconductor chip 10 itself. In each semiconductor chip 10, a parasitic resistance Rg1 due to the gate electrode 56 and a built-in resistance Rg2 due to the gate resistor 15 are connected in series between the PG 33 and the gate electrode 56 of the MOSFET 20.

[0083] The variation in the parasitic resistance Rg1 due to the gate electrode 56 is large in each semiconductor chip 10. Therefore, by adjusting the resistance value of the built-in resistance Rg2 due to the gate resistor 15 added to the semiconductor chip 10, the resistance value of the gate resistance Rg3 of the semiconductor chip 10 determined by the resistance value of the built-in resistance Rg2 is controlled. The semiconductor chips 10 are sorted based on the resistance value of the built-in resistance Rg2 due to the gate resistor 15 measured using the measurement pad 13, and only the semiconductor chips 10 in which the resistance value of the gate resistance Rg3 is within a predetermined range are mounted on the semiconductor module 30. Thereby, the switching variation of the plurality of semiconductor chips 10 connected in parallel in the semiconductor module 30 can be reduced.

[0084] When assembling the semiconductor module 30, the measurement pads 13 of each semiconductor chip 10 are in an exposed state. When solder material wets and spreads from the gate pad 12 onto the measurement pad 13 during soldering of the external lead wiring 32b to the gate pad 12, and the gate pad 12 and the measurement pad 13 are short-circuited via the solder layer 31, the gate pad 12 and the source pad 11 are short-circuited by the solder layer 31 (FIG. 3). Therefore, even if the MOSFETs 20 respectively fabricated on each semiconductor chip 10 are connected in parallel, it is possible to detect the defective chip 10b in which the gate pad 12 and the measurement pad 13 are at the same potential.

[0085] The operation of the semiconductor device 20-1 mounted on the semiconductor module 30 will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 56 while a positive voltage is applied to the drain electrode 18 with respect to the source electrode 59, in the p-type base region 51, n + a channel (n-type inversion layer) is formed along the side wall of the trench 54 in the region between the n ++ type source region 52 and the n-type current diffusion region 58. As a result, from the n - type drain region 27, a drift current (main current) flows through the n + type drift region 21, the n-type current diffusion region 58, and the channel toward the n

[0086] type source region 52, and the MOSFET 20 turns on. + On the other hand, when the applied voltage to the gate electrode 56 is less than the gate threshold voltage while a positive voltage is applied to the drain electrode 18 with respect to the source electrode 59, the pn junctions (main junctions) between the p-type base region 51 and the p - type region 57 and the n-type current diffusion region 58 and the n

[0087] type drift region 21 are reverse-biased, so the MOSFET 20 maintains the off state. As the depletion layer spreads longitudinally (toward the source electrode 59 side and the drain electrode 18 side) within the active region from the pn junction, and spreads laterally from the active region toward the inactive region and the edge termination region 2, a predetermined breakdown voltage is ensured. + During the period when the MOSFET 20 transitions from on to off, the parasitic pn junction diode (body diode) formed by the pn junctions between the p-type base region 51, the p + type region 57, and the p - type outer peripheral region 22, and the n-type current diffusion region 58 and the n - type drift region 21 conducts in the forward direction, and carriers (holes and electrons) are injected and accumulated in the n - type drift region 21. When the MOSFET 20 turns off (the body diode undergoes reverse recovery) from this state, the holes in the n +It flows into the outer peripheral region 22 and is discharged to the source electrode 59, and the MOSFET 20 is turned off.

[0088] Since the distance between the gate pad 12 and the measurement pad 13 is relatively short, it is possible to suppress the potential rise of the field oxide film 24 due to the displacement current flowing during the period when the MOSFET 20 transitions from on to off. Further, in the semiconductor module 30, only the semiconductor chip 10 in which the resistance value of the gate resistor Rg3 is within a predetermined range is mounted, and the switching variation of the plurality of semiconductor chips 10 connected in parallel within the semiconductor module 30 is reduced. Further, among the semiconductor chips 10 mounted on the semiconductor module 30, it is possible to detect a defective chip 10b in which the gate pad 12 and the measurement pad 13 are short-circuited.

[0089] As described above, according to the first embodiment, a part of the source pad is interposed between the gate pad and the measurement pad. When the gate pad and the measurement pad are short-circuited by the solder material flowing out from above the gate pad during the soldering of the external lead wiring to the gate pad in the assembly process of the semiconductor module, the gate pad and the source pad are short-circuited. For this reason, among the semiconductor chips mounted on the semiconductor module and connected in parallel, it is possible to detect a defective chip in which the gate pad and the measurement pad are at the same potential. Therefore, it is possible to prevent the outflow of the product (semiconductor module) in which the defective chip is mounted.

[0090] Further, according to the first embodiment, since a short circuit between the gate pad and the measurement pad can be reliably detected, the gate pad and the measurement pad can be arranged close to each other. As a result, it is possible to increase the overall gate resistance value of the MOSFET and improve the breakdown tolerance against the displacement current during switching of the MOSFET.

[0091] (Details of the Second Embodiment) Next, a semiconductor device and a semiconductor module according to Embodiment 2 for solving the above-described problems will be described. FIG. 5 is a plan view showing a layout example of a semiconductor chip mounted on the semiconductor module according to Embodiment 2 as viewed from the front side. The semiconductor module according to Embodiment 2 is the same as that obtained by replacing reference numeral 13 in FIG. 4 with reference numeral 62. In the semiconductor device 20-2 according to Embodiment 2, the planar shape of the source pad 61 and the arrangement of the measurement pad 62 are different from those of the semiconductor device 20-1 (see FIGS. 1 to 3) according to Embodiment 1.

[0092] In Embodiment 2, a portion of the source electrode 59 (see FIGS. 2 and 3) of the MOSFET 20 that is exposed at the opening 26d of the passivation film 26 functions as the source pad 61. The source pad 61, the gate pad 12, and the measurement pad 62 are respectively exposed at different openings 26d, 26b, and 26e of the passivation film 26 and are arranged apart from each other. The source pad 61 has a substantially rectangular planar shape with a part recessed so as to surround the periphery of the gate pad 12, and surrounds three sides around the gate pad 12. A part 61a of the source pad 61 is interposed between the gate pad 12 and the measurement pad 62.

[0093] The gate pad 12 is arranged near the center of a predetermined one side of the outer periphery of the active region 1 near the outer periphery of the active region 1. The measurement pad 62 is arranged at a corner portion close to the gate pad 12 among the four corner portions (vertices) of the active region 1. The source pad 61 is arranged so as to overlap as much as possible on a straight path from the gate pad 12 to the measurement pad 62 as viewed from the front side of the semiconductor chip 10. The configuration other than the planar shape of the source pad 61 is the same as that of the source pad 11 (including the structure of the MOSFET 20) in Embodiment 1. The configuration other than the arrangement of the measurement pad 62 is the same as that of the measurement pad 13 in Embodiment 1.

[0094] Even if the distance between the gate pad 12 and the measurement pad 62 is made sufficiently large, there is a risk that the gate pad 12 and the measurement pad 13 may be short-circuited due to the attachment of conductive foreign matter (not shown). Even if the gate pad 12 and the measurement pad 13 are short-circuited due to the attachment of conductive foreign matter, it is possible to induce a short circuit between the gate pad 12 and the source pad 11 by the attached matter between the gate pad 12 and the measurement pad 13. For this reason, even in a configuration where the distance between the gate pad 12 and the measurement pad 62 is large, it is possible to detect the defective chip 10b in which the gate pad 12 and the measurement pad 62 are short-circuited.

[0095] As described above, according to the second embodiment, even in a configuration where the distance between the gate pad and the measurement pad is large, the breakdown tolerance against the displacement current during switching of the MOSFET slightly decreases, but the same effect as in the first embodiment can be obtained.

[0096] As described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. For example, as a bonding material used for bonding the external lead-out wiring to the source pad and the gate pad, a metal sintered material such as silver (Ag) nanosinter may be used instead of the solder material. Further, instead of the trench gate structure, a planar gate structure may be provided. Electrode pads other than the source pad, the gate pad, and the measurement pad may be arranged on the front surface of the semiconductor chip. The semiconductor material of the semiconductor chip may be silicon (Si).

Industrial Applicability

[0097] As described above, the semiconductor device and the semiconductor module according to the present disclosure are useful for power semiconductor modules used in power supply devices such as power conversion devices and various industrial machines.

Explanation of Signs

[0098] 1,101 Active region 2,102 Edge termination region 10,110 Semiconductor chip 10a, 110a Good chip 10b, 110b Defective chip 11, 61, 111 Source pad 11a, 61a Part of the source pad between the gate pad and the measurement pad 12, 112 Gate pad 13, 62, 113 Measurement pad 14, 114 Gate runner 15, 115 Gate resistor 16, 17 Gate polysilicon layer 18 Drain electrode 20-1, 20-2, 120-1, 120-2 Semiconductor device 21, 121 n - -type drift region 22 p + -type peripheral region 23 p ++ -type peripheral region 24, 123 Field oxide film 25 Interlayer insulating film 26, 124 Passivation film 26a~26e, 124a~124c Openings in the passivation film 27 n + -type drain region 30, 130 Semiconductor module 31, 31a, 31b, 131 Solder layer 32, 32a, 32b, 132 Wiring for external connection 41 n + -type starting substrate 42, 43 Epitaxial layer 51 p-type base region 52 n + -type source region 53 p ++ -type contact region 54 Trench 55 Gate insulating film 56, 125 Gate electrode 57 p + -type region 58 n-type current diffusion region 59 Source electrode 122 p-type region d1 Distance between gate pad and source pad d2 Distance between measurement pad and source pad t1, t2 Thickness of solder layer

Claims

1. A semiconductor device comprising an insulating gate having a three-layer structure of a metal film - an oxide film - a semiconductor provided on a semiconductor substrate, a main electrode pad provided on a first main surface of the semiconductor substrate and to which a first external member for conducting the semiconductor device is metal-bonded, a gate pad provided on the first main surface of the semiconductor substrate via an insulating film, a gate runner provided on the first main surface of the semiconductor substrate via the insulating film and having a gate electrode, which is the metal film of the insulating gate, electrically connected thereto, a gate resistor provided on the first main surface of the semiconductor substrate via the insulating film and electrically connecting the gate pad and the gate runner, a measurement pad provided on the first main surface of the semiconductor substrate via the insulating film and electrically connected to the gate runner for measuring the resistance value of the gate resistor, and comprising, a semiconductor device, characterized in that a part of the main electrode pad is interposed between the gate pad and the measurement pad in a plan view.

2. The semiconductor device according to claim 1, characterized in that a second external member is metal-bonded to the gate pad.

3. The semiconductor device according to claim 1, characterized in that the surface area of a first metal bonding layer for bonding the main electrode pad and the first external member in a plan view is larger than the opening surface area of the main electrode pad.

4. Comprising a passivation film covering the first main surface of the semiconductor substrate, the main electrode pad being exposed in a first opening of the passivation film, the semiconductor device according to claim 1, characterized in that a first metal bonding layer for bonding the main electrode pad and the first external member is filled in the first opening and extends on the surface of the passivation film.

5. The semiconductor device according to claim 2, characterized in that the surface area of a second metal bonding layer for bonding the gate pad and the second external member in a plan view is larger than the opening surface area of the gate pad.

6. Comprising a passivation film covering the first main surface of the semiconductor substrate, the gate pad being exposed in a second opening of the passivation film, the semiconductor device according to claim 2, characterized in that a second metal bonding layer for bonding the gate pad and the second external member is filled in the second opening and extends on the surface of the passivation film.

7. The semiconductor device according to claim 3, characterized in that the first metal bonding layer is made of a solder material or a metal sintered material.

8. The semiconductor device according to claim 5, wherein the second metal bonding layer is made of a solder material or a metal sintered material.

9. The first metal bonding layer is made of a solder material, The semiconductor device according to claim 3, wherein the main electrode pad is bonded to the first metal bonding layer via a plating film.

10. The second metal bonding layer is made of a solder material, The semiconductor device according to claim 5, wherein the gate pad is bonded to the second metal bonding layer via a plating film.

11. A semiconductor module mounting the semiconductor device according to any one of claims 1 to 9, A plurality of the semiconductor elements are mounted, The plurality of semiconductor elements are connected in parallel to each other, A semiconductor module, wherein the first external member is metal-bonded to the main electrode pads of the plurality of semiconductor elements, respectively.

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