Semiconductor device

Abstract

To improve an aperture ratio of a semiconductor device.SOLUTION: A semiconductor device is provided in which a pixel portion including a first thin film transistor and a driver circuit including a second thin film transistor are provided over one substrate. The thin film transistor of the pixel portion includes: a gate electrode layer; a gate insulation layer; an oxide semiconductor layer having a thin film thickness in a peripheral edge; an oxide insulation layer that is in contact with one part of the oxide semiconductor layer; a source electrode layer and a drain electrode layer; and a pixel electrode layer. Each of the gate electrode layer, the gate insulation layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulation layer, and a pixel electrode layer, of the first thin film transistor has a light transmissivity. The source electrode layer and the drain electrode layer of the thin film transistor of the driver circuit are covered with a protection insulation layer and made of a conductive material of which a resistance is lower than that of the source electrode layer and the drain electrode layer of the pixel portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Metal oxides having light transmitting properties are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as indium tin oxide (ITO) (hereafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides that have light-transmitting properties are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected that this technology will be applied to the channel layer of a FT (fiber-transistor-type thin-film transistor).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina, which is used in display devices, etc. There is growing expectation that this material will replace or surpass rufus silicon.

[0006] In addition, a TFT is formed using a light-transmitting oxide conductor and an oxide semiconductor. This makes it possible to fabricate a light-transmitting TFT (see, for example, Non-Patent Document 1).

[0007] In addition, a TFT using an oxide semiconductor for the channel layer has a high field-effect mobility. Therefore , it is also possible to configure a drive circuit such as a display device using the TFT (for example, see Non-Patent Document 2). ).

Prior Art Documents

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] One aspect of the present invention aims to reduce the manufacturing cost of a semiconductor device as one of the problems.

[0010] One aspect of the present invention aims to improve the aperture ratio of a semiconductor device as one of the problems.

[0011] One aspect of the present invention aims to enhance the definition of an image displayed on a display portion of a semiconductor device as one of the problems .

[0012] One aspect of the present invention aims to provide a semiconductor device capable of high-speed driving as one of the problems.

Means for Solving the Problems

[0013] One aspect of the present invention has a drive circuit portion and a display portion (also referred to as a pixel portion) on the same substrate, and the drive circuit portion includes a source electrode (also referred to as a source electrode layer) and a drain electrode (drain electrode A driving circuit thin film transistor in which a layer (also referred to as a layer) is made of a metal and a semiconductor layer is made of an oxide semiconductor, and a wiring for a driving circuit made of a metal. The display portion has a pixel thin film transistor in which a source electrode layer and a drain electrode layer are made of an oxide conductor and a semiconductor layer is made of an oxide semiconductor, and a wiring for a display portion made of an oxide conductor. A semiconductor device having a driving circuit thin film transistor composed of a metal and a wiring for a driving circuit composed of a metal. The display portion has a pixel thin film transistor in which a source electrode layer and a drain electrode layer are made of an oxide conductor and a semiconductor layer is made of an oxide semiconductor, and a wiring for a display portion made of an oxide conductor. A semiconductor device having a pixel thin film transistor in which a source electrode layer and a drain electrode layer are made of an oxide conductor and a semiconductor layer is made of an oxide semiconductor, and a wiring for a display portion made of an oxide conductor. A semiconductor device having a pixel thin film transistor in which a source electrode layer and a drain electrode layer are made of an oxide conductor and a semiconductor layer is made of an oxide semiconductor, and a wiring for a display portion made of an oxide conductor.

[0014] As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer. As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer. As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer. As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer. As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer. As the pixel thin film transistor and the driving circuit thin film transistor, an inverted staggered type thin film transistor having a bottom gate structure is used. The pixel thin film transistor is a channel protection type (channel stop type) thin film transistor in which a channel protection layer is provided on a channel formation region of a semiconductor layer, while the driving circuit thin film transistor is a channel etch type thin film transistor in which an oxide insulating film in contact with the semiconductor layer is provided in a region between a source electrode layer and a drain electrode layer.

[0015] In addition, Non-Patent Document 1 does not disclose a specific manufacturing process of a TFT and the structure of other elements (for example, a capacitor element, etc.) constituting a semiconductor device. Also, there is no description of manufacturing a driving circuit and a light-transmissive TFT on the same substrate. In addition, Non-Patent Document 1 does not disclose a specific manufacturing process of a TFT and the structure of other elements (for example, a capacitor element, etc.) constituting a semiconductor device. Also, there is no description of manufacturing a driving circuit and a light-transmissive TFT on the same substrate. In addition, Non-Patent Document 1 does not disclose a specific manufacturing process of a TFT and the structure of other elements (for example, a capacitor element, etc.) constituting a semiconductor device. Also, there is no description of manufacturing a driving circuit and a light-transmissive TFT on the same substrate.

[0016] A semiconductor device according to an aspect of the present invention has a driving circuit portion having a driving circuit TFT and a display portion having a pixel TFT manufactured on the same substrate. Therefore, the manufacturing cost of the semiconductor device can be reduced. A semiconductor device according to an aspect of the present invention has a driving circuit portion having a driving circuit TFT and a display portion having a pixel TFT manufactured on the same substrate. Therefore, the manufacturing cost of the semiconductor device can be reduced. A semiconductor device according to an aspect of the present invention has a driving circuit portion having a driving circuit TFT and a display portion having a pixel TFT manufactured on the same substrate. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0017] Further, a semiconductor device according to an aspect of the present invention has a source electrode and a drain electrode made of an oxide in the display portion. A pixel TFT composed of a conductor and having a semiconductor layer made of an oxide semiconductor, and a wiring for a display portion composed of an oxide conductor. That is, the semiconductor device can have a region where the pixel TFT and the wiring for the display portion are formed as a display region of the pixel portion. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] Also, a semiconductor device according to one aspect of the present invention has, in a display portion, a pixel TFT in which a source electrode and a drain electrode are made of an oxide conductor and a semiconductor layer is made of an oxide semiconductor, and a wiring for a display portion composed of an oxide conductor. That is, the semiconductor device can design the pixel size without being limited by the size of the pixel TFT. Therefore, the image displayed on the display portion of the semiconductor device can be made high-definition.

[0019] Also, a semiconductor device according to one aspect of the present invention has, in a drive circuit portion, a drive circuit TFT in which a source electrode and a drain electrode are made of a metal and a channel layer is made of an oxide semiconductor, and a wiring for a drive circuit made of a metal. That is, the semiconductor device has a drive circuit configured by a TFT showing a high field-effect mobility and a wiring with low resistance. Therefore, the semiconductor device can be made a semiconductor device capable of high-speed driving.

[0020] Also, the oxide semiconductor used in this specification forms a thin film represented by InMO 3 (ZnO) m (m>0), and manufactures a thin film transistor using the thin film as an oxide semiconductor layer. Note that M is one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. It represents a metal element. For example, as M, it may be Ga, and in addition, the above metal elements other than Ga such as Ga and Ni or Ga and Fe may be included. Also, in the above oxide semiconductor, in addition to the metal element included as M, impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals are included in some cases. In this specification, In MO MO 3 (ZnO) m (m>0), among the oxide semiconductor layers having the structure represented by, the oxide semiconductor having a structure containing Ga as M is referred to as an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an I n-Ga-Zn-O-based non-single crystal film.

[0021] In addition to the above, as the metal oxide applied to the oxide semiconductor layer, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In- O system, Sn-O system, Zn-O system metal oxides can be applied. Also, silicon oxide may be included in the oxide semiconductor layer composed of the above metal oxide. By including silicon oxide (SiOx (X>0)) that inhibits crystallization in the oxide semiconductor layer, it is possible to suppress crystallization when heat treatment is performed after the formation of the oxide semiconductor layer during the manufacturing process. Note that the oxide semiconductor layer is preferably in an amorphous state, and may be partially crystallized .

[0022] The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. Dehydration or dehydrogenation is effective for making the oxide semiconductor layer of type I (intrinsic).

[0023] In an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure By performing heat treatment on the oxide semiconductor layer, the oxide semiconductor layer is made oxygen-deficient to reduce its resistance, That is, it is made N-type (N - doping, etc.), and then, by forming an oxide insulating film in contact with the oxide semiconductor layer The oxide semiconductor layer is made oxygen-rich to increase its resistance, that is, it is made I-type doped. Thereby, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0024] As the heat treatment for dehydration or dehydrogenation, for example, in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure, a heat treatment at 350 °C or higher, preferably 400 °C or higher and below the strain point of the substrate is performed. By this heat treatment, the oxide semiconductor layer is dehydrated or dehydrogenated, and impurities containing hydrogen such as the contained moisture in the oxide semiconductor layer are reduced.

[0025] The heat treatment for dehydration or dehydrogenation is preferably carried out under heat treatment conditions such that when measured by thermal desorption spectroscopy (hereinafter referred to as TDS) up to 450 °C for the oxide semiconductor layer after dehydration or dehydrogenation, no two peaks of water or at least one peak appearing around 300 °C are detected. Even when TDS measurement is performed up to 450 °C for the thin film transistor using the oxide semiconductor layer on which the heat treatment for dehydration or dehydrogenation has been carried out under these conditions, no peak of water appearing around at least 300 °C is detected.

[0026] ​​​​​​​​Cooling after heating is performed using the same furnace that has undergone dehydration or dehydrogenation, and the cooling is carried out without exposing it to the atmosphere to prevent the oxide semiconductor layer from coming into contact with water or hydrogen. Heat treatment for dehydration or dehydrogenation is performed to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (N - doping, etc.). After that, when a thin film transistor is fabricated using an oxide semiconductor layer that has been made highly resistive to form an I-type, the threshold voltage value of the thin film transistor can be made positive, and a so-called normally-off switch element can be realized. It is desirable for the display device that the channel is formed at a threshold voltage where the gate voltage of the thin film transistor is as close to 0V as possible. Note that if the threshold voltage value of the thin film transistor is negative, a current easily flows between the source electrode and the drain electrode even when the gate voltage is 0V, resulting in a so-called normally-on state. In an active matrix type display device, the electrical characteristics of the thin film transistors that make up the circuit are important, and this electrical characteristic affects the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as a TFT cannot be achieved in a state where the driving voltage is low, and there is a risk of becoming a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only after a positive voltage is applied to the gate voltage. A transistor that does not form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state In the display device, the electrical characteristics of the thin film transistors that make up the circuit are important, and this electrical characteristic affects the performance of the display device. In particular, among the electrical characteristics of the thin film transistor, the threshold voltage is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it is difficult to control as a circuit. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, the driving voltage is low and the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only after a positive voltage is applied to the gate voltage. A transistor that does not form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, the driving voltage is low and the switching function as a TFT cannot be achieved, and there is a risk of becoming a load. In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only after a positive voltage is applied to the gate voltage. A transistor that does not form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only after a positive voltage is applied to the gate voltage. A transistor that does not form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state is not desirable. When a positive voltage is applied to the gate voltage, a channel is formed and a drain current flows A transistor that does not form a channel unless the driving voltage is increased, or a transistor in which a channel is formed even in a negative voltage state A transistor formed to allow a drain current to flow is not suitable as a thin film transistor used in a circuit. It is unsuitable.

[0027] Also, the cooling after heating may be performed after switching the temperature-rising gas atmosphere to a different gas. For example, without exposing to the atmosphere in the same furnace where the heat treatment for dehydration or dehydrogenation has been performed, the inside of the furnace may be filled with high-purity oxygen gas or N 2 2O gas, ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) and cooled.

[0028] After reducing impurities containing hydrogen such as the contained moisture in the film by the heat treatment for dehydration or dehydrogenation, using an oxide semiconductor film slowly cooled (or cooled) under an atmosphere not containing moisture (dew point of -40°C or lower, preferably -60°C or lower ), the electrical characteristics of the thin film transistor are improved, and a thin film transistor having both mass productivity and high performance is realized. While improving the electrical characteristics of the thin film transistor, a thin film transistor having both mass productivity and high performance is realized.

[0029] In this specification, the heat treatment under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure is called the heat treatment for dehydration or dehydrogenation. In this specification, not only desorbing as H 2 by this heat treatment, but also including desorbing H, OH, etc. is conveniently called dehydration or dehydrogenation. For convenience, it is called dehydration or dehydrogenation including desorbing H, OH, etc.

[0030] When the heat treatment is performed under an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or under reduced pressure, the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and has a lower resistance, that is, it becomes N-type (N - -type, etc.). As a result, an oxygen-deficient type region overlaps with the drain electrode layer. In this way, a high-resistance drain region (also called an HRD region) is formed.

[0031] Specifically, the carrier concentration in the high-resistance drain region is 1×10 17 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 17 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0032] In addition, a low-resistance drain region (L Specifically, the carrier concentration of the low-resistance drain region may be is larger than the high resistance drain region (HRD region), for example, 1×10 20 / cm 3 End 1×10 21 / cm 3 It is within the following range.

[0033] Then, at least a part of the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is By making the material oxygen-rich, the resistance is increased, that is, the material is made I-type, and a channel formation region is formed. Note that the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is heated in an oxygen-excess state. As a treatment for the above-mentioned state, a heat treatment for dehydration or dehydrogenation is performed on an oxide semiconductor layer. A contact oxide insulating film is formed by sputtering, or heating is performed for dehydration or dehydrogenation. An oxide insulating film is formed so as to be in contact with the treated oxide semiconductor layer, and heat treatment is further performed. Alternatively, the oxide semiconductor layer that has been subjected to heat treatment for dehydration or dehydrogenation is treated to include oxygen. Oxides that are heat-treated in an inert atmosphere or heat-treated for dehydration or dehydrogenation Heat the semiconductor layer in an inert gas atmosphere and then perform a cooling treatment in an oxygen atmosphere. Also Heat the oxide semiconductor layer that has been heat-treated for dehydration or dehydrogenation in an inert gas atmosphere And then cool it with ultra-dry air (dew point of -40 °C or lower, preferably -60 °C or lower). Examples of such treatments include

[0034] In addition, in order to make at least a part of the oxide semiconductor layer that has been heat-treated for dehydration or dehydrogenation (the part that overlaps with the gate electrode (also referred to as the gate electrode layer)) the channel formation region, by selectively making it in an oxygen-excess state, it is also possible to increase the resistance, that is, to make it into the I-type. On the oxide semiconductor layer that has been heat-treated for dehydration Or dehydrogenation, a source electrode layer or a drain electrode layer made of a metal such as Ti is formed in contact with it, and a region that does not overlap with the source electrode layer or the drain electrode layer is selectively made in an oxygen-excess state to form the channel formation region. When selectively making it in an oxygen-excess state, a first high-resistance drain region that overlaps with the source electrode layer and A second high-resistance drain region that overlaps with the drain electrode layer are formed, and the region between the first high-resistance drain region and the second high-resistance drain region becomes the channel formation region. That is, the channel Formation region is formed self-aligned between the source electrode layer and the drain electrode layer. In this way, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Note that in the oxide semiconductor layer that overlaps with the drain electrode layer (and the source electrode layer), the high-resistance drain Region Region Region

[0035] By this, it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Region

[0036] Note that in the oxide semiconductor layer that overlaps with the drain electrode layer (and the source electrode layer), the high-resistance drain By forming a rain region, it is possible to improve the reliability when forming a drive circuit. Specifically, by forming a high-resistance drain region, a structure can be achieved in which the conductivity can be changed stepwise from the drain electrode layer to the high-resistance drain region and the channel formation region. Therefore, when the drain electrode layer is connected to a wiring for supplying a high power supply potential VDD and operated, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and a configuration can be achieved in which the breakdown voltage of the transistor is improved. Also, a low-resistance drain region (also referred to as an LRN region) may be formed between the drain electrode layer (and the source electrode layer) made of a metal material and the oxide semiconductor layer. By forming the low-resistance drain region (also referred to as an L RN region), a configuration can be achieved in which the breakdown voltage of the transistor is further improved. Moreover, by forming a high-resistance drain region in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer), it is possible to reduce the leakage

[0037] current in the channel formation region when forming a drive circuit. Specifically, by forming a high-resistance drain region, as a path of the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer, the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the high-resistance drain region on the source electrode layer side, and the source electrode layer are in this order. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is concentrated near the interface between the gate insulating layer, which becomes high-resistance when the transistor is off, and the channel formation region.

[0038] Also, by forming a high-resistance drain region in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer), it is possible to reduce the leakage current in the channel formation region when forming a drive circuit. Specifically, by forming a high-resistance drain region, as a path of the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer, the drain electrode layer, the high-resistance drain region on the drain electrode layer side, the channel formation region, the high-resistance drain region on the source electrode layer side, and the source electrode layer are in this order. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is concentrated near the interface between the gate insulating layer, which becomes high-resistance when the transistor is off, and the channel formation region. layer side, and the source electrode layer are in this order. At this time, in the channel formation region, the leakage current flowing from the high-resistance drain region on the drain electrode layer side to the channel formation region is concentrated near the interface between the gate insulating layer, which becomes high-resistance when the transistor is off, and the channel formation region. than the high-resistance drain region on the drain electrode layer side, and concentrated near the interface between the gate insulating layer, which becomes high-resistance when the transistor is off, and the channel formation region. ​​​ can be achieved, and the leakage current in the back channel portion (a part of the surface of the channel formation region away from the gate electrode layer) can be reduced.

[0039] Also, by forming the first high-resistance drain region overlapping the source electrode layer and the second high-resistance drain region overlapping the drain electrode layer so as to overlap via a part of the gate electrode layer and the gate insulating layer, the electric field strength near the end of the drain electrode layer can be more effectively relaxed.

[0040] Further, by adopting a configuration having a low-resistance drain region between the source electrode layer and the drain electrode layer and the oxide semiconductor layer, it has a thermally stable operation compared to a Schottky junction. The low-resistance drain region has a lower resistance than the oxide semiconductor layer and uses an oxide conductive layer having a higher resistance than the source electrode layer and the drain electrode layer, so that the contact resistance between the oxide semiconductor layer and the source electrode layer or the drain electrode layer can be reduced.

[0041] One form of the configuration of the invention disclosed in this specification has a pixel portion having a first thin-film transistor and a driving circuit having a second thin-film transistor on the same substrate. The first thin-film transistor has a gate electrode layer on the substrate, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer having a thin region with a thin film thickness at the periphery on the gate insulating layer, an oxide insulating layer in contact with a part of the oxide semiconductor layer, a source electrode layer and a drain electrode layer on the oxide insulating layer and the oxide semiconductor layer, and a pixel electrode layer electrically connected to the source electrode layer or the drain electrode layer. The gate electrode layer, gate insulating layer, oxide semiconductor layer, source electrode layer, drain electrode layer, and oxide of the first thin-film transistor The oxide insulating layer and the pixel electrode layer have translucency, and the source electrode layer and the drain electrode layer of the second thin film transistor are covered with a protective insulating layer, and the source electrode layer and the drain electrode layer of the first thin film transistor are made of a conductive material having a lower resistance than the source electrode layer and the drain electrode layer of the first thin

[0042] film transistor, and is a semiconductor device. Further, in the semiconductor device described above, between the oxide semiconductor layer of the second thin film transistor and the source electrode layer and the drain electrode layer, there may be a low resistance

[0043] drain region made of the same material as the source electrode layer and the drain electrode layer of the first thin film transistor. Further, in the semiconductor device described above, between the oxide semiconductor layer of the second thin film transistor and the source electrode layer and the drain electrode layer, there is a low resistance drain

[0044] region, and the end portion of the oxide semiconductor layer protrudes from the end surface of the low resistance drain region and may have the same thickness as the thickness of the channel formation region of the second thin film transistor.

[0045] Further, in the semiconductor device described above, at least one of the oxide semiconductor layers of the first or second thin film transistor may have a high resistance drain region that is lower in resistance than the channel formation region at a position overlapping the source electrode layer or the drain electrode layer.

[0046] In the above semiconductor device, the source electrode layer and drain electrode layer of the first thin film transistor, and the pixel electrode layer are preferably made of indium oxide, indium tin oxide alloy, indium zinc oxide alloy, or zinc oxide. The source electrode layer, drain electrode layer, and pixel electrode layer are preferably made of indium oxide, indium tin oxide alloy, indium zinc oxide alloy, or zinc oxide.

[0047] In the above semiconductor device, a capacitor portion is further provided on the same substrate. The capacitor portion has a capacitor wiring and a capacitor electrode overlapping the capacitor wiring, and the capacitor wiring and the capacitor electrode may be translucent. In the above semiconductor device, a capacitor portion is further provided on the same substrate. The capacitor portion has a capacitor wiring and a capacitor electrode overlapping the capacitor wiring, and the capacitor wiring and the capacitor electrode may be translucent.

[0048] In the above semiconductor device, the oxide semiconductor layer of the second thin film transistor has a channel formation region that is thinner than the region overlapping the source electrode layer or the drain electrode layer, and a conductive layer may be provided on the channel formation region via a protective insulating layer. In the above semiconductor device, the oxide semiconductor layer of the second thin film transistor has a channel formation region that is thinner than the region overlapping the source electrode layer or the drain electrode layer, and a conductive layer may be provided on the channel formation region via a protective insulating layer.

[0049] One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer One form of the configuration of the invention disclosed in this specification is to form a first gate electrode layer and a second gate electrode layer on the same substrate, form a gate insulating layer on the first gate electrode layer and the second gate electrode layer, form an oxide semiconductor film on the gate insulating layer, perform a heat treatment for dehydration or dehydrogenation of the oxide semiconductor film, and then, in order to prevent the oxide semiconductor film from coming into contact with water or hydrogen, without exposing it to the atmosphere, form first and second low-resistance drain regions on the first oxide semiconductor layer, the second oxide semiconductor layer, and the second oxide semiconductor layer, form a second source electrode layer and a second drain electrode layer on the first and second low-resistance drain regions respectively, form a second oxide insulating layer that is in contact with a part of the second oxide semiconductor layer and is in contact with the upper surface and side surfaces of the second source electrode layer and the second drain electrode layer, and the first gate electrode layer of the first oxide semiconductor layer ​​​A first oxide insulating layer is formed in a region overlapping therewith, and a first source electrode layer and a first drain electrode layer are formed on the first oxide semiconductor layer and the first oxide insulating layer. A protective insulating layer is formed on the first oxide insulating layer, the first source electrode layer, the first drain electrode layer, and the second oxide insulating layer. A pixel electrode layer electrically connected to the first drain electrode layer or the first source electrode layer and a conductive layer overlapping the second oxide semiconductor layer are formed. This is a method for manufacturing a semiconductor device. On the first oxide insulating layer, the first source electrode layer and the first drain electrode layer are formed. A protective insulating layer is formed on the first oxide insulating layer, the first source electrode layer, the first drain electrode layer, and the second oxide insulating layer. On the protective insulating layer, a pixel electrode layer electrically connected to the first drain electrode layer or the first source electrode layer and a conductive layer overlapping the second oxide semiconductor layer are formed. This is a method for manufacturing a semiconductor device.

[0050] In the above configuration, the oxide semiconductor layer of the second thin film transistor may have a region with a thickness thinner than the region overlapping the source electrode layer or the drain electrode layer. Also, the oxide semiconductor layer of the second thin film transistor may have a channel formation region with a thickness thinner than the region overlapping the source electrode layer or the drain electrode layer, and may have a structure in which a conductive layer is provided thereon via a second oxide insulating layer. The oxide semiconductor layer of the second thin film transistor may have a region with a thickness thinner than the region overlapping the source electrode layer or the drain electrode layer. The oxide semiconductor layer of the second thin film transistor may have a region with a thickness thinner than the region overlapping the source electrode layer or the drain electrode layer. The oxide semiconductor layer of the second thin film transistor may have a channel formation region with a thickness thinner than the region overlapping the source electrode layer or the drain electrode layer, and may have a structure in which a conductive layer is provided thereon via a second oxide insulating layer.

[0051] Since the first oxide insulating layer and the second oxide insulating layer can be formed in the same process, an insulating material having the same light transmittance can be used.

[0052] Note that the ordinal numbers attached as first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate unique names for matters specific to identifying the invention in this specification. Note that the ordinal numbers attached as first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate unique names for matters specific to identifying the invention in this specification.

[0053] In addition, as a display device having a driving circuit, in addition to a liquid crystal display device, a display device using a light-emitting element, and a display device also called an electronic paper using an electrophoretic display element can be mentioned. In addition to a liquid crystal display device, a display device using a light-emitting element, and a display device also called an electronic paper using an electrophoretic display element can be mentioned.

[0054] ​​​​​In a light-emitting display device using a light-emitting element, a plurality of thin-film transistors are provided in a pixel portion, and there is a portion in the pixel portion where the gate electrode of a certain thin-film transistor is connected to the source wiring (also referred to as a source wiring layer) of another transistor, or the drain wiring (also referred to as a drain wiring layer). Also, in the drive circuit of a light-emitting display device using a light-emitting element, there is a portion where the gate electrode of a thin-film transistor is connected to the source wiring or the drain wiring of that thin-film transistor. In the pixel portion, there is also a location where the gate electrode of a certain thin-film transistor is connected to the source wiring (also referred to as the source wiring layer) of another transistor, or the drain wiring (also referred to as the drain wiring layer). section. In addition, in the drive circuit of a light-emitting display device using a light-emitting element, there is a location where the gate electrode of a thin-film transistor is connected to the source wiring or the drain wiring of that thin-film transistor. section. location.

Effect of the Invention

[0055] According to one aspect of the present invention, a thin-film transistor having stable electrical characteristics can be manufactured and provided. Therefore, a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability can be provided. Therefore, a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability can be provided. device can be provided.

Brief Description of the Drawings

[0056]

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Embodiments for Carrying Out the Invention

[0057] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. be easily understood. Also, the present invention is not construed as being limited to the description of the embodiments shown below. be construed as being limited to the description of the embodiments shown below.

[0058] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 3. FIGS. 1(B) and (C) show an example of the cross-sectional structure of two thin-film transistors having different structures fabricated on the same substrate. The thin-film transistor 460 shown in FIG. 1 is one of the bottom-gate structures called the channel-etch type, and the thin-film transistor 470 is one of the bottom-gate structures called the channel-protection type (also referred to as the channel-stop type). The thin-film transistor 460 and the thin-film transistor 470 are also referred to as reverse staggered thin-film transistors. transistor 470 are also referred to as reverse staggered thin-film transistors. transistor 470 are also referred to as reverse staggered thin-film transistors. transistor 470 are also referred to as reverse staggered thin-film transistors.

[0059] FIG. 1(A1) is a plan view of the thin-film transistor 460 arranged in the drive circuit, and FIG. 1(A 2) is a plan view of the thin-film transistor 470 arranged in the pixel portion. Also, FIG. 1(B) is a cross-sectional view taken along line G1-G2 of FIG. 1(A1) and line H1-H2 of FIG. 1(A2). Also FIG. 1(C) is a cross-sectional view taken along line G3-G4 of FIG. 1(A1) and line H3-H4 of FIG. 1(A2). is a cross-sectional view taken along line G3-G4 of FIG. 1(A1) and line H3-H4 of FIG. 1(A2).

[0060] The thin film transistor 460 disposed in the drive circuit is a channel etch type thin film transistor, and on a substrate 450 having an insulating surface, a gate electrode layer 461, a first gate insulating layer 45 2a, a second gate insulating layer 452b, at least a channel formation region 463, a first high resistance drain region 464a, and a second high resistance drain region 464b are included in the oxide semiconductor layer 462, a first low resistance drain region 408a, a second low resistance drain region 408b, a source electrode layer 465a, and a drain electrode layer 465b. Further, an oxide insulating layer 466 that covers the thin film transistor 460 and is in contact with the channel formation region 463 is provided.

[0061] The first high resistance drain region 464a is self-alignedly formed in contact with the lower surface of the first low resistance drain region 408a. Also, the second high resistance drain region 464b is self-alignedly formed in contact with the lower surface of the second low resistance drain region 408b. Further, the channel formation region 463 is in contact with the oxide insulating layer 466 and has a thinner film thickness than the first high resistance drain region 464a and the second high resistance drain region 464b, and is a region (type I region) having a higher resistance than the first high resistance drain region 464a and the second high resistance drain region 464b.

[0062] Also, for the thin film transistor 460, it is preferable to use a metal material for the source electrode layer 465a and the drain electrode layer 465b in order to reduce the resistance of the wiring.

[0063] Also, in a liquid crystal display device, when a pixel portion and a drive circuit are formed on the same substrate, in the drive circuit logic gates such as an inverter circuit, a NAND circuit, a NOR circuit, and a latch circuit ​​thin film transistors that make up, sense amplifiers, constant voltage generation circuits, voltage controlled oscillators (VC The thin film transistors that make up analog circuits such as O) have only a positive polarity or only a negative polarity applied between the source electrode and the drain electrode . Therefore, the width of the second high-resistance drain region 464b that requires breakdown voltage may be designed wider than the width of the first high-resistance drain region 464a . Also, the widths of the first high-resistance drain region 464a and the second high-resistance drain region 4 64b overlapping the gate electrode layer may be widened .

[0064] Also, although the thin film transistor 460 disposed in the drive circuit has been described using a single-gate structure thin film transistor , if necessary, a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed .

[0065] Also, a conductive layer 467 overlapping above the channel formation region 463 is provided. By electrically connecting the conductive layer 467 to the gate electrode layer 461 and setting them to the same potential, a gate voltage can be applied to the oxide semiconductor layer 462 disposed between the gate electrode layer 461 and the conductive layer 4 67 from above and below . Also, when the gate electrode layer 461 and the conductive layer 467 are set to different potentials, for example, a fixed potential, GND , 0V, the electrical characteristics of the TFT, such as the threshold voltage, can be controlled . That is, by making the gate electrode layer 461 function as the first gate electrode layer and the conductive layer 467 function as the second gate electrode layer, the thin film transistor 460 can be used as a four-terminal thin film transistor .

[0066] Also, a protective insulating layer 453 and a planarizing insulating layer 4 are laminated between the conductive layer 467 and the oxide insulating layer 466 .

[0067] Further, the protective insulating layer 453 is preferably configured to be in contact with the first gate insulating layer 452 provided below the protective insulating layer 453 or an insulating film serving as a base, and blocks the intrusion of moisture, hydrogen ions, OH - and other impurities from the side surface of the substrate. In particular, it is effective to form the first gate insulating layer 452a or the insulating film serving as a base in contact with the protective insulating layer 453 as a silicon nitride film.

[0068] Also, the thin film transistor 470 disposed in the pixel is a channel stop type thin film transistor, and includes a gate electrode layer 471, a first gate insulating layer 452a, a second gate insulating layer 452b, an oxide semiconductor layer 472 including a channel formation region on a substrate 450 having an insulating surface, a source electrode layer 475a, and a drain electrode layer 475b. Further, a channel protection layer 476, a source electrode layer 475a, and a drain electrode layer 47 5b are covered with the thin film transistor 470, and a protective insulating layer 453 and a planarizing insulating layer 454 are laminated and provided in contact therewith. On the planarizing insulating layer 454, a pixel electrode layer 477 in contact with the drain electrode layer 475b is provided and is electrically connected to the thin film transistor 470. Note that the materials of the first low resistance drain region 408a and the second low resistance drain region 408b of the thin film transistor 460 for the driving circuit are preferably the same as the materials of the source electrode layer 475a and the drain electrode layer 47 5b of the thin film transistor for the pixel. However, in the liquid crystal display device, in order to prevent deterioration of the liquid crystal, AC driving is performed. By this AC driving, the polarity of the signal potential applied to the pixel electrode layer is positive or negative at every certain period.

[0069] It is inverted. The TFT connected to the pixel electrode layer has a pair of electrodes that alternately serve as the source electrode layer and the drain electrode layer. In this specification, for convenience, one electrode of the thin film transistor of the pixel is referred to as the source electrode layer, and the other electrode is referred to as the drain electrode layer. However, in actuality, during AC driving one electrode alternately functions as the source electrode layer and the drain electrode layer. Also, in order to reduce leakage current the width of the gate electrode layer 471 of the thin film transistor 470 disposed in the pixel may be made narrower than the width of the gate electrode layer 461 of the thin film transistor 460 in the driving circuit. Also, in order to reduce leakage current, the gate electrode layer 471 of the thin film transistor 470 disposed in the pixel may be designed so as not to overlap with the source electrode layer 475a or the drain electrode layer 475b.

[0070] Also, although the thin film transistor 470 disposed in the pixel has been described using a single-gate structure thin film transistor a multi-gate structure thin film transistor having a plurality of channel formation regions can also be formed as needed.

[0071] Also, after the formation of the oxide semiconductor film, a heat treatment (heat treatment for dehydration or dehydrogenation) for reducing impurities such as moisture is performed. After performing the heat treatment for dehydration or dehydrogenation and slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer, etc., to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the electrical characteristics and reliability of the thin film transistor 470.

[0072] Note that the oxide semiconductor layer 472 is formed below the source electrode layer 475a and the drain electrode layer 475b and partially overlaps. Also, the oxide semiconductor layer 472 is the gate electrode layer 471​​ It overlaps via the first gate insulating layer 452a and the second gate insulating layer 452b. The channel formation region of the thin film transistor 470 disposed in the pixel is the oxide semiconductor layer 472 Among them, the side surface of the source electrode layer 475a and the side surface of the drain electrode layer 475b facing the side surface The region sandwiched between the side surfaces, that is, the region in contact with the second gate insulating layer 452b and overlapping with the gate electrode layer 4 71.

[0073] Also, the thin film transistor 470 has a high aperture ratio as a thin film transistor having translucency, and in order to realize a display device having the same, the source electrode layer 475a and the drain electrode layer 475b Use a conductive film having translucency.

[0074] Also, the gate electrode layer 471 of the thin film transistor 470 also uses a conductive film having translucency.

[0075] Also, in the pixel where the thin film transistor 470 is disposed, a conductive film having translucency with respect to visible light is used for the pixel electrode layer 477 or other Electrode layers (such as capacitive electrodes) and other wiring layers (such as capacitive wiring layers) to realize a display device having a high aperture ratio. Of course, it is preferable to use a film having translucency with respect to visible light for the first gate insulating Layer 452a, the second gate insulating layer 452b, and the channel protection layer 476.

[0076] In this specification, the film having translucency refers to a film having a visible light transmittance of 75 to 100%, and when the film has conductivity, it is also called a transparent conductive film. Also, as a metal oxide applied to the gate electrode layer, the source Electrode layer, drain electrode layer, pixel electrode layer, or other electrode layers and other wiring layers, a semi-transparent conductive film with respect to visible light may be used. With respect to visible light ​​​​​Semitransparent means that the transmittance of visible light is 50 to 75%.

[0077] Hereinafter, using FIGS. 2(A) to (E) and FIGS. 3(A) to (E), the manufacturing process of thin film transistors 460 and thin film transistors 470 on the same substrate will be described. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0078] First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. First, after forming a conductive film having translucency on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process. Also, in the pixel portion, a capacitive wiring is formed by the same material and the same first photolithography process as the gate electrode layers 461 and 471. Further, when a capacitor is required not only in the pixel portion but also in the driving circuit, a capacitive wiring (also referred to as a capacitive wiring layer) is formed in the driving circuit. Note that the resist mask may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0079] There is no major limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. As the substrate 450 having an insulating surface, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used. There is no major limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. As the substrate 450 having an insulating surface, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used. There is no major limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. As the substrate 450 having an insulating surface, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used. There is no major limitation on the substrate that can be used for the substrate 450 having an insulating surface, but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. As the substrate 450 having an insulating surface, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used.

[0080] Also, when using a glass substrate as the substrate 450, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. Also, when using a glass substrate as the substrate 450, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that compared with boric acid, barium oxide Also, when using a glass substrate as the substrate 450, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. Also, when using a glass substrate as the substrate 450, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that compared with boric acid, barium oxide Also, when using a glass substrate as the substrate 450, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. Also, when using a glass substrate as the substrate 450, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that compared with boric acid, barium oxide Also, when using a glass substrate as the substrate 450, when the temperature of the subsequent heat treatment is high, it is preferable to use one having a strain point of 730 °C or higher. Also, when using a glass substrate as the substrate 450, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that compared with boric acid, barium oxide By incorporating a large amount of barium oxide (BaO), a more practical heat-resistant glass can be obtained. Therefore , B 2 O 3 it is preferable to use a glass substrate containing more BaO than B

[0081] Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as substrate 450. Additionally, crystallized glass or the like can also be used for this purpose.

[0082] Also, an insulating film serving as an underlayer may be provided between substrate 450 and gate electrode layers 461 and 471. The underlayer has a function of preventing the diffusion of impurity elements from substrate 450 and can be formed by a stacked structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0083] The materials of gate electrode layers 461 and 471 are conductive materials having translucency to visible light, for example In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-G a-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al -Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied, and the film thickness can be appropriately selected within the range of 50 nm or more and 300 nm or less. The film formation method of the metal oxides used for gate electrode layers 461 and 4 71 is to use a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method ), an arc discharge ion plating method, or a spraying method. Also, when using the sputtering method, a target containing 2 wt% or more and 10 wt% or less of SiO is used for film formation , and SiOx (X>0) that inhibits crystallization is included in the conductive film having translucency, and this is done in a subsequent process 2 ​​​​​It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. I wish.

[0084] Next, a gate insulating layer is formed on the gate electrode layers 461 and 471 .

[0085] The gate insulating layer is a silicon oxide layer, a nitride layer, etc., formed by plasma CVD or sputtering. The silicon layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, the deposition gas is SiH 4 The oxygen and nitrogen were used to produce the acid by plasma CVD. A silicon nitride layer may be formed.

[0086] In this embodiment, a first gate insulating layer 452a having a thickness of 50 nm or more and 200 nm or less, A second gate insulating layer 452b having a thickness of 50 nm to 300 nm is a stacked gate insulating layer. The first gate insulating layer 452a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. The second gate insulating layer 452b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0087] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 452b. After the oxide semiconductor film is formed, the oxide semiconductor film is dehydrated or dehydrogenated. In order to make the oxide semiconductor layer amorphous even after the heat treatment for the purpose of the present invention, the thickness of the oxide semiconductor layer is set to 50 nm. It is preferable to make the oxide semiconductor layer as thin as or less. When a heat treatment is performed after the formation of the film, crystallization can be suppressed.

[0088] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma Reverse sputtering that generates a plasma is performed to remove the particles adhering to the surface of the second gate insulating layer 452b. It is preferable to remove the particles. Reverse sputtering is a method of forming a plasma near the substrate by applying a voltage to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the target side to modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. It is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. It is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere. It is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0089] The oxide semiconductor film is an In-Ga-Zn-O-based non-single crystal film, an In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. 2 It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step. It is an In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film. In this embodiment, a film is formed by a sputtering method using an In-Ga-Zn-O-based oxide semiconductor target. Further, the oxide semiconductor film can be formed by a sputtering method in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO is used for film formation to include SiOx (X>0) that inhibits crystallization in the oxide semiconductor film and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step.

[0090] Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 350°C or higher and lower than the distortion point of the substrate, preferably 400°C or higher and lower than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses. Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 350°C or higher and lower than the distortion point of the substrate, preferably 400°C or higher and lower than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses. Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 350°C or higher and lower than the distortion point of the substrate, preferably 400°C or higher and lower than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses. After the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere, In order to prevent water or hydrogen from re-mixing into the oxide semiconductor layer, the oxide semiconductor layer is cooled slowly without being exposed to the air. In this embodiment, the oxide semiconductor layer is dehydrated. Or, heat the same furnace from the heating temperature T at which dehydrogenation takes place to a temperature high enough to prevent water from entering again. Specifically, the temperature is gradually cooled in a nitrogen atmosphere until it is 100°C lower than the heating temperature T. In addition, the atmosphere is not limited to nitrogen, and may be a rare gas atmosphere such as helium, neon, argon, or the like, or a reduced pressure atmosphere. A heat treatment is carried out under pressure for dehydration or dehydrogenation.

[0091] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0092] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, the oxide semiconductor film may be crystallized and microcrystallized. In some cases, the film may be a crystalline or polycrystalline film.

[0093] Note that the first heat treatment of the oxide semiconductor film 480 is performed after the oxide semiconductor layer is processed into an island shape. It can also be done.

[0094] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400℃ or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) It may be performed below the point to remove impurities such as hydrogen and water contained in the gate insulating layer.

[0095] Next, an oxide conductive layer for use as a low-resistance drain region and a conductive layer are formed on the oxide semiconductor layer 481. And a conductive layer are formed.

[0096] As a method for forming the oxide conductive layer, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spraying method is used. As a material for the low-resistance drain region, an oxide conductive material can be used. For example, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Note that the oxide conductive material used as the low-resistance drain region has a lower resistance than the oxide semiconductor layer 483 and a higher resistance than the conductive layer 484, and a material can be appropriately selected and used. Also, when using the sputtering method, it is preferable to perform film formation using a target containing 2 wt% or more and 10 wt% or less of SiO to include SiOx (X>0) that inhibits crystallization in the conductive film having translucency, and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. And a spraying method is used. As a material for the low-resistance drain region, an oxide conductive material can be used. For example, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Note that the oxide conductive material used as the low-resistance drain region has a lower resistance than the oxide semiconductor layer 483 and a higher resistance than the conductive layer 484, and a material can be appropriately selected and used. Also, when using the sputtering method, it is preferable to perform film formation using a target containing 2 wt% or more and 10 wt% or less of SiO to include SiOx (X>0) that inhibits crystallization in the conductive film having translucency, and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. An oxide conductive material can be used. For example, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based metal oxides can be applied. And a Zn-O-based metal oxide can be applied. Note that the oxide conductive material used as the low-resistance drain region has a lower resistance than the oxide semiconductor layer 483 and a higher resistance than the conductive layer 484, and a material can be appropriately selected and used. The oxide conductive material used as the low-resistance drain region has a lower resistance than the oxide semiconductor layer 483 and a higher resistance than the conductive layer 484, and a material can be appropriately selected and used. A material with a higher resistance than the conductive layer 484 can be appropriately selected and used. Also, when using the sputtering method, SiO 2 Perform film formation using a target containing 2 wt% or more and 10 wt% or less to include SiOx (X>0) that inhibits crystallization in the conductive film having translucency, and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. Perform film formation using a target containing 2 wt% or more and 10 wt% or less to include SiOx (X>0) that inhibits crystallization in the conductive film having translucency, and suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation performed in a later process.

[0097] Also, as a material for the conductive layer, an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc. There are an alloy containing the above-described elements as components, or an alloy combining the above-described elements, etc.

[0098] As the conductive layer, an aluminum layer is laminated on a titanium layer, and a titanium layer is laminated on the aluminum layer. A formed three-layer laminated structure, or an aluminum layer on a molybdenum layer, and on the aluminum layer It is preferable to form a three-layer laminated structure in which a molybdenum layer is laminated. Of course, it may be a single layer, or a two-layer structure, or a laminated structure of four or more layers as the conductive layer.

[0099] After forming the oxide conductive layer and the conductive layer, resist masks 482a and 482b used in the second photolithography process are formed. Note that the resist masks 482a and the resist mask 482b may be formed by an inkjet method. Since the resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing cost can be reduced.

[0100] The resist mask 482a in this embodiment is a resist mask having concave portions or convex portions. In other words, it can also be said to be a resist mask composed of a plurality of regions (here, two regions) having different thicknesses. In the resist mask 482a, the thick region is called the convex portion of the resist mask 482a, and the thin region is called the concave portion of the resist mask 482a.

[0101] In the resist mask 482a, convex portions are formed in the portions where the source electrode layer and the drain electrode layer will be formed later, and are sandwiched between the source electrode layer and the drain electrode layer, and concave portions are formed in the portion that will become the later channel formation region.

[0102] The resist mask 482a can be formed by using a multi-tone mask. A multi-tone mask is a mask capable of performing exposure with multi-stage light amounts. Typically, it refers to a mask that performs exposure with three light amounts in the exposed region, semi-exposed region, and unexposed region. The multi-tone mask is ​​​​​By using this method, multiple thicknesses (typically two types) can be produced by a single exposure and development process. Therefore, by using a multi-tone mask, The number of photomasks can be reduced.

[0103] By exposing and developing using a multi-tone mask, a resist mask with regions of different thicknesses is created. However, the present invention is not limited to this, and a multi-tone mask may be used. Alternatively, the resist mask 482a may be formed without performing the etching.

[0104] Next, a conductive layer and a low resistance The drain region and the oxide semiconductor layer 481 are selectively and simultaneously etched to form an island-like The oxide semiconductor layers 483 and 485 and the low-resistance drain regions 406 and 4 07, and conductive layers 484 and 486 are formed (FIG. 2(C)). When a laminated conductive film of an aluminum film and a titanium film is used, dry etching using chlorine gas is performed. The etching can be performed by a etching method.

[0105] Next, the resist masks 482a and 482b are recessed (reduced). The resist mask is then recessed (reduced). To do this, ashing using oxygen plasma may be performed. By this, the conductive portion between the resist mask 487a and the resist mask 487b is The conductive layer 484 is exposed.

[0106] Next, the conductive layer 48 between the resist mask 487a and the resist mask 487b is 4 and the low-resistance drain region 406 in contact with the region are covered with a resist mask 487a and a resist The source electrode layer 465a is selectively etched using the mask 487b. and the drain electrode layer 465b, the first low-resistance drain region 408a and the second low-resistance drain In this case, the oxide semiconductor layer is only partially The oxide semiconductor layer 488 is etched to have a groove (depression).

[0107] As shown in FIG. 2(D), the resist masks 482a and 482b are recessed (reduced). The resist mask 487a and the resist mask 487b are used for etching to form an oxidized A thin region is formed on the periphery of the oxide semiconductor layers 483 and 485. The ends of the body layer 488 are closer to the ends of the first and second low-resistance drain regions 408a, 408b. The end of the oxide semiconductor layer 489 also protrudes further than the end of the low-resistance drain region 409. Note that the periphery of the oxide semiconductor layer 483 and the oxide semiconductor layer 484 which will be a channel formation region later are The groove (recess) of the semiconductor layer 488 has the same thickness.

[0108] Next, the resist masks 487a, 487b, and 487c are removed, and a third photolithography process is performed. A resist mask 491 is formed by a photolithography process, and selective etching is performed to remove the acid from the pixel area. The low-resistance drain region 409 and the conductive layer 490 formed on the nitride semiconductor layer 489 are then removed. (Figure 2(E)).

[0109] Note that the low-resistance drain region overlapping with the oxide semiconductor layer 489 is formed in the third photolithography process. In order to selectively remove the region 409 and the conductive layer 490, the oxide semiconductor layer Appropriately adjust each material and etching condition so that 489 is not removed. Also, The resist mask 491 may be formed by an inkjet method. Since forming a resist mask by the inkjet method does not use a photomask, the manufacturing cost can be reduced.

[0110] Next, remove the resist mask 491, and form an oxide insulating film 492 that serves as a protective insulating film in contact with the upper surface and side surfaces of the oxide semiconductor layer 489 and in contact with the groove portion (concave portion) of the oxide semiconductor layer 488. The oxide insulating film 492 is formed to have a film thickness of at least 1 nm or more, and a method such as a sputtering method that does not mix impurities such as water and hydrogen into the oxide insulating film 492 can be appropriately used. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 492 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by a sputtering method in an atmosphere of oxygen and nitrogen using a silicon target. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0111] The oxide insulating film 492 is formed to have a film thickness of at least 1 nm or more, and a method such as a sputtering method that does not mix impurities such as water and hydrogen into the oxide insulating film 492 can be appropriately used. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 492 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by a sputtering method in an atmosphere of oxygen and nitrogen using a silicon target. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 is formed to have a film thickness of at least 1 nm or more, and a method such as a sputtering method that does not mix impurities such as water and hydrogen into the oxide insulating film 492 can be appropriately used. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 492 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be performed in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by a sputtering method in an atmosphere of oxygen and nitrogen using a silicon target. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. - The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. The oxide insulating film 492 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH, and blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used.

[0112] Next, a second heat treatment (preferably 2 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere (Fig. 3(A)). For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed the groove portion of the oxide semiconductor layer 488, the upper surface and side surfaces of the oxide semiconductor layer 489 are heated in contact with the oxide insulating film 492.

[0113] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor film after film formation to reduce the resistance, a part of the oxide semiconductor film is selectively made in an oxygen-excessive state. As a result, the channel formation region 463 overlapping the gate electrode layer 461 becomes of type I, and the first high-resistance drain region 464a overlapping the source electrode layer 465a and the second high-resistance drain region 464b overlapping the drain electrode layer 465b are self-alignedly formed. Also, the oxide semiconductor layer 472 overlapping the gate electrode layer 471 becomes entirely of type I. In addition, by forming the second high-resistance drain region 464b (or the first high-resistance drain region 464a

[0114] in the oxide semiconductor layer overlapping the drain electrode layer 465b (and the source electrode layer 465a), it is possible to improve the reliability when forming a drive circuit. Specifically, by forming the second high-resistance drain region 464b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer to the second high-resistance drain region 464b and the channel formation region. Therefore, a high power supply potential is applied to the drain electrode layer 465b ​​​When operating by connecting to the wiring that supplies VDD, even if a high electric field is applied between the gate electrode layer 461 and the drain electrode layer 465b, the high-resistance drain region serves as a buffer and a local high electric field is not applied, enabling a configuration that improves the breakdown voltage of the transistor.

[0115] Also, in the oxide semiconductor layer superimposed on the drain electrode layer 465b (and the source electrode layer 465a), by forming the second high-resistance drain region 464b (or the first high-resistance drain region 464a ), it is possible to reduce the leakage current in the channel formation region 463 when forming the drive circuit.

[0116] Also, by having a configuration with a second low-resistance drain region 408b (and a first low-resistance drain region 408a) between the drain electrode layer 465b (and the source electrode layer 465a) and the oxide semiconductor layer, it can have a thermally stable operation compared to a Schottky junction. The first low -resistance drain region 408a and the second low-resistance drain region 408b have a lower resistance than the oxide semiconductor layer and a higher resistance than the drain electrode layer 465b (and the source electrode layer 465a). Therefore, the contact resistance between the oxide semiconductor layer and the drain or source electrode layer can be reduced

[0117] Next, resist masks 493a and 493b are formed by the fourth photolithography process, and the oxide insulating film 492 is selectively etched to form an oxide insulating layer (channel protection layer) 476 on the channel formation region of the oxide semiconductor layer 472 of the pixel portion (FIG. 3(B)). By providing the channel protection layer 476, in the channel formation region of the oxide semiconductor layer 472 Damage during the process (film loss due to plasma or etching agent during etching, etc.) Therefore, the reliability of the thin film transistor can be improved. Note that in the case where an oxide insulating layer is used as the gate insulating layer 452b as in this embodiment, Part of the gate insulating layer 452b is also etched by the etching process of the oxide insulating layer 492. The oxide insulating layer 452b may be formed by the oxide insulating film. When a nitride insulating film having a smaller etching rate than the insulating film 492 is used, the gate insulating layer 45 This can prevent 2b from being partially etched.

[0118] In addition, after dehydration or dehydrogenation, the channel protection layer 476 is continuously formed without exposure to air. By continuously treating the surface without exposing it to air, the interface can be formed as follows: Contamination by atmospheric components or impurities suspended in the air, such as water or hydrocarbons Since each lamination interface can be formed without any trouble, the variation in the thin film transistor characteristics can be reduced. It is possible.

[0119] The resist masks 493a and 493b may be formed by an ink-jet method. When the photomask is formed by the inkjet method, no photomask is used, so the manufacturing cost is reduced. It can be reduced.

[0120] Next, the second gate insulating layer 452b, the oxide semiconductor layer 472, and the channel protection layer 474 in the pixel portion are After forming a light-transmitting conductive film on the protective layer 476, a fifth photolithography process is performed. Thus, a source electrode layer 475a and a drain electrode layer 475b are formed (FIG. 3C). The methods for forming conductive films with optical properties include sputtering, vacuum deposition (electron beam deposition, etc.), and , an arc discharge ion plating method or a spray method is used. As the material of the conductive film, a conductive material having translucency to visible light, for example, In-Sn-Zn-O system, In-Al- Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system , a metal oxide of the Zn-O system can be applied, and the film thickness is appropriately selected within the range of 50 nm or more and 300 nm or less. When using the sputtering method, SiO is used to form a film using a target containing 2% by weight or more and 10% by weight or less of SiO 2 , and it is preferable to include SiOx (X>0) that inhibits crystallization in the conductive film having translucency.

[0121] In addition, a resist mask for forming the source electrode layer 475a and the drain electrode layer 475b may be formed by an inkjet method. Since a photomask is not used when forming the resist mask by an inkjet method, the manufacturing cost can be reduced.

[0122] Next, a protective insulating layer 453 is formed on the oxide insulating layer 466, the channel protection layer 476, the source electrode layer 475a, and the drain electrode layer 475b (FIG. 3(D)). In this embodiment, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a film formation method for the protective insulating layer 453 because of its good mass productivity. The protective insulating layer 453 does not contain impurities such as moisture, hydrogen ions, and OH , and an inorganic insulating film that blocks these from entering from the outside is used, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film. Of course, the protective insulating layer 453 is an insulating film having translucency. -

[0123] Further, the protective insulating layer 453 is preferably configured to be in contact with the first gate insulating layer 452 provided below the protective insulating layer 453 or an insulating film serving as a base, and blocks the intrusion of moisture, hydrogen ions, OH and other impurities from the vicinity of the side surface of the substrate. In particular, it is effective to use a silicon nitride film for the first gate insulating layer 452a or the insulating film serving as a base that contacts the protective insulating layer 453. That is, providing a silicon nitride film so as to surround the lower surface, upper surface, and side surface of the oxide semiconductor layer improves the reliability of the display device. - Next, a planarization insulating layer 454 is formed on the protective insulating layer 453. As the planarization insulating layer 454, heat-resistant organic materials such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the planarization insulating layer 454 may be formed by laminating a plurality of insulating films formed of these materials.

[0124]

[0125] Note that the siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

[0126] The method for forming the planarization insulating layer 454 is not particularly limited, and depending on the material, sputtering method, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing method), etc. can be used. - Methods such as screen printing, offset printing, etc., and tools such as doctor blades, roll coaters, curtain coaters, knife coaters, etc. can be used.

[0127] Next, a sixth photolithography process is performed to form a resist mask, and contact holes 494 reaching the drain electrode layer 475b are formed by etching the planarization insulating layer 454 and the protective insulating layer 453. Also, contact holes reaching the gate electrode layers 461 and 471 are formed by the etching here. Further, a resist mask for forming the contact holes reaching the drain electrode layer 475b may be formed by an inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced.

[0128] Next, after removing the resist mask, a conductive film having translucency is formed. As materials for the conductive film having translucency, indium oxide (In 2 O 3 ), indium tin oxide alloy (In 2 O 3 ―SnO 2 , abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, etc. As other materials for the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, i.e., an Al-Zn-O-N-based non-single crystal film, a Zn-O-based non-single crystal film containing nitrogen, i.e., a Zn-O-N-based non-single crystal film, or a Sn-Zn-O-based non-single crystal film containing nitrogen, i.e., a Sn-Zn-O-N-based non-single crystal film, may be used. Note that the composition ratio (atomic%) of zinc in the Al-Zn-O-N-based non-single crystal film is 47 atomic% or less, and the aluminum in the non-single crystal film is greater than the composition ratio (atomic %) of aluminum in the non-single crystal film, and the composition ratio (atomic %) of aluminum in the non-single crystal film is greater than the composition ratio (atomic %) of nitrogen in the non-single crystal film. The etching treatment of such a material is performed with an acid-based solution. However, especially for the etching of ITO, residues are likely to occur, so indium zinc oxide alloy (In ―ZnO) may be used to improve the etching processability. Note that the unit of the composition ratio of the conductive film having translucency is atomic %, and it shall be evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer 2 O 3 ―ZnO). Next, a seventh photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 477 and the conductive layer 467 (see Fig. 3(E).

[0129] By the above steps, using seven masks, the thin film transistor 460 and the thin film transistor 470 can be separately fabricated as a driving circuit or a pixel portion on the same substrate. The thin film transistor 460 for the driving circuit is a channel etch type thin film transistor including an oxide semiconductor layer including a first high-resistance drain region 464a, a second high-resistance drain region 464b, and a channel formation region 463, and the thin film transistor 470 for the pixel is a channel protection (channel stop) type thin film transistor including a channel protection type thin film transistor including an oxide semiconductor layer 472 that is entirely I-type. (EPMA: Electron Probe X-ray MicroAnalyzer ).

[0130] ).

[0131]

[0132] ​​​​​​​​​In addition, a storage capacitor formed by using a first gate insulating layer 452a and a second gate insulating layer 452b as dielectrics, a capacitance wiring and a capacitance electrode can also be formed on the same substrate. A thin film transistor 470 and the storage capacitor are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having a thin film transistor 460 is arranged around the pixel portion, whereby an active matrix type display device can be manufactured as one substrate. In this specification, for convenience, such a substrate is referred to as an active matrix substrate.

[0133] Note that the pixel electrode layer 477 is electrically connected to the capacitance electrode through contact holes formed in the planarization insulating layer 454 and the protective insulating layer 453. The capacitance electrode can be formed of the same material and in the same process as the source electrode 47 5a and the drain electrode layer 475b. By providing the conductive layer 467 at a position overlapping with the channel formation region 463 of the oxide semiconductor layer,

[0134] in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 460 before and after the BT test can be reduced. Further, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer . Further, the potential of the conductive layer 467 may be GND, 0V, or in a floating state . . .

[0135] In addition, a resist mask for forming the pixel electrode layer 477 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0136] This embodiment can be freely combined with other embodiments.

[0137] (Embodiment 2) In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device different from those of Embodiment 1 will be described with reference to FIG. 4. Specifically, in the semiconductor device shown in FIG. 1, both the thin film transistor disposed in the drive circuit and the thin film transistor disposed in the pixel portion have at least a channel formation region, a first high-resistance drain region, and a second high-resistance drain region, and a semiconductor device having an oxide semiconductor layer as an active layer will be described. Note that the thin film transistor disposed in the drive circuit in this embodiment has the same structure as the thin film transistor 460 shown in Embodiment 1 and can be manufactured by the same process. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted. formation region, a first high-resistance drain region, and a second high-resistance drain region, and a semiconductor device having an oxide semiconductor layer as an active layer will be described. Note that the thin film transistor disposed in the drive circuit in this embodiment has the same structure as the thin film transistor 460 shown in Embodiment 1 and can be manufactured by the same process. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted. In this embodiment, the thin film transistor disposed in the drive circuit has the same structure as the thin film transistor 460 shown in Embodiment 1 and can be manufactured by the same process. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted. In this embodiment, the same portions or portions having the same functions as those in Embodiment 1, and the processes can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted.

[0138] On a substrate 450 having an insulating surface, a gate electrode layer 461, 471, a first gate insulating layer 4 52a, and a second gate insulating layer 452b are formed. In the drive circuit portion, a channel formation region 463, a first high-resistance drain region 464a, and a second high-resistance drain region 464b are included in an oxide semiconductor layer, a first low-resistance drain region 408a, a second low-resistance drain region 40 8b, a source electrode layer 465a, a drain electrode layer 465b, and an oxide insulating layer 466 are formed In the pixel portion, an oxide semiconductor layer 472 and a channel protection layer 476 are formed (FIG. 4(A)). The oxide semiconductor layer 472 is of a highly resistive type I. 4(A)). The oxide semiconductor layer 472 is of a highly resistive type I.

[0139] In addition, thin regions in terms of film thickness are formed at the periphery of the oxide semiconductor layer of the thin film transistor 460 provided in the drive circuit section and the oxide semiconductor layer 472. That is, the end portion of the oxide semiconductor layer of the thin film transistor 460 protrudes beyond the end portions of the first low-resistance drain region 408a and the second low-resistance drain region 408b. Note that the peripheral portion of the oxide semiconductor layer of the thin film transistor 460 and the groove portion (recessed portion) of the oxide semiconductor layer that will later become the channel formation region have the same film thickness.

[0140] In this embodiment, heat treatment is performed in an inert gas atmosphere such as nitrogen or under reduced pressure with at least a part of the oxide semiconductor layer 472 being exposed. When heat treatment is performed in an inert gas atmosphere such as nitrogen or under reduced pressure with a part of the highly resistive (type-I converted) oxide semiconductor layer 472 being exposed, the exposed highly resistive (type-I converted) region in the oxide semiconductor layer 472 can be made to have a lower resistance to form a high-resistance drain region.

[0141] The heat treatment for reducing the resistance of the highly resistive (type-I converted) region in the oxide semiconductor layer 472 is preferably performed at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0142] In this embodiment, the substrate is introduced into an electric furnace which is one of the heat treatment apparatuses, and after heat treatment is performed on the oxide semiconductor layer 472 in a nitrogen atmosphere, it is gradually cooled in a nitrogen atmosphere without being exposed to the air from the heating temperature T until the temperature drops by 100°C or more from the heating temperature T. Further, the atmosphere is not limited to a nitrogen atmosphere, and degassing is performed in an atmosphere such as helium, neon, argon, etc. or under reduced pressure. ​​​​​​​​​​​​​​ Perform hydration or dehydrogenation. In the heat treatment, it is preferable that nitrogen, or noble gases such as helium, neon , argon, etc. do not contain water, hydrogen, etc. Or, the purity of nitrogen or noble gases such as helium, neon, argon, etc. introduced into the heat treatment device is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0143] By heat treatment of the oxide semiconductor layer 472 in an inert gas atmosphere such as nitrogen or under reduced pressure , the exposed region of the oxide semiconductor layer 472 has a lower resistance, and the first high-resistance drain region 4 74a and the second high-resistance drain region 474b are formed. Note that the region of the oxide semiconductor layer 472 covered by the channel protection layer 476 remains a high-resistance region and becomes the I-type channel formation region 473. Therefore, an oxide semiconductor layer 495 including the first high-resistance drain region 474 a, the second high-resistance drain region 474b, and the channel formation region 473 is formed (see FIG. 4(B)).

[0144] Next, after forming a transparent conductive film on the oxide semiconductor layer 495 and the channel protection layer 476 , the source electrode layer 475a and the drain electrode layer 475b are formed by the fifth photolithography process (FIG. 4(C)).

[0145] Next, a protective insulating layer 453 and a planarizing insulating layer 454 are laminated and formed on the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the cha nnel protection layer 476.

[0146] ​Next, a sixth photolithography process is performed to form a resist mask, and a planarization insulating layer 4 54 and a contact hole 494 reaching the drain electrode layer 475b are formed by etching the protective insulating layer 453 (FIG. 4(D)).

[0147] Next, after removing the resist mask, a conductive film having translucency is formed.

[0148] Next, a seventh photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the pixel electrode layer 477 and the conductive layer 467 (FIG. 4(E)).

[0149] Through the above processes, using seven masks, the thin film transistor 460 and the thin film transistor 498 can be separately fabricated in the driving circuit or the pixel portion on the same substrate. The thin film transistor 460 disposed in the driving circuit is a channel etch type thin film transistor including an oxide semiconductor layer including a first high-resistance drain region 464a, a second high-resistance drain region 464b, and a channel formation region 463, and the thin film transistor 498 disposed in the pixel portion is also a channel protection type thin film transistor including an oxide semiconductor layer 495 including a first high-resistance drain region 474a, a second high-resistance drain region 474b, and a channel formation region 473. Therefore, even when a high electric field is applied, the high-resistance drain region serves as a buffer in the thin film transistors 460 and 498, and a local high electric field is not applied, and the breakdown voltage of the transistor is improved.

[0150] In the thin film transistor 460, a second low-resistance drain region 408b (and a first low-resistance drain region) is provided between the drain electrode layer 465b (and the source electrode layer 465a) and the oxide semiconductor layer. By adopting a configuration having a drain region 408a), it is possible to achieve thermally stable operation compared to a Schottky junction. The first low-resistance drain region 408a and the second low-resistance drain region 408b have a lower resistance than the oxide semiconductor layer and a higher resistance than the drain electrode layer 465b (and the source electrode layer 465a). Therefore, the contact resistance between the oxide semiconductor layer and the drain or source electrode layer can be reduced. Also, a holding capacitor formed by the first gate insulating layer 452a, the second gate insulating layer 452b as dielectrics, the capacitance wiring layer, and the capacitive electrode can be formed on the same substrate. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. Note that this embodiment can be freely combined with other embodiments.

[0151] Moreover, a holding capacitor formed by the first gate insulating layer 452a, the second gate insulating layer 452b as dielectrics, the capacitance wiring layer, and the capacitive electrode can be formed on the same substrate. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device. Moreover, a holding capacitor formed by the first gate insulating layer 452a, the second gate insulating layer 452b as dielectrics, the capacitance wiring layer, and the capacitive electrode can be formed on the same substrate. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device. The thin-film transistors 498 and the holding capacitors are arranged in a matrix corresponding to individual pixels to form a pixel portion, and a driving circuit having thin-film transistors 460 is arranged around the pixel portion, thereby making it possible to use it as one substrate for manufacturing an active matrix type display device.

[0152] By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region 463 of the oxide semiconductor layer, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin-film transistor, the change amount of the threshold voltage of the thin-film transistor 460 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state.

[0153] Note that this embodiment can be freely combined with other embodiments.

[0154] (Embodiment 3) In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device, which are different from those in Embodiments 1 and 2, will be described with reference to FIG. 5. Specifically, in the semiconductor device shown in FIG. 1, both the thin film transistor disposed in the driving circuit and the thin film transistor disposed in the pixel portion have an oxide semiconductor layer in which the entire channel formation region overlapping with the gate electrode layer is of type I as an active layer. A semiconductor device having such a structure will be described. Note that the same portions and portions having similar functions in this embodiment as those in Embodiment 1, and the processes can be carried out in the same manner as in Embodiment 1, and repeated descriptions will be omitted. In this embodiment, the same portions as those in Embodiment 1 and portions having similar functions, and the processes can be carried out in the same manner as in Embodiment 1, and repeated descriptions will be omitted.

[0155] Cross-sectional views of the manufacturing process of the thin film transistor 498 are shown in FIGS. 5(A) to 5(C). First, in accordance with Embodiment 1, after forming a transparent conductive film on a substrate 450 having an insulating surface, gate electrode layers 461 and 471 are formed by a first photolithography process.

[0156] Next, a stack of a first gate insulating layer 452a and a second gate insulating layer 452b is formed on the gate electrode layers 461 and 471. Next, an oxide semiconductor film 480 having a film thickness of 2 nm or more and 200 nm or less is formed on the second gate insulating layer 452b (FIG. 5(A)). Note that the processes up to this point are the same as those in Embodiment 1, and FIG. 5(A) corresponds to FIG. 2(A).

[0157] Next, dehydration or dehydrogenation of the oxide semiconductor film 480 is performed in an inert gas atmosphere or under reduced pressure. The temperature of the first heat treatment for performing dehydration or dehydrogenation is 350°C or higher and lower than the strain point of the substrate, preferably 400°C or higher. Here, one of the heat treatment apparatuses is Introduce the substrate into an electric furnace and perform heat treatment on the oxide semiconductor film in a nitrogen atmosphere. After that, without exposing it to the atmosphere, prevent re-mixing of water and hydrogen into the oxide semiconductor film, and make the oxide semiconductor film oxygen-deficient type to reduce the resistance, that is, make it N-type (N - doping, etc.). Then, in the same furnace introduce high-purity oxygen gas or high-purity N 2 O gas, or ultra-dry air (dew point is -40°C or lower , preferably -60°C or lower) to perform cooling. It is preferable that water, 2 hydrogen, etc. are not contained in the oxygen gas or N O gas. Or, the purity of the oxygen gas or N 2 O gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.9999 9%) or higher, (that is, the impurity concentration in the oxygen gas or N 2 O gas is 1 ppm or lower, preferably 0.1 ppm or lower).

[0158] Also, after the first heat treatment for dehydration or dehydrogenation, in an oxygen gas atmosphere or N O gas atmosphere at a temperature of 200°C or higher and 400°C or lower, preferably 2 200°C or higher and 300°C or lower, or in an ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) atmosphere perform heat treatment.

[0159] By going through the above steps, the entire oxide semiconductor film 496 is made in an oxygen-excess state, thereby increasing the resistance, that is, making it I-type (Fig. 5(B)).

[0160] As a result, the reliability of the thin film transistor formed later can be improved.

[0161] Next, the oxide semiconductor film is formed into island-shaped oxide semiconductor layers by a photolithography process. Process the oxide semiconductor layers 497 and 472.

[0162] In an inert gas atmosphere or under reduced pressure, dehydration or dehydrogenation of the oxide semiconductor film is performed, and after cooling in an inert gas atmosphere, it is processed into the island-shaped oxide semiconductor layers 497 and 472 by a photolithography process, and then heated at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, in an oxygen gas atmosphere, or in an NO gas atmosphere or an ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) atmosphere. It may be performed. After forming the oxide semiconductor film, dehydration or dehydrogenation may be performed, and after cooling in an inert gas atmosphere, it is processed into the island-shaped oxide semiconductor layers 497 and 472 by a photolithography process, and then heated at a temperature of 200°C or higher and 400°C or lower, preferably 200°C or higher and 300°C or lower, in an oxygen gas atmosphere, or in an NO gas atmosphere or an ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) atmosphere. It may be performed. 2 O gas atmosphere or an ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower) atmosphere. It may be performed.

[0163] Before forming the oxide semiconductor film, heat treatment (at a temperature of 400°C or higher and less than the distortion point of the substrate) may be performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), an oxygen atmosphere, or under reduced pressure to remove impurities such as hydrogen and water contained in the layer, and it may be used as a gate insulating layer. It may be performed. It may be performed. It may be used as a gate insulating layer.

[0164] However, when heat treatment is performed in a nitrogen or inert gas atmosphere or under reduced pressure in a state where the highly resistive (type-I) oxide semiconductor layers 497 and 472 are exposed, the highly resistive (type-I) oxide semiconductor layers 497 and 472 become low resistive and form a high-resistance drain region. Therefore, heat treatment performed in a state where the oxide semiconductor layers 497 and 472 are exposed is performed in an oxygen gas, NO gas atmosphere, or ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower). It may be performed. It may be performed. It may be performed. O gas 2 atmosphere or an ultra-dry air (dew point is -40°C or lower, preferably -60°C or lower). It may be performed.

[0165] In this embodiment, an example of performing dehydration or dehydrogenation after forming the oxide semiconductor film is Although shown, it is not particularly limited, and the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film after being processed into an island-shaped oxide semiconductor layer. It can also be performed on the oxide semiconductor film after being processed into

[0166] Next, in the same manner as FIGS. 2(C) to (E) and FIGS. 3(A) to (E) in Embodiment 1, in the peripheral drive circuit portion, only a part of the oxide semiconductor layer 497 is etched to form an oxide semiconductor layer 497 having a groove portion (recess), and a first low-resistance drain region 408a, a second low-resistance drain region 408b, a source electrode layer 465a which is a conductive layer, a drain electrode layer 465b, and an oxide insulating layer 466 in contact with the oxide semiconductor layer 497 are formed to fabricate a thin-film transistor 499 for a drive circuit. On the other hand, in the pixel portion, a channel protection layer 476 is formed on the channel formation region of the oxide semiconductor layer 472, and a source electrode layer 475a and a drain electrode layer 475b which are conductive layers having translucency are formed to fabricate a thin-film transistor 47 0 for a pixel.

[0167] Note that thin regions are formed at the peripheries of the oxide semiconductor layers 497 and 472. That is, the end portion of the oxide semiconductor layer 483 protrudes more than the end portions of the first low-resistance drain region 408a and the second low-resistance drain region 408b. Note that the peripheral portion of the oxide semiconductor layer 483 and the groove portion (recess) of the oxide semiconductor layer 483 which will later become the channel formation region have the same film thickness.

[0168] Next, a second heat treatment (preferably 2 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere.

[0169] ​​​​ Next, a protective insulating layer 453 is formed in contact with the thin film transistors 499 and 470, covering the oxide insulating layer 466, the channel protection layer 476, and the source electrode layer 475a and the drain electrode layer 475b, and the planarization insulating layer 454 is laminated. Contact holes reaching the drain electrode layer 475b are formed in the protective insulating layer 453 and the planarization insulating layer 45 4, and a conductive film having translucency is formed on the contact holes and the planarization insulating layer 454. The conductive film having translucency is selectively etched to form the pixel electrode layer 477 electrically connected to the thin film transistor 470, and the conductive layer 467 (FIG. 5(C)).

[0170] Through the above steps, using seven masks, the thin film transistors 499 and thin film transistors 470 can be respectively fabricated and made into a driving circuit or a pixel portion on the same substrate to be made. The thin film transistor 499 for the driving circuit is a channel etch type thin film transistor including an oxide semiconductor layer 497 entirely converted into the I-type, and the thin film transistor 470 for the pixel is also a channel protection type thin film transistor including an oxide semiconductor layer 472 entirely converted into the I-type. In addition, in the thin film transistor 499, by adopting a configuration having a second low-resistance drain region 408b (and a first low-resistance

[0171] drain region 408a) between the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a thermally stable operation can be achieved as compared with a Schottky junction. Since the first low-resistance drain region 408a and the second low-resistance drain region 408b have a lower resistance than the oxide semiconductor layer and a higher resistance than the drain electrode layer 465b (and the source electrode layer 465a), the oxide semiconductor layer and the drain or source electrode are formed. The contact resistance with the layer can be reduced.

[0172] Also, the first gate insulating layer 452a and the second gate insulating layer 452b are used as dielectrics, and the storage capacitor formed by the capacitance wiring layer and the capacitance electrode can also be formed on the same substrate. The thin film transistor 470 and the storage capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion , and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby an active matrix type display device can be used as one substrate for manufacturing.

[0173] By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias - thermal stress test (hereinafter referred to as the BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as that of the gate electrode layer 461 or different, and it can also function as the second gate electrode layer. Also, the potential of the conductive layer 467 may be GND, 0V, or in a floating state. .

[0174] Note that this embodiment can be freely combined with other embodiments.

[0175] (Embodiment 4) In this embodiment, a semiconductor device and a method for manufacturing the semiconductor device different from those in Embodiments 1 to 3 will be described with reference to FIG. 6. Specifically, in the semiconductor device shown in FIG. 1, the thin film transistor arranged in the driving circuit has an oxide semiconductor layer of type I throughout the channel formation region overlapping the gate electrode layer as an active layer, and the thin film transistor arranged in the pixel portion has at least a channel ... An oxide having a channel formation region, a first high-resistance drain region, and a second high-resistance drain region A semiconductor device having a structure with a semiconductor layer as an active layer will be described. In this embodiment portions and processes that are the same as or have similar functions to those in Embodiment 1 can be performed in the same manner as in Embodiment 1, and repeated explanations will be omitted.

[0176] Cross-sectional views of the manufacturing processes of thin film transistors 499 and 498 are shown in FIGS. 6(A) to (D).

[0177] First, according to Embodiment 3, the process up to FIG. 5(B) in Embodiment 3 is performed. FIG. 6( A) is the same as the process of FIG. 5(B).

[0178] On a substrate 450 having an insulating surface, gate electrode layers 461 and 471, a first gate insulating layer 4 52a, and a second gate insulating layer 452b are formed, and an oxide semiconductor film 496 is formed on the second gate insulating layer 452b (FIG. 6(A)). The oxide semiconductor film 496 is of a highly resistive type I.

[0179] Next, the oxide semiconductor film 496 is processed into island-shaped oxide semiconductor layers, namely oxide semiconductor layers 497 and 472, by a photolithography process.

[0180] Next, in the same manner as FIGS. 2(C) to (E) and FIGS. 3(A) to (E) in Embodiment 1, in the peripheral drive circuit section, only a part of the oxide semiconductor layer 497 is etched to form an oxide semiconductor layer 497 having a groove (recess), and a first low-resistance drain region 408a, a second low-resistance drain region 408b, a source electrode layer 465a which is a conductive layer, a drain electrode layer 465b, and an oxide insulating layer 466 in contact with the oxide semiconductor layer 497 are formed to form a drive circuit for ​​​​​​​ A thin film transistor 499 is fabricated. On the other hand, in the pixel portion, a channel protection layer 476 is formed over the channel formation region of the oxide semiconductor layer 472 (FIG. 6(B)).

[0181] Note that thin regions with a reduced film thickness are formed at the peripheries of the oxide semiconductor layers 497 and 472. That is , the end portion of the oxide semiconductor layer 483 protrudes beyond the end portions of the first low-resistance drain region 408a and the second low-resistance drain region 408b. Note that the peripheral portion of the oxide semiconductor layer 483 and the groove portion (recess) of the oxide semiconductor layer 483 that will later become the channel formation region have the same film thickness .

[0182] Similar to Embodiment 2, in this embodiment, heat treatment is performed in an inert gas atmosphere such as nitrogen or under reduced pressure with at least a part of the oxide semiconductor layer 472 exposed . When heat treatment is performed in an inert gas atmosphere such as nitrogen or under reduced pressure with the highly resistive (type-I) oxide semiconductor layer 472 exposed , the highly resistive (type-I) region exposed in the oxide semiconductor layer 472 can be made into a low-resistance drain region by reducing its resistance .

[0183] The heat treatment for reducing the resistance of the highly resistive (type-I) region in the oxide semiconductor layer 472 is preferably performed at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower . For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere .

[0184] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and after heat treatment is performed on the oxide semiconductor layer 4 72 in a nitrogen atmosphere, without being exposed to the atmosphere, the heating temperature ​​​The specimen is gradually cooled in a nitrogen atmosphere from the heating temperature T to a temperature 100°C or more lower than the heating temperature T. Dehydration is performed under an atmosphere (not limited to nitrogen, but may be performed under helium, neon, argon, etc.) or reduced pressure. In the heat treatment, nitrogen, helium, neon, or arsenic is used. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the 9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0185] The oxide semiconductor layer 472 is subjected to heat treatment in an inert gas atmosphere such as nitrogen or under reduced pressure. By the heat treatment, the resistance of an exposed region of the oxide semiconductor layer 472 is reduced, and the first high-resistance drain A first high-resistance drain region 474a and a second high-resistance drain region 474b are formed. The region of the layer 472 covered by the channel protection layer 476 is a high resistance region. The first high-resistance drain region 473 remains as it is and becomes an I-type channel formation region 473. The oxide layer 474 includes a first high-resistance drain region 474a, a second high-resistance drain region 474b, and a channel forming region 473. A compound semiconductor layer 495 is formed (FIG. 6(C)).

[0186] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 495 and the channel protective layer 476. After the formation, the source electrode layer 475a and the drain electrode layer 475b are formed by a fifth photolithography process. An electrode layer 475b is formed.

[0187] Then, the oxide insulating layer 466, the source electrode layer 475a, the drain electrode layer 475b, and the channel electrode layer 475c are A protective insulating layer 453 and a planarizing insulating layer 454 are stacked over the panel protective layer 476 .

[0188] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 54, and the protective insulating layer 453 is etched to form a contact that reaches the drain electrode layer 475b. Forms a cut hole 494.

[0189] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0190] Next, a seventh photolithography step is performed to form a resist mask and to form a Then, unnecessary portions are removed to form a pixel electrode layer 477 and a conductive layer 467 (FIG. 6(D)).

[0191] Through the above process, seven masks are used to form a thin film transistor 499 and a thin The film transistor 498 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 499 for the driver circuit has an oxide semiconductor layer 497 which is entirely i-type. The pixel thin film transistor 498 is a channel-etched thin film transistor including the first A first high-resistance drain region 474a, a second high-resistance drain region 474b, and a channel type The channel-protective thin film transistor includes an oxide semiconductor layer 472 having a semiconductor region 473. The thin film transistor 498 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents a high electric field from being applied locally, improving the breakdown voltage of the transistor.

[0192] In the thin film transistor 499, the drain electrode layer 465b (and the source electrode layer 46 5a) and the oxide semiconductor layer, a second low-resistance drain region 408b (and a first low-resistance By adopting a configuration having a drain region 408a), thermal stability can be achieved as compared with a Schottky junction. The first low-resistance drain region 408a and the second low-resistance drain region 408b have a lower resistance than the oxide semiconductor layer and a higher resistance than the drain electrode layer 465b (and the source electrode layer 465a). Therefore, the contact resistance between the oxide semiconductor layer and the drain or source electrode layer can be reduced. Also, the first gate insulating layer 452a and the second gate insulating layer 452b can be used as dielectrics to form a holding capacitor formed by the capacitance wiring layer and the capacitance electrode on the same substrate. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. Note that this embodiment can be freely combined with other embodiments. (Embodiment 5)

[0193] Moreover, a holding capacitor formed by the capacitance wiring layer and the capacitance electrode can be formed on the same substrate using the first gate insulating layer 452a and the second gate insulating layer 452b as dielectrics. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. Moreover, a holding capacitor formed by the capacitance wiring layer and the capacitance electrode can be formed on the same substrate using the first gate insulating layer 452a and the second gate insulating layer 452b as dielectrics. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. Moreover, a holding capacitor formed by the capacitance wiring layer and the capacitance electrode can be formed on the same substrate using the first gate insulating layer 452a and the second gate insulating layer 452b as dielectrics. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. Moreover, a holding capacitor formed by the capacitance wiring layer and the capacitance electrode can be formed on the same substrate using the first gate insulating layer 452a and the second gate insulating layer 452b as dielectrics. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained. Moreover, a holding capacitor formed by the capacitance wiring layer and the capacitance electrode can be formed on the same substrate using the first gate insulating layer 452a and the second gate insulating layer 452b as dielectrics. The thin film transistor 498 and the holding capacitor are arranged in a matrix corresponding to each pixel to form a pixel portion, and a driving circuit having a thin film transistor 499 is arranged around the pixel portion, whereby one substrate for manufacturing an active matrix type display device can be obtained.

[0194] By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state. By providing the conductive layer 467 at a position overlapping the channel formation region of the oxide semiconductor layer 497, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 499 before and after the BT test can be reduced. Also, the potential of the conductive layer 467 may be the same as or different from that of the gate electrode layer 461, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 467 may be in a GND, 0V, or floating state.

[0195] Note that this embodiment can be freely combined with other embodiments.

[0196] (Embodiment 5) In this embodiment, an example of manufacturing an active matrix type liquid crystal display device using the active matrix substrate shown in Embodiment 1 is shown. Note that this embodiment can also be applied to the active matrix substrates shown in Embodiments 2 to 4.

[0197] An example of the cross-sectional structure of the active matrix substrate is shown in FIG. 7(A).

[0198] In Embodiment 1, the thin film transistors of the driving circuit and the thin film transistors of the pixel portion are illustrated on the same substrate. However, in this embodiment, in addition to those thin film transistors, the terminal portions of the holding capacitor, the gate wiring, and the source wiring are also illustrated and described. The terminal portions of the capacitor, the gate wiring, and the source wiring can be formed by the same processes as the manufacturing processes shown in Embodiment 1, and can be manufactured without increasing the number of photomasks or the number of processes. Further, in the portion that becomes the display area of the pixel portion, the gate wiring, the source wiring, and the capacitor wiring layer are all formed of a conductive film having translucency, realizing a high aperture ratio. Also, for the source wiring layer in the portion that is not the display area, a metal wiring can be used to reduce the wiring resistance to a low resistance.

[0199] In FIG. 7(A), the thin film transistor 210 is a channel etch type thin film transistor provided in the driving circuit, and the thin film transistor 220 that is electrically connected to the pixel electrode layer 227 is a channel protection type thin film transistor provided in the pixel portion.

[0200] As the thin film transistor 220 formed above the substrate 200, in this embodiment, the same structure as the thin film transistor 470 of Embodiment 1 is used.

[0201] A material having the same light transmissibility as the gate electrode layer of the thin film transistor 220 and formed in the same process The capacitor wiring layer 230 formed is overlapped with the capacitor electrode 231 via the first gate insulating layer 202a and the second gate insulating layer 202b serving as dielectrics to form a holding capacitor. Note that the capacitor electrode 231 has the same light transmissibility as the source electrode layer or the drain electrode layer of the thin film transistor 220 and is formed in the same process. Therefore, in addition to the thin film transistor 220 having light transmissibility, each holding capacitor also has light transmissibility, so that the aperture ratio can be improved.

[0202] The holding capacitor having light transmissibility is important for improving the aperture ratio. Especially in a small liquid crystal display panel of 10 inches or less, in order to increase the number of gate wirings and refine the display image, even if the pixel size is miniaturized, a high aperture ratio can be realized. Also, by using a film having light transmissibility for the components of the thin film transistor 220 and the holding capacitor, in order to realize a wide viewing angle, even if one pixel is divided into a plurality of sub-pixels, a high aperture ratio can be realized. That is, even if a high-density thin film transistor group is arranged, the aperture ratio can be increased, and the area of the display region can be sufficiently secured. For example, when one pixel has 2 to 4 sub-pixels and a holding capacitor, in addition to the thin film transistor having light transmissibility, each holding capacitor also has light transmissibility, so that the aperture ratio can be improved.

[0203] Note that the holding capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is electrically connected to the pixel electrode layer 227.

[0204] ​​​​​​​​​​​​​​​In this embodiment, a storage capacitor is formed using the capacitive electrode 231 and the capacitive wiring layer 230. Although an example has been shown, the structure for forming the storage capacitor is not particularly limited. For example, without providing a capacitive wiring layer, the pixel electrode layer may be stacked via the gate wiring of adjacent pixels, the planarization insulating layer, the protective insulating layer, and the first gate insulating layer and the second gate insulating layer to form a storage capacitor.

[0205] Also, a plurality of gate wirings, source wirings, and capacitive wiring layers are provided according to the pixel density. At the terminal portion, a plurality of first terminal electrodes having the same potential as the gate wiring, second terminal electrodes having the same potential as the source wiring, third terminal electrodes having the same potential as the capacitive wiring layer, etc. are arranged side by side. The number of each terminal electrode may be arbitrarily set, and the implementer may appropriately determine it.

[0206] At the terminal portion, the first terminal electrode having the same potential as the gate wiring can be formed of a material having the same light transmissivity as the pixel electrode layer 227. The first terminal electrode is electrically connected to the gate wiring via a contact hole reaching the gate wiring. The contact hole reaching the gate wiring is formed using the same photomask as the contact hole for electrically connecting the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227, and selectively etching the planarization insulating layer 204, the protective insulating layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202a.

[0207] Also, the gate electrode layer of the thin film transistor 210 in the driving circuit may be structured to be electrically connected to a conductive layer 217 provided above the oxide semiconductor layer. In that case, the thin film transistor ​​​​​​​​A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227 Using the same photomask as the contact hole, the planarization insulating layer 204, the protective insulating layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202a are selectively etched to form a contact hole. Through this contact hole, the conductive layer 217 is electrically connected to the gate electrode layer of the thin film transistor 210 in the driving circuit.

[0208] Also, the second terminal electrode 235 having the same potential as the source wiring 234c in the driving circuit can be formed of a material having the same light transmittance as the pixel electrode layer 2 27. The source wiring 234c can be fabricated in the same process as the source electrode or drain electrode layer of the thin film tra nsistor 210, and an oxide semiconductor layer 234a and a low-resistance drain region 234 b are laminated between the source wiring 234c and the substrate. Further, the second terminal electrode 235 is electrically connected to the source wiring through a contact hole reaching the source wiring 234c. The source wiring is a metal wiring, formed of the same material and in the same process as the source electrode layer of the thin film transistor 210 and having the same potential .. The third terminal electrode having the same potential as the capacitor wiring layer 230 can be formed of a material having the same light transmittance as the pixel electrode layer 227. Also, the contact hole reaching the capacitor wiring layer 230 can be formed using the same photomask and in the same process as the contact hole for electrically connecting the capacitor electrode 231 to the pixel electrode layer 227.

[0209] In addition, when manufacturing an active matrix type liquid crystal display device, an active matrix is the same as the contact hole for electrically connecting the capacitor electrode 231 to the pixel electrode layer 227, and can be formed using the same photomask and in the same process. formed using the same photomask and in the same process.

[0210] Also, when manufacturing an active matrix type liquid crystal display device, the active matrix A liquid crystal layer is provided between the substrate and the counter substrate provided with counter electrodes (also referred to as counter electrode layers). The active matrix substrate and the counter substrate are fixed. Note that a common electrode that is electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrode that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227. And a fourth terminal electrode that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227. And a fourth terminal electrode that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227. And a fourth terminal electrode that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227. And a fourth terminal electrode that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal electrode is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, etc. The fourth terminal electrode can be formed of a material having the same light transmittance as the pixel electrode layer 227.

[0211] Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped. Also, the configuration for electrically connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 is not particularly limited. For example, a connection electrode connecting the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be formed in the same process as the pixel electrode layer 227. Also, in a portion that is not the display area, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 may be configured to be in contact with each other and overlapped.

[0212] Note that the cross-sectional structure of the gate wiring layer 232 of the drive circuit is shown in FIG. 7(A). Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer 232 of the drive circuit uses a material having the same light transmittance as the gate electrode layer of the thin film transistor 220. Note that the cross-sectional structure of the gate wiring layer 232 of the drive circuit is shown in FIG. 7(A). Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer 232 of the drive circuit uses a material having the same light transmittance as the gate electrode layer of the thin film transistor 220. Note that the cross-sectional structure of the gate wiring layer 232 of the drive circuit is shown in FIG. 7(A). Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer 232 of the drive circuit uses a material having the same light transmittance as the gate electrode layer of the thin film transistor 220. Note that the cross-sectional structure of the gate wiring layer 232 of the drive circuit is shown in FIG. 7(A). Since this embodiment is an example of a small liquid crystal display panel of 10 inches or less, the gate wiring layer 232 of the drive circuit uses a material having the same light transmittance as the gate electrode layer of the thin film transistor 220.

[0213] Also, if the same material is used for the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, or other electrode layers, or other wiring layers, a common sputter target and a common manufacturing apparatus can be used, and the material cost and the etchant used during etching (or Also, if the same material is used for the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, or other electrode layers, or other wiring layers, a common sputter target and a common manufacturing apparatus can be used, and the material cost and the etchant used during etching (or Also, if the same material is used for the gate electrode layer, the source electrode layer, the drain electrode layer, the pixel electrode layer, or other electrode layers, or other wiring layers, a common sputter target and a common manufacturing apparatus can be used, and the material cost and the etchant used during etching (or The cost required for the (etching gas) can be reduced, and as a result, the manufacturing cost can be reduced. It can be achieved.

[0214] Also, in the structure of FIG. 7(A), when a photosensitive resin material is used as the planarization insulating layer 204 the step of forming a resist mask can be omitted.

[0215] Also, FIG. 7(B) shows a cross-sectional structure partially different from that of FIG. 7(A). Since FIG. 7(B) is the same as FIG. 7( A) except that the planarization insulating layer 204 does not exist, the same reference numerals are used for the same locations, and the detailed description of the same locations is omitted. In FIG. 7(B), a pixel electrode layer 227, a conductive layer 217, and a second terminal electrode 235 are formed in contact with the protection insulating layer 203.

[0216] With the structure of FIG. 7(B), the step of forming the planarization insulating layer 204 can be omitted.

[0217] This embodiment can be freely combined with other embodiments.

[0218] (Embodiment 6) In this embodiment, when the size of the liquid crystal display panel exceeds 10 inches, 60 inches, and further 120 inches, there is a risk that the wiring resistance of the wiring having light transmittance may become a problem. Therefore an example of reducing the wiring resistance by using a part of the gate wiring as a metal wiring is shown.

[0219] Note that in FIG. 8(A), the same reference numerals are used for the same locations as in FIG. 7(A), and the detailed description of the same locations is omitted.

[0220] FIG. 8(A) is an example in which a part of the gate wiring of the drive circuit is formed as a metal wiring and is in contact with a wiring having the same light transmittance as the gate electrode layer of the thin film transistor 210. Note that the metal wiring is formed To achieve this, the number of photomasks increases compared to Embodiment 1.

[0221] First, a heat-resistant conductive material film (with a film thickness of 100 nm or more and 500 nm or less) that can withstand the first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (with a film thickness of 100 nm or more and 500 nm or less) that can withstand the first heat treatment for dehydration or dehydrogenation is formed.

[0222] In this embodiment, a tungsten film with a film thickness of 370 nm and a tantalum nitride film with a film thickness of 50 nm are formed. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film, but it is not particularly limited. It can be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy containing the above-mentioned elements as components, an alloy combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components. The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used. Here, the conductive film is a laminate of a tantalum nitride film and a tungsten film, but it is not particularly limited. It is not particularly limited and can be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy containing the above-mentioned elements as components, an alloy combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components. It is not particularly limited and can be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or an alloy containing the above-mentioned elements as components, an alloy combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components. The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used. The heat-resistant conductive material film is not limited to a single layer containing the above-mentioned elements, and a laminate of two or more layers can be used.

[0223] Metal wiring is formed by the first photolithography process to form the first metal wiring layer 236 and the second metal wiring layer 237. For etching the tungsten film and the tantalum nitride film, an ICP (Inductively Coupled Plasma) etching method is preferably used. By using the ICP etching method and appropriately adjusting the etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.), the film can be etched into a desired tapered shape. By making the first metal wiring layer 236 and the second metal wiring layer 237 have a tapered shape, it is possible to reduce the film formation defect of the conductive film having translucency formed in contact therewith above. Metal wiring is formed by the first photolithography process to form the first metal wiring layer 236 and the second metal wiring layer 237. For etching the tungsten film and the tantalum nitride film, an ICP (Inductively Coupled Plasma) etching method is preferably used. For etching the tungsten film and the tantalum nitride film, an ICP (Inductively Coupled Plasma) etching method is preferably used. By using the ICP etching method and appropriately adjusting the etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.), the film can be etched into a desired tapered shape. By using the ICP etching method and appropriately adjusting the etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.), the film can be etched into a desired tapered shape. By making the first metal wiring layer 236 and the second metal wiring layer 237 have a tapered shape, it is possible to reduce the film formation defect of the conductive film having translucency formed in contact therewith above. By making the first metal wiring layer 236 and the second metal wiring layer 237 have a tapered shape, it is possible to reduce the film formation defect of the conductive film having translucency formed in contact therewith above.

[0224] Next, after forming a conductive film having translucency, a gate is formed by the second photolithography process. Form the gate wiring layer 238, the gate electrode layer of the thin film transistor 210, and the gate electrode layer of the thin film transistor 220. The conductive film having translucency uses the conductive material having translucency with respect to visible light described in Embodiment 1.

[0225] Note that depending on the material of the conductive film having translucency, for example, at the interface where the gate wiring layer 238 contacts the first metal wiring layer 236 or the second metal wiring layer 237, an oxide film may be formed by subsequent heat treatment or the like, and the contact resistance may increase. Therefore, it is preferable to use a metal nitride film for the second metal wiring layer 237 to prevent oxidation of the first metal wiring layer 236.

[0226] Next, a gate insulating layer, an oxide semiconductor layer, etc. are formed by the same process as in Embodiment 1. The subsequent processes produce an active matrix substrate according to Embodiment 1.

[0227] Also, in this embodiment, an example is shown in which after forming the planarization insulating layer 204, the planarization insulating layer of the terminal portion is selectively removed using a photomask. In the terminal portion, it is preferable that there is no planarization insulating layer for good connection with the FPC.

[0228] In FIG. 8(A), the second terminal electrode 235 is formed on the protective insulating layer 203. Also, in FIG. 8(A), the gate wiring layer 238 overlapping a part of the second metal wiring layer 237 is shown, but it may also be a gate wiring layer covering all of the first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 can be called auxiliary wirings for reducing the resistance of the gate wiring layer 238.

[0229] ​​​​​​​​​​​​Also, in the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed on the protective insulating layer 203 and is electrically connected to the second metal wiring layer 237. The wiring routed from the terminal portion is also formed of a metal wiring.

[0230] Also, for the gate wiring layer and the capacitor wiring layer in the portion that is not the display area, in order to reduce the wiring resistance to a low resistance the metal wirings, that is, the first metal wiring layer 236 and the second metal wiring layer 237 can also be used as auxiliary wirings

[0231] Also, FIG. 8(B) shows a cross-sectional structure that is partially different from that of FIG. 8(A). FIG. 8(B) is the same as FIG. 8( A) except that the material of the gate electrode layer of the thin film transistor in the driving circuit is different. Therefore, the same reference numerals are used for the same locations, and detailed descriptions of the same locations are omitted.

[0232] FIG. 8(B) is an example in which the gate electrode layer of the thin film transistor in the driving circuit is a metal wiring. In the driving circuit, the gate electrode layer is not limited to a material having translucency.

[0233] In FIG. 8(B), the thin film transistor 240 in the driving circuit has a gate electrode layer in which the second metal wiring layer 241 is laminated on the first metal wiring layer 242. Note that the first metal wiring layer 242 can be formed of the same material and in the same process as the first metal wiring layer 236. Also, the second metal wiring layer 241 can be formed of the same material and in the same process as the second metal wiring layer 237.

[0234] Also, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, it is preferable that the second metal wiring layer 241 for preventing oxidation of the first metal wiring layer 242 is a metal nitride film

[0235] ​​​​​ In this embodiment, by using a part of the metal wiring to reduce the wiring resistance, even when the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even 120 inches, high definition of the displayed image can be achieved, and a high aperture ratio can be realized.

[0236] This embodiment can be freely combined with other embodiments.

[0237] (Embodiment 7) In this embodiment, regarding the configuration of the holding capacitance, examples different from those in Embodiment 5 are shown in FIGS. 9(A) and 9(B). Since FIG. 9(A) is the same as FIG. 7(A) except for the difference in the configuration of the holding capacitance, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted. Note that FIG. 9 (A) shows a cross-sectional structure of the thin film transistor 220 disposed in the pixel and the holding capacitance.

[0238] FIG. 9(A) shows an example in which the dielectric is the oxide insulating layer 216, the protective insulating layer 203, and the planarization insulating layer 20 4, and the holding capacitance is formed by the pixel electrode layer 227 and the capacitance wiring layer 250 overlapping the pixel electrode layer 227. The capacitance wiring layer 250 has the same light transmissivity as the source electrode layer of the thin film transistor 220 disposed in the pixel and is formed in the same process, and thus is laid out so as not to overlap the source wiring layer of the thin film transistor 220.

[0239] The holding capacitance shown in FIG. 9(A) has light transmissivity for a pair of electrodes and the dielectric, and has light transmissivity as a whole for the entire holding capacitance.

[0240] Also, FIG. 9(B) shows an example of a configuration of the holding capacitance different from that of FIG. 9(A). Since FIG. 9(B) is the same as FIG. 7(A) except for the difference in the configuration of the holding capacitance, the same reference numerals are used for the same parts. A detailed description of the same location will be omitted.

[0241] FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220. FIG. 9(B) shows a case where a dielectric is used as the first gate insulating layer 202a and the second gate insulating layer 202b and a capacitor wiring layer 230, and a storage capacitor is formed by laminating an oxide semiconductor layer 251 and a capacitor electrode 231 that overlap the capacitor wiring layer 230. Further, the capacitor electrode 231 is laminated in contact with the oxide semiconductor layer 251 and functions as one electrode of the storage capacitor. Note that the capacitor electrode 231 is formed of the same light-transmissive material as the source electrode layer or the drain electrode layer of the thin film transistor 220 and in the same process. Also, since the capacitor wiring layer 230 is formed of the same light-transmissive material as the gate electrode layer of the thin film transistor 220 and in the same process, it is laid out so as not to overlap the gate wiring layer of the thin film transistor 220.

[0242] Also, the capacitor electrode 231 is electrically connected to the pixel electrode layer 227.

[0243] The storage capacitor shown in FIG. 9(B) also has light-transmissive electrodes and dielectric, and the entire storage capacitor has light-transmittance. The storage capacitor shown in FIG. 9(B) also has light-transmissive electrodes and dielectric, and the entire storage capacitor has light-transmittance.

[0244] The storage capacitors shown in FIGS. 9(A) and 9(B) have light-transmittance. Even if the pixel size is reduced in order to increase the definition of the displayed image by increasing the number of gate wirings or the like, a sufficient capacitance can be obtained and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have light-transmittance. Even if the pixel size is reduced in order to increase the definition of the displayed image by increasing the number of gate wirings or the like, a sufficient capacitance can be obtained and a high aperture ratio can be realized. The storage capacitors shown in FIGS. 9(A) and 9(B) have light-transmittance. Even if the pixel size is reduced in order to increase the definition of the displayed image by increasing the number of gate wirings or the like, a sufficient capacitance can be obtained and a high aperture ratio can be realized.

[0245] This embodiment can be freely combined with other embodiments.

[0246] (Embodiment 8) In this embodiment, at least a part of the driving circuit and thin film transistors to be arranged in the pixel portion are provided on the same substrate. An example of manufacturing a transistor will be described below.

[0247] The thin film transistor disposed in the pixel portion is formed according to Embodiments 1 to 4. Also, since the thin film transistors shown in Embodiments 1 to 4 are n-channel type TFTs, a part of the drive circuit that can be configured by n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion. Since the thin film transistors shown in Embodiments 1 to 4 are n-channel type TFTs, a part of the drive circuit that can be configured by n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion. Among them, a part of the drive circuit that can be configured by n-channel type TFTs is formed on the same substrate as the thin film transistor in the pixel portion. A part of the drive circuit that can be configured by n-channel type TFTs is formed on the same substrate as the thin film transistor in the pixel portion.

[0248] An example of a block diagram of an active matrix type display device is shown in FIG. 14(A). On the substrate 5300 of the display device, there are a pixel portion 5301, a first scanning line drive circuit 5302, a second scanning line drive circuit 5303, and a signal line drive circuit 5304. In the pixel portion 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 and are arranged. In the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or control IC) via a connection portion such as an FPC (Flexible Printed Circuit). On the substrate 5300 of the display device, there are a pixel portion 5301, a first scanning line drive circuit 5302, a second scanning line drive circuit 5303, and a signal line drive circuit 5304. In the pixel portion 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 and are arranged. In the pixel portion 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 and are arranged. In the pixel portion 5301, a plurality of signal lines extend from the signal line drive circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line drive circuit 5302 and the second scanning line drive circuit 5303 and are arranged. In the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. In the intersection region of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or control IC) via a connection portion such as an FPC (Flexible Printed Circuit). Also, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or control IC) via a connection portion such as an FPC (Flexible Printed Circuit).

[0249] In FIG. 14(A), the first scanning line drive circuit 5302, the second scanning line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as the drive circuit provided outside is reduced, and cost reduction can be achieved. Also, when a drive circuit is provided outside the substrate 5300, the wiring at the connection portion due to extending the wiring is... In FIG. 14(A), the first scanning line drive circuit 5302, the second scanning line drive circuit 5303, and the signal line drive circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of components such as the drive circuit provided outside is reduced, and cost reduction can be achieved. Also, when a drive circuit is provided outside the substrate 5300, the wiring at the connection portion due to extending the wiring is... The number of connections can be reduced, and the reliability or the yield can be improved.

[0250] Note that the timing control circuit 5305 supplies, as an example, a start signal for the first scanning line driving circuit 5302 (the start signal is also referred to as a start pulse) and a clock signal for the scanning line driving circuit (GCK1). Further, the timing control circuit 5305 supplies, as an example, a start signal for the second scanning line driving circuit 5303 and a clock signal for the scanning line driving circuit (GCK2). The signal line driving circuit 5304 is supplied with a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), data for the video signal (simply referred to as the video signal) and a latch signal (LAT). Each clock signal may be a plurality of clock signals with a shifted period, or may be supplied together with a signal (CKB) obtained by inverting the clock signal. Note that one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 can be omitted.

[0251]

[0252] In FIG. 14(B), a configuration is shown in which the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 are formed on the same substrate 5300 as the pixel portion 5301, and the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301.

[0252] Also, the thin film transistors shown in Embodiments 1 to 4 are n-channel type TFTs. In FIGS. 15(A) and 15(B), an example of the configuration and operation of a signal line driving circuit configured by n-channel type TFTs will be shown and described.

[0253] ​The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 includes a plurality of circuits such as switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of transistors such as thin film transistors 5603_1 to 5603_k (k is a natural number). An example where the thin film transistors 5603_1 to 5603_k are N-channel type TFTs will be described.

[0254] Regarding the connection relationship of the signal line driving circuit, an example will be described using the switching circuit 5602_1. The first terminals of the thin film transistors 5603_1 to 5603_k are each connected to wirings 5604_1 to 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are each connected to signal lines S1 to Sk. The gates of the thin film transistors 5603_1 to 5603_k are connected to the wiring 5605_1.

[0255] The shift register 5601 outputs signals of H level (also referred to as H signal, high power supply potential level) to the wirings 5605_1 to 5605_N in sequence, and has a function of selecting the switching circuits 5602_1 to 5602_N in sequence.

[0256] The switching circuit 5602_1 has a function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, a function of controlling whether to supply the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. Also, the thin film transistors 5603_1 to 5603_k each have the wirings 5604_1 to 5604_k. ​​​​​​​​ A function of controlling the conduction states with the signal lines S1 to Sk, that is, wirings 5604_1 to 5604_k has a function of supplying the potentials thereof to the signal lines S1 to Sk. Thus, the thin film transistors 56 03_1 to 5603_k each have a function as a switch.

[0257] Note that video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often an analog signal corresponding to image information or an image signal.

[0258] Next, the operation of the signal line driving circuit in Fig. 15(A) will be described with reference to the timing chart in Fig. 15(B). Fig. 15(B) shows an example of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata _k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing video signal data (DATA) to the pixels belonging to the selected row.

[0259] Note that the blurring of the signal waveforms of each configuration shown in the drawings and the like of the present embodiment may be exaggeratedly represented for clarity. Therefore, it is noted that it is not necessarily limited to that scale.

[0260] During periods T1 to TN, the shift register 5601 outputs a signal at the H level to wirings 560 5_1 to 5605_N in sequence. For example, during period T1, the shift register 5 601 outputs a high-level signal to wiring 5605_1. Then, the thin-film transistors 5603_1 to 5603_k turn on, so wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state. At this time, Data(S1) to Data(Sk) are input to wirings 5604_1 to 5604_k. Data(S1) to Data(Sk ) are written to the pixels in the first to k-th columns among the pixels belonging to the selected row, respectively, via the thin-film transistors 5603_1 to 5603_k. In this way, during periods T1 to TN, the video signal data (DATA) is written to the pixels belonging to the selected row, k columns at a time in sequence.

[0261] As described above, by writing the video signal data (DATA) to the pixels in multiple columns at a time, the number of the video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal to the pixels in multiple columns at a time, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0262] Note that as the shift register 5601 and the switching circuit 5602, a circuit composed of the thin-film transistors shown in Embodiments 1 to 4 can be used.

[0263] A form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 16 and 17.

[0264] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the gate electrodes of the transistors of one line of pixels are connected. Therefore, since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used. Therefore, since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used.

[0265] The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 16(A)). In the shift register shown in FIG. 16(A), the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are supplied with a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14. In the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. In the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) from the second stage onward, a signal from the pulse output circuit of the previous stage (referred to as the previous stage signal OUT(n - 1)) is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, a signal from the (n + 2)th pulse output circuit two stages later is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. In the first pulse output circuit 10_1, a signal from the third pulse output circuit 10_3 two stages later is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, a signal from the (n + 2)th pulse output circuit two stages later is input. A signal from the pulse output circuit 10_(n+2) (referred to as the subsequent-stage signal OUT(n+2)) is input. Therefore, from each stage's pulse output circuit, a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent-stage and / or previous-stage pulse output circuits, and a second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. Note that, as shown in FIG. 16(A), since the subsequent-stage signal OUT(n+2) is not input to the two final stages of the shift register, as an example, a separate second start pulse SP2 and a third start pulse SP3 may be respectively input. The clock signal (CK) is a signal that repeats between the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In this embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. Note that the clock signal may also be referred to as GCK, SCK depending on the input driving circuit, but here it will be described as CK.

[0266] FIG. 16(B) shows one of the pulse output circuits 10_N shown in FIG. 16(A). The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 16(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 16(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second

[0267] input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. 14. For example, in FIG. 16(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. is electrically connected to 13. Also, the second pulse output circuit 10_2 has a first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14.

[0268] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see FIG. 16(B)). In the first pulse output circuit 10_1, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, a third clock signal CK3 is input to the third input terminal 23, a start pulse is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT(1) is output from the second output terminal 27. In addition to the three-terminal thin film transistor (also referred to as TFT: Thin Film Transistor), the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N can use the four-terminal thin film transistor described in the above embodiment. In this specification, when the thin film transistor has two gate electrodes via a semiconductor layer,

[0269] the gate electrode below the semiconductor layer is also called the lower gate electrode, and the gate electrode above the semiconductor layer is also called the upper gate electrode.

[0270] ​​​​​When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, the manufacturing process may cause the threshold voltage to shift to the negative side or the positive side. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region, a configuration capable of controlling the threshold voltage is preferable. The threshold voltage of a four-terminal thin film transistor can be controlled to a desired value by providing gate electrodes via gate insulating films above and below the channel formation region of the thin film transistor and controlling the potentials of the upper and / or lower gate electrodes. The threshold voltage of a four-terminal thin film transistor can be controlled to a desired value by providing gate electrodes via gate insulating films above and below the channel formation region of the thin film transistor and controlling the potentials of the upper and / or lower gate electrodes. The threshold voltage of a four-terminal thin film transistor can be controlled to a desired value by providing gate electrodes via gate insulating films above and below the channel formation region of the thin film transistor and controlling the potentials of the upper and / or lower gate electrodes. value.

[0271] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. 16 (C).

[0272] The pulse output circuit shown in FIG. 16(C) includes transistors 31 to 43 of the first to thirteenth transistors (see FIG. 16(D)). In addition to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which the first high power supply potential V DD is supplied, a power supply line 52 to which the second high power supply potential VCC is supplied, and a power supply line 53 to which the low power supply potential VSS is supplied, signals or power supply potentials are supplied to the transistors 31 to 43 of the first to thirteenth transistors . Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(C) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. Note that the first clock signal (CK1) to the fourth clock signal (CK4) are signals that repeat the H level and the L level at regular intervals, and it is assumed that they are at VDD when at the H level and at VSS when at the L level. The threshold voltage of a four-terminal thin film transistor can be controlled to a desired value by providing gate electrodes via gate insulating films above and below the channel formation region of the thin film transistor and controlling the potentials of the upper and / or lower gate electrodes. By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, the operation can be carried out without affecting it, and the potential applied to the gate electrode of the transistor can be kept low so that the shift of the threshold value of the transistor can be reduced and degradation can be suppressed. Note that among the first transistor 31 to the thirteenth transistor 43, the first transistor 31 and the sixth transistor 36 to the ninth transistor 39 preferably use four-terminal thin-film transistors . The operations of the first transistor 31, the sixth transistor 36 to the ninth transistors 39 are transistors for which it is required to switch the potential of a node to which one of the electrodes serving as the source or drain is connected by the control signal of the gate electrode , and are transistors for which the response to the control signal input to the gate electrode is fast (the rise of the on-current is steep ) so that malfunction of the pulse output circuit can be further reduced. Therefore, by using four-terminal thin-film transistors, the threshold voltage can be controlled , and a pulse output circuit with further reduced malfunction can be obtained.

[0273] In FIG. 16(C), for the first transistor 31, the first terminal is electrically connected to the power supply line 51 , the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24 . For the second transistor 32, the first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. For the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26 is continued. The fourth transistor 34 has its first terminal electrically connected to the power supply line 53, and its second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power supply line 53, and its second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode is connected to the fourth input terminal 24 electrically. The sixth transistor 36 has its first terminal electrically connected to the power supply line 52, and its second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power supply line 52, and its second terminal is electrically connected to the second terminal of the eighth transistor 38 , and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 , and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the second input terminal 22. The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the power supply line 51 . The tenth transistor 40 has its first terminal electrically connected to the first input terminal 2 and its second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the power supply line 51 . The tenth transistor 40 has its first terminal electrically connected to the first input terminal 2 and its second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and its second terminal is electrically connected to 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The twelfth transistor 42 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode ). The thirteenth transistor 43 has its first terminal electrically connected to the power supply line 5 3, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode).

[0274] In FIG. 16(C), the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 0, and the second terminal of the ninth transistor 39 is defined as node A. Also, the connection point of the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41 is defined as node B .

[0275] In FIG. 17(A), when the pulse output circuit described in FIG. 16(C) is applied to the first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26​ and a signal input to or output from a second output terminal 27.

[0276] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse (SP1) is input to the fourth input terminal 24, and a fifth The next stage signal OUT(3) is input to the first input terminal 25, and the first output terminal 26 outputs the first output The signal OUT(1) (SR) is output, and the second output signal OUT( 1) is output.

[0277] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. A semiconductor device has a terminal and a channel region formed in a region overlapping with the gate. By controlling the gate potential, the drain and source are connected via the channel region. The current flowing between the source and drain can be controlled by the thin film transistor. Which is the source and which is the drain depends on the transistor structure and operating conditions, etc. Therefore, the regions that function as the source and drain are In some cases, the term "source" or "drain" is not used. In such cases, for example, They may be written as terminal or second terminal.

[0278] In FIG. 16(C) and FIG. 17(A), the node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0279] Here, the timing chart of a shift register including a plurality of pulse output circuits shown in Fig. 17(A) is shown in Fig. 17(B). When the shift register is a scanning line drive circuit, the period 61 in Fig. 17(B) is the vertical blanking period, and the period 62 corresponds to the gate selection period.

[0280] As shown in Fig. 17(A), by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, there are the following advantages before and after the bootstrap operation.

[0281] When there is no ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, when the potential of node A rises due to the bootstrap operation, the potential of the source, which is the second terminal of the first transistor 31, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising although the potential of node A rises due to the bootstrap operation. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of the present embodiment, the ​​​​​​​​​​​​​​​ The negative bias voltage applied between the gate and the source can also be reduced, so that the degradation of the first transistor 31 due to stress can be suppressed.

[0282] Regarding the location where the ninth transistor 39 is provided, it may be provided in such a configuration that it is connected via a first terminal and a second terminal between the second terminal of the first transistor 31 and the gate of the third transistor 33. In the case of a shift register having a plurality of pulse output circuits according to the present embodiment, in a signal line driving circuit having a larger number of stages than the scanning line driving circuit, the ninth transistor 39 may be omitted, and there is an advantage in reducing the number of transistors.

[0283] By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, the off-current of the thin film transistor can be reduced, the on-current and the field effect mobility can be increased, and the degree of degradation can be reduced. Therefore, malfunction in the circuit can be reduced. Further, a transistor using an oxide semiconductor has a smaller degree of degradation of the transistor due to the application of a high potential to the gate electrode than a transistor using amorphous silicon. Therefore, even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, the same operation can be obtained, and the number of power supply lines for wiring between circuits can be reduced, so that the circuit can be miniaturized.

[0284] The gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 are supplied with a clock signal CK3 supplied by the third input terminal 23, and the eighth transistor 38 ​​​​​​​​​​​​​The clock signal CK2 supplied to the gate electrodes (the lower gate electrode and the upper gate electrode) by the second input terminal 22 is the same as the clock signal CK2 supplied to the gate electrodes (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 by the second input terminal 22, and the clock signal CK 2 supplied to the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 38 is the clock signal CK3 supplied by the third input terminal 23. Even if the connection relationship is changed, the same operation is achieved. At this time, in the shift register shown in Fig. 17(A), when both the seventh transistor 37 and the eighth transistor 38 are turned on, then the seventh transistor 37 is turned off and the eighth transistor 38 is turned on, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the potential of the node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in Fig. 17(A), as in the period of Fig. 17(B), when both the seventh transistor 37 and the eighth transistor 38 are turned on, then the seventh transistor 37 is turned on and the eighth transistor 38 is turned off, and then the seventh transistor 37 is turned off and the eighth transistor 38 is turned off, the decrease in the potential of the node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the clock signal CK is input from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37 state, the potential of the node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the clock signal CK is input from the third input terminal 23 to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) so that the potential of the node B caused by the decrease in the potential of the second input terminal 22 and the third input terminal 23 can be reduced once by the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the clock signal CK is input from the third input terminal 23 to the gate electrode​ 3 is supplied, and the clock signal CK2 is supplied from the second input terminal 22 to the gate electrodes (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This wiring relationship is preferable. This is because the number of fluctuations in the potential of node B is reduced and noise can be reduced.

[0285] In this way, by configuring such that a signal of the H level is periodically supplied to node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level, malfunction of the pulse output circuit can be suppressed.

[0286] (Embodiment 9) According to one aspect of the present invention, a thin film transistor can be manufactured, and a semiconductor device (also referred to as a display device) having a display function can be manufactured by using the thin film transistor in a pixel portion and further in a driving circuit. Also, a part or all of the driving circuit using the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel.

[0287] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage. Specifically, it includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like. Also, electronic ink or a display medium whose contrast changes by an electric action can be applied.

[0288] Further, the display device includes a panel in which the display element is sealed, and a controller for the panel. ​​​​​​​​​​It includes a module in a state where an IC or the like is mounted. Further, in the process of manufacturing the display device The element substrate corresponding to a form before the display element is completed includes means for supplying current to the display element to each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes (also referred to as pixel electrode layers) of the display element are formed, or may be in a state after forming a conductive film to be a pixel electrode and before etching to form the pixel electrode and any form applies.

[0289] In addition, the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device.

[0290] The appearance and cross-section of a liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 10. FIGS. 10(A1) and (A2) are plan views of the panel in which the thin film transistors 4010, 4011, and the liquid crystal element 4013 are sealed between the first substrate 4001 and the second substrate 4006 by a sealing material 4005, and FIG. 10(B) corresponds to a cross-sectional view taken along M-N of FIGS. 10(A1) and (A2).

[0291] ​​​​​​​​​​​​A pixel portion 4002 provided on a first substrate 4001 and a scanning line driving circuit 4004 are surrounded by a sealing material 4005 is provided in such a manner. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with a liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0292] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method or the like can be used. FIG. 10(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 10(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method.

[0293] Also, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 have a plurality of thin film transistors. In FIG. 10(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. An insulating layer 4041, a protective insulating layer 4020, and an insulating layer 4021 are provided on the thin film transistors 4010 and 4011. Also, the thin film transistor 4010 has a channel protection layer 4042.

[0294] The thin film transistors 4010 and 4011 are formed of the oxide semiconductor layer shown in Embodiments 1 to 4. A highly reliable thin film transistor can be applied. The thin film transistor for the driving circuit 4011 can be the thin film transistors 460, 499, shown in Embodiments 1 to 4. The thin film transistor 4010 for the pixel can be used by combining the thin film transistors 470 and 498. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin

[0295] film transistors. On the insulating layer 4021, a conductive layer 4040 is provided at a position overlapping the channel formation region of the oxide semiconductor layer of the thin film transistor 4011 for the driving circuit. By providing the conductive layer 4040 at a position overlapping the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the thin film transistor 4011 before and after the BT test can be reduced. Also, the potential of the conductive layer

[0296] 4040 may be the same as or different from the gate electrode layer of the thin film transistor 4011, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or in a floating state. The pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal

[0297] Note that as the first substrate 4001 and the second substrate 4006, a light-transmissive substrate can be used, and glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used.

[0298] Also, the spacer 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Further, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using a common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected via conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 4005.

[0299] Also, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears within a relatively narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require alignment treatment, and has a small viewing angle dependence.

[0300] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a transflective liquid crystal display device.

[0301] In a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and an example is shown in which a colored layer (color filter) and an electrode layer used for the display element are provided in this order. However, the polarizing plate may be provided on the inner side of the substrate. Further, the laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the colored layer. In addition, a light shielding film that functions as a black matrix may be provided outside the display portion.

[0302] A protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. Here, a silicon nitride film is formed as the protective insulating layer 4020 by the RF sputtering method. Note that the protective insulating layer 4020 may be formed of the same material and method as the protective insulating layer 453 shown in Embodiment 1.

[0303] An insulating layer 4021 is formed as a planarizing insulating film. The insulating layer 4021 may be formed of the same material and method as the planarizing insulating layer 454 shown in Embodiment 1, and an organic material having heat resistance such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, a low dielectric constant material (low -k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass) etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0304] In the present embodiment, a configuration in which a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film ​It is also possible. Using a nitride insulating film for the protective insulating layer 4020 and the gate insulating layer, as shown in FIG. 10 A configuration may be adopted in which a region where the protective insulating layer 4020 and the gate insulating layer are in contact with each other is provided so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process it is possible to prevent the intrusion of moisture from the outside. Also, even after the device is completed as a semiconductor device, for example, a display device, it is possible to prevent the intrusion of moisture from the outside in the long term, and the long-term reliability of the device can be improved.

[0305] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. As substituents, the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group. Also, the organic group may have a fluoro group

[0306] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, sputtering method, SOG method spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), or methods such as doctor knife, roll coater, curtain coater, knife coater, etc. can be used. By combining the firing process of the insulating layer 4021 with the annealing of the semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0307] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0308] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0309] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0310] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0311] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0312] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0313] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. Although an example of the installation is shown, it is not limited to this configuration. The scanning line driving circuit may be separately formed and implemented, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and implemented.

[0314] FIG. 19 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by the manufacturing method disclosed in this specification.

[0315] FIG. 19 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. Polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer.

[0316] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, ​​​​​​​​​​​Alignment mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. Alignment mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used.

[0317] Through the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device.

[0318] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0319] (Embodiment 10) An example of electronic paper is shown as a form of a semiconductor device.

[0320] Electronic paper that drives electronic ink using an element electrically connected to a switching element may be used. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as the same readability as paper, low power consumption compared to other display devices, and the ability to be thin and lightweight. Electronic paper that drives electronic ink using an element electrically connected to a switching element may be used. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as the same readability as paper, low power consumption compared to other display devices, and the ability to be thin and lightweight. and the ability to be thin and lightweight.

[0321] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the micro Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the micro capsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or solute, and by applying an electric field to the microcapsule, the micro ​​​Move the particles in the capsule in opposite directions to each other and display only the color of the particles that have gathered on one side It is a thing that does. The first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). (including colorless).

[0322] In this way, the electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The electrophoresis display does not require a polarizing plate necessary for a liquid crystal display device.

[0323] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having a color filter or a pigment.

[0324] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 4 can be used.

[0325] The first particle and the second particle in the microcapsule may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0326] ​​​​​​​​​​​FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The semiconductor The thin film transistor 581 used in the device can be manufactured in the same manner as the thin film transistor shown in Embodiment 1, and is a highly reliable thin film transistor including an oxide semiconductor layer. Also the thin film transistors shown in Embodiments 2 to 4 can also be applied as the thin film transistor 581 of the present embodiment.

[0327] The electronic paper in FIG. 18 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by disposing spherical particles painted white and black between a first electrode layer and a second electrode layer that are electrode layers used in a display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles.

[0328] The thin film transistor 581 formed on the substrate 580 is a thin film transistor having a bottom gate structure and is covered with an insulating film 583 in contact with the semiconductor layer. The source electrode layer or drain electrode layer of the thin film transistor 581 is in contact with and electrically connected to the first electrode layer 587 through an opening formed in the insulating film 583 and the insulating layer 585. Between the first electrode layer 587 and the second electrode layer 588 formed on the substrate 596, spherical particles 589 including a cavity 594 having black regions 590a and white regions 590b and filled with a liquid around are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin. The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. 88 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 581. It is possible. By using the common connection portion, the second electrode layer can be electrically connected to the common potential line 588 through the conductive particles disposed between the pair of substrates.

[0329] Also, instead of using the element with the twist ball, it is also possible to use an electrophoretic element. A transparent liquid, positively charged white fine particles, and negatively charged black fine particles are encapsulated in microcapsules having a diameter of about 10 μm to 200 μm. The microcapsules provided between the first electrode layer and the second electrode layer move the white fine particles and the black fine particles in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, and a device using the electrophoretic display element is generally called an electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, the power consumption is small, and the display portion can be recognized even in a dim place. Also, even when no power is supplied to the display portion, since the image once displayed can be held, it is possible to keep the displayed image even when the semiconductor device with a display function (simply referred to as a display device or a semiconductor device including the display device) is far from the radio wave transmission source.

[0330] Through the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0331] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0332] (Embodiment 11) ​​​​​​​​​An example of a light-emitting display device as a semiconductor device is shown. As the display element of the display device, here is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that utilizes electroluminescence is classified depending on whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0333] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when those carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0334] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of the light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which the light-emitting layer is sandwiched between dielectric layers, and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation.

[0335] FIG. 12 is a diagram showing an example of a pixel configuration to which digital time-graded driving can be applied as an example of a semiconductor device.

[0336] ​​​The configuration of pixels to which digital time gradation driving can be applied and the operation of the pixels will be described. Here shows an example in which one pixel uses two n-channel transistors that use an oxide semiconductor layer as a channel formation region. Two are used for each pixel.

[0337] Pixel 6400 has a switching transistor 6401, a light-emitting element driving transistor 6 402, a light-emitting element 6404, and a capacitor element 6403. The switching transistor 6401 has its gate connected to the scanning line 6406, its first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) connected to the gate of the light-emitting element driving transistor 6402. The light-emitting element driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitor element 6403 , its first electrode connected to the power supply line 6407, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0338] Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set on the power supply line 6407, and the low power supply potential < is a potential that satisfies the high power supply potential, and for example, GND, 0 V, etc. may be set as the low power supply potential. A potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the potential difference between the high power supply potential and the low power supply potential is set so as to be equal to or higher than the forward threshold voltage of the light-emitting element 6404. Each potential is set accordingly.

[0339] Note that the capacitive element 6403 can also be used to substitute for the gate capacitance of the transistor 6402 for driving the light-emitting element. It is also possible to omit it. Regarding the gate capacitance of the transistor 6402 for driving the light-emitting element a capacitance may be formed between the channel region and the gate electrode.

[0340] Here, in the case of the voltage input voltage driving method, a video signal that causes the transistor 6402 for driving the light-emitting element to be in one of two states, either fully on or off, is input to the gate of the transistor 6402 for driving the light-emitting element. That is, the transistor 6402 for driving the light-emitting element operates in the linear region. Since the transistor 6402 for driving the light-emitting element operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the transistor 6402 for driving the light-emitting element. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the transistor 6402 for driving the light-emitting element) is applied to the signal line 6405.

[0341] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 12 can be used by changing the signal input.

[0342] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light-emitting element 6404 + the Vth of the transistor 6402 for driving the light-emitting element is applied to the gate of the transistor 6402 for driving the light-emitting element. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and is at least greater than the forward threshold voltage. Note that a video signal that causes the transistor 6402 for driving the light-emitting element to operate in the saturation region is input to cause a current to flow through the light-emitting element 6404. ​​​​​​​​​​​This is possible. In order to operate the transistor 6402 for driving the light-emitting element in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the transistor 6402 for driving the light-emitting element. By using the video signal as an analog signal, a current corresponding to the video signal can be passed through the light-emitting element 6404, and analog gradation driving can be performed.

[0343] Note that the pixel configuration shown in FIG. 12 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit, etc. may be added to the pixel shown in FIG. 12.

[0344] Next, the configuration of the light-emitting element will be described with reference to FIG. 13. Here, the case where the TFT for driving the light-emitting element is of the n-type will be taken as an example to describe the cross-sectional structure of the pixel. The TFTs 7001, 7011, and 7021, which are the TFTs for driving the light-emitting element used in the semiconductor devices of FIGS. 13(A), (B), and (C), can be fabricated in the same manner as the thin-film transistors arranged in the pixels shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer. Also, the thin-film transistors arranged in the pixels shown in Embodiments 2 to 4 can be applied as the TFTs 7001, 7011, and 7021. For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, there are top emission light-emitting elements that form thin-film transistors and light-emitting elements on a substrate and extract light from the surface opposite to the substrate, bottom emission light-emitting elements that extract light from the surface on the substrate side, and double-sided emission light-emitting elements that extract light from both the substrate side and the surface opposite to the substrate, and the pixel configuration can be applied to light-emitting elements of any emission structure.

[0345]

[0346] ​​​​​​​​​​The light-emitting element with an upper emission structure will be described with reference to Fig. 13(A).

[0347] Fig. 13(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a TFT for driving a light-emitting element, is of the n-type and the light emitted from the light-emitting element 700 2 leaks to the anode 7005 side. In Fig. 13(A ), the cathode 7003 of the light-emitting element 7002 is electrically connected to the TFT 7001, which is a TFT for driving the light-emitting element , and a light-emitting layer 7004 and an anode 7005 are sequentially laminated on the cathode 7003 . The cathode 7003 can be made of various materials as long as it is a conductive film with a low work function and that reflects light . For example, Ca, Al, MgAg, AlLi, etc. are desirable . The light-emitting layer 7004 may be composed of a single layer or a plurality of layers laminated . When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are laminated in this order on the cathode 7003 . Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties , and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium stannate containing titanium oxide , indium tin oxide (hereinafter referred to as ITO), indium zinc oxide , or a conductive film having light-transmitting properties such as indium tin oxide added with silicon oxide may be used .

[0348] Also, a partition wall 7009 is provided between the cathode 7008 of the pixel adjacent to the cathode 7003, covering their respective ends . The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic resin, polyamide, or epoxy resin, an inorganic insulating film, or an organic polysiloxane. The partition wall 70​ 09 is preferably formed using a photosensitive resin material such that the side surface of the partition wall 7009 forms an inclined surface with a continuous curvature. When using a photosensitive resin material as the partition wall 7009, the process of forming a resist mask can be omitted.

[0349] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 13(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow.

[0350] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 13(B). A cross-sectional view of a pixel is shown when the TFT 7011 for driving the light-emitting element is of the n-type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. In Fig. 13(B), the cathode 7013 of the light-emitting element 7012 is formed on a translucent conductive film 7017 that is electrically connected to the TFT 7011 for driving the light-emitting element. The light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7015 is translucent, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. Similar to the case of Fig. 13(A), the cathode 7013 can be made of various conductive materials as long as they have a small work function. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7014, similar to Fig. 13(A), can be composed of a single layer or a plurality of laminated layers. The anode 7015 is translucent. Although not necessary, it can be formed using a conductive material having translucency, as in FIG. 13(A). The shielding film 7016 can be formed using, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin added with a black pigment can also be used.

[0351] Also, between the conductive films 7018 of the pixels adjacent to the conductive film 7017, cover the respective ends and provide a partition wall 7019. The partition wall 7019 is formed using an organic resin film such as polyimide, acrylic resin, polyamide, epoxy resin, an inorganic insulating film, or an organic polysiloxane. The partition wall 7019 is preferably formed using a photosensitive resin material so that the side surface of the partition wall 7019 becomes an inclined surface formed with a continuous curvature and is formed. When a photosensitive resin material is used as the partition wall 7019, the step of forming a resist mask can be omitted.

[0352] The region sandwiching the light-emitting layer 7014 between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012 In the case of the pixel shown in FIG. 13(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0353] Next, a light-emitting element having a double-sided emission structure will be described with reference to FIG. 13(C). FIG. 13(C) shows that the cathode 7023 of the light-emitting element 7022 is formed on a translucent conductive film 702 7 electrically connected to the TFT 7021 for driving the light-emitting element, and the light-emitting layer 7 024 and the anode 7025 are sequentially laminated on the cathode 7023. The cathode 7023 can be formed using various materials as long as they are conductive materials having a small work function, as in the case of FIG. 13(A). However, the film thickness thereof should be such that light can pass through. For example, Al having a film thickness of 20 nm is used for the cathode 702​​ It can be used as 3. And the light-emitting layer 7024 may be composed of a single layer or a plurality of layers laminated in the same manner as in Fig. 13(A). Either way is acceptable. The anode 7025 can be formed using a conductive material having light-transmitting properties that transmit light, similar to Fig. 13(A). It can be formed.

[0354] Also, between the conductive films 7028 of the pixels adjacent to the conductive film 7027, partition walls 7029 are provided to cover the respective ends. The partition walls 7029 are formed using an organic resin film such as polyimide, acrylic resin, polyamide, epoxy resin, an inorganic insulating film, or an organic polysiloxane. The partition walls 7029 are preferably formed using a photosensitive resin material so that the side surfaces of the partition walls 7029 become inclined surfaces formed with continuous curvature. When a photosensitive resin material is used as the partition walls 7029, the step of forming a resist mask can be omitted. When a photosensitive resin material is used as the partition walls 7029, the step of forming a resist mask can be omitted. It is preferably formed so that the side surfaces of the partition walls 7029 become inclined surfaces formed with continuous curvature. When a photosensitive resin material is used as the partition walls 7029, the step of forming a resist mask can be omitted. When a photosensitive resin material is used as the partition walls 7029, the step of forming a resist mask can be omitted.

[0355] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. In the case of the pixel shown in Fig. 13(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows. The light is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0356] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element. It is also possible to provide an inorganic EL element as the light-emitting element.

[0357] Although an example in which a thin-film transistor (TFT for driving a light-emitting element) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element has been shown, a configuration in which a current control TFT is connected between the TFT for driving the light-emitting element and the light-emitting element may also be acceptable. Although an example in which a thin-film transistor (TFT for driving a light-emitting element) for controlling the driving of the light-emitting element is electrically connected to the light-emitting element has been shown, a configuration in which a current control TFT is connected between the TFT for driving the light-emitting element and the light-emitting element may also be acceptable. A configuration in which a current control TFT is connected between the TFT for driving the light-emitting element and the light-emitting element may also be acceptable.

[0358] Note that the semiconductor device is not limited to the configuration shown in FIG. 13, and various modifications based on the technical idea disclosed in this specification are possible.

[0359] Next, the appearance and cross section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 11. FIG. 11(A) is a plan view of a panel in which a thin film transistor and a light-emitting element formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 11(B) corresponds to a cross-sectional view taken along H-I in FIG. 11(A).

[0360] A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on a first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b are sealed together with a filler 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (laminating film, ultraviolet curable resin film, etc.) or cover material so as not to be exposed to the outside air.

[0361] Also, the pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of thin film transistors. ​​​​​​​​​In FIG. 11(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated. The thin film transistors 4509 and 4510 can be applied with highly reliable thin film transistors including the oxide semiconductor layer shown in Embodiments 1 to 4. As the thin film transistor 4509 disposed in the driving circuit, the thin film transistors 460 and 499 shown in Embodiments 1 to 4 can be used. As the thin film transistor 4510 disposed in the pixel, the thin film transistors 470 and 498 can be used in combination. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0362] On the insulating layer 4544, a conductive layer 4540 is provided at a position overlapping the channel formation region of the oxide semiconductor layer of the thin film transistor 4509 for the driving circuit. By providing the conductive layer 4540 at a position overlapping the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the thin film transistor 4509 before and after the BT test can be reduced. Also, the potential of the conductive layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509, or may be different, and it can also function as a second gate electrode layer. Further, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. In addition, an insulating layer 4543 is formed on the thin film transistors 4509 and 4510. Here, as the insulating layer 4543, a silicon nitride film is formed by the RF sputtering method. Note that the insulating layer 4543 is formed of the same material and method as the protective insulating layer 453 shown in Embodiment 1. The thin film transistor 4509 disposed in the driving circuit can be the thin film transistors 460 and 499 shown in Embodiments 1 to 4. The thin film transistor 4510 disposed in the pixel can be the thin film transistors 470 and 498 used in combination. In this embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors. On the insulating...

Claims

[Claim 1] A pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor are provided on the same substrate, the first thin film transistor includes a gate electrode layer over a substrate, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer having a thin-film region on a periphery of the gate insulating layer, an oxide insulating layer in contact with a part of the oxide semiconductor layer, a source electrode layer and a drain electrode layer over the oxide insulating layer and the oxide semiconductor layer, and a pixel electrode layer electrically connected to the source electrode layer or the drain electrode layer; the gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source electrode layer, the drain electrode layer, the oxide insulating layer, and the pixel electrode layer of the first thin film transistor have a light-transmitting property; a source electrode layer and a drain electrode layer of the second thin film transistor are covered with a protective insulating layer, are made of a different material from the source electrode layer and the drain electrode layer of the first thin film transistor, and are made of a conductive material having a lower resistance than the source electrode layer and the drain electrode layer of the first thin film transistor.

Images